36 lines · c
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py2// RUN: %clang_cc1 -triple riscv64 -target-feature +zknd -emit-llvm %s -o - \3// RUN: -disable-O0-optnone | opt -S -passes=mem2reg \4// RUN: | FileCheck %s -check-prefix=RV64ZKND5 6#include <riscv_crypto.h>7 8// RV64ZKND-LABEL: @aes64dsm(9// RV64ZKND-NEXT: entry:10// RV64ZKND-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.aes64dsm(i64 [[RS1:%.*]], i64 [[RS2:%.*]])11// RV64ZKND-NEXT: ret i64 [[TMP0]]12//13uint64_t aes64dsm(uint64_t rs1, uint64_t rs2) {14 return __riscv_aes64dsm(rs1, rs2);15}16 17 18// RV64ZKND-LABEL: @aes64ds(19// RV64ZKND-NEXT: entry:20// RV64ZKND-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.aes64ds(i64 [[RS1:%.*]], i64 [[RS2:%.*]])21// RV64ZKND-NEXT: ret i64 [[TMP0]]22//23uint64_t aes64ds(uint64_t rs1, uint64_t rs2) {24 return __riscv_aes64ds(rs1, rs2);25}26 27 28// RV64ZKND-LABEL: @aes64im(29// RV64ZKND-NEXT: entry:30// RV64ZKND-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.aes64im(i64 [[RS1:%.*]])31// RV64ZKND-NEXT: ret i64 [[TMP0]]32//33uint64_t aes64im(uint64_t rs1) {34 return __riscv_aes64im(rs1);35}36