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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py2// RUN: %clang_cc1 -triple riscv64 -target-feature +zknh -emit-llvm %s -o - \3// RUN: -disable-O0-optnone | opt -S -passes=mem2reg \4// RUN: | FileCheck %s -check-prefix=RV64ZKNH5 6#include <riscv_crypto.h>7 8// RV64ZKNH-LABEL: @sha512sig0(9// RV64ZKNH-NEXT: entry:10// RV64ZKNH-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sha512sig0(i64 [[RS1:%.*]])11// RV64ZKNH-NEXT: ret i64 [[TMP0]]12//13uint64_t sha512sig0(uint64_t rs1) {14 return __riscv_sha512sig0(rs1);15}16 17 18// RV64ZKNH-LABEL: @sha512sig1(19// RV64ZKNH-NEXT: entry:20// RV64ZKNH-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sha512sig1(i64 [[RS1:%.*]])21// RV64ZKNH-NEXT: ret i64 [[TMP0]]22//23uint64_t sha512sig1(uint64_t rs1) {24 return __riscv_sha512sig1(rs1);25}26 27 28// RV64ZKNH-LABEL: @sha512sum0(29// RV64ZKNH-NEXT: entry:30// RV64ZKNH-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sha512sum0(i64 [[RS1:%.*]])31// RV64ZKNH-NEXT: ret i64 [[TMP0]]32//33uint64_t sha512sum0(uint64_t rs1) {34 return __riscv_sha512sum0(rs1);35}36 37 38// RV64ZKNH-LABEL: @sha512sum1(39// RV64ZKNH-NEXT: entry:40// RV64ZKNH-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sha512sum1(i64 [[RS1:%.*]])41// RV64ZKNH-NEXT: ret i64 [[TMP0]]42//43uint64_t sha512sum1(uint64_t rs1) {44 return __riscv_sha512sum1(rs1);45}46 47 48// RV64ZKNH-LABEL: @sha256sig0(49// RV64ZKNH-NEXT: entry:50// RV64ZKNH-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.sha256sig0(i32 [[RS1:%.*]])51// RV64ZKNH-NEXT: ret i32 [[TMP0]]52//53uint32_t sha256sig0(uint32_t rs1) {54 return __riscv_sha256sig0(rs1);55}56 57// RV64ZKNH-LABEL: @sha256sig1(58// RV64ZKNH-NEXT: entry:59// RV64ZKNH-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.sha256sig1(i32 [[RS1:%.*]])60// RV64ZKNH-NEXT: ret i32 [[TMP0]]61//62uint32_t sha256sig1(uint32_t rs1) {63 return __riscv_sha256sig1(rs1);64}65 66 67// RV64ZKNH-LABEL: @sha256sum0(68// RV64ZKNH-NEXT: entry:69// RV64ZKNH-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.sha256sum0(i32 [[RS1:%.*]])70// RV64ZKNH-NEXT: ret i32 [[TMP0]]71//72uint32_t sha256sum0(uint32_t rs1) {73 return __riscv_sha256sum0(rs1);74}75 76// RV64ZKNH-LABEL: @sha256sum1(77// RV64ZKNH-NEXT: entry:78// RV64ZKNH-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.sha256sum1(i32 [[RS1:%.*]])79// RV64ZKNH-NEXT: ret i32 [[TMP0]]80//81uint32_t sha256sum1(uint32_t rs1) {82 return __riscv_sha256sum1(rs1);83}84