460 lines · c
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 22// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \4// RUN: -target-feature +zvfh -disable-O0-optnone \5// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \6// RUN: FileCheck --check-prefix=CHECK-RV64 %s7 8#include <riscv_vector.h>9 10// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmv_v_f_f16mf411// CHECK-RV64-SAME: (half noundef [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {12// CHECK-RV64-NEXT: entry:13// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16.i64(<vscale x 1 x half> poison, half [[SRC]], i64 [[VL]])14// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]15//16vfloat16mf4_t test_vfmv_v_f_f16mf4(_Float16 src, size_t vl) {17 return __riscv_vfmv_v_f_f16mf4(src, vl);18}19 20// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmv_v_f_f16mf221// CHECK-RV64-SAME: (half noundef [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {22// CHECK-RV64-NEXT: entry:23// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16.i64(<vscale x 2 x half> poison, half [[SRC]], i64 [[VL]])24// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]25//26vfloat16mf2_t test_vfmv_v_f_f16mf2(_Float16 src, size_t vl) {27 return __riscv_vfmv_v_f_f16mf2(src, vl);28}29 30// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmv_v_f_f16m131// CHECK-RV64-SAME: (half noundef [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {32// CHECK-RV64-NEXT: entry:33// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16.i64(<vscale x 4 x half> poison, half [[SRC]], i64 [[VL]])34// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]35//36vfloat16m1_t test_vfmv_v_f_f16m1(_Float16 src, size_t vl) {37 return __riscv_vfmv_v_f_f16m1(src, vl);38}39 40// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmv_v_f_f16m241// CHECK-RV64-SAME: (half noundef [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {42// CHECK-RV64-NEXT: entry:43// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16.i64(<vscale x 8 x half> poison, half [[SRC]], i64 [[VL]])44// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]45//46vfloat16m2_t test_vfmv_v_f_f16m2(_Float16 src, size_t vl) {47 return __riscv_vfmv_v_f_f16m2(src, vl);48}49 50// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmv_v_f_f16m451// CHECK-RV64-SAME: (half noundef [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {52// CHECK-RV64-NEXT: entry:53// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16.i64(<vscale x 16 x half> poison, half [[SRC]], i64 [[VL]])54// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]55//56vfloat16m4_t test_vfmv_v_f_f16m4(_Float16 src, size_t vl) {57 return __riscv_vfmv_v_f_f16m4(src, vl);58}59 60// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmv_v_f_f16m861// CHECK-RV64-SAME: (half noundef [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {62// CHECK-RV64-NEXT: entry:63// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16.i64(<vscale x 32 x half> poison, half [[SRC]], i64 [[VL]])64// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]65//66vfloat16m8_t test_vfmv_v_f_f16m8(_Float16 src, size_t vl) {67 return __riscv_vfmv_v_f_f16m8(src, vl);68}69 70// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmv_v_f_f32mf271// CHECK-RV64-SAME: (float noundef [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {72// CHECK-RV64-NEXT: entry:73// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32.i64(<vscale x 1 x float> poison, float [[SRC]], i64 [[VL]])74// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]75//76vfloat32mf2_t test_vfmv_v_f_f32mf2(float src, size_t vl) {77 return __riscv_vfmv_v_f_f32mf2(src, vl);78}79 80// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmv_v_f_f32m181// CHECK-RV64-SAME: (float noundef [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {82// CHECK-RV64-NEXT: entry:83// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.i64(<vscale x 2 x float> poison, float [[SRC]], i64 [[VL]])84// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]85//86vfloat32m1_t test_vfmv_v_f_f32m1(float src, size_t vl) {87 return __riscv_vfmv_v_f_f32m1(src, vl);88}89 90// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmv_v_f_f32m291// CHECK-RV64-SAME: (float noundef [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {92// CHECK-RV64-NEXT: entry:93// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmv.v.f.nxv4f32.i64(<vscale x 4 x float> poison, float [[SRC]], i64 [[VL]])94// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]95//96vfloat32m2_t test_vfmv_v_f_f32m2(float src, size_t vl) {97 return __riscv_vfmv_v_f_f32m2(src, vl);98}99 100// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmv_v_f_f32m4101// CHECK-RV64-SAME: (float noundef [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {102// CHECK-RV64-NEXT: entry:103// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmv.v.f.nxv8f32.i64(<vscale x 8 x float> poison, float [[SRC]], i64 [[VL]])104// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]105//106vfloat32m4_t test_vfmv_v_f_f32m4(float src, size_t vl) {107 return __riscv_vfmv_v_f_f32m4(src, vl);108}109 110// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmv_v_f_f32m8111// CHECK-RV64-SAME: (float noundef [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {112// CHECK-RV64-NEXT: entry:113// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmv.v.f.nxv16f32.i64(<vscale x 16 x float> poison, float [[SRC]], i64 [[VL]])114// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]115//116vfloat32m8_t test_vfmv_v_f_f32m8(float src, size_t vl) {117 return __riscv_vfmv_v_f_f32m8(src, vl);118}119 120// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmv_v_f_f64m1121// CHECK-RV64-SAME: (double noundef [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {122// CHECK-RV64-NEXT: entry:123// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64.i64(<vscale x 1 x double> poison, double [[SRC]], i64 [[VL]])124// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]125//126vfloat64m1_t test_vfmv_v_f_f64m1(double src, size_t vl) {127 return __riscv_vfmv_v_f_f64m1(src, vl);128}129 130// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmv_v_f_f64m2131// CHECK-RV64-SAME: (double noundef [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {132// CHECK-RV64-NEXT: entry:133// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmv.v.f.nxv2f64.i64(<vscale x 2 x double> poison, double [[SRC]], i64 [[VL]])134// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]135//136vfloat64m2_t test_vfmv_v_f_f64m2(double src, size_t vl) {137 return __riscv_vfmv_v_f_f64m2(src, vl);138}139 140// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmv_v_f_f64m4141// CHECK-RV64-SAME: (double noundef [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {142// CHECK-RV64-NEXT: entry:143// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmv.v.f.nxv4f64.i64(<vscale x 4 x double> poison, double [[SRC]], i64 [[VL]])144// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]145//146vfloat64m4_t test_vfmv_v_f_f64m4(double src, size_t vl) {147 return __riscv_vfmv_v_f_f64m4(src, vl);148}149 150// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmv_v_f_f64m8151// CHECK-RV64-SAME: (double noundef [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {152// CHECK-RV64-NEXT: entry:153// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmv.v.f.nxv8f64.i64(<vscale x 8 x double> poison, double [[SRC]], i64 [[VL]])154// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]155//156vfloat64m8_t test_vfmv_v_f_f64m8(double src, size_t vl) {157 return __riscv_vfmv_v_f_f64m8(src, vl);158}159 160// CHECK-RV64-LABEL: define dso_local half @test_vfmv_f_s_f16mf4_f16161// CHECK-RV64-SAME: (<vscale x 1 x half> [[SRC:%.*]]) #[[ATTR0]] {162// CHECK-RV64-NEXT: entry:163// CHECK-RV64-NEXT: [[TMP0:%.*]] = call half @llvm.riscv.vfmv.f.s.nxv1f16(<vscale x 1 x half> [[SRC]])164// CHECK-RV64-NEXT: ret half [[TMP0]]165//166_Float16 test_vfmv_f_s_f16mf4_f16(vfloat16mf4_t src) {167 return __riscv_vfmv_f_s_f16mf4_f16(src);168}169 170// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmv_s_f_f16mf4171// CHECK-RV64-SAME: (half noundef [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {172// CHECK-RV64-NEXT: entry:173// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmv.s.f.nxv1f16.i64(<vscale x 1 x half> poison, half [[SRC]], i64 [[VL]])174// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]175//176vfloat16mf4_t test_vfmv_s_f_f16mf4(_Float16 src, size_t vl) {177 return __riscv_vfmv_s_f_f16mf4(src, vl);178}179 180// CHECK-RV64-LABEL: define dso_local half @test_vfmv_f_s_f16mf2_f16181// CHECK-RV64-SAME: (<vscale x 2 x half> [[SRC:%.*]]) #[[ATTR0]] {182// CHECK-RV64-NEXT: entry:183// CHECK-RV64-NEXT: [[TMP0:%.*]] = call half @llvm.riscv.vfmv.f.s.nxv2f16(<vscale x 2 x half> [[SRC]])184// CHECK-RV64-NEXT: ret half [[TMP0]]185//186_Float16 test_vfmv_f_s_f16mf2_f16(vfloat16mf2_t src) {187 return __riscv_vfmv_f_s_f16mf2_f16(src);188}189 190// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmv_s_f_f16mf2191// CHECK-RV64-SAME: (half noundef [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {192// CHECK-RV64-NEXT: entry:193// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmv.s.f.nxv2f16.i64(<vscale x 2 x half> poison, half [[SRC]], i64 [[VL]])194// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]195//196vfloat16mf2_t test_vfmv_s_f_f16mf2(_Float16 src, size_t vl) {197 return __riscv_vfmv_s_f_f16mf2(src, vl);198}199 200// CHECK-RV64-LABEL: define dso_local half @test_vfmv_f_s_f16m1_f16201// CHECK-RV64-SAME: (<vscale x 4 x half> [[SRC:%.*]]) #[[ATTR0]] {202// CHECK-RV64-NEXT: entry:203// CHECK-RV64-NEXT: [[TMP0:%.*]] = call half @llvm.riscv.vfmv.f.s.nxv4f16(<vscale x 4 x half> [[SRC]])204// CHECK-RV64-NEXT: ret half [[TMP0]]205//206_Float16 test_vfmv_f_s_f16m1_f16(vfloat16m1_t src) {207 return __riscv_vfmv_f_s_f16m1_f16(src);208}209 210// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmv_s_f_f16m1211// CHECK-RV64-SAME: (half noundef [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {212// CHECK-RV64-NEXT: entry:213// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmv.s.f.nxv4f16.i64(<vscale x 4 x half> poison, half [[SRC]], i64 [[VL]])214// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]215//216vfloat16m1_t test_vfmv_s_f_f16m1(_Float16 src, size_t vl) {217 return __riscv_vfmv_s_f_f16m1(src, vl);218}219 220// CHECK-RV64-LABEL: define dso_local half @test_vfmv_f_s_f16m2_f16221// CHECK-RV64-SAME: (<vscale x 8 x half> [[SRC:%.*]]) #[[ATTR0]] {222// CHECK-RV64-NEXT: entry:223// CHECK-RV64-NEXT: [[TMP0:%.*]] = call half @llvm.riscv.vfmv.f.s.nxv8f16(<vscale x 8 x half> [[SRC]])224// CHECK-RV64-NEXT: ret half [[TMP0]]225//226_Float16 test_vfmv_f_s_f16m2_f16(vfloat16m2_t src) {227 return __riscv_vfmv_f_s_f16m2_f16(src);228}229 230// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmv_s_f_f16m2231// CHECK-RV64-SAME: (half noundef [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {232// CHECK-RV64-NEXT: entry:233// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmv.s.f.nxv8f16.i64(<vscale x 8 x half> poison, half [[SRC]], i64 [[VL]])234// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]235//236vfloat16m2_t test_vfmv_s_f_f16m2(_Float16 src, size_t vl) {237 return __riscv_vfmv_s_f_f16m2(src, vl);238}239 240// CHECK-RV64-LABEL: define dso_local half @test_vfmv_f_s_f16m4_f16241// CHECK-RV64-SAME: (<vscale x 16 x half> [[SRC:%.*]]) #[[ATTR0]] {242// CHECK-RV64-NEXT: entry:243// CHECK-RV64-NEXT: [[TMP0:%.*]] = call half @llvm.riscv.vfmv.f.s.nxv16f16(<vscale x 16 x half> [[SRC]])244// CHECK-RV64-NEXT: ret half [[TMP0]]245//246_Float16 test_vfmv_f_s_f16m4_f16(vfloat16m4_t src) {247 return __riscv_vfmv_f_s_f16m4_f16(src);248}249 250// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmv_s_f_f16m4251// CHECK-RV64-SAME: (half noundef [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {252// CHECK-RV64-NEXT: entry:253// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmv.s.f.nxv16f16.i64(<vscale x 16 x half> poison, half [[SRC]], i64 [[VL]])254// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]255//256vfloat16m4_t test_vfmv_s_f_f16m4(_Float16 src, size_t vl) {257 return __riscv_vfmv_s_f_f16m4(src, vl);258}259 260// CHECK-RV64-LABEL: define dso_local half @test_vfmv_f_s_f16m8_f16261// CHECK-RV64-SAME: (<vscale x 32 x half> [[SRC:%.*]]) #[[ATTR0]] {262// CHECK-RV64-NEXT: entry:263// CHECK-RV64-NEXT: [[TMP0:%.*]] = call half @llvm.riscv.vfmv.f.s.nxv32f16(<vscale x 32 x half> [[SRC]])264// CHECK-RV64-NEXT: ret half [[TMP0]]265//266_Float16 test_vfmv_f_s_f16m8_f16(vfloat16m8_t src) {267 return __riscv_vfmv_f_s_f16m8_f16(src);268}269 270// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmv_s_f_f16m8271// CHECK-RV64-SAME: (half noundef [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {272// CHECK-RV64-NEXT: entry:273// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmv.s.f.nxv32f16.i64(<vscale x 32 x half> poison, half [[SRC]], i64 [[VL]])274// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]275//276vfloat16m8_t test_vfmv_s_f_f16m8(_Float16 src, size_t vl) {277 return __riscv_vfmv_s_f_f16m8(src, vl);278}279 280// CHECK-RV64-LABEL: define dso_local float @test_vfmv_f_s_f32mf2_f32281// CHECK-RV64-SAME: (<vscale x 1 x float> [[SRC:%.*]]) #[[ATTR0]] {282// CHECK-RV64-NEXT: entry:283// CHECK-RV64-NEXT: [[TMP0:%.*]] = call float @llvm.riscv.vfmv.f.s.nxv1f32(<vscale x 1 x float> [[SRC]])284// CHECK-RV64-NEXT: ret float [[TMP0]]285//286float test_vfmv_f_s_f32mf2_f32(vfloat32mf2_t src) {287 return __riscv_vfmv_f_s_f32mf2_f32(src);288}289 290// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmv_s_f_f32mf2291// CHECK-RV64-SAME: (float noundef [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {292// CHECK-RV64-NEXT: entry:293// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmv.s.f.nxv1f32.i64(<vscale x 1 x float> poison, float [[SRC]], i64 [[VL]])294// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]295//296vfloat32mf2_t test_vfmv_s_f_f32mf2(float src, size_t vl) {297 return __riscv_vfmv_s_f_f32mf2(src, vl);298}299 300// CHECK-RV64-LABEL: define dso_local float @test_vfmv_f_s_f32m1_f32301// CHECK-RV64-SAME: (<vscale x 2 x float> [[SRC:%.*]]) #[[ATTR0]] {302// CHECK-RV64-NEXT: entry:303// CHECK-RV64-NEXT: [[TMP0:%.*]] = call float @llvm.riscv.vfmv.f.s.nxv2f32(<vscale x 2 x float> [[SRC]])304// CHECK-RV64-NEXT: ret float [[TMP0]]305//306float test_vfmv_f_s_f32m1_f32(vfloat32m1_t src) {307 return __riscv_vfmv_f_s_f32m1_f32(src);308}309 310// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmv_s_f_f32m1311// CHECK-RV64-SAME: (float noundef [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {312// CHECK-RV64-NEXT: entry:313// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmv.s.f.nxv2f32.i64(<vscale x 2 x float> poison, float [[SRC]], i64 [[VL]])314// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]315//316vfloat32m1_t test_vfmv_s_f_f32m1(float src, size_t vl) {317 return __riscv_vfmv_s_f_f32m1(src, vl);318}319 320// CHECK-RV64-LABEL: define dso_local float @test_vfmv_f_s_f32m2_f32321// CHECK-RV64-SAME: (<vscale x 4 x float> [[SRC:%.*]]) #[[ATTR0]] {322// CHECK-RV64-NEXT: entry:323// CHECK-RV64-NEXT: [[TMP0:%.*]] = call float @llvm.riscv.vfmv.f.s.nxv4f32(<vscale x 4 x float> [[SRC]])324// CHECK-RV64-NEXT: ret float [[TMP0]]325//326float test_vfmv_f_s_f32m2_f32(vfloat32m2_t src) {327 return __riscv_vfmv_f_s_f32m2_f32(src);328}329 330// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmv_s_f_f32m2331// CHECK-RV64-SAME: (float noundef [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {332// CHECK-RV64-NEXT: entry:333// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmv.s.f.nxv4f32.i64(<vscale x 4 x float> poison, float [[SRC]], i64 [[VL]])334// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]335//336vfloat32m2_t test_vfmv_s_f_f32m2(float src, size_t vl) {337 return __riscv_vfmv_s_f_f32m2(src, vl);338}339 340// CHECK-RV64-LABEL: define dso_local float @test_vfmv_f_s_f32m4_f32341// CHECK-RV64-SAME: (<vscale x 8 x float> [[SRC:%.*]]) #[[ATTR0]] {342// CHECK-RV64-NEXT: entry:343// CHECK-RV64-NEXT: [[TMP0:%.*]] = call float @llvm.riscv.vfmv.f.s.nxv8f32(<vscale x 8 x float> [[SRC]])344// CHECK-RV64-NEXT: ret float [[TMP0]]345//346float test_vfmv_f_s_f32m4_f32(vfloat32m4_t src) {347 return __riscv_vfmv_f_s_f32m4_f32(src);348}349 350// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmv_s_f_f32m4351// CHECK-RV64-SAME: (float noundef [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {352// CHECK-RV64-NEXT: entry:353// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmv.s.f.nxv8f32.i64(<vscale x 8 x float> poison, float [[SRC]], i64 [[VL]])354// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]355//356vfloat32m4_t test_vfmv_s_f_f32m4(float src, size_t vl) {357 return __riscv_vfmv_s_f_f32m4(src, vl);358}359 360// CHECK-RV64-LABEL: define dso_local float @test_vfmv_f_s_f32m8_f32361// CHECK-RV64-SAME: (<vscale x 16 x float> [[SRC:%.*]]) #[[ATTR0]] {362// CHECK-RV64-NEXT: entry:363// CHECK-RV64-NEXT: [[TMP0:%.*]] = call float @llvm.riscv.vfmv.f.s.nxv16f32(<vscale x 16 x float> [[SRC]])364// CHECK-RV64-NEXT: ret float [[TMP0]]365//366float test_vfmv_f_s_f32m8_f32(vfloat32m8_t src) {367 return __riscv_vfmv_f_s_f32m8_f32(src);368}369 370// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmv_s_f_f32m8371// CHECK-RV64-SAME: (float noundef [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {372// CHECK-RV64-NEXT: entry:373// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmv.s.f.nxv16f32.i64(<vscale x 16 x float> poison, float [[SRC]], i64 [[VL]])374// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]375//376vfloat32m8_t test_vfmv_s_f_f32m8(float src, size_t vl) {377 return __riscv_vfmv_s_f_f32m8(src, vl);378}379 380// CHECK-RV64-LABEL: define dso_local double @test_vfmv_f_s_f64m1_f64381// CHECK-RV64-SAME: (<vscale x 1 x double> [[SRC:%.*]]) #[[ATTR0]] {382// CHECK-RV64-NEXT: entry:383// CHECK-RV64-NEXT: [[TMP0:%.*]] = call double @llvm.riscv.vfmv.f.s.nxv1f64(<vscale x 1 x double> [[SRC]])384// CHECK-RV64-NEXT: ret double [[TMP0]]385//386double test_vfmv_f_s_f64m1_f64(vfloat64m1_t src) {387 return __riscv_vfmv_f_s_f64m1_f64(src);388}389 390// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmv_s_f_f64m1391// CHECK-RV64-SAME: (double noundef [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {392// CHECK-RV64-NEXT: entry:393// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmv.s.f.nxv1f64.i64(<vscale x 1 x double> poison, double [[SRC]], i64 [[VL]])394// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]395//396vfloat64m1_t test_vfmv_s_f_f64m1(double src, size_t vl) {397 return __riscv_vfmv_s_f_f64m1(src, vl);398}399 400// CHECK-RV64-LABEL: define dso_local double @test_vfmv_f_s_f64m2_f64401// CHECK-RV64-SAME: (<vscale x 2 x double> [[SRC:%.*]]) #[[ATTR0]] {402// CHECK-RV64-NEXT: entry:403// CHECK-RV64-NEXT: [[TMP0:%.*]] = call double @llvm.riscv.vfmv.f.s.nxv2f64(<vscale x 2 x double> [[SRC]])404// CHECK-RV64-NEXT: ret double [[TMP0]]405//406double test_vfmv_f_s_f64m2_f64(vfloat64m2_t src) {407 return __riscv_vfmv_f_s_f64m2_f64(src);408}409 410// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmv_s_f_f64m2411// CHECK-RV64-SAME: (double noundef [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {412// CHECK-RV64-NEXT: entry:413// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmv.s.f.nxv2f64.i64(<vscale x 2 x double> poison, double [[SRC]], i64 [[VL]])414// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]415//416vfloat64m2_t test_vfmv_s_f_f64m2(double src, size_t vl) {417 return __riscv_vfmv_s_f_f64m2(src, vl);418}419 420// CHECK-RV64-LABEL: define dso_local double @test_vfmv_f_s_f64m4_f64421// CHECK-RV64-SAME: (<vscale x 4 x double> [[SRC:%.*]]) #[[ATTR0]] {422// CHECK-RV64-NEXT: entry:423// CHECK-RV64-NEXT: [[TMP0:%.*]] = call double @llvm.riscv.vfmv.f.s.nxv4f64(<vscale x 4 x double> [[SRC]])424// CHECK-RV64-NEXT: ret double [[TMP0]]425//426double test_vfmv_f_s_f64m4_f64(vfloat64m4_t src) {427 return __riscv_vfmv_f_s_f64m4_f64(src);428}429 430// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmv_s_f_f64m4431// CHECK-RV64-SAME: (double noundef [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {432// CHECK-RV64-NEXT: entry:433// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmv.s.f.nxv4f64.i64(<vscale x 4 x double> poison, double [[SRC]], i64 [[VL]])434// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]435//436vfloat64m4_t test_vfmv_s_f_f64m4(double src, size_t vl) {437 return __riscv_vfmv_s_f_f64m4(src, vl);438}439 440// CHECK-RV64-LABEL: define dso_local double @test_vfmv_f_s_f64m8_f64441// CHECK-RV64-SAME: (<vscale x 8 x double> [[SRC:%.*]]) #[[ATTR0]] {442// CHECK-RV64-NEXT: entry:443// CHECK-RV64-NEXT: [[TMP0:%.*]] = call double @llvm.riscv.vfmv.f.s.nxv8f64(<vscale x 8 x double> [[SRC]])444// CHECK-RV64-NEXT: ret double [[TMP0]]445//446double test_vfmv_f_s_f64m8_f64(vfloat64m8_t src) {447 return __riscv_vfmv_f_s_f64m8_f64(src);448}449 450// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmv_s_f_f64m8451// CHECK-RV64-SAME: (double noundef [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {452// CHECK-RV64-NEXT: entry:453// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmv.s.f.nxv8f64.i64(<vscale x 8 x double> poison, double [[SRC]], i64 [[VL]])454// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]455//456vfloat64m8_t test_vfmv_s_f_f64m8(double src, size_t vl) {457 return __riscv_vfmv_s_f_f64m8(src, vl);458}459 460