brintos / llvm-project-archived public Read only

1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 22// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \4// RUN:   -target-feature +zvfh -disable-O0-optnone  \5// RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \6// RUN:   FileCheck --check-prefix=CHECK-RV64 %s7 8#include <riscv_vector.h>9 10// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_i8mf811// CHECK-RV64-SAME: (<vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {12// CHECK-RV64-NEXT:  entry:13// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> poison, <vscale x 1 x half> [[SRC]], i64 7, i64 [[VL]])14// CHECK-RV64-NEXT:    ret <vscale x 1 x i8> [[TMP0]]15//16vint8mf8_t test_vfncvt_x_f_w_i8mf8(vfloat16mf4_t src, size_t vl) {17  return __riscv_vfncvt_x_f_w_i8mf8(src, vl);18}19 20// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vfncvt_x_f_w_i8mf421// CHECK-RV64-SAME: (<vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {22// CHECK-RV64-NEXT:  entry:23// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> poison, <vscale x 2 x half> [[SRC]], i64 7, i64 [[VL]])24// CHECK-RV64-NEXT:    ret <vscale x 2 x i8> [[TMP0]]25//26vint8mf4_t test_vfncvt_x_f_w_i8mf4(vfloat16mf2_t src, size_t vl) {27  return __riscv_vfncvt_x_f_w_i8mf4(src, vl);28}29 30// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vfncvt_x_f_w_i8mf231// CHECK-RV64-SAME: (<vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {32// CHECK-RV64-NEXT:  entry:33// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> poison, <vscale x 4 x half> [[SRC]], i64 7, i64 [[VL]])34// CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[TMP0]]35//36vint8mf2_t test_vfncvt_x_f_w_i8mf2(vfloat16m1_t src, size_t vl) {37  return __riscv_vfncvt_x_f_w_i8mf2(src, vl);38}39 40// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vfncvt_x_f_w_i8m141// CHECK-RV64-SAME: (<vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {42// CHECK-RV64-NEXT:  entry:43// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> poison, <vscale x 8 x half> [[SRC]], i64 7, i64 [[VL]])44// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]45//46vint8m1_t test_vfncvt_x_f_w_i8m1(vfloat16m2_t src, size_t vl) {47  return __riscv_vfncvt_x_f_w_i8m1(src, vl);48}49 50// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vfncvt_x_f_w_i8m251// CHECK-RV64-SAME: (<vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {52// CHECK-RV64-NEXT:  entry:53// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> poison, <vscale x 16 x half> [[SRC]], i64 7, i64 [[VL]])54// CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]55//56vint8m2_t test_vfncvt_x_f_w_i8m2(vfloat16m4_t src, size_t vl) {57  return __riscv_vfncvt_x_f_w_i8m2(src, vl);58}59 60// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vfncvt_x_f_w_i8m461// CHECK-RV64-SAME: (<vscale x 32 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {62// CHECK-RV64-NEXT:  entry:63// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> poison, <vscale x 32 x half> [[SRC]], i64 7, i64 [[VL]])64// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]65//66vint8m4_t test_vfncvt_x_f_w_i8m4(vfloat16m8_t src, size_t vl) {67  return __riscv_vfncvt_x_f_w_i8m4(src, vl);68}69 70// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vfncvt_xu_f_w_u8mf871// CHECK-RV64-SAME: (<vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {72// CHECK-RV64-NEXT:  entry:73// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> poison, <vscale x 1 x half> [[SRC]], i64 7, i64 [[VL]])74// CHECK-RV64-NEXT:    ret <vscale x 1 x i8> [[TMP0]]75//76vuint8mf8_t test_vfncvt_xu_f_w_u8mf8(vfloat16mf4_t src, size_t vl) {77  return __riscv_vfncvt_xu_f_w_u8mf8(src, vl);78}79 80// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vfncvt_xu_f_w_u8mf481// CHECK-RV64-SAME: (<vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {82// CHECK-RV64-NEXT:  entry:83// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> poison, <vscale x 2 x half> [[SRC]], i64 7, i64 [[VL]])84// CHECK-RV64-NEXT:    ret <vscale x 2 x i8> [[TMP0]]85//86vuint8mf4_t test_vfncvt_xu_f_w_u8mf4(vfloat16mf2_t src, size_t vl) {87  return __riscv_vfncvt_xu_f_w_u8mf4(src, vl);88}89 90// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vfncvt_xu_f_w_u8mf291// CHECK-RV64-SAME: (<vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {92// CHECK-RV64-NEXT:  entry:93// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> poison, <vscale x 4 x half> [[SRC]], i64 7, i64 [[VL]])94// CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[TMP0]]95//96vuint8mf2_t test_vfncvt_xu_f_w_u8mf2(vfloat16m1_t src, size_t vl) {97  return __riscv_vfncvt_xu_f_w_u8mf2(src, vl);98}99 100// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vfncvt_xu_f_w_u8m1101// CHECK-RV64-SAME: (<vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {102// CHECK-RV64-NEXT:  entry:103// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> poison, <vscale x 8 x half> [[SRC]], i64 7, i64 [[VL]])104// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]105//106vuint8m1_t test_vfncvt_xu_f_w_u8m1(vfloat16m2_t src, size_t vl) {107  return __riscv_vfncvt_xu_f_w_u8m1(src, vl);108}109 110// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vfncvt_xu_f_w_u8m2111// CHECK-RV64-SAME: (<vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {112// CHECK-RV64-NEXT:  entry:113// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> poison, <vscale x 16 x half> [[SRC]], i64 7, i64 [[VL]])114// CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]115//116vuint8m2_t test_vfncvt_xu_f_w_u8m2(vfloat16m4_t src, size_t vl) {117  return __riscv_vfncvt_xu_f_w_u8m2(src, vl);118}119 120// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vfncvt_xu_f_w_u8m4121// CHECK-RV64-SAME: (<vscale x 32 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {122// CHECK-RV64-NEXT:  entry:123// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> poison, <vscale x 32 x half> [[SRC]], i64 7, i64 [[VL]])124// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]125//126vuint8m4_t test_vfncvt_xu_f_w_u8m4(vfloat16m8_t src, size_t vl) {127  return __riscv_vfncvt_xu_f_w_u8m4(src, vl);128}129 130// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vfncvt_x_f_w_i16mf4131// CHECK-RV64-SAME: (<vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {132// CHECK-RV64-NEXT:  entry:133// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfncvt.x.f.w.nxv1i16.nxv1f32.i64(<vscale x 1 x i16> poison, <vscale x 1 x float> [[SRC]], i64 7, i64 [[VL]])134// CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]135//136vint16mf4_t test_vfncvt_x_f_w_i16mf4(vfloat32mf2_t src, size_t vl) {137  return __riscv_vfncvt_x_f_w_i16mf4(src, vl);138}139 140// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vfncvt_x_f_w_i16mf2141// CHECK-RV64-SAME: (<vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {142// CHECK-RV64-NEXT:  entry:143// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfncvt.x.f.w.nxv2i16.nxv2f32.i64(<vscale x 2 x i16> poison, <vscale x 2 x float> [[SRC]], i64 7, i64 [[VL]])144// CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]145//146vint16mf2_t test_vfncvt_x_f_w_i16mf2(vfloat32m1_t src, size_t vl) {147  return __riscv_vfncvt_x_f_w_i16mf2(src, vl);148}149 150// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfncvt_x_f_w_i16m1151// CHECK-RV64-SAME: (<vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {152// CHECK-RV64-NEXT:  entry:153// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfncvt.x.f.w.nxv4i16.nxv4f32.i64(<vscale x 4 x i16> poison, <vscale x 4 x float> [[SRC]], i64 7, i64 [[VL]])154// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]155//156vint16m1_t test_vfncvt_x_f_w_i16m1(vfloat32m2_t src, size_t vl) {157  return __riscv_vfncvt_x_f_w_i16m1(src, vl);158}159 160// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfncvt_x_f_w_i16m2161// CHECK-RV64-SAME: (<vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {162// CHECK-RV64-NEXT:  entry:163// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfncvt.x.f.w.nxv8i16.nxv8f32.i64(<vscale x 8 x i16> poison, <vscale x 8 x float> [[SRC]], i64 7, i64 [[VL]])164// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]165//166vint16m2_t test_vfncvt_x_f_w_i16m2(vfloat32m4_t src, size_t vl) {167  return __riscv_vfncvt_x_f_w_i16m2(src, vl);168}169 170// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfncvt_x_f_w_i16m4171// CHECK-RV64-SAME: (<vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {172// CHECK-RV64-NEXT:  entry:173// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfncvt.x.f.w.nxv16i16.nxv16f32.i64(<vscale x 16 x i16> poison, <vscale x 16 x float> [[SRC]], i64 7, i64 [[VL]])174// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]175//176vint16m4_t test_vfncvt_x_f_w_i16m4(vfloat32m8_t src, size_t vl) {177  return __riscv_vfncvt_x_f_w_i16m4(src, vl);178}179 180// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vfncvt_xu_f_w_u16mf4181// CHECK-RV64-SAME: (<vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {182// CHECK-RV64-NEXT:  entry:183// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv1i16.nxv1f32.i64(<vscale x 1 x i16> poison, <vscale x 1 x float> [[SRC]], i64 7, i64 [[VL]])184// CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]185//186vuint16mf4_t test_vfncvt_xu_f_w_u16mf4(vfloat32mf2_t src, size_t vl) {187  return __riscv_vfncvt_xu_f_w_u16mf4(src, vl);188}189 190// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vfncvt_xu_f_w_u16mf2191// CHECK-RV64-SAME: (<vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {192// CHECK-RV64-NEXT:  entry:193// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv2i16.nxv2f32.i64(<vscale x 2 x i16> poison, <vscale x 2 x float> [[SRC]], i64 7, i64 [[VL]])194// CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]195//196vuint16mf2_t test_vfncvt_xu_f_w_u16mf2(vfloat32m1_t src, size_t vl) {197  return __riscv_vfncvt_xu_f_w_u16mf2(src, vl);198}199 200// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfncvt_xu_f_w_u16m1201// CHECK-RV64-SAME: (<vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {202// CHECK-RV64-NEXT:  entry:203// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv4i16.nxv4f32.i64(<vscale x 4 x i16> poison, <vscale x 4 x float> [[SRC]], i64 7, i64 [[VL]])204// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]205//206vuint16m1_t test_vfncvt_xu_f_w_u16m1(vfloat32m2_t src, size_t vl) {207  return __riscv_vfncvt_xu_f_w_u16m1(src, vl);208}209 210// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfncvt_xu_f_w_u16m2211// CHECK-RV64-SAME: (<vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {212// CHECK-RV64-NEXT:  entry:213// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv8i16.nxv8f32.i64(<vscale x 8 x i16> poison, <vscale x 8 x float> [[SRC]], i64 7, i64 [[VL]])214// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]215//216vuint16m2_t test_vfncvt_xu_f_w_u16m2(vfloat32m4_t src, size_t vl) {217  return __riscv_vfncvt_xu_f_w_u16m2(src, vl);218}219 220// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfncvt_xu_f_w_u16m4221// CHECK-RV64-SAME: (<vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {222// CHECK-RV64-NEXT:  entry:223// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv16i16.nxv16f32.i64(<vscale x 16 x i16> poison, <vscale x 16 x float> [[SRC]], i64 7, i64 [[VL]])224// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]225//226vuint16m4_t test_vfncvt_xu_f_w_u16m4(vfloat32m8_t src, size_t vl) {227  return __riscv_vfncvt_xu_f_w_u16m4(src, vl);228}229 230// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfncvt_f_x_w_f16mf4231// CHECK-RV64-SAME: (<vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {232// CHECK-RV64-NEXT:  entry:233// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.x.w.nxv1f16.nxv1i32.i64(<vscale x 1 x half> poison, <vscale x 1 x i32> [[SRC]], i64 7, i64 [[VL]])234// CHECK-RV64-NEXT:    ret <vscale x 1 x half> [[TMP0]]235//236vfloat16mf4_t test_vfncvt_f_x_w_f16mf4(vint32mf2_t src, size_t vl) {237  return __riscv_vfncvt_f_x_w_f16mf4(src, vl);238}239 240// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfncvt_f_x_w_f16mf2241// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {242// CHECK-RV64-NEXT:  entry:243// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.x.w.nxv2f16.nxv2i32.i64(<vscale x 2 x half> poison, <vscale x 2 x i32> [[SRC]], i64 7, i64 [[VL]])244// CHECK-RV64-NEXT:    ret <vscale x 2 x half> [[TMP0]]245//246vfloat16mf2_t test_vfncvt_f_x_w_f16mf2(vint32m1_t src, size_t vl) {247  return __riscv_vfncvt_f_x_w_f16mf2(src, vl);248}249 250// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfncvt_f_x_w_f16m1251// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {252// CHECK-RV64-NEXT:  entry:253// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.x.w.nxv4f16.nxv4i32.i64(<vscale x 4 x half> poison, <vscale x 4 x i32> [[SRC]], i64 7, i64 [[VL]])254// CHECK-RV64-NEXT:    ret <vscale x 4 x half> [[TMP0]]255//256vfloat16m1_t test_vfncvt_f_x_w_f16m1(vint32m2_t src, size_t vl) {257  return __riscv_vfncvt_f_x_w_f16m1(src, vl);258}259 260// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfncvt_f_x_w_f16m2261// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {262// CHECK-RV64-NEXT:  entry:263// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.x.w.nxv8f16.nxv8i32.i64(<vscale x 8 x half> poison, <vscale x 8 x i32> [[SRC]], i64 7, i64 [[VL]])264// CHECK-RV64-NEXT:    ret <vscale x 8 x half> [[TMP0]]265//266vfloat16m2_t test_vfncvt_f_x_w_f16m2(vint32m4_t src, size_t vl) {267  return __riscv_vfncvt_f_x_w_f16m2(src, vl);268}269 270// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfncvt_f_x_w_f16m4271// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {272// CHECK-RV64-NEXT:  entry:273// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.x.w.nxv16f16.nxv16i32.i64(<vscale x 16 x half> poison, <vscale x 16 x i32> [[SRC]], i64 7, i64 [[VL]])274// CHECK-RV64-NEXT:    ret <vscale x 16 x half> [[TMP0]]275//276vfloat16m4_t test_vfncvt_f_x_w_f16m4(vint32m8_t src, size_t vl) {277  return __riscv_vfncvt_f_x_w_f16m4(src, vl);278}279 280// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfncvt_f_xu_w_f16mf4281// CHECK-RV64-SAME: (<vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {282// CHECK-RV64-NEXT:  entry:283// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.xu.w.nxv1f16.nxv1i32.i64(<vscale x 1 x half> poison, <vscale x 1 x i32> [[SRC]], i64 7, i64 [[VL]])284// CHECK-RV64-NEXT:    ret <vscale x 1 x half> [[TMP0]]285//286vfloat16mf4_t test_vfncvt_f_xu_w_f16mf4(vuint32mf2_t src, size_t vl) {287  return __riscv_vfncvt_f_xu_w_f16mf4(src, vl);288}289 290// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfncvt_f_xu_w_f16mf2291// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {292// CHECK-RV64-NEXT:  entry:293// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.xu.w.nxv2f16.nxv2i32.i64(<vscale x 2 x half> poison, <vscale x 2 x i32> [[SRC]], i64 7, i64 [[VL]])294// CHECK-RV64-NEXT:    ret <vscale x 2 x half> [[TMP0]]295//296vfloat16mf2_t test_vfncvt_f_xu_w_f16mf2(vuint32m1_t src, size_t vl) {297  return __riscv_vfncvt_f_xu_w_f16mf2(src, vl);298}299 300// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfncvt_f_xu_w_f16m1301// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {302// CHECK-RV64-NEXT:  entry:303// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.xu.w.nxv4f16.nxv4i32.i64(<vscale x 4 x half> poison, <vscale x 4 x i32> [[SRC]], i64 7, i64 [[VL]])304// CHECK-RV64-NEXT:    ret <vscale x 4 x half> [[TMP0]]305//306vfloat16m1_t test_vfncvt_f_xu_w_f16m1(vuint32m2_t src, size_t vl) {307  return __riscv_vfncvt_f_xu_w_f16m1(src, vl);308}309 310// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfncvt_f_xu_w_f16m2311// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {312// CHECK-RV64-NEXT:  entry:313// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.xu.w.nxv8f16.nxv8i32.i64(<vscale x 8 x half> poison, <vscale x 8 x i32> [[SRC]], i64 7, i64 [[VL]])314// CHECK-RV64-NEXT:    ret <vscale x 8 x half> [[TMP0]]315//316vfloat16m2_t test_vfncvt_f_xu_w_f16m2(vuint32m4_t src, size_t vl) {317  return __riscv_vfncvt_f_xu_w_f16m2(src, vl);318}319 320// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfncvt_f_xu_w_f16m4321// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {322// CHECK-RV64-NEXT:  entry:323// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.xu.w.nxv16f16.nxv16i32.i64(<vscale x 16 x half> poison, <vscale x 16 x i32> [[SRC]], i64 7, i64 [[VL]])324// CHECK-RV64-NEXT:    ret <vscale x 16 x half> [[TMP0]]325//326vfloat16m4_t test_vfncvt_f_xu_w_f16m4(vuint32m8_t src, size_t vl) {327  return __riscv_vfncvt_f_xu_w_f16m4(src, vl);328}329 330 331// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfncvt_x_f_w_i32mf2332// CHECK-RV64-SAME: (<vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {333// CHECK-RV64-NEXT:  entry:334// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfncvt.x.f.w.nxv1i32.nxv1f64.i64(<vscale x 1 x i32> poison, <vscale x 1 x double> [[SRC]], i64 7, i64 [[VL]])335// CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]336//337vint32mf2_t test_vfncvt_x_f_w_i32mf2(vfloat64m1_t src, size_t vl) {338  return __riscv_vfncvt_x_f_w_i32mf2(src, vl);339}340 341// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfncvt_x_f_w_i32m1342// CHECK-RV64-SAME: (<vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {343// CHECK-RV64-NEXT:  entry:344// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfncvt.x.f.w.nxv2i32.nxv2f64.i64(<vscale x 2 x i32> poison, <vscale x 2 x double> [[SRC]], i64 7, i64 [[VL]])345// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]346//347vint32m1_t test_vfncvt_x_f_w_i32m1(vfloat64m2_t src, size_t vl) {348  return __riscv_vfncvt_x_f_w_i32m1(src, vl);349}350 351// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfncvt_x_f_w_i32m2352// CHECK-RV64-SAME: (<vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {353// CHECK-RV64-NEXT:  entry:354// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfncvt.x.f.w.nxv4i32.nxv4f64.i64(<vscale x 4 x i32> poison, <vscale x 4 x double> [[SRC]], i64 7, i64 [[VL]])355// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]356//357vint32m2_t test_vfncvt_x_f_w_i32m2(vfloat64m4_t src, size_t vl) {358  return __riscv_vfncvt_x_f_w_i32m2(src, vl);359}360 361// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfncvt_x_f_w_i32m4362// CHECK-RV64-SAME: (<vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {363// CHECK-RV64-NEXT:  entry:364// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfncvt.x.f.w.nxv8i32.nxv8f64.i64(<vscale x 8 x i32> poison, <vscale x 8 x double> [[SRC]], i64 7, i64 [[VL]])365// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]366//367vint32m4_t test_vfncvt_x_f_w_i32m4(vfloat64m8_t src, size_t vl) {368  return __riscv_vfncvt_x_f_w_i32m4(src, vl);369}370 371// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfncvt_xu_f_w_u32mf2372// CHECK-RV64-SAME: (<vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {373// CHECK-RV64-NEXT:  entry:374// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv1i32.nxv1f64.i64(<vscale x 1 x i32> poison, <vscale x 1 x double> [[SRC]], i64 7, i64 [[VL]])375// CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]376//377vuint32mf2_t test_vfncvt_xu_f_w_u32mf2(vfloat64m1_t src, size_t vl) {378  return __riscv_vfncvt_xu_f_w_u32mf2(src, vl);379}380 381// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfncvt_xu_f_w_u32m1382// CHECK-RV64-SAME: (<vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {383// CHECK-RV64-NEXT:  entry:384// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv2i32.nxv2f64.i64(<vscale x 2 x i32> poison, <vscale x 2 x double> [[SRC]], i64 7, i64 [[VL]])385// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]386//387vuint32m1_t test_vfncvt_xu_f_w_u32m1(vfloat64m2_t src, size_t vl) {388  return __riscv_vfncvt_xu_f_w_u32m1(src, vl);389}390 391// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfncvt_xu_f_w_u32m2392// CHECK-RV64-SAME: (<vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {393// CHECK-RV64-NEXT:  entry:394// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv4i32.nxv4f64.i64(<vscale x 4 x i32> poison, <vscale x 4 x double> [[SRC]], i64 7, i64 [[VL]])395// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]396//397vuint32m2_t test_vfncvt_xu_f_w_u32m2(vfloat64m4_t src, size_t vl) {398  return __riscv_vfncvt_xu_f_w_u32m2(src, vl);399}400 401// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfncvt_xu_f_w_u32m4402// CHECK-RV64-SAME: (<vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {403// CHECK-RV64-NEXT:  entry:404// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv8i32.nxv8f64.i64(<vscale x 8 x i32> poison, <vscale x 8 x double> [[SRC]], i64 7, i64 [[VL]])405// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]406//407vuint32m4_t test_vfncvt_xu_f_w_u32m4(vfloat64m8_t src, size_t vl) {408  return __riscv_vfncvt_xu_f_w_u32m4(src, vl);409}410 411// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfncvt_f_x_w_f32mf2412// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {413// CHECK-RV64-NEXT:  entry:414// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.x.w.nxv1f32.nxv1i64.i64(<vscale x 1 x float> poison, <vscale x 1 x i64> [[SRC]], i64 7, i64 [[VL]])415// CHECK-RV64-NEXT:    ret <vscale x 1 x float> [[TMP0]]416//417vfloat32mf2_t test_vfncvt_f_x_w_f32mf2(vint64m1_t src, size_t vl) {418  return __riscv_vfncvt_f_x_w_f32mf2(src, vl);419}420 421// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfncvt_f_x_w_f32m1422// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {423// CHECK-RV64-NEXT:  entry:424// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.x.w.nxv2f32.nxv2i64.i64(<vscale x 2 x float> poison, <vscale x 2 x i64> [[SRC]], i64 7, i64 [[VL]])425// CHECK-RV64-NEXT:    ret <vscale x 2 x float> [[TMP0]]426//427vfloat32m1_t test_vfncvt_f_x_w_f32m1(vint64m2_t src, size_t vl) {428  return __riscv_vfncvt_f_x_w_f32m1(src, vl);429}430 431// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfncvt_f_x_w_f32m2432// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {433// CHECK-RV64-NEXT:  entry:434// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.x.w.nxv4f32.nxv4i64.i64(<vscale x 4 x float> poison, <vscale x 4 x i64> [[SRC]], i64 7, i64 [[VL]])435// CHECK-RV64-NEXT:    ret <vscale x 4 x float> [[TMP0]]436//437vfloat32m2_t test_vfncvt_f_x_w_f32m2(vint64m4_t src, size_t vl) {438  return __riscv_vfncvt_f_x_w_f32m2(src, vl);439}440 441// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfncvt_f_x_w_f32m4442// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {443// CHECK-RV64-NEXT:  entry:444// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.x.w.nxv8f32.nxv8i64.i64(<vscale x 8 x float> poison, <vscale x 8 x i64> [[SRC]], i64 7, i64 [[VL]])445// CHECK-RV64-NEXT:    ret <vscale x 8 x float> [[TMP0]]446//447vfloat32m4_t test_vfncvt_f_x_w_f32m4(vint64m8_t src, size_t vl) {448  return __riscv_vfncvt_f_x_w_f32m4(src, vl);449}450 451// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfncvt_f_xu_w_f32mf2452// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {453// CHECK-RV64-NEXT:  entry:454// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.xu.w.nxv1f32.nxv1i64.i64(<vscale x 1 x float> poison, <vscale x 1 x i64> [[SRC]], i64 7, i64 [[VL]])455// CHECK-RV64-NEXT:    ret <vscale x 1 x float> [[TMP0]]456//457vfloat32mf2_t test_vfncvt_f_xu_w_f32mf2(vuint64m1_t src, size_t vl) {458  return __riscv_vfncvt_f_xu_w_f32mf2(src, vl);459}460 461// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfncvt_f_xu_w_f32m1462// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {463// CHECK-RV64-NEXT:  entry:464// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.xu.w.nxv2f32.nxv2i64.i64(<vscale x 2 x float> poison, <vscale x 2 x i64> [[SRC]], i64 7, i64 [[VL]])465// CHECK-RV64-NEXT:    ret <vscale x 2 x float> [[TMP0]]466//467vfloat32m1_t test_vfncvt_f_xu_w_f32m1(vuint64m2_t src, size_t vl) {468  return __riscv_vfncvt_f_xu_w_f32m1(src, vl);469}470 471// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfncvt_f_xu_w_f32m2472// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {473// CHECK-RV64-NEXT:  entry:474// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.xu.w.nxv4f32.nxv4i64.i64(<vscale x 4 x float> poison, <vscale x 4 x i64> [[SRC]], i64 7, i64 [[VL]])475// CHECK-RV64-NEXT:    ret <vscale x 4 x float> [[TMP0]]476//477vfloat32m2_t test_vfncvt_f_xu_w_f32m2(vuint64m4_t src, size_t vl) {478  return __riscv_vfncvt_f_xu_w_f32m2(src, vl);479}480 481// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfncvt_f_xu_w_f32m4482// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {483// CHECK-RV64-NEXT:  entry:484// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.xu.w.nxv8f32.nxv8i64.i64(<vscale x 8 x float> poison, <vscale x 8 x i64> [[SRC]], i64 7, i64 [[VL]])485// CHECK-RV64-NEXT:    ret <vscale x 8 x float> [[TMP0]]486//487vfloat32m4_t test_vfncvt_f_xu_w_f32m4(vuint64m8_t src, size_t vl) {488  return __riscv_vfncvt_f_xu_w_f32m4(src, vl);489}490 491// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_i8mf8_m492// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {493// CHECK-RV64-NEXT:  entry:494// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> poison, <vscale x 1 x half> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)495// CHECK-RV64-NEXT:    ret <vscale x 1 x i8> [[TMP0]]496//497vint8mf8_t test_vfncvt_x_f_w_i8mf8_m(vbool64_t mask, vfloat16mf4_t src, size_t vl) {498  return __riscv_vfncvt_x_f_w_i8mf8_m(mask, src, vl);499}500 501// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vfncvt_x_f_w_i8mf4_m502// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {503// CHECK-RV64-NEXT:  entry:504// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> poison, <vscale x 2 x half> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)505// CHECK-RV64-NEXT:    ret <vscale x 2 x i8> [[TMP0]]506//507vint8mf4_t test_vfncvt_x_f_w_i8mf4_m(vbool32_t mask, vfloat16mf2_t src, size_t vl) {508  return __riscv_vfncvt_x_f_w_i8mf4_m(mask, src, vl);509}510 511// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vfncvt_x_f_w_i8mf2_m512// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {513// CHECK-RV64-NEXT:  entry:514// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> poison, <vscale x 4 x half> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)515// CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[TMP0]]516//517vint8mf2_t test_vfncvt_x_f_w_i8mf2_m(vbool16_t mask, vfloat16m1_t src, size_t vl) {518  return __riscv_vfncvt_x_f_w_i8mf2_m(mask, src, vl);519}520 521// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vfncvt_x_f_w_i8m1_m522// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {523// CHECK-RV64-NEXT:  entry:524// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> poison, <vscale x 8 x half> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)525// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]526//527vint8m1_t test_vfncvt_x_f_w_i8m1_m(vbool8_t mask, vfloat16m2_t src, size_t vl) {528  return __riscv_vfncvt_x_f_w_i8m1_m(mask, src, vl);529}530 531// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vfncvt_x_f_w_i8m2_m532// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {533// CHECK-RV64-NEXT:  entry:534// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> poison, <vscale x 16 x half> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)535// CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]536//537vint8m2_t test_vfncvt_x_f_w_i8m2_m(vbool4_t mask, vfloat16m4_t src, size_t vl) {538  return __riscv_vfncvt_x_f_w_i8m2_m(mask, src, vl);539}540 541// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vfncvt_x_f_w_i8m4_m542// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {543// CHECK-RV64-NEXT:  entry:544// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> poison, <vscale x 32 x half> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)545// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]546//547vint8m4_t test_vfncvt_x_f_w_i8m4_m(vbool2_t mask, vfloat16m8_t src, size_t vl) {548  return __riscv_vfncvt_x_f_w_i8m4_m(mask, src, vl);549}550 551// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vfncvt_xu_f_w_u8mf8_m552// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {553// CHECK-RV64-NEXT:  entry:554// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> poison, <vscale x 1 x half> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)555// CHECK-RV64-NEXT:    ret <vscale x 1 x i8> [[TMP0]]556//557vuint8mf8_t test_vfncvt_xu_f_w_u8mf8_m(vbool64_t mask, vfloat16mf4_t src, size_t vl) {558  return __riscv_vfncvt_xu_f_w_u8mf8_m(mask, src, vl);559}560 561// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vfncvt_xu_f_w_u8mf4_m562// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {563// CHECK-RV64-NEXT:  entry:564// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> poison, <vscale x 2 x half> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)565// CHECK-RV64-NEXT:    ret <vscale x 2 x i8> [[TMP0]]566//567vuint8mf4_t test_vfncvt_xu_f_w_u8mf4_m(vbool32_t mask, vfloat16mf2_t src, size_t vl) {568  return __riscv_vfncvt_xu_f_w_u8mf4_m(mask, src, vl);569}570 571// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vfncvt_xu_f_w_u8mf2_m572// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {573// CHECK-RV64-NEXT:  entry:574// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> poison, <vscale x 4 x half> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)575// CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[TMP0]]576//577vuint8mf2_t test_vfncvt_xu_f_w_u8mf2_m(vbool16_t mask, vfloat16m1_t src, size_t vl) {578  return __riscv_vfncvt_xu_f_w_u8mf2_m(mask, src, vl);579}580 581// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vfncvt_xu_f_w_u8m1_m582// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {583// CHECK-RV64-NEXT:  entry:584// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> poison, <vscale x 8 x half> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)585// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]586//587vuint8m1_t test_vfncvt_xu_f_w_u8m1_m(vbool8_t mask, vfloat16m2_t src, size_t vl) {588  return __riscv_vfncvt_xu_f_w_u8m1_m(mask, src, vl);589}590 591// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vfncvt_xu_f_w_u8m2_m592// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {593// CHECK-RV64-NEXT:  entry:594// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> poison, <vscale x 16 x half> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)595// CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]596//597vuint8m2_t test_vfncvt_xu_f_w_u8m2_m(vbool4_t mask, vfloat16m4_t src, size_t vl) {598  return __riscv_vfncvt_xu_f_w_u8m2_m(mask, src, vl);599}600 601// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vfncvt_xu_f_w_u8m4_m602// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {603// CHECK-RV64-NEXT:  entry:604// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> poison, <vscale x 32 x half> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)605// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]606//607vuint8m4_t test_vfncvt_xu_f_w_u8m4_m(vbool2_t mask, vfloat16m8_t src, size_t vl) {608  return __riscv_vfncvt_xu_f_w_u8m4_m(mask, src, vl);609}610 611// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vfncvt_x_f_w_i16mf4_m612// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {613// CHECK-RV64-NEXT:  entry:614// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv1i16.nxv1f32.i64(<vscale x 1 x i16> poison, <vscale x 1 x float> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)615// CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]616//617vint16mf4_t test_vfncvt_x_f_w_i16mf4_m(vbool64_t mask, vfloat32mf2_t src, size_t vl) {618  return __riscv_vfncvt_x_f_w_i16mf4_m(mask, src, vl);619}620 621// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vfncvt_x_f_w_i16mf2_m622// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {623// CHECK-RV64-NEXT:  entry:624// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv2i16.nxv2f32.i64(<vscale x 2 x i16> poison, <vscale x 2 x float> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)625// CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]626//627vint16mf2_t test_vfncvt_x_f_w_i16mf2_m(vbool32_t mask, vfloat32m1_t src, size_t vl) {628  return __riscv_vfncvt_x_f_w_i16mf2_m(mask, src, vl);629}630 631// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfncvt_x_f_w_i16m1_m632// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {633// CHECK-RV64-NEXT:  entry:634// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv4i16.nxv4f32.i64(<vscale x 4 x i16> poison, <vscale x 4 x float> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)635// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]636//637vint16m1_t test_vfncvt_x_f_w_i16m1_m(vbool16_t mask, vfloat32m2_t src, size_t vl) {638  return __riscv_vfncvt_x_f_w_i16m1_m(mask, src, vl);639}640 641// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfncvt_x_f_w_i16m2_m642// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {643// CHECK-RV64-NEXT:  entry:644// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv8i16.nxv8f32.i64(<vscale x 8 x i16> poison, <vscale x 8 x float> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)645// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]646//647vint16m2_t test_vfncvt_x_f_w_i16m2_m(vbool8_t mask, vfloat32m4_t src, size_t vl) {648  return __riscv_vfncvt_x_f_w_i16m2_m(mask, src, vl);649}650 651// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfncvt_x_f_w_i16m4_m652// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {653// CHECK-RV64-NEXT:  entry:654// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv16i16.nxv16f32.i64(<vscale x 16 x i16> poison, <vscale x 16 x float> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)655// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]656//657vint16m4_t test_vfncvt_x_f_w_i16m4_m(vbool4_t mask, vfloat32m8_t src, size_t vl) {658  return __riscv_vfncvt_x_f_w_i16m4_m(mask, src, vl);659}660 661// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vfncvt_xu_f_w_u16mf4_m662// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {663// CHECK-RV64-NEXT:  entry:664// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i16.nxv1f32.i64(<vscale x 1 x i16> poison, <vscale x 1 x float> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)665// CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]666//667vuint16mf4_t test_vfncvt_xu_f_w_u16mf4_m(vbool64_t mask, vfloat32mf2_t src, size_t vl) {668  return __riscv_vfncvt_xu_f_w_u16mf4_m(mask, src, vl);669}670 671// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vfncvt_xu_f_w_u16mf2_m672// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {673// CHECK-RV64-NEXT:  entry:674// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv2i16.nxv2f32.i64(<vscale x 2 x i16> poison, <vscale x 2 x float> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)675// CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]676//677vuint16mf2_t test_vfncvt_xu_f_w_u16mf2_m(vbool32_t mask, vfloat32m1_t src, size_t vl) {678  return __riscv_vfncvt_xu_f_w_u16mf2_m(mask, src, vl);679}680 681// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfncvt_xu_f_w_u16m1_m682// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {683// CHECK-RV64-NEXT:  entry:684// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv4i16.nxv4f32.i64(<vscale x 4 x i16> poison, <vscale x 4 x float> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)685// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]686//687vuint16m1_t test_vfncvt_xu_f_w_u16m1_m(vbool16_t mask, vfloat32m2_t src, size_t vl) {688  return __riscv_vfncvt_xu_f_w_u16m1_m(mask, src, vl);689}690 691// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfncvt_xu_f_w_u16m2_m692// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {693// CHECK-RV64-NEXT:  entry:694// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv8i16.nxv8f32.i64(<vscale x 8 x i16> poison, <vscale x 8 x float> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)695// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]696//697vuint16m2_t test_vfncvt_xu_f_w_u16m2_m(vbool8_t mask, vfloat32m4_t src, size_t vl) {698  return __riscv_vfncvt_xu_f_w_u16m2_m(mask, src, vl);699}700 701// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfncvt_xu_f_w_u16m4_m702// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {703// CHECK-RV64-NEXT:  entry:704// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv16i16.nxv16f32.i64(<vscale x 16 x i16> poison, <vscale x 16 x float> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)705// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]706//707vuint16m4_t test_vfncvt_xu_f_w_u16m4_m(vbool4_t mask, vfloat32m8_t src, size_t vl) {708  return __riscv_vfncvt_xu_f_w_u16m4_m(mask, src, vl);709}710 711// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfncvt_f_x_w_f16mf4_m712// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {713// CHECK-RV64-NEXT:  entry:714// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv1f16.nxv1i32.i64(<vscale x 1 x half> poison, <vscale x 1 x i32> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)715// CHECK-RV64-NEXT:    ret <vscale x 1 x half> [[TMP0]]716//717vfloat16mf4_t test_vfncvt_f_x_w_f16mf4_m(vbool64_t mask, vint32mf2_t src, size_t vl) {718  return __riscv_vfncvt_f_x_w_f16mf4_m(mask, src, vl);719}720 721// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfncvt_f_x_w_f16mf2_m722// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {723// CHECK-RV64-NEXT:  entry:724// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv2f16.nxv2i32.i64(<vscale x 2 x half> poison, <vscale x 2 x i32> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)725// CHECK-RV64-NEXT:    ret <vscale x 2 x half> [[TMP0]]726//727vfloat16mf2_t test_vfncvt_f_x_w_f16mf2_m(vbool32_t mask, vint32m1_t src, size_t vl) {728  return __riscv_vfncvt_f_x_w_f16mf2_m(mask, src, vl);729}730 731// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfncvt_f_x_w_f16m1_m732// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {733// CHECK-RV64-NEXT:  entry:734// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv4f16.nxv4i32.i64(<vscale x 4 x half> poison, <vscale x 4 x i32> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)735// CHECK-RV64-NEXT:    ret <vscale x 4 x half> [[TMP0]]736//737vfloat16m1_t test_vfncvt_f_x_w_f16m1_m(vbool16_t mask, vint32m2_t src, size_t vl) {738  return __riscv_vfncvt_f_x_w_f16m1_m(mask, src, vl);739}740 741// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfncvt_f_x_w_f16m2_m742// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {743// CHECK-RV64-NEXT:  entry:744// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv8f16.nxv8i32.i64(<vscale x 8 x half> poison, <vscale x 8 x i32> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)745// CHECK-RV64-NEXT:    ret <vscale x 8 x half> [[TMP0]]746//747vfloat16m2_t test_vfncvt_f_x_w_f16m2_m(vbool8_t mask, vint32m4_t src, size_t vl) {748  return __riscv_vfncvt_f_x_w_f16m2_m(mask, src, vl);749}750 751// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfncvt_f_x_w_f16m4_m752// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {753// CHECK-RV64-NEXT:  entry:754// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv16f16.nxv16i32.i64(<vscale x 16 x half> poison, <vscale x 16 x i32> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)755// CHECK-RV64-NEXT:    ret <vscale x 16 x half> [[TMP0]]756//757vfloat16m4_t test_vfncvt_f_x_w_f16m4_m(vbool4_t mask, vint32m8_t src, size_t vl) {758  return __riscv_vfncvt_f_x_w_f16m4_m(mask, src, vl);759}760 761// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfncvt_f_xu_w_f16mf4_m762// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {763// CHECK-RV64-NEXT:  entry:764// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv1f16.nxv1i32.i64(<vscale x 1 x half> poison, <vscale x 1 x i32> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)765// CHECK-RV64-NEXT:    ret <vscale x 1 x half> [[TMP0]]766//767vfloat16mf4_t test_vfncvt_f_xu_w_f16mf4_m(vbool64_t mask, vuint32mf2_t src, size_t vl) {768  return __riscv_vfncvt_f_xu_w_f16mf4_m(mask, src, vl);769}770 771// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfncvt_f_xu_w_f16mf2_m772// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {773// CHECK-RV64-NEXT:  entry:774// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv2f16.nxv2i32.i64(<vscale x 2 x half> poison, <vscale x 2 x i32> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)775// CHECK-RV64-NEXT:    ret <vscale x 2 x half> [[TMP0]]776//777vfloat16mf2_t test_vfncvt_f_xu_w_f16mf2_m(vbool32_t mask, vuint32m1_t src, size_t vl) {778  return __riscv_vfncvt_f_xu_w_f16mf2_m(mask, src, vl);779}780 781// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfncvt_f_xu_w_f16m1_m782// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {783// CHECK-RV64-NEXT:  entry:784// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv4f16.nxv4i32.i64(<vscale x 4 x half> poison, <vscale x 4 x i32> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)785// CHECK-RV64-NEXT:    ret <vscale x 4 x half> [[TMP0]]786//787vfloat16m1_t test_vfncvt_f_xu_w_f16m1_m(vbool16_t mask, vuint32m2_t src, size_t vl) {788  return __riscv_vfncvt_f_xu_w_f16m1_m(mask, src, vl);789}790 791// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfncvt_f_xu_w_f16m2_m792// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {793// CHECK-RV64-NEXT:  entry:794// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv8f16.nxv8i32.i64(<vscale x 8 x half> poison, <vscale x 8 x i32> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)795// CHECK-RV64-NEXT:    ret <vscale x 8 x half> [[TMP0]]796//797vfloat16m2_t test_vfncvt_f_xu_w_f16m2_m(vbool8_t mask, vuint32m4_t src, size_t vl) {798  return __riscv_vfncvt_f_xu_w_f16m2_m(mask, src, vl);799}800 801// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfncvt_f_xu_w_f16m4_m802// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {803// CHECK-RV64-NEXT:  entry:804// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv16f16.nxv16i32.i64(<vscale x 16 x half> poison, <vscale x 16 x i32> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)805// CHECK-RV64-NEXT:    ret <vscale x 16 x half> [[TMP0]]806//807vfloat16m4_t test_vfncvt_f_xu_w_f16m4_m(vbool4_t mask, vuint32m8_t src, size_t vl) {808  return __riscv_vfncvt_f_xu_w_f16m4_m(mask, src, vl);809}810 811// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfncvt_x_f_w_i32mf2_m812// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {813// CHECK-RV64-NEXT:  entry:814// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfncvt.x.f.w.mask.nxv1i32.nxv1f64.i64(<vscale x 1 x i32> poison, <vscale x 1 x double> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)815// CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]816//817vint32mf2_t test_vfncvt_x_f_w_i32mf2_m(vbool64_t mask, vfloat64m1_t src, size_t vl) {818  return __riscv_vfncvt_x_f_w_i32mf2_m(mask, src, vl);819}820 821// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfncvt_x_f_w_i32m1_m822// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {823// CHECK-RV64-NEXT:  entry:824// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfncvt.x.f.w.mask.nxv2i32.nxv2f64.i64(<vscale x 2 x i32> poison, <vscale x 2 x double> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)825// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]826//827vint32m1_t test_vfncvt_x_f_w_i32m1_m(vbool32_t mask, vfloat64m2_t src, size_t vl) {828  return __riscv_vfncvt_x_f_w_i32m1_m(mask, src, vl);829}830 831// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfncvt_x_f_w_i32m2_m832// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {833// CHECK-RV64-NEXT:  entry:834// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfncvt.x.f.w.mask.nxv4i32.nxv4f64.i64(<vscale x 4 x i32> poison, <vscale x 4 x double> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)835// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]836//837vint32m2_t test_vfncvt_x_f_w_i32m2_m(vbool16_t mask, vfloat64m4_t src, size_t vl) {838  return __riscv_vfncvt_x_f_w_i32m2_m(mask, src, vl);839}840 841// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfncvt_x_f_w_i32m4_m842// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {843// CHECK-RV64-NEXT:  entry:844// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfncvt.x.f.w.mask.nxv8i32.nxv8f64.i64(<vscale x 8 x i32> poison, <vscale x 8 x double> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)845// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]846//847vint32m4_t test_vfncvt_x_f_w_i32m4_m(vbool8_t mask, vfloat64m8_t src, size_t vl) {848  return __riscv_vfncvt_x_f_w_i32m4_m(mask, src, vl);849}850 851// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfncvt_xu_f_w_u32mf2_m852// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {853// CHECK-RV64-NEXT:  entry:854// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i32.nxv1f64.i64(<vscale x 1 x i32> poison, <vscale x 1 x double> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)855// CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]856//857vuint32mf2_t test_vfncvt_xu_f_w_u32mf2_m(vbool64_t mask, vfloat64m1_t src, size_t vl) {858  return __riscv_vfncvt_xu_f_w_u32mf2_m(mask, src, vl);859}860 861// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfncvt_xu_f_w_u32m1_m862// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {863// CHECK-RV64-NEXT:  entry:864// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfncvt.xu.f.w.mask.nxv2i32.nxv2f64.i64(<vscale x 2 x i32> poison, <vscale x 2 x double> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)865// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]866//867vuint32m1_t test_vfncvt_xu_f_w_u32m1_m(vbool32_t mask, vfloat64m2_t src, size_t vl) {868  return __riscv_vfncvt_xu_f_w_u32m1_m(mask, src, vl);869}870 871// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfncvt_xu_f_w_u32m2_m872// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {873// CHECK-RV64-NEXT:  entry:874// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfncvt.xu.f.w.mask.nxv4i32.nxv4f64.i64(<vscale x 4 x i32> poison, <vscale x 4 x double> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)875// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]876//877vuint32m2_t test_vfncvt_xu_f_w_u32m2_m(vbool16_t mask, vfloat64m4_t src, size_t vl) {878  return __riscv_vfncvt_xu_f_w_u32m2_m(mask, src, vl);879}880 881// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfncvt_xu_f_w_u32m4_m882// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {883// CHECK-RV64-NEXT:  entry:884// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfncvt.xu.f.w.mask.nxv8i32.nxv8f64.i64(<vscale x 8 x i32> poison, <vscale x 8 x double> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)885// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]886//887vuint32m4_t test_vfncvt_xu_f_w_u32m4_m(vbool8_t mask, vfloat64m8_t src, size_t vl) {888  return __riscv_vfncvt_xu_f_w_u32m4_m(mask, src, vl);889}890 891// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfncvt_f_x_w_f32mf2_m892// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {893// CHECK-RV64-NEXT:  entry:894// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.x.w.mask.nxv1f32.nxv1i64.i64(<vscale x 1 x float> poison, <vscale x 1 x i64> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)895// CHECK-RV64-NEXT:    ret <vscale x 1 x float> [[TMP0]]896//897vfloat32mf2_t test_vfncvt_f_x_w_f32mf2_m(vbool64_t mask, vint64m1_t src, size_t vl) {898  return __riscv_vfncvt_f_x_w_f32mf2_m(mask, src, vl);899}900 901// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfncvt_f_x_w_f32m1_m902// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {903// CHECK-RV64-NEXT:  entry:904// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.x.w.mask.nxv2f32.nxv2i64.i64(<vscale x 2 x float> poison, <vscale x 2 x i64> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)905// CHECK-RV64-NEXT:    ret <vscale x 2 x float> [[TMP0]]906//907vfloat32m1_t test_vfncvt_f_x_w_f32m1_m(vbool32_t mask, vint64m2_t src, size_t vl) {908  return __riscv_vfncvt_f_x_w_f32m1_m(mask, src, vl);909}910 911// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfncvt_f_x_w_f32m2_m912// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {913// CHECK-RV64-NEXT:  entry:914// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.x.w.mask.nxv4f32.nxv4i64.i64(<vscale x 4 x float> poison, <vscale x 4 x i64> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)915// CHECK-RV64-NEXT:    ret <vscale x 4 x float> [[TMP0]]916//917vfloat32m2_t test_vfncvt_f_x_w_f32m2_m(vbool16_t mask, vint64m4_t src, size_t vl) {918  return __riscv_vfncvt_f_x_w_f32m2_m(mask, src, vl);919}920 921// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfncvt_f_x_w_f32m4_m922// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {923// CHECK-RV64-NEXT:  entry:924// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.x.w.mask.nxv8f32.nxv8i64.i64(<vscale x 8 x float> poison, <vscale x 8 x i64> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)925// CHECK-RV64-NEXT:    ret <vscale x 8 x float> [[TMP0]]926//927vfloat32m4_t test_vfncvt_f_x_w_f32m4_m(vbool8_t mask, vint64m8_t src, size_t vl) {928  return __riscv_vfncvt_f_x_w_f32m4_m(mask, src, vl);929}930 931// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfncvt_f_xu_w_f32mf2_m932// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {933// CHECK-RV64-NEXT:  entry:934// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.xu.w.mask.nxv1f32.nxv1i64.i64(<vscale x 1 x float> poison, <vscale x 1 x i64> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)935// CHECK-RV64-NEXT:    ret <vscale x 1 x float> [[TMP0]]936//937vfloat32mf2_t test_vfncvt_f_xu_w_f32mf2_m(vbool64_t mask, vuint64m1_t src, size_t vl) {938  return __riscv_vfncvt_f_xu_w_f32mf2_m(mask, src, vl);939}940 941// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfncvt_f_xu_w_f32m1_m942// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {943// CHECK-RV64-NEXT:  entry:944// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.xu.w.mask.nxv2f32.nxv2i64.i64(<vscale x 2 x float> poison, <vscale x 2 x i64> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)945// CHECK-RV64-NEXT:    ret <vscale x 2 x float> [[TMP0]]946//947vfloat32m1_t test_vfncvt_f_xu_w_f32m1_m(vbool32_t mask, vuint64m2_t src, size_t vl) {948  return __riscv_vfncvt_f_xu_w_f32m1_m(mask, src, vl);949}950 951// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfncvt_f_xu_w_f32m2_m952// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {953// CHECK-RV64-NEXT:  entry:954// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.xu.w.mask.nxv4f32.nxv4i64.i64(<vscale x 4 x float> poison, <vscale x 4 x i64> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)955// CHECK-RV64-NEXT:    ret <vscale x 4 x float> [[TMP0]]956//957vfloat32m2_t test_vfncvt_f_xu_w_f32m2_m(vbool16_t mask, vuint64m4_t src, size_t vl) {958  return __riscv_vfncvt_f_xu_w_f32m2_m(mask, src, vl);959}960 961// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfncvt_f_xu_w_f32m4_m962// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {963// CHECK-RV64-NEXT:  entry:964// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.xu.w.mask.nxv8f32.nxv8i64.i64(<vscale x 8 x float> poison, <vscale x 8 x i64> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)965// CHECK-RV64-NEXT:    ret <vscale x 8 x float> [[TMP0]]966//967vfloat32m4_t test_vfncvt_f_xu_w_f32m4_m(vbool8_t mask, vuint64m8_t src, size_t vl) {968  return __riscv_vfncvt_f_xu_w_f32m4_m(mask, src, vl);969}970 971// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_i8mf8_rm972// CHECK-RV64-SAME: (<vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {973// CHECK-RV64-NEXT:  entry:974// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> poison, <vscale x 1 x half> [[SRC]], i64 0, i64 [[VL]])975// CHECK-RV64-NEXT:    ret <vscale x 1 x i8> [[TMP0]]976//977vint8mf8_t test_vfncvt_x_f_w_i8mf8_rm(vfloat16mf4_t src, size_t vl) {978  return __riscv_vfncvt_x_f_w_i8mf8_rm(src, __RISCV_FRM_RNE, vl);979}980 981// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vfncvt_x_f_w_i8mf4_rm982// CHECK-RV64-SAME: (<vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {983// CHECK-RV64-NEXT:  entry:984// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> poison, <vscale x 2 x half> [[SRC]], i64 0, i64 [[VL]])985// CHECK-RV64-NEXT:    ret <vscale x 2 x i8> [[TMP0]]986//987vint8mf4_t test_vfncvt_x_f_w_i8mf4_rm(vfloat16mf2_t src, size_t vl) {988  return __riscv_vfncvt_x_f_w_i8mf4_rm(src, __RISCV_FRM_RNE, vl);989}990 991// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vfncvt_x_f_w_i8mf2_rm992// CHECK-RV64-SAME: (<vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {993// CHECK-RV64-NEXT:  entry:994// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> poison, <vscale x 4 x half> [[SRC]], i64 0, i64 [[VL]])995// CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[TMP0]]996//997vint8mf2_t test_vfncvt_x_f_w_i8mf2_rm(vfloat16m1_t src, size_t vl) {998  return __riscv_vfncvt_x_f_w_i8mf2_rm(src, __RISCV_FRM_RNE, vl);999}1000 1001// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vfncvt_x_f_w_i8m1_rm1002// CHECK-RV64-SAME: (<vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1003// CHECK-RV64-NEXT:  entry:1004// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> poison, <vscale x 8 x half> [[SRC]], i64 0, i64 [[VL]])1005// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]1006//1007vint8m1_t test_vfncvt_x_f_w_i8m1_rm(vfloat16m2_t src, size_t vl) {1008  return __riscv_vfncvt_x_f_w_i8m1_rm(src, __RISCV_FRM_RNE, vl);1009}1010 1011// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vfncvt_x_f_w_i8m2_rm1012// CHECK-RV64-SAME: (<vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1013// CHECK-RV64-NEXT:  entry:1014// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> poison, <vscale x 16 x half> [[SRC]], i64 0, i64 [[VL]])1015// CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]1016//1017vint8m2_t test_vfncvt_x_f_w_i8m2_rm(vfloat16m4_t src, size_t vl) {1018  return __riscv_vfncvt_x_f_w_i8m2_rm(src, __RISCV_FRM_RNE, vl);1019}1020 1021// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vfncvt_x_f_w_i8m4_rm1022// CHECK-RV64-SAME: (<vscale x 32 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1023// CHECK-RV64-NEXT:  entry:1024// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> poison, <vscale x 32 x half> [[SRC]], i64 0, i64 [[VL]])1025// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]1026//1027vint8m4_t test_vfncvt_x_f_w_i8m4_rm(vfloat16m8_t src, size_t vl) {1028  return __riscv_vfncvt_x_f_w_i8m4_rm(src, __RISCV_FRM_RNE, vl);1029}1030 1031// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vfncvt_xu_f_w_u8mf8_rm1032// CHECK-RV64-SAME: (<vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1033// CHECK-RV64-NEXT:  entry:1034// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> poison, <vscale x 1 x half> [[SRC]], i64 0, i64 [[VL]])1035// CHECK-RV64-NEXT:    ret <vscale x 1 x i8> [[TMP0]]1036//1037vuint8mf8_t test_vfncvt_xu_f_w_u8mf8_rm(vfloat16mf4_t src, size_t vl) {1038  return __riscv_vfncvt_xu_f_w_u8mf8_rm(src, __RISCV_FRM_RNE, vl);1039}1040 1041// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vfncvt_xu_f_w_u8mf4_rm1042// CHECK-RV64-SAME: (<vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1043// CHECK-RV64-NEXT:  entry:1044// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> poison, <vscale x 2 x half> [[SRC]], i64 0, i64 [[VL]])1045// CHECK-RV64-NEXT:    ret <vscale x 2 x i8> [[TMP0]]1046//1047vuint8mf4_t test_vfncvt_xu_f_w_u8mf4_rm(vfloat16mf2_t src, size_t vl) {1048  return __riscv_vfncvt_xu_f_w_u8mf4_rm(src, __RISCV_FRM_RNE, vl);1049}1050 1051// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vfncvt_xu_f_w_u8mf2_rm1052// CHECK-RV64-SAME: (<vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1053// CHECK-RV64-NEXT:  entry:1054// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> poison, <vscale x 4 x half> [[SRC]], i64 0, i64 [[VL]])1055// CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[TMP0]]1056//1057vuint8mf2_t test_vfncvt_xu_f_w_u8mf2_rm(vfloat16m1_t src, size_t vl) {1058  return __riscv_vfncvt_xu_f_w_u8mf2_rm(src, __RISCV_FRM_RNE, vl);1059}1060 1061// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vfncvt_xu_f_w_u8m1_rm1062// CHECK-RV64-SAME: (<vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1063// CHECK-RV64-NEXT:  entry:1064// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> poison, <vscale x 8 x half> [[SRC]], i64 0, i64 [[VL]])1065// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]1066//1067vuint8m1_t test_vfncvt_xu_f_w_u8m1_rm(vfloat16m2_t src, size_t vl) {1068  return __riscv_vfncvt_xu_f_w_u8m1_rm(src, __RISCV_FRM_RNE, vl);1069}1070 1071// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vfncvt_xu_f_w_u8m2_rm1072// CHECK-RV64-SAME: (<vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1073// CHECK-RV64-NEXT:  entry:1074// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> poison, <vscale x 16 x half> [[SRC]], i64 0, i64 [[VL]])1075// CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]1076//1077vuint8m2_t test_vfncvt_xu_f_w_u8m2_rm(vfloat16m4_t src, size_t vl) {1078  return __riscv_vfncvt_xu_f_w_u8m2_rm(src, __RISCV_FRM_RNE, vl);1079}1080 1081// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vfncvt_xu_f_w_u8m4_rm1082// CHECK-RV64-SAME: (<vscale x 32 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1083// CHECK-RV64-NEXT:  entry:1084// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> poison, <vscale x 32 x half> [[SRC]], i64 0, i64 [[VL]])1085// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]1086//1087vuint8m4_t test_vfncvt_xu_f_w_u8m4_rm(vfloat16m8_t src, size_t vl) {1088  return __riscv_vfncvt_xu_f_w_u8m4_rm(src, __RISCV_FRM_RNE, vl);1089}1090 1091// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vfncvt_x_f_w_i16mf4_rm1092// CHECK-RV64-SAME: (<vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1093// CHECK-RV64-NEXT:  entry:1094// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfncvt.x.f.w.nxv1i16.nxv1f32.i64(<vscale x 1 x i16> poison, <vscale x 1 x float> [[SRC]], i64 0, i64 [[VL]])1095// CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]1096//1097vint16mf4_t test_vfncvt_x_f_w_i16mf4_rm(vfloat32mf2_t src, size_t vl) {1098  return __riscv_vfncvt_x_f_w_i16mf4_rm(src, __RISCV_FRM_RNE, vl);1099}1100 1101// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vfncvt_x_f_w_i16mf2_rm1102// CHECK-RV64-SAME: (<vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1103// CHECK-RV64-NEXT:  entry:1104// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfncvt.x.f.w.nxv2i16.nxv2f32.i64(<vscale x 2 x i16> poison, <vscale x 2 x float> [[SRC]], i64 0, i64 [[VL]])1105// CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]1106//1107vint16mf2_t test_vfncvt_x_f_w_i16mf2_rm(vfloat32m1_t src, size_t vl) {1108  return __riscv_vfncvt_x_f_w_i16mf2_rm(src, __RISCV_FRM_RNE, vl);1109}1110 1111// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfncvt_x_f_w_i16m1_rm1112// CHECK-RV64-SAME: (<vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1113// CHECK-RV64-NEXT:  entry:1114// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfncvt.x.f.w.nxv4i16.nxv4f32.i64(<vscale x 4 x i16> poison, <vscale x 4 x float> [[SRC]], i64 0, i64 [[VL]])1115// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]1116//1117vint16m1_t test_vfncvt_x_f_w_i16m1_rm(vfloat32m2_t src, size_t vl) {1118  return __riscv_vfncvt_x_f_w_i16m1_rm(src, __RISCV_FRM_RNE, vl);1119}1120 1121// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfncvt_x_f_w_i16m2_rm1122// CHECK-RV64-SAME: (<vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1123// CHECK-RV64-NEXT:  entry:1124// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfncvt.x.f.w.nxv8i16.nxv8f32.i64(<vscale x 8 x i16> poison, <vscale x 8 x float> [[SRC]], i64 0, i64 [[VL]])1125// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]1126//1127vint16m2_t test_vfncvt_x_f_w_i16m2_rm(vfloat32m4_t src, size_t vl) {1128  return __riscv_vfncvt_x_f_w_i16m2_rm(src, __RISCV_FRM_RNE, vl);1129}1130 1131// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfncvt_x_f_w_i16m4_rm1132// CHECK-RV64-SAME: (<vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1133// CHECK-RV64-NEXT:  entry:1134// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfncvt.x.f.w.nxv16i16.nxv16f32.i64(<vscale x 16 x i16> poison, <vscale x 16 x float> [[SRC]], i64 0, i64 [[VL]])1135// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]1136//1137vint16m4_t test_vfncvt_x_f_w_i16m4_rm(vfloat32m8_t src, size_t vl) {1138  return __riscv_vfncvt_x_f_w_i16m4_rm(src, __RISCV_FRM_RNE, vl);1139}1140 1141// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vfncvt_xu_f_w_u16mf4_rm1142// CHECK-RV64-SAME: (<vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1143// CHECK-RV64-NEXT:  entry:1144// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv1i16.nxv1f32.i64(<vscale x 1 x i16> poison, <vscale x 1 x float> [[SRC]], i64 0, i64 [[VL]])1145// CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]1146//1147vuint16mf4_t test_vfncvt_xu_f_w_u16mf4_rm(vfloat32mf2_t src, size_t vl) {1148  return __riscv_vfncvt_xu_f_w_u16mf4_rm(src, __RISCV_FRM_RNE, vl);1149}1150 1151// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vfncvt_xu_f_w_u16mf2_rm1152// CHECK-RV64-SAME: (<vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1153// CHECK-RV64-NEXT:  entry:1154// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv2i16.nxv2f32.i64(<vscale x 2 x i16> poison, <vscale x 2 x float> [[SRC]], i64 0, i64 [[VL]])1155// CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]1156//1157vuint16mf2_t test_vfncvt_xu_f_w_u16mf2_rm(vfloat32m1_t src, size_t vl) {1158  return __riscv_vfncvt_xu_f_w_u16mf2_rm(src, __RISCV_FRM_RNE, vl);1159}1160 1161// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfncvt_xu_f_w_u16m1_rm1162// CHECK-RV64-SAME: (<vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1163// CHECK-RV64-NEXT:  entry:1164// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv4i16.nxv4f32.i64(<vscale x 4 x i16> poison, <vscale x 4 x float> [[SRC]], i64 0, i64 [[VL]])1165// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]1166//1167vuint16m1_t test_vfncvt_xu_f_w_u16m1_rm(vfloat32m2_t src, size_t vl) {1168  return __riscv_vfncvt_xu_f_w_u16m1_rm(src, __RISCV_FRM_RNE, vl);1169}1170 1171// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfncvt_xu_f_w_u16m2_rm1172// CHECK-RV64-SAME: (<vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1173// CHECK-RV64-NEXT:  entry:1174// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv8i16.nxv8f32.i64(<vscale x 8 x i16> poison, <vscale x 8 x float> [[SRC]], i64 0, i64 [[VL]])1175// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]1176//1177vuint16m2_t test_vfncvt_xu_f_w_u16m2_rm(vfloat32m4_t src, size_t vl) {1178  return __riscv_vfncvt_xu_f_w_u16m2_rm(src, __RISCV_FRM_RNE, vl);1179}1180 1181// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfncvt_xu_f_w_u16m4_rm1182// CHECK-RV64-SAME: (<vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1183// CHECK-RV64-NEXT:  entry:1184// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv16i16.nxv16f32.i64(<vscale x 16 x i16> poison, <vscale x 16 x float> [[SRC]], i64 0, i64 [[VL]])1185// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]1186//1187vuint16m4_t test_vfncvt_xu_f_w_u16m4_rm(vfloat32m8_t src, size_t vl) {1188  return __riscv_vfncvt_xu_f_w_u16m4_rm(src, __RISCV_FRM_RNE, vl);1189}1190 1191// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfncvt_f_x_w_f16mf4_rm1192// CHECK-RV64-SAME: (<vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1193// CHECK-RV64-NEXT:  entry:1194// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.x.w.nxv1f16.nxv1i32.i64(<vscale x 1 x half> poison, <vscale x 1 x i32> [[SRC]], i64 0, i64 [[VL]])1195// CHECK-RV64-NEXT:    ret <vscale x 1 x half> [[TMP0]]1196//1197vfloat16mf4_t test_vfncvt_f_x_w_f16mf4_rm(vint32mf2_t src, size_t vl) {1198  return __riscv_vfncvt_f_x_w_f16mf4_rm(src, __RISCV_FRM_RNE, vl);1199}1200 1201// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfncvt_f_x_w_f16mf2_rm1202// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1203// CHECK-RV64-NEXT:  entry:1204// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.x.w.nxv2f16.nxv2i32.i64(<vscale x 2 x half> poison, <vscale x 2 x i32> [[SRC]], i64 0, i64 [[VL]])1205// CHECK-RV64-NEXT:    ret <vscale x 2 x half> [[TMP0]]1206//1207vfloat16mf2_t test_vfncvt_f_x_w_f16mf2_rm(vint32m1_t src, size_t vl) {1208  return __riscv_vfncvt_f_x_w_f16mf2_rm(src, __RISCV_FRM_RNE, vl);1209}1210 1211// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfncvt_f_x_w_f16m1_rm1212// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1213// CHECK-RV64-NEXT:  entry:1214// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.x.w.nxv4f16.nxv4i32.i64(<vscale x 4 x half> poison, <vscale x 4 x i32> [[SRC]], i64 0, i64 [[VL]])1215// CHECK-RV64-NEXT:    ret <vscale x 4 x half> [[TMP0]]1216//1217vfloat16m1_t test_vfncvt_f_x_w_f16m1_rm(vint32m2_t src, size_t vl) {1218  return __riscv_vfncvt_f_x_w_f16m1_rm(src, __RISCV_FRM_RNE, vl);1219}1220 1221// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfncvt_f_x_w_f16m2_rm1222// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1223// CHECK-RV64-NEXT:  entry:1224// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.x.w.nxv8f16.nxv8i32.i64(<vscale x 8 x half> poison, <vscale x 8 x i32> [[SRC]], i64 0, i64 [[VL]])1225// CHECK-RV64-NEXT:    ret <vscale x 8 x half> [[TMP0]]1226//1227vfloat16m2_t test_vfncvt_f_x_w_f16m2_rm(vint32m4_t src, size_t vl) {1228  return __riscv_vfncvt_f_x_w_f16m2_rm(src, __RISCV_FRM_RNE, vl);1229}1230 1231// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfncvt_f_x_w_f16m4_rm1232// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1233// CHECK-RV64-NEXT:  entry:1234// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.x.w.nxv16f16.nxv16i32.i64(<vscale x 16 x half> poison, <vscale x 16 x i32> [[SRC]], i64 0, i64 [[VL]])1235// CHECK-RV64-NEXT:    ret <vscale x 16 x half> [[TMP0]]1236//1237vfloat16m4_t test_vfncvt_f_x_w_f16m4_rm(vint32m8_t src, size_t vl) {1238  return __riscv_vfncvt_f_x_w_f16m4_rm(src, __RISCV_FRM_RNE, vl);1239}1240 1241// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfncvt_f_xu_w_f16mf4_rm1242// CHECK-RV64-SAME: (<vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1243// CHECK-RV64-NEXT:  entry:1244// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.xu.w.nxv1f16.nxv1i32.i64(<vscale x 1 x half> poison, <vscale x 1 x i32> [[SRC]], i64 0, i64 [[VL]])1245// CHECK-RV64-NEXT:    ret <vscale x 1 x half> [[TMP0]]1246//1247vfloat16mf4_t test_vfncvt_f_xu_w_f16mf4_rm(vuint32mf2_t src, size_t vl) {1248  return __riscv_vfncvt_f_xu_w_f16mf4_rm(src, __RISCV_FRM_RNE, vl);1249}1250 1251// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfncvt_f_xu_w_f16mf2_rm1252// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1253// CHECK-RV64-NEXT:  entry:1254// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.xu.w.nxv2f16.nxv2i32.i64(<vscale x 2 x half> poison, <vscale x 2 x i32> [[SRC]], i64 0, i64 [[VL]])1255// CHECK-RV64-NEXT:    ret <vscale x 2 x half> [[TMP0]]1256//1257vfloat16mf2_t test_vfncvt_f_xu_w_f16mf2_rm(vuint32m1_t src, size_t vl) {1258  return __riscv_vfncvt_f_xu_w_f16mf2_rm(src, __RISCV_FRM_RNE, vl);1259}1260 1261// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfncvt_f_xu_w_f16m1_rm1262// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1263// CHECK-RV64-NEXT:  entry:1264// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.xu.w.nxv4f16.nxv4i32.i64(<vscale x 4 x half> poison, <vscale x 4 x i32> [[SRC]], i64 0, i64 [[VL]])1265// CHECK-RV64-NEXT:    ret <vscale x 4 x half> [[TMP0]]1266//1267vfloat16m1_t test_vfncvt_f_xu_w_f16m1_rm(vuint32m2_t src, size_t vl) {1268  return __riscv_vfncvt_f_xu_w_f16m1_rm(src, __RISCV_FRM_RNE, vl);1269}1270 1271// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfncvt_f_xu_w_f16m2_rm1272// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1273// CHECK-RV64-NEXT:  entry:1274// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.xu.w.nxv8f16.nxv8i32.i64(<vscale x 8 x half> poison, <vscale x 8 x i32> [[SRC]], i64 0, i64 [[VL]])1275// CHECK-RV64-NEXT:    ret <vscale x 8 x half> [[TMP0]]1276//1277vfloat16m2_t test_vfncvt_f_xu_w_f16m2_rm(vuint32m4_t src, size_t vl) {1278  return __riscv_vfncvt_f_xu_w_f16m2_rm(src, __RISCV_FRM_RNE, vl);1279}1280 1281// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfncvt_f_xu_w_f16m4_rm1282// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1283// CHECK-RV64-NEXT:  entry:1284// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.xu.w.nxv16f16.nxv16i32.i64(<vscale x 16 x half> poison, <vscale x 16 x i32> [[SRC]], i64 0, i64 [[VL]])1285// CHECK-RV64-NEXT:    ret <vscale x 16 x half> [[TMP0]]1286//1287vfloat16m4_t test_vfncvt_f_xu_w_f16m4_rm(vuint32m8_t src, size_t vl) {1288  return __riscv_vfncvt_f_xu_w_f16m4_rm(src, __RISCV_FRM_RNE, vl);1289}1290 1291// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfncvt_x_f_w_i32mf2_rm1292// CHECK-RV64-SAME: (<vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1293// CHECK-RV64-NEXT:  entry:1294// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfncvt.x.f.w.nxv1i32.nxv1f64.i64(<vscale x 1 x i32> poison, <vscale x 1 x double> [[SRC]], i64 0, i64 [[VL]])1295// CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]1296//1297vint32mf2_t test_vfncvt_x_f_w_i32mf2_rm(vfloat64m1_t src, size_t vl) {1298  return __riscv_vfncvt_x_f_w_i32mf2_rm(src, __RISCV_FRM_RNE, vl);1299}1300 1301// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfncvt_x_f_w_i32m1_rm1302// CHECK-RV64-SAME: (<vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1303// CHECK-RV64-NEXT:  entry:1304// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfncvt.x.f.w.nxv2i32.nxv2f64.i64(<vscale x 2 x i32> poison, <vscale x 2 x double> [[SRC]], i64 0, i64 [[VL]])1305// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]1306//1307vint32m1_t test_vfncvt_x_f_w_i32m1_rm(vfloat64m2_t src, size_t vl) {1308  return __riscv_vfncvt_x_f_w_i32m1_rm(src, __RISCV_FRM_RNE, vl);1309}1310 1311// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfncvt_x_f_w_i32m2_rm1312// CHECK-RV64-SAME: (<vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1313// CHECK-RV64-NEXT:  entry:1314// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfncvt.x.f.w.nxv4i32.nxv4f64.i64(<vscale x 4 x i32> poison, <vscale x 4 x double> [[SRC]], i64 0, i64 [[VL]])1315// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]1316//1317vint32m2_t test_vfncvt_x_f_w_i32m2_rm(vfloat64m4_t src, size_t vl) {1318  return __riscv_vfncvt_x_f_w_i32m2_rm(src, __RISCV_FRM_RNE, vl);1319}1320 1321// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfncvt_x_f_w_i32m4_rm1322// CHECK-RV64-SAME: (<vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1323// CHECK-RV64-NEXT:  entry:1324// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfncvt.x.f.w.nxv8i32.nxv8f64.i64(<vscale x 8 x i32> poison, <vscale x 8 x double> [[SRC]], i64 0, i64 [[VL]])1325// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]1326//1327vint32m4_t test_vfncvt_x_f_w_i32m4_rm(vfloat64m8_t src, size_t vl) {1328  return __riscv_vfncvt_x_f_w_i32m4_rm(src, __RISCV_FRM_RNE, vl);1329}1330 1331// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfncvt_xu_f_w_u32mf2_rm1332// CHECK-RV64-SAME: (<vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1333// CHECK-RV64-NEXT:  entry:1334// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv1i32.nxv1f64.i64(<vscale x 1 x i32> poison, <vscale x 1 x double> [[SRC]], i64 0, i64 [[VL]])1335// CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]1336//1337vuint32mf2_t test_vfncvt_xu_f_w_u32mf2_rm(vfloat64m1_t src, size_t vl) {1338  return __riscv_vfncvt_xu_f_w_u32mf2_rm(src, __RISCV_FRM_RNE, vl);1339}1340 1341// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfncvt_xu_f_w_u32m1_rm1342// CHECK-RV64-SAME: (<vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1343// CHECK-RV64-NEXT:  entry:1344// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv2i32.nxv2f64.i64(<vscale x 2 x i32> poison, <vscale x 2 x double> [[SRC]], i64 0, i64 [[VL]])1345// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]1346//1347vuint32m1_t test_vfncvt_xu_f_w_u32m1_rm(vfloat64m2_t src, size_t vl) {1348  return __riscv_vfncvt_xu_f_w_u32m1_rm(src, __RISCV_FRM_RNE, vl);1349}1350 1351// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfncvt_xu_f_w_u32m2_rm1352// CHECK-RV64-SAME: (<vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1353// CHECK-RV64-NEXT:  entry:1354// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv4i32.nxv4f64.i64(<vscale x 4 x i32> poison, <vscale x 4 x double> [[SRC]], i64 0, i64 [[VL]])1355// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]1356//1357vuint32m2_t test_vfncvt_xu_f_w_u32m2_rm(vfloat64m4_t src, size_t vl) {1358  return __riscv_vfncvt_xu_f_w_u32m2_rm(src, __RISCV_FRM_RNE, vl);1359}1360 1361// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfncvt_xu_f_w_u32m4_rm1362// CHECK-RV64-SAME: (<vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1363// CHECK-RV64-NEXT:  entry:1364// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv8i32.nxv8f64.i64(<vscale x 8 x i32> poison, <vscale x 8 x double> [[SRC]], i64 0, i64 [[VL]])1365// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]1366//1367vuint32m4_t test_vfncvt_xu_f_w_u32m4_rm(vfloat64m8_t src, size_t vl) {1368  return __riscv_vfncvt_xu_f_w_u32m4_rm(src, __RISCV_FRM_RNE, vl);1369}1370 1371// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfncvt_f_x_w_f32mf2_rm1372// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1373// CHECK-RV64-NEXT:  entry:1374// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.x.w.nxv1f32.nxv1i64.i64(<vscale x 1 x float> poison, <vscale x 1 x i64> [[SRC]], i64 0, i64 [[VL]])1375// CHECK-RV64-NEXT:    ret <vscale x 1 x float> [[TMP0]]1376//1377vfloat32mf2_t test_vfncvt_f_x_w_f32mf2_rm(vint64m1_t src, size_t vl) {1378  return __riscv_vfncvt_f_x_w_f32mf2_rm(src, __RISCV_FRM_RNE, vl);1379}1380 1381// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfncvt_f_x_w_f32m1_rm1382// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1383// CHECK-RV64-NEXT:  entry:1384// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.x.w.nxv2f32.nxv2i64.i64(<vscale x 2 x float> poison, <vscale x 2 x i64> [[SRC]], i64 0, i64 [[VL]])1385// CHECK-RV64-NEXT:    ret <vscale x 2 x float> [[TMP0]]1386//1387vfloat32m1_t test_vfncvt_f_x_w_f32m1_rm(vint64m2_t src, size_t vl) {1388  return __riscv_vfncvt_f_x_w_f32m1_rm(src, __RISCV_FRM_RNE, vl);1389}1390 1391// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfncvt_f_x_w_f32m2_rm1392// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1393// CHECK-RV64-NEXT:  entry:1394// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.x.w.nxv4f32.nxv4i64.i64(<vscale x 4 x float> poison, <vscale x 4 x i64> [[SRC]], i64 0, i64 [[VL]])1395// CHECK-RV64-NEXT:    ret <vscale x 4 x float> [[TMP0]]1396//1397vfloat32m2_t test_vfncvt_f_x_w_f32m2_rm(vint64m4_t src, size_t vl) {1398  return __riscv_vfncvt_f_x_w_f32m2_rm(src, __RISCV_FRM_RNE, vl);1399}1400 1401// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfncvt_f_x_w_f32m4_rm1402// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1403// CHECK-RV64-NEXT:  entry:1404// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.x.w.nxv8f32.nxv8i64.i64(<vscale x 8 x float> poison, <vscale x 8 x i64> [[SRC]], i64 0, i64 [[VL]])1405// CHECK-RV64-NEXT:    ret <vscale x 8 x float> [[TMP0]]1406//1407vfloat32m4_t test_vfncvt_f_x_w_f32m4_rm(vint64m8_t src, size_t vl) {1408  return __riscv_vfncvt_f_x_w_f32m4_rm(src, __RISCV_FRM_RNE, vl);1409}1410 1411// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfncvt_f_xu_w_f32mf2_rm1412// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1413// CHECK-RV64-NEXT:  entry:1414// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.xu.w.nxv1f32.nxv1i64.i64(<vscale x 1 x float> poison, <vscale x 1 x i64> [[SRC]], i64 0, i64 [[VL]])1415// CHECK-RV64-NEXT:    ret <vscale x 1 x float> [[TMP0]]1416//1417vfloat32mf2_t test_vfncvt_f_xu_w_f32mf2_rm(vuint64m1_t src, size_t vl) {1418  return __riscv_vfncvt_f_xu_w_f32mf2_rm(src, __RISCV_FRM_RNE, vl);1419}1420 1421// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfncvt_f_xu_w_f32m1_rm1422// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1423// CHECK-RV64-NEXT:  entry:1424// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.xu.w.nxv2f32.nxv2i64.i64(<vscale x 2 x float> poison, <vscale x 2 x i64> [[SRC]], i64 0, i64 [[VL]])1425// CHECK-RV64-NEXT:    ret <vscale x 2 x float> [[TMP0]]1426//1427vfloat32m1_t test_vfncvt_f_xu_w_f32m1_rm(vuint64m2_t src, size_t vl) {1428  return __riscv_vfncvt_f_xu_w_f32m1_rm(src, __RISCV_FRM_RNE, vl);1429}1430 1431// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfncvt_f_xu_w_f32m2_rm1432// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1433// CHECK-RV64-NEXT:  entry:1434// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.xu.w.nxv4f32.nxv4i64.i64(<vscale x 4 x float> poison, <vscale x 4 x i64> [[SRC]], i64 0, i64 [[VL]])1435// CHECK-RV64-NEXT:    ret <vscale x 4 x float> [[TMP0]]1436//1437vfloat32m2_t test_vfncvt_f_xu_w_f32m2_rm(vuint64m4_t src, size_t vl) {1438  return __riscv_vfncvt_f_xu_w_f32m2_rm(src, __RISCV_FRM_RNE, vl);1439}1440 1441// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfncvt_f_xu_w_f32m4_rm1442// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1443// CHECK-RV64-NEXT:  entry:1444// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.xu.w.nxv8f32.nxv8i64.i64(<vscale x 8 x float> poison, <vscale x 8 x i64> [[SRC]], i64 0, i64 [[VL]])1445// CHECK-RV64-NEXT:    ret <vscale x 8 x float> [[TMP0]]1446//1447vfloat32m4_t test_vfncvt_f_xu_w_f32m4_rm(vuint64m8_t src, size_t vl) {1448  return __riscv_vfncvt_f_xu_w_f32m4_rm(src, __RISCV_FRM_RNE, vl);1449}1450 1451// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_i8mf8_rm_m1452// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1453// CHECK-RV64-NEXT:  entry:1454// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> poison, <vscale x 1 x half> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1455// CHECK-RV64-NEXT:    ret <vscale x 1 x i8> [[TMP0]]1456//1457vint8mf8_t test_vfncvt_x_f_w_i8mf8_rm_m(vbool64_t mask, vfloat16mf4_t src, size_t vl) {1458  return __riscv_vfncvt_x_f_w_i8mf8_rm_m(mask, src, __RISCV_FRM_RNE, vl);1459}1460 1461// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vfncvt_x_f_w_i8mf4_rm_m1462// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1463// CHECK-RV64-NEXT:  entry:1464// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> poison, <vscale x 2 x half> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1465// CHECK-RV64-NEXT:    ret <vscale x 2 x i8> [[TMP0]]1466//1467vint8mf4_t test_vfncvt_x_f_w_i8mf4_rm_m(vbool32_t mask, vfloat16mf2_t src, size_t vl) {1468  return __riscv_vfncvt_x_f_w_i8mf4_rm_m(mask, src, __RISCV_FRM_RNE, vl);1469}1470 1471// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vfncvt_x_f_w_i8mf2_rm_m1472// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1473// CHECK-RV64-NEXT:  entry:1474// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> poison, <vscale x 4 x half> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1475// CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[TMP0]]1476//1477vint8mf2_t test_vfncvt_x_f_w_i8mf2_rm_m(vbool16_t mask, vfloat16m1_t src, size_t vl) {1478  return __riscv_vfncvt_x_f_w_i8mf2_rm_m(mask, src, __RISCV_FRM_RNE, vl);1479}1480 1481// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vfncvt_x_f_w_i8m1_rm_m1482// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1483// CHECK-RV64-NEXT:  entry:1484// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> poison, <vscale x 8 x half> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1485// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]1486//1487vint8m1_t test_vfncvt_x_f_w_i8m1_rm_m(vbool8_t mask, vfloat16m2_t src, size_t vl) {1488  return __riscv_vfncvt_x_f_w_i8m1_rm_m(mask, src, __RISCV_FRM_RNE, vl);1489}1490 1491// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vfncvt_x_f_w_i8m2_rm_m1492// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1493// CHECK-RV64-NEXT:  entry:1494// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> poison, <vscale x 16 x half> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1495// CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]1496//1497vint8m2_t test_vfncvt_x_f_w_i8m2_rm_m(vbool4_t mask, vfloat16m4_t src, size_t vl) {1498  return __riscv_vfncvt_x_f_w_i8m2_rm_m(mask, src, __RISCV_FRM_RNE, vl);1499}1500 1501// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vfncvt_x_f_w_i8m4_rm_m1502// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1503// CHECK-RV64-NEXT:  entry:1504// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> poison, <vscale x 32 x half> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1505// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]1506//1507vint8m4_t test_vfncvt_x_f_w_i8m4_rm_m(vbool2_t mask, vfloat16m8_t src, size_t vl) {1508  return __riscv_vfncvt_x_f_w_i8m4_rm_m(mask, src, __RISCV_FRM_RNE, vl);1509}1510 1511// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vfncvt_xu_f_w_u8mf8_rm_m1512// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1513// CHECK-RV64-NEXT:  entry:1514// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> poison, <vscale x 1 x half> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1515// CHECK-RV64-NEXT:    ret <vscale x 1 x i8> [[TMP0]]1516//1517vuint8mf8_t test_vfncvt_xu_f_w_u8mf8_rm_m(vbool64_t mask, vfloat16mf4_t src, size_t vl) {1518  return __riscv_vfncvt_xu_f_w_u8mf8_rm_m(mask, src, __RISCV_FRM_RNE, vl);1519}1520 1521// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vfncvt_xu_f_w_u8mf4_rm_m1522// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1523// CHECK-RV64-NEXT:  entry:1524// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> poison, <vscale x 2 x half> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1525// CHECK-RV64-NEXT:    ret <vscale x 2 x i8> [[TMP0]]1526//1527vuint8mf4_t test_vfncvt_xu_f_w_u8mf4_rm_m(vbool32_t mask, vfloat16mf2_t src, size_t vl) {1528  return __riscv_vfncvt_xu_f_w_u8mf4_rm_m(mask, src, __RISCV_FRM_RNE, vl);1529}1530 1531// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vfncvt_xu_f_w_u8mf2_rm_m1532// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1533// CHECK-RV64-NEXT:  entry:1534// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> poison, <vscale x 4 x half> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1535// CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[TMP0]]1536//1537vuint8mf2_t test_vfncvt_xu_f_w_u8mf2_rm_m(vbool16_t mask, vfloat16m1_t src, size_t vl) {1538  return __riscv_vfncvt_xu_f_w_u8mf2_rm_m(mask, src, __RISCV_FRM_RNE, vl);1539}1540 1541// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vfncvt_xu_f_w_u8m1_rm_m1542// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1543// CHECK-RV64-NEXT:  entry:1544// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> poison, <vscale x 8 x half> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1545// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]1546//1547vuint8m1_t test_vfncvt_xu_f_w_u8m1_rm_m(vbool8_t mask, vfloat16m2_t src, size_t vl) {1548  return __riscv_vfncvt_xu_f_w_u8m1_rm_m(mask, src, __RISCV_FRM_RNE, vl);1549}1550 1551// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vfncvt_xu_f_w_u8m2_rm_m1552// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1553// CHECK-RV64-NEXT:  entry:1554// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> poison, <vscale x 16 x half> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1555// CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]1556//1557vuint8m2_t test_vfncvt_xu_f_w_u8m2_rm_m(vbool4_t mask, vfloat16m4_t src, size_t vl) {1558  return __riscv_vfncvt_xu_f_w_u8m2_rm_m(mask, src, __RISCV_FRM_RNE, vl);1559}1560 1561// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vfncvt_xu_f_w_u8m4_rm_m1562// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1563// CHECK-RV64-NEXT:  entry:1564// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> poison, <vscale x 32 x half> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1565// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]1566//1567vuint8m4_t test_vfncvt_xu_f_w_u8m4_rm_m(vbool2_t mask, vfloat16m8_t src, size_t vl) {1568  return __riscv_vfncvt_xu_f_w_u8m4_rm_m(mask, src, __RISCV_FRM_RNE, vl);1569}1570 1571// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vfncvt_x_f_w_i16mf4_rm_m1572// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1573// CHECK-RV64-NEXT:  entry:1574// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv1i16.nxv1f32.i64(<vscale x 1 x i16> poison, <vscale x 1 x float> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1575// CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]1576//1577vint16mf4_t test_vfncvt_x_f_w_i16mf4_rm_m(vbool64_t mask, vfloat32mf2_t src, size_t vl) {1578  return __riscv_vfncvt_x_f_w_i16mf4_rm_m(mask, src, __RISCV_FRM_RNE, vl);1579}1580 1581// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vfncvt_x_f_w_i16mf2_rm_m1582// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1583// CHECK-RV64-NEXT:  entry:1584// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv2i16.nxv2f32.i64(<vscale x 2 x i16> poison, <vscale x 2 x float> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1585// CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]1586//1587vint16mf2_t test_vfncvt_x_f_w_i16mf2_rm_m(vbool32_t mask, vfloat32m1_t src, size_t vl) {1588  return __riscv_vfncvt_x_f_w_i16mf2_rm_m(mask, src, __RISCV_FRM_RNE, vl);1589}1590 1591// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfncvt_x_f_w_i16m1_rm_m1592// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1593// CHECK-RV64-NEXT:  entry:1594// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv4i16.nxv4f32.i64(<vscale x 4 x i16> poison, <vscale x 4 x float> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1595// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]1596//1597vint16m1_t test_vfncvt_x_f_w_i16m1_rm_m(vbool16_t mask, vfloat32m2_t src, size_t vl) {1598  return __riscv_vfncvt_x_f_w_i16m1_rm_m(mask, src, __RISCV_FRM_RNE, vl);1599}1600 1601// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfncvt_x_f_w_i16m2_rm_m1602// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1603// CHECK-RV64-NEXT:  entry:1604// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv8i16.nxv8f32.i64(<vscale x 8 x i16> poison, <vscale x 8 x float> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1605// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]1606//1607vint16m2_t test_vfncvt_x_f_w_i16m2_rm_m(vbool8_t mask, vfloat32m4_t src, size_t vl) {1608  return __riscv_vfncvt_x_f_w_i16m2_rm_m(mask, src, __RISCV_FRM_RNE, vl);1609}1610 1611// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfncvt_x_f_w_i16m4_rm_m1612// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1613// CHECK-RV64-NEXT:  entry:1614// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv16i16.nxv16f32.i64(<vscale x 16 x i16> poison, <vscale x 16 x float> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1615// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]1616//1617vint16m4_t test_vfncvt_x_f_w_i16m4_rm_m(vbool4_t mask, vfloat32m8_t src, size_t vl) {1618  return __riscv_vfncvt_x_f_w_i16m4_rm_m(mask, src, __RISCV_FRM_RNE, vl);1619}1620 1621// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vfncvt_xu_f_w_u16mf4_rm_m1622// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1623// CHECK-RV64-NEXT:  entry:1624// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i16.nxv1f32.i64(<vscale x 1 x i16> poison, <vscale x 1 x float> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1625// CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]1626//1627vuint16mf4_t test_vfncvt_xu_f_w_u16mf4_rm_m(vbool64_t mask, vfloat32mf2_t src, size_t vl) {1628  return __riscv_vfncvt_xu_f_w_u16mf4_rm_m(mask, src, __RISCV_FRM_RNE, vl);1629}1630 1631// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vfncvt_xu_f_w_u16mf2_rm_m1632// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1633// CHECK-RV64-NEXT:  entry:1634// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv2i16.nxv2f32.i64(<vscale x 2 x i16> poison, <vscale x 2 x float> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1635// CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]1636//1637vuint16mf2_t test_vfncvt_xu_f_w_u16mf2_rm_m(vbool32_t mask, vfloat32m1_t src, size_t vl) {1638  return __riscv_vfncvt_xu_f_w_u16mf2_rm_m(mask, src, __RISCV_FRM_RNE, vl);1639}1640 1641// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfncvt_xu_f_w_u16m1_rm_m1642// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1643// CHECK-RV64-NEXT:  entry:1644// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv4i16.nxv4f32.i64(<vscale x 4 x i16> poison, <vscale x 4 x float> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1645// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]1646//1647vuint16m1_t test_vfncvt_xu_f_w_u16m1_rm_m(vbool16_t mask, vfloat32m2_t src, size_t vl) {1648  return __riscv_vfncvt_xu_f_w_u16m1_rm_m(mask, src, __RISCV_FRM_RNE, vl);1649}1650 1651// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfncvt_xu_f_w_u16m2_rm_m1652// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1653// CHECK-RV64-NEXT:  entry:1654// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv8i16.nxv8f32.i64(<vscale x 8 x i16> poison, <vscale x 8 x float> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1655// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]1656//1657vuint16m2_t test_vfncvt_xu_f_w_u16m2_rm_m(vbool8_t mask, vfloat32m4_t src, size_t vl) {1658  return __riscv_vfncvt_xu_f_w_u16m2_rm_m(mask, src, __RISCV_FRM_RNE, vl);1659}1660 1661// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfncvt_xu_f_w_u16m4_rm_m1662// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1663// CHECK-RV64-NEXT:  entry:1664// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv16i16.nxv16f32.i64(<vscale x 16 x i16> poison, <vscale x 16 x float> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1665// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]1666//1667vuint16m4_t test_vfncvt_xu_f_w_u16m4_rm_m(vbool4_t mask, vfloat32m8_t src, size_t vl) {1668  return __riscv_vfncvt_xu_f_w_u16m4_rm_m(mask, src, __RISCV_FRM_RNE, vl);1669}1670 1671// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfncvt_f_x_w_f16mf4_rm_m1672// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1673// CHECK-RV64-NEXT:  entry:1674// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv1f16.nxv1i32.i64(<vscale x 1 x half> poison, <vscale x 1 x i32> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1675// CHECK-RV64-NEXT:    ret <vscale x 1 x half> [[TMP0]]1676//1677vfloat16mf4_t test_vfncvt_f_x_w_f16mf4_rm_m(vbool64_t mask, vint32mf2_t src, size_t vl) {1678  return __riscv_vfncvt_f_x_w_f16mf4_rm_m(mask, src, __RISCV_FRM_RNE, vl);1679}1680 1681// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfncvt_f_x_w_f16mf2_rm_m1682// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1683// CHECK-RV64-NEXT:  entry:1684// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv2f16.nxv2i32.i64(<vscale x 2 x half> poison, <vscale x 2 x i32> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1685// CHECK-RV64-NEXT:    ret <vscale x 2 x half> [[TMP0]]1686//1687vfloat16mf2_t test_vfncvt_f_x_w_f16mf2_rm_m(vbool32_t mask, vint32m1_t src, size_t vl) {1688  return __riscv_vfncvt_f_x_w_f16mf2_rm_m(mask, src, __RISCV_FRM_RNE, vl);1689}1690 1691// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfncvt_f_x_w_f16m1_rm_m1692// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1693// CHECK-RV64-NEXT:  entry:1694// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv4f16.nxv4i32.i64(<vscale x 4 x half> poison, <vscale x 4 x i32> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1695// CHECK-RV64-NEXT:    ret <vscale x 4 x half> [[TMP0]]1696//1697vfloat16m1_t test_vfncvt_f_x_w_f16m1_rm_m(vbool16_t mask, vint32m2_t src, size_t vl) {1698  return __riscv_vfncvt_f_x_w_f16m1_rm_m(mask, src, __RISCV_FRM_RNE, vl);1699}1700 1701// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfncvt_f_x_w_f16m2_rm_m1702// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1703// CHECK-RV64-NEXT:  entry:1704// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv8f16.nxv8i32.i64(<vscale x 8 x half> poison, <vscale x 8 x i32> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1705// CHECK-RV64-NEXT:    ret <vscale x 8 x half> [[TMP0]]1706//1707vfloat16m2_t test_vfncvt_f_x_w_f16m2_rm_m(vbool8_t mask, vint32m4_t src, size_t vl) {1708  return __riscv_vfncvt_f_x_w_f16m2_rm_m(mask, src, __RISCV_FRM_RNE, vl);1709}1710 1711// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfncvt_f_x_w_f16m4_rm_m1712// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1713// CHECK-RV64-NEXT:  entry:1714// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv16f16.nxv16i32.i64(<vscale x 16 x half> poison, <vscale x 16 x i32> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1715// CHECK-RV64-NEXT:    ret <vscale x 16 x half> [[TMP0]]1716//1717vfloat16m4_t test_vfncvt_f_x_w_f16m4_rm_m(vbool4_t mask, vint32m8_t src, size_t vl) {1718  return __riscv_vfncvt_f_x_w_f16m4_rm_m(mask, src, __RISCV_FRM_RNE, vl);1719}1720 1721// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfncvt_f_xu_w_f16mf4_rm_m1722// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1723// CHECK-RV64-NEXT:  entry:1724// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv1f16.nxv1i32.i64(<vscale x 1 x half> poison, <vscale x 1 x i32> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1725// CHECK-RV64-NEXT:    ret <vscale x 1 x half> [[TMP0]]1726//1727vfloat16mf4_t test_vfncvt_f_xu_w_f16mf4_rm_m(vbool64_t mask, vuint32mf2_t src, size_t vl) {1728  return __riscv_vfncvt_f_xu_w_f16mf4_rm_m(mask, src, __RISCV_FRM_RNE, vl);1729}1730 1731// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfncvt_f_xu_w_f16mf2_rm_m1732// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1733// CHECK-RV64-NEXT:  entry:1734// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv2f16.nxv2i32.i64(<vscale x 2 x half> poison, <vscale x 2 x i32> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1735// CHECK-RV64-NEXT:    ret <vscale x 2 x half> [[TMP0]]1736//1737vfloat16mf2_t test_vfncvt_f_xu_w_f16mf2_rm_m(vbool32_t mask, vuint32m1_t src, size_t vl) {1738  return __riscv_vfncvt_f_xu_w_f16mf2_rm_m(mask, src, __RISCV_FRM_RNE, vl);1739}1740 1741// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfncvt_f_xu_w_f16m1_rm_m1742// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1743// CHECK-RV64-NEXT:  entry:1744// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv4f16.nxv4i32.i64(<vscale x 4 x half> poison, <vscale x 4 x i32> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1745// CHECK-RV64-NEXT:    ret <vscale x 4 x half> [[TMP0]]1746//1747vfloat16m1_t test_vfncvt_f_xu_w_f16m1_rm_m(vbool16_t mask, vuint32m2_t src, size_t vl) {1748  return __riscv_vfncvt_f_xu_w_f16m1_rm_m(mask, src, __RISCV_FRM_RNE, vl);1749}1750 1751// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfncvt_f_xu_w_f16m2_rm_m1752// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1753// CHECK-RV64-NEXT:  entry:1754// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv8f16.nxv8i32.i64(<vscale x 8 x half> poison, <vscale x 8 x i32> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1755// CHECK-RV64-NEXT:    ret <vscale x 8 x half> [[TMP0]]1756//1757vfloat16m2_t test_vfncvt_f_xu_w_f16m2_rm_m(vbool8_t mask, vuint32m4_t src, size_t vl) {1758  return __riscv_vfncvt_f_xu_w_f16m2_rm_m(mask, src, __RISCV_FRM_RNE, vl);1759}1760 1761// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfncvt_f_xu_w_f16m4_rm_m1762// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1763// CHECK-RV64-NEXT:  entry:1764// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv16f16.nxv16i32.i64(<vscale x 16 x half> poison, <vscale x 16 x i32> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1765// CHECK-RV64-NEXT:    ret <vscale x 16 x half> [[TMP0]]1766//1767vfloat16m4_t test_vfncvt_f_xu_w_f16m4_rm_m(vbool4_t mask, vuint32m8_t src, size_t vl) {1768  return __riscv_vfncvt_f_xu_w_f16m4_rm_m(mask, src, __RISCV_FRM_RNE, vl);1769}1770 1771// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfncvt_x_f_w_i32mf2_rm_m1772// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1773// CHECK-RV64-NEXT:  entry:1774// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfncvt.x.f.w.mask.nxv1i32.nxv1f64.i64(<vscale x 1 x i32> poison, <vscale x 1 x double> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1775// CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]1776//1777vint32mf2_t test_vfncvt_x_f_w_i32mf2_rm_m(vbool64_t mask, vfloat64m1_t src, size_t vl) {1778  return __riscv_vfncvt_x_f_w_i32mf2_rm_m(mask, src, __RISCV_FRM_RNE, vl);1779}1780 1781// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfncvt_x_f_w_i32m1_rm_m1782// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1783// CHECK-RV64-NEXT:  entry:1784// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfncvt.x.f.w.mask.nxv2i32.nxv2f64.i64(<vscale x 2 x i32> poison, <vscale x 2 x double> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1785// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]1786//1787vint32m1_t test_vfncvt_x_f_w_i32m1_rm_m(vbool32_t mask, vfloat64m2_t src, size_t vl) {1788  return __riscv_vfncvt_x_f_w_i32m1_rm_m(mask, src, __RISCV_FRM_RNE, vl);1789}1790 1791// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfncvt_x_f_w_i32m2_rm_m1792// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1793// CHECK-RV64-NEXT:  entry:1794// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfncvt.x.f.w.mask.nxv4i32.nxv4f64.i64(<vscale x 4 x i32> poison, <vscale x 4 x double> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1795// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]1796//1797vint32m2_t test_vfncvt_x_f_w_i32m2_rm_m(vbool16_t mask, vfloat64m4_t src, size_t vl) {1798  return __riscv_vfncvt_x_f_w_i32m2_rm_m(mask, src, __RISCV_FRM_RNE, vl);1799}1800 1801// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfncvt_x_f_w_i32m4_rm_m1802// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1803// CHECK-RV64-NEXT:  entry:1804// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfncvt.x.f.w.mask.nxv8i32.nxv8f64.i64(<vscale x 8 x i32> poison, <vscale x 8 x double> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1805// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]1806//1807vint32m4_t test_vfncvt_x_f_w_i32m4_rm_m(vbool8_t mask, vfloat64m8_t src, size_t vl) {1808  return __riscv_vfncvt_x_f_w_i32m4_rm_m(mask, src, __RISCV_FRM_RNE, vl);1809}1810 1811// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfncvt_xu_f_w_u32mf2_rm_m1812// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1813// CHECK-RV64-NEXT:  entry:1814// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i32.nxv1f64.i64(<vscale x 1 x i32> poison, <vscale x 1 x double> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1815// CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]1816//1817vuint32mf2_t test_vfncvt_xu_f_w_u32mf2_rm_m(vbool64_t mask, vfloat64m1_t src, size_t vl) {1818  return __riscv_vfncvt_xu_f_w_u32mf2_rm_m(mask, src, __RISCV_FRM_RNE, vl);1819}1820 1821// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfncvt_xu_f_w_u32m1_rm_m1822// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1823// CHECK-RV64-NEXT:  entry:1824// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfncvt.xu.f.w.mask.nxv2i32.nxv2f64.i64(<vscale x 2 x i32> poison, <vscale x 2 x double> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1825// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]1826//1827vuint32m1_t test_vfncvt_xu_f_w_u32m1_rm_m(vbool32_t mask, vfloat64m2_t src, size_t vl) {1828  return __riscv_vfncvt_xu_f_w_u32m1_rm_m(mask, src, __RISCV_FRM_RNE, vl);1829}1830 1831// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfncvt_xu_f_w_u32m2_rm_m1832// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1833// CHECK-RV64-NEXT:  entry:1834// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfncvt.xu.f.w.mask.nxv4i32.nxv4f64.i64(<vscale x 4 x i32> poison, <vscale x 4 x double> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1835// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]1836//1837vuint32m2_t test_vfncvt_xu_f_w_u32m2_rm_m(vbool16_t mask, vfloat64m4_t src, size_t vl) {1838  return __riscv_vfncvt_xu_f_w_u32m2_rm_m(mask, src, __RISCV_FRM_RNE, vl);1839}1840 1841// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfncvt_xu_f_w_u32m4_rm_m1842// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1843// CHECK-RV64-NEXT:  entry:1844// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfncvt.xu.f.w.mask.nxv8i32.nxv8f64.i64(<vscale x 8 x i32> poison, <vscale x 8 x double> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1845// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]1846//1847vuint32m4_t test_vfncvt_xu_f_w_u32m4_rm_m(vbool8_t mask, vfloat64m8_t src, size_t vl) {1848  return __riscv_vfncvt_xu_f_w_u32m4_rm_m(mask, src, __RISCV_FRM_RNE, vl);1849}1850 1851// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfncvt_f_x_w_f32mf2_rm_m1852// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1853// CHECK-RV64-NEXT:  entry:1854// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.x.w.mask.nxv1f32.nxv1i64.i64(<vscale x 1 x float> poison, <vscale x 1 x i64> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1855// CHECK-RV64-NEXT:    ret <vscale x 1 x float> [[TMP0]]1856//1857vfloat32mf2_t test_vfncvt_f_x_w_f32mf2_rm_m(vbool64_t mask, vint64m1_t src, size_t vl) {1858  return __riscv_vfncvt_f_x_w_f32mf2_rm_m(mask, src, __RISCV_FRM_RNE, vl);1859}1860 1861// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfncvt_f_x_w_f32m1_rm_m1862// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1863// CHECK-RV64-NEXT:  entry:1864// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.x.w.mask.nxv2f32.nxv2i64.i64(<vscale x 2 x float> poison, <vscale x 2 x i64> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1865// CHECK-RV64-NEXT:    ret <vscale x 2 x float> [[TMP0]]1866//1867vfloat32m1_t test_vfncvt_f_x_w_f32m1_rm_m(vbool32_t mask, vint64m2_t src, size_t vl) {1868  return __riscv_vfncvt_f_x_w_f32m1_rm_m(mask, src, __RISCV_FRM_RNE, vl);1869}1870 1871// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfncvt_f_x_w_f32m2_rm_m1872// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1873// CHECK-RV64-NEXT:  entry:1874// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.x.w.mask.nxv4f32.nxv4i64.i64(<vscale x 4 x float> poison, <vscale x 4 x i64> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1875// CHECK-RV64-NEXT:    ret <vscale x 4 x float> [[TMP0]]1876//1877vfloat32m2_t test_vfncvt_f_x_w_f32m2_rm_m(vbool16_t mask, vint64m4_t src, size_t vl) {1878  return __riscv_vfncvt_f_x_w_f32m2_rm_m(mask, src, __RISCV_FRM_RNE, vl);1879}1880 1881// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfncvt_f_x_w_f32m4_rm_m1882// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1883// CHECK-RV64-NEXT:  entry:1884// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.x.w.mask.nxv8f32.nxv8i64.i64(<vscale x 8 x float> poison, <vscale x 8 x i64> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1885// CHECK-RV64-NEXT:    ret <vscale x 8 x float> [[TMP0]]1886//1887vfloat32m4_t test_vfncvt_f_x_w_f32m4_rm_m(vbool8_t mask, vint64m8_t src, size_t vl) {1888  return __riscv_vfncvt_f_x_w_f32m4_rm_m(mask, src, __RISCV_FRM_RNE, vl);1889}1890 1891// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfncvt_f_xu_w_f32mf2_rm_m1892// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1893// CHECK-RV64-NEXT:  entry:1894// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.xu.w.mask.nxv1f32.nxv1i64.i64(<vscale x 1 x float> poison, <vscale x 1 x i64> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1895// CHECK-RV64-NEXT:    ret <vscale x 1 x float> [[TMP0]]1896//1897vfloat32mf2_t test_vfncvt_f_xu_w_f32mf2_rm_m(vbool64_t mask, vuint64m1_t src, size_t vl) {1898  return __riscv_vfncvt_f_xu_w_f32mf2_rm_m(mask, src, __RISCV_FRM_RNE, vl);1899}1900 1901// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfncvt_f_xu_w_f32m1_rm_m1902// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1903// CHECK-RV64-NEXT:  entry:1904// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.xu.w.mask.nxv2f32.nxv2i64.i64(<vscale x 2 x float> poison, <vscale x 2 x i64> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1905// CHECK-RV64-NEXT:    ret <vscale x 2 x float> [[TMP0]]1906//1907vfloat32m1_t test_vfncvt_f_xu_w_f32m1_rm_m(vbool32_t mask, vuint64m2_t src, size_t vl) {1908  return __riscv_vfncvt_f_xu_w_f32m1_rm_m(mask, src, __RISCV_FRM_RNE, vl);1909}1910 1911// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfncvt_f_xu_w_f32m2_rm_m1912// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1913// CHECK-RV64-NEXT:  entry:1914// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.xu.w.mask.nxv4f32.nxv4i64.i64(<vscale x 4 x float> poison, <vscale x 4 x i64> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1915// CHECK-RV64-NEXT:    ret <vscale x 4 x float> [[TMP0]]1916//1917vfloat32m2_t test_vfncvt_f_xu_w_f32m2_rm_m(vbool16_t mask, vuint64m4_t src, size_t vl) {1918  return __riscv_vfncvt_f_xu_w_f32m2_rm_m(mask, src, __RISCV_FRM_RNE, vl);1919}1920 1921// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfncvt_f_xu_w_f32m4_rm_m1922// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1923// CHECK-RV64-NEXT:  entry:1924// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.xu.w.mask.nxv8f32.nxv8i64.i64(<vscale x 8 x float> poison, <vscale x 8 x i64> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1925// CHECK-RV64-NEXT:    ret <vscale x 8 x float> [[TMP0]]1926//1927vfloat32m4_t test_vfncvt_f_xu_w_f32m4_rm_m(vbool8_t mask, vuint64m8_t src, size_t vl) {1928  return __riscv_vfncvt_f_xu_w_f32m4_rm_m(mask, src, __RISCV_FRM_RNE, vl);1929}1930 1931