370 lines · c
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 22// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \4// RUN: -target-feature +zvfh -disable-O0-optnone \5// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \6// RUN: FileCheck --check-prefix=CHECK-RV64 %s7 8#include <riscv_vector.h>9 10// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfwcvt_rtz_x_f_v_i32mf211// CHECK-RV64-SAME: (<vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {12// CHECK-RV64-NEXT: entry:13// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> poison, <vscale x 1 x half> [[SRC]], i64 [[VL]])14// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]15//16vint32mf2_t test_vfwcvt_rtz_x_f_v_i32mf2(vfloat16mf4_t src, size_t vl) {17 return __riscv_vfwcvt_rtz_x_f_v_i32mf2(src, vl);18}19 20// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfwcvt_rtz_x_f_v_i32m121// CHECK-RV64-SAME: (<vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {22// CHECK-RV64-NEXT: entry:23// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> poison, <vscale x 2 x half> [[SRC]], i64 [[VL]])24// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]25//26vint32m1_t test_vfwcvt_rtz_x_f_v_i32m1(vfloat16mf2_t src, size_t vl) {27 return __riscv_vfwcvt_rtz_x_f_v_i32m1(src, vl);28}29 30// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfwcvt_rtz_x_f_v_i32m231// CHECK-RV64-SAME: (<vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {32// CHECK-RV64-NEXT: entry:33// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> poison, <vscale x 4 x half> [[SRC]], i64 [[VL]])34// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]35//36vint32m2_t test_vfwcvt_rtz_x_f_v_i32m2(vfloat16m1_t src, size_t vl) {37 return __riscv_vfwcvt_rtz_x_f_v_i32m2(src, vl);38}39 40// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfwcvt_rtz_x_f_v_i32m441// CHECK-RV64-SAME: (<vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {42// CHECK-RV64-NEXT: entry:43// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> poison, <vscale x 8 x half> [[SRC]], i64 [[VL]])44// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]45//46vint32m4_t test_vfwcvt_rtz_x_f_v_i32m4(vfloat16m2_t src, size_t vl) {47 return __riscv_vfwcvt_rtz_x_f_v_i32m4(src, vl);48}49 50// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfwcvt_rtz_x_f_v_i32m851// CHECK-RV64-SAME: (<vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {52// CHECK-RV64-NEXT: entry:53// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> poison, <vscale x 16 x half> [[SRC]], i64 [[VL]])54// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]55//56vint32m8_t test_vfwcvt_rtz_x_f_v_i32m8(vfloat16m4_t src, size_t vl) {57 return __riscv_vfwcvt_rtz_x_f_v_i32m8(src, vl);58}59 60// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfwcvt_rtz_xu_f_v_u32mf261// CHECK-RV64-SAME: (<vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {62// CHECK-RV64-NEXT: entry:63// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> poison, <vscale x 1 x half> [[SRC]], i64 [[VL]])64// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]65//66vuint32mf2_t test_vfwcvt_rtz_xu_f_v_u32mf2(vfloat16mf4_t src, size_t vl) {67 return __riscv_vfwcvt_rtz_xu_f_v_u32mf2(src, vl);68}69 70// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfwcvt_rtz_xu_f_v_u32m171// CHECK-RV64-SAME: (<vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {72// CHECK-RV64-NEXT: entry:73// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> poison, <vscale x 2 x half> [[SRC]], i64 [[VL]])74// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]75//76vuint32m1_t test_vfwcvt_rtz_xu_f_v_u32m1(vfloat16mf2_t src, size_t vl) {77 return __riscv_vfwcvt_rtz_xu_f_v_u32m1(src, vl);78}79 80// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfwcvt_rtz_xu_f_v_u32m281// CHECK-RV64-SAME: (<vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {82// CHECK-RV64-NEXT: entry:83// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> poison, <vscale x 4 x half> [[SRC]], i64 [[VL]])84// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]85//86vuint32m2_t test_vfwcvt_rtz_xu_f_v_u32m2(vfloat16m1_t src, size_t vl) {87 return __riscv_vfwcvt_rtz_xu_f_v_u32m2(src, vl);88}89 90// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfwcvt_rtz_xu_f_v_u32m491// CHECK-RV64-SAME: (<vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {92// CHECK-RV64-NEXT: entry:93// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> poison, <vscale x 8 x half> [[SRC]], i64 [[VL]])94// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]95//96vuint32m4_t test_vfwcvt_rtz_xu_f_v_u32m4(vfloat16m2_t src, size_t vl) {97 return __riscv_vfwcvt_rtz_xu_f_v_u32m4(src, vl);98}99 100// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfwcvt_rtz_xu_f_v_u32m8101// CHECK-RV64-SAME: (<vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {102// CHECK-RV64-NEXT: entry:103// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> poison, <vscale x 16 x half> [[SRC]], i64 [[VL]])104// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]105//106vuint32m8_t test_vfwcvt_rtz_xu_f_v_u32m8(vfloat16m4_t src, size_t vl) {107 return __riscv_vfwcvt_rtz_xu_f_v_u32m8(src, vl);108}109 110// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfwcvt_rtz_x_f_v_i64m1111// CHECK-RV64-SAME: (<vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {112// CHECK-RV64-NEXT: entry:113// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32.i64(<vscale x 1 x i64> poison, <vscale x 1 x float> [[SRC]], i64 [[VL]])114// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]115//116vint64m1_t test_vfwcvt_rtz_x_f_v_i64m1(vfloat32mf2_t src, size_t vl) {117 return __riscv_vfwcvt_rtz_x_f_v_i64m1(src, vl);118}119 120// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfwcvt_rtz_x_f_v_i64m2121// CHECK-RV64-SAME: (<vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {122// CHECK-RV64-NEXT: entry:123// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i64.nxv2f32.i64(<vscale x 2 x i64> poison, <vscale x 2 x float> [[SRC]], i64 [[VL]])124// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]125//126vint64m2_t test_vfwcvt_rtz_x_f_v_i64m2(vfloat32m1_t src, size_t vl) {127 return __riscv_vfwcvt_rtz_x_f_v_i64m2(src, vl);128}129 130// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfwcvt_rtz_x_f_v_i64m4131// CHECK-RV64-SAME: (<vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {132// CHECK-RV64-NEXT: entry:133// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i64.nxv4f32.i64(<vscale x 4 x i64> poison, <vscale x 4 x float> [[SRC]], i64 [[VL]])134// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]135//136vint64m4_t test_vfwcvt_rtz_x_f_v_i64m4(vfloat32m2_t src, size_t vl) {137 return __riscv_vfwcvt_rtz_x_f_v_i64m4(src, vl);138}139 140// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfwcvt_rtz_x_f_v_i64m8141// CHECK-RV64-SAME: (<vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {142// CHECK-RV64-NEXT: entry:143// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i64.nxv8f32.i64(<vscale x 8 x i64> poison, <vscale x 8 x float> [[SRC]], i64 [[VL]])144// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]145//146vint64m8_t test_vfwcvt_rtz_x_f_v_i64m8(vfloat32m4_t src, size_t vl) {147 return __riscv_vfwcvt_rtz_x_f_v_i64m8(src, vl);148}149 150// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfwcvt_rtz_xu_f_v_u64m1151// CHECK-RV64-SAME: (<vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {152// CHECK-RV64-NEXT: entry:153// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i64.nxv1f32.i64(<vscale x 1 x i64> poison, <vscale x 1 x float> [[SRC]], i64 [[VL]])154// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]155//156vuint64m1_t test_vfwcvt_rtz_xu_f_v_u64m1(vfloat32mf2_t src, size_t vl) {157 return __riscv_vfwcvt_rtz_xu_f_v_u64m1(src, vl);158}159 160// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfwcvt_rtz_xu_f_v_u64m2161// CHECK-RV64-SAME: (<vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {162// CHECK-RV64-NEXT: entry:163// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i64.nxv2f32.i64(<vscale x 2 x i64> poison, <vscale x 2 x float> [[SRC]], i64 [[VL]])164// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]165//166vuint64m2_t test_vfwcvt_rtz_xu_f_v_u64m2(vfloat32m1_t src, size_t vl) {167 return __riscv_vfwcvt_rtz_xu_f_v_u64m2(src, vl);168}169 170// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfwcvt_rtz_xu_f_v_u64m4171// CHECK-RV64-SAME: (<vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {172// CHECK-RV64-NEXT: entry:173// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i64.nxv4f32.i64(<vscale x 4 x i64> poison, <vscale x 4 x float> [[SRC]], i64 [[VL]])174// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]175//176vuint64m4_t test_vfwcvt_rtz_xu_f_v_u64m4(vfloat32m2_t src, size_t vl) {177 return __riscv_vfwcvt_rtz_xu_f_v_u64m4(src, vl);178}179 180// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfwcvt_rtz_xu_f_v_u64m8181// CHECK-RV64-SAME: (<vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {182// CHECK-RV64-NEXT: entry:183// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i64.nxv8f32.i64(<vscale x 8 x i64> poison, <vscale x 8 x float> [[SRC]], i64 [[VL]])184// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]185//186vuint64m8_t test_vfwcvt_rtz_xu_f_v_u64m8(vfloat32m4_t src, size_t vl) {187 return __riscv_vfwcvt_rtz_xu_f_v_u64m8(src, vl);188}189 190// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfwcvt_rtz_x_f_v_i32mf2_m191// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {192// CHECK-RV64-NEXT: entry:193// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> poison, <vscale x 1 x half> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)194// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]195//196vint32mf2_t test_vfwcvt_rtz_x_f_v_i32mf2_m(vbool64_t mask, vfloat16mf4_t src, size_t vl) {197 return __riscv_vfwcvt_rtz_x_f_v_i32mf2_m(mask, src, vl);198}199 200// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfwcvt_rtz_x_f_v_i32m1_m201// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {202// CHECK-RV64-NEXT: entry:203// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> poison, <vscale x 2 x half> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)204// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]205//206vint32m1_t test_vfwcvt_rtz_x_f_v_i32m1_m(vbool32_t mask, vfloat16mf2_t src, size_t vl) {207 return __riscv_vfwcvt_rtz_x_f_v_i32m1_m(mask, src, vl);208}209 210// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfwcvt_rtz_x_f_v_i32m2_m211// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {212// CHECK-RV64-NEXT: entry:213// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> poison, <vscale x 4 x half> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)214// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]215//216vint32m2_t test_vfwcvt_rtz_x_f_v_i32m2_m(vbool16_t mask, vfloat16m1_t src, size_t vl) {217 return __riscv_vfwcvt_rtz_x_f_v_i32m2_m(mask, src, vl);218}219 220// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfwcvt_rtz_x_f_v_i32m4_m221// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {222// CHECK-RV64-NEXT: entry:223// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> poison, <vscale x 8 x half> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)224// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]225//226vint32m4_t test_vfwcvt_rtz_x_f_v_i32m4_m(vbool8_t mask, vfloat16m2_t src, size_t vl) {227 return __riscv_vfwcvt_rtz_x_f_v_i32m4_m(mask, src, vl);228}229 230// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfwcvt_rtz_x_f_v_i32m8_m231// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {232// CHECK-RV64-NEXT: entry:233// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> poison, <vscale x 16 x half> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3)234// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]235//236vint32m8_t test_vfwcvt_rtz_x_f_v_i32m8_m(vbool4_t mask, vfloat16m4_t src, size_t vl) {237 return __riscv_vfwcvt_rtz_x_f_v_i32m8_m(mask, src, vl);238}239 240// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfwcvt_rtz_xu_f_v_u32mf2_m241// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {242// CHECK-RV64-NEXT: entry:243// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> poison, <vscale x 1 x half> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)244// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]245//246vuint32mf2_t test_vfwcvt_rtz_xu_f_v_u32mf2_m(vbool64_t mask, vfloat16mf4_t src, size_t vl) {247 return __riscv_vfwcvt_rtz_xu_f_v_u32mf2_m(mask, src, vl);248}249 250// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfwcvt_rtz_xu_f_v_u32m1_m251// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {252// CHECK-RV64-NEXT: entry:253// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> poison, <vscale x 2 x half> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)254// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]255//256vuint32m1_t test_vfwcvt_rtz_xu_f_v_u32m1_m(vbool32_t mask, vfloat16mf2_t src, size_t vl) {257 return __riscv_vfwcvt_rtz_xu_f_v_u32m1_m(mask, src, vl);258}259 260// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfwcvt_rtz_xu_f_v_u32m2_m261// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {262// CHECK-RV64-NEXT: entry:263// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> poison, <vscale x 4 x half> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)264// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]265//266vuint32m2_t test_vfwcvt_rtz_xu_f_v_u32m2_m(vbool16_t mask, vfloat16m1_t src, size_t vl) {267 return __riscv_vfwcvt_rtz_xu_f_v_u32m2_m(mask, src, vl);268}269 270// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfwcvt_rtz_xu_f_v_u32m4_m271// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {272// CHECK-RV64-NEXT: entry:273// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> poison, <vscale x 8 x half> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)274// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]275//276vuint32m4_t test_vfwcvt_rtz_xu_f_v_u32m4_m(vbool8_t mask, vfloat16m2_t src, size_t vl) {277 return __riscv_vfwcvt_rtz_xu_f_v_u32m4_m(mask, src, vl);278}279 280// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfwcvt_rtz_xu_f_v_u32m8_m281// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {282// CHECK-RV64-NEXT: entry:283// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> poison, <vscale x 16 x half> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3)284// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]285//286vuint32m8_t test_vfwcvt_rtz_xu_f_v_u32m8_m(vbool4_t mask, vfloat16m4_t src, size_t vl) {287 return __riscv_vfwcvt_rtz_xu_f_v_u32m8_m(mask, src, vl);288}289 290// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfwcvt_rtz_x_f_v_i64m1_m291// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {292// CHECK-RV64-NEXT: entry:293// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv1i64.nxv1f32.i64(<vscale x 1 x i64> poison, <vscale x 1 x float> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)294// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]295//296vint64m1_t test_vfwcvt_rtz_x_f_v_i64m1_m(vbool64_t mask, vfloat32mf2_t src, size_t vl) {297 return __riscv_vfwcvt_rtz_x_f_v_i64m1_m(mask, src, vl);298}299 300// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfwcvt_rtz_x_f_v_i64m2_m301// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {302// CHECK-RV64-NEXT: entry:303// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv2i64.nxv2f32.i64(<vscale x 2 x i64> poison, <vscale x 2 x float> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)304// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]305//306vint64m2_t test_vfwcvt_rtz_x_f_v_i64m2_m(vbool32_t mask, vfloat32m1_t src, size_t vl) {307 return __riscv_vfwcvt_rtz_x_f_v_i64m2_m(mask, src, vl);308}309 310// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfwcvt_rtz_x_f_v_i64m4_m311// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {312// CHECK-RV64-NEXT: entry:313// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv4i64.nxv4f32.i64(<vscale x 4 x i64> poison, <vscale x 4 x float> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)314// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]315//316vint64m4_t test_vfwcvt_rtz_x_f_v_i64m4_m(vbool16_t mask, vfloat32m2_t src, size_t vl) {317 return __riscv_vfwcvt_rtz_x_f_v_i64m4_m(mask, src, vl);318}319 320// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfwcvt_rtz_x_f_v_i64m8_m321// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {322// CHECK-RV64-NEXT: entry:323// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv8i64.nxv8f32.i64(<vscale x 8 x i64> poison, <vscale x 8 x float> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)324// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]325//326vint64m8_t test_vfwcvt_rtz_x_f_v_i64m8_m(vbool8_t mask, vfloat32m4_t src, size_t vl) {327 return __riscv_vfwcvt_rtz_x_f_v_i64m8_m(mask, src, vl);328}329 330// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfwcvt_rtz_xu_f_v_u64m1_m331// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {332// CHECK-RV64-NEXT: entry:333// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv1i64.nxv1f32.i64(<vscale x 1 x i64> poison, <vscale x 1 x float> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)334// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]335//336vuint64m1_t test_vfwcvt_rtz_xu_f_v_u64m1_m(vbool64_t mask, vfloat32mf2_t src, size_t vl) {337 return __riscv_vfwcvt_rtz_xu_f_v_u64m1_m(mask, src, vl);338}339 340// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfwcvt_rtz_xu_f_v_u64m2_m341// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {342// CHECK-RV64-NEXT: entry:343// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv2i64.nxv2f32.i64(<vscale x 2 x i64> poison, <vscale x 2 x float> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)344// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]345//346vuint64m2_t test_vfwcvt_rtz_xu_f_v_u64m2_m(vbool32_t mask, vfloat32m1_t src, size_t vl) {347 return __riscv_vfwcvt_rtz_xu_f_v_u64m2_m(mask, src, vl);348}349 350// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfwcvt_rtz_xu_f_v_u64m4_m351// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {352// CHECK-RV64-NEXT: entry:353// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv4i64.nxv4f32.i64(<vscale x 4 x i64> poison, <vscale x 4 x float> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)354// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]355//356vuint64m4_t test_vfwcvt_rtz_xu_f_v_u64m4_m(vbool16_t mask, vfloat32m2_t src, size_t vl) {357 return __riscv_vfwcvt_rtz_xu_f_v_u64m4_m(mask, src, vl);358}359 360// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfwcvt_rtz_xu_f_v_u64m8_m361// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {362// CHECK-RV64-NEXT: entry:363// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv8i64.nxv8f32.i64(<vscale x 8 x i64> poison, <vscale x 8 x float> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)364// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]365//366vuint64m8_t test_vfwcvt_rtz_xu_f_v_u64m8_m(vbool8_t mask, vfloat32m4_t src, size_t vl) {367 return __riscv_vfwcvt_rtz_xu_f_v_u64m8_m(mask, src, vl);368}369 370