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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 22// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \4// RUN: -target-feature +zvfh -disable-O0-optnone \5// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \6// RUN: FileCheck --check-prefix=CHECK-RV64 %s7 8#include <riscv_vector.h>9 10// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwnmacc_vv_f32mf211// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {12// CHECK-RV64-NEXT: entry:13// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)14// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]15//16vfloat32mf2_t test_vfwnmacc_vv_f32mf2(vfloat32mf2_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {17 return __riscv_vfwnmacc_vv_f32mf2(vd, vs1, vs2, vl);18}19 20// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwnmacc_vf_f32mf221// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], half noundef [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {22// CHECK-RV64-NEXT: entry:23// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> [[VD]], half [[VS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)24// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]25//26vfloat32mf2_t test_vfwnmacc_vf_f32mf2(vfloat32mf2_t vd, _Float16 vs1, vfloat16mf4_t vs2, size_t vl) {27 return __riscv_vfwnmacc_vf_f32mf2(vd, vs1, vs2, vl);28}29 30// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwnmacc_vv_f32m131// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {32// CHECK-RV64-NEXT: entry:33// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)34// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]35//36vfloat32m1_t test_vfwnmacc_vv_f32m1(vfloat32m1_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {37 return __riscv_vfwnmacc_vv_f32m1(vd, vs1, vs2, vl);38}39 40// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwnmacc_vf_f32m141// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], half noundef [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {42// CHECK-RV64-NEXT: entry:43// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> [[VD]], half [[VS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)44// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]45//46vfloat32m1_t test_vfwnmacc_vf_f32m1(vfloat32m1_t vd, _Float16 vs1, vfloat16mf2_t vs2, size_t vl) {47 return __riscv_vfwnmacc_vf_f32m1(vd, vs1, vs2, vl);48}49 50// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwnmacc_vv_f32m251// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {52// CHECK-RV64-NEXT: entry:53// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)54// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]55//56vfloat32m2_t test_vfwnmacc_vv_f32m2(vfloat32m2_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {57 return __riscv_vfwnmacc_vv_f32m2(vd, vs1, vs2, vl);58}59 60// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwnmacc_vf_f32m261// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], half noundef [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {62// CHECK-RV64-NEXT: entry:63// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> [[VD]], half [[VS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)64// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]65//66vfloat32m2_t test_vfwnmacc_vf_f32m2(vfloat32m2_t vd, _Float16 vs1, vfloat16m1_t vs2, size_t vl) {67 return __riscv_vfwnmacc_vf_f32m2(vd, vs1, vs2, vl);68}69 70// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwnmacc_vv_f32m471// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {72// CHECK-RV64-NEXT: entry:73// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)74// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]75//76vfloat32m4_t test_vfwnmacc_vv_f32m4(vfloat32m4_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {77 return __riscv_vfwnmacc_vv_f32m4(vd, vs1, vs2, vl);78}79 80// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwnmacc_vf_f32m481// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], half noundef [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {82// CHECK-RV64-NEXT: entry:83// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> [[VD]], half [[VS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)84// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]85//86vfloat32m4_t test_vfwnmacc_vf_f32m4(vfloat32m4_t vd, _Float16 vs1, vfloat16m2_t vs2, size_t vl) {87 return __riscv_vfwnmacc_vf_f32m4(vd, vs1, vs2, vl);88}89 90// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwnmacc_vv_f32m891// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {92// CHECK-RV64-NEXT: entry:93// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwnmacc.nxv16f32.nxv16f16.nxv16f16.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)94// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]95//96vfloat32m8_t test_vfwnmacc_vv_f32m8(vfloat32m8_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {97 return __riscv_vfwnmacc_vv_f32m8(vd, vs1, vs2, vl);98}99 100// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwnmacc_vf_f32m8101// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], half noundef [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {102// CHECK-RV64-NEXT: entry:103// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwnmacc.nxv16f32.f16.nxv16f16.i64(<vscale x 16 x float> [[VD]], half [[VS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)104// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]105//106vfloat32m8_t test_vfwnmacc_vf_f32m8(vfloat32m8_t vd, _Float16 vs1, vfloat16m4_t vs2, size_t vl) {107 return __riscv_vfwnmacc_vf_f32m8(vd, vs1, vs2, vl);108}109 110// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwnmacc_vv_f64m1111// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {112// CHECK-RV64-NEXT: entry:113// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwnmacc.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)114// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]115//116vfloat64m1_t test_vfwnmacc_vv_f64m1(vfloat64m1_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {117 return __riscv_vfwnmacc_vv_f64m1(vd, vs1, vs2, vl);118}119 120// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwnmacc_vf_f64m1121// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], float noundef [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {122// CHECK-RV64-NEXT: entry:123// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwnmacc.nxv1f64.f32.nxv1f32.i64(<vscale x 1 x double> [[VD]], float [[VS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)124// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]125//126vfloat64m1_t test_vfwnmacc_vf_f64m1(vfloat64m1_t vd, float vs1, vfloat32mf2_t vs2, size_t vl) {127 return __riscv_vfwnmacc_vf_f64m1(vd, vs1, vs2, vl);128}129 130// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfwnmacc_vv_f64m2131// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {132// CHECK-RV64-NEXT: entry:133// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwnmacc.nxv2f64.nxv2f32.nxv2f32.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)134// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]135//136vfloat64m2_t test_vfwnmacc_vv_f64m2(vfloat64m2_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {137 return __riscv_vfwnmacc_vv_f64m2(vd, vs1, vs2, vl);138}139 140// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfwnmacc_vf_f64m2141// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], float noundef [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {142// CHECK-RV64-NEXT: entry:143// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwnmacc.nxv2f64.f32.nxv2f32.i64(<vscale x 2 x double> [[VD]], float [[VS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)144// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]145//146vfloat64m2_t test_vfwnmacc_vf_f64m2(vfloat64m2_t vd, float vs1, vfloat32m1_t vs2, size_t vl) {147 return __riscv_vfwnmacc_vf_f64m2(vd, vs1, vs2, vl);148}149 150// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfwnmacc_vv_f64m4151// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {152// CHECK-RV64-NEXT: entry:153// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwnmacc.nxv4f64.nxv4f32.nxv4f32.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)154// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]155//156vfloat64m4_t test_vfwnmacc_vv_f64m4(vfloat64m4_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {157 return __riscv_vfwnmacc_vv_f64m4(vd, vs1, vs2, vl);158}159 160// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfwnmacc_vf_f64m4161// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], float noundef [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {162// CHECK-RV64-NEXT: entry:163// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwnmacc.nxv4f64.f32.nxv4f32.i64(<vscale x 4 x double> [[VD]], float [[VS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)164// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]165//166vfloat64m4_t test_vfwnmacc_vf_f64m4(vfloat64m4_t vd, float vs1, vfloat32m2_t vs2, size_t vl) {167 return __riscv_vfwnmacc_vf_f64m4(vd, vs1, vs2, vl);168}169 170// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfwnmacc_vv_f64m8171// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {172// CHECK-RV64-NEXT: entry:173// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwnmacc.nxv8f64.nxv8f32.nxv8f32.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)174// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]175//176vfloat64m8_t test_vfwnmacc_vv_f64m8(vfloat64m8_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {177 return __riscv_vfwnmacc_vv_f64m8(vd, vs1, vs2, vl);178}179 180// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfwnmacc_vf_f64m8181// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], float noundef [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {182// CHECK-RV64-NEXT: entry:183// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwnmacc.nxv8f64.f32.nxv8f32.i64(<vscale x 8 x double> [[VD]], float [[VS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)184// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]185//186vfloat64m8_t test_vfwnmacc_vf_f64m8(vfloat64m8_t vd, float vs1, vfloat32m4_t vs2, size_t vl) {187 return __riscv_vfwnmacc_vf_f64m8(vd, vs1, vs2, vl);188}189 190// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwnmacc_vv_f32mf2_m191// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {192// CHECK-RV64-NEXT: entry:193// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.mask.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)194// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]195//196vfloat32mf2_t test_vfwnmacc_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {197 return __riscv_vfwnmacc_vv_f32mf2_m(mask, vd, vs1, vs2, vl);198}199 200// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwnmacc_vf_f32mf2_m201// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], half noundef [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {202// CHECK-RV64-NEXT: entry:203// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.mask.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> [[VD]], half [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)204// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]205//206vfloat32mf2_t test_vfwnmacc_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, _Float16 vs1, vfloat16mf4_t vs2, size_t vl) {207 return __riscv_vfwnmacc_vf_f32mf2_m(mask, vd, vs1, vs2, vl);208}209 210// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwnmacc_vv_f32m1_m211// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {212// CHECK-RV64-NEXT: entry:213// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.mask.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)214// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]215//216vfloat32m1_t test_vfwnmacc_vv_f32m1_m(vbool32_t mask, vfloat32m1_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {217 return __riscv_vfwnmacc_vv_f32m1_m(mask, vd, vs1, vs2, vl);218}219 220// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwnmacc_vf_f32m1_m221// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], half noundef [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {222// CHECK-RV64-NEXT: entry:223// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.mask.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> [[VD]], half [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)224// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]225//226vfloat32m1_t test_vfwnmacc_vf_f32m1_m(vbool32_t mask, vfloat32m1_t vd, _Float16 vs1, vfloat16mf2_t vs2, size_t vl) {227 return __riscv_vfwnmacc_vf_f32m1_m(mask, vd, vs1, vs2, vl);228}229 230// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwnmacc_vv_f32m2_m231// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {232// CHECK-RV64-NEXT: entry:233// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.mask.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)234// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]235//236vfloat32m2_t test_vfwnmacc_vv_f32m2_m(vbool16_t mask, vfloat32m2_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {237 return __riscv_vfwnmacc_vv_f32m2_m(mask, vd, vs1, vs2, vl);238}239 240// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwnmacc_vf_f32m2_m241// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], half noundef [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {242// CHECK-RV64-NEXT: entry:243// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.mask.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> [[VD]], half [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)244// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]245//246vfloat32m2_t test_vfwnmacc_vf_f32m2_m(vbool16_t mask, vfloat32m2_t vd, _Float16 vs1, vfloat16m1_t vs2, size_t vl) {247 return __riscv_vfwnmacc_vf_f32m2_m(mask, vd, vs1, vs2, vl);248}249 250// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwnmacc_vv_f32m4_m251// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {252// CHECK-RV64-NEXT: entry:253// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.mask.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)254// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]255//256vfloat32m4_t test_vfwnmacc_vv_f32m4_m(vbool8_t mask, vfloat32m4_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {257 return __riscv_vfwnmacc_vv_f32m4_m(mask, vd, vs1, vs2, vl);258}259 260// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwnmacc_vf_f32m4_m261// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], half noundef [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {262// CHECK-RV64-NEXT: entry:263// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.mask.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> [[VD]], half [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)264// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]265//266vfloat32m4_t test_vfwnmacc_vf_f32m4_m(vbool8_t mask, vfloat32m4_t vd, _Float16 vs1, vfloat16m2_t vs2, size_t vl) {267 return __riscv_vfwnmacc_vf_f32m4_m(mask, vd, vs1, vs2, vl);268}269 270// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwnmacc_vv_f32m8_m271// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {272// CHECK-RV64-NEXT: entry:273// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwnmacc.mask.nxv16f32.nxv16f16.nxv16f16.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)274// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]275//276vfloat32m8_t test_vfwnmacc_vv_f32m8_m(vbool4_t mask, vfloat32m8_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {277 return __riscv_vfwnmacc_vv_f32m8_m(mask, vd, vs1, vs2, vl);278}279 280// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwnmacc_vf_f32m8_m281// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], half noundef [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {282// CHECK-RV64-NEXT: entry:283// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwnmacc.mask.nxv16f32.f16.nxv16f16.i64(<vscale x 16 x float> [[VD]], half [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)284// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]285//286vfloat32m8_t test_vfwnmacc_vf_f32m8_m(vbool4_t mask, vfloat32m8_t vd, _Float16 vs1, vfloat16m4_t vs2, size_t vl) {287 return __riscv_vfwnmacc_vf_f32m8_m(mask, vd, vs1, vs2, vl);288}289 290// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwnmacc_vv_f64m1_m291// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {292// CHECK-RV64-NEXT: entry:293// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwnmacc.mask.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)294// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]295//296vfloat64m1_t test_vfwnmacc_vv_f64m1_m(vbool64_t mask, vfloat64m1_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {297 return __riscv_vfwnmacc_vv_f64m1_m(mask, vd, vs1, vs2, vl);298}299 300// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwnmacc_vf_f64m1_m301// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], float noundef [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {302// CHECK-RV64-NEXT: entry:303// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwnmacc.mask.nxv1f64.f32.nxv1f32.i64(<vscale x 1 x double> [[VD]], float [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)304// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]305//306vfloat64m1_t test_vfwnmacc_vf_f64m1_m(vbool64_t mask, vfloat64m1_t vd, float vs1, vfloat32mf2_t vs2, size_t vl) {307 return __riscv_vfwnmacc_vf_f64m1_m(mask, vd, vs1, vs2, vl);308}309 310// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfwnmacc_vv_f64m2_m311// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {312// CHECK-RV64-NEXT: entry:313// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwnmacc.mask.nxv2f64.nxv2f32.nxv2f32.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)314// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]315//316vfloat64m2_t test_vfwnmacc_vv_f64m2_m(vbool32_t mask, vfloat64m2_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {317 return __riscv_vfwnmacc_vv_f64m2_m(mask, vd, vs1, vs2, vl);318}319 320// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfwnmacc_vf_f64m2_m321// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], float noundef [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {322// CHECK-RV64-NEXT: entry:323// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwnmacc.mask.nxv2f64.f32.nxv2f32.i64(<vscale x 2 x double> [[VD]], float [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)324// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]325//326vfloat64m2_t test_vfwnmacc_vf_f64m2_m(vbool32_t mask, vfloat64m2_t vd, float vs1, vfloat32m1_t vs2, size_t vl) {327 return __riscv_vfwnmacc_vf_f64m2_m(mask, vd, vs1, vs2, vl);328}329 330// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfwnmacc_vv_f64m4_m331// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {332// CHECK-RV64-NEXT: entry:333// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwnmacc.mask.nxv4f64.nxv4f32.nxv4f32.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)334// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]335//336vfloat64m4_t test_vfwnmacc_vv_f64m4_m(vbool16_t mask, vfloat64m4_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {337 return __riscv_vfwnmacc_vv_f64m4_m(mask, vd, vs1, vs2, vl);338}339 340// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfwnmacc_vf_f64m4_m341// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], float noundef [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {342// CHECK-RV64-NEXT: entry:343// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwnmacc.mask.nxv4f64.f32.nxv4f32.i64(<vscale x 4 x double> [[VD]], float [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)344// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]345//346vfloat64m4_t test_vfwnmacc_vf_f64m4_m(vbool16_t mask, vfloat64m4_t vd, float vs1, vfloat32m2_t vs2, size_t vl) {347 return __riscv_vfwnmacc_vf_f64m4_m(mask, vd, vs1, vs2, vl);348}349 350// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfwnmacc_vv_f64m8_m351// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {352// CHECK-RV64-NEXT: entry:353// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwnmacc.mask.nxv8f64.nxv8f32.nxv8f32.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)354// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]355//356vfloat64m8_t test_vfwnmacc_vv_f64m8_m(vbool8_t mask, vfloat64m8_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {357 return __riscv_vfwnmacc_vv_f64m8_m(mask, vd, vs1, vs2, vl);358}359 360// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfwnmacc_vf_f64m8_m361// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], float noundef [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {362// CHECK-RV64-NEXT: entry:363// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwnmacc.mask.nxv8f64.f32.nxv8f32.i64(<vscale x 8 x double> [[VD]], float [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)364// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]365//366vfloat64m8_t test_vfwnmacc_vf_f64m8_m(vbool8_t mask, vfloat64m8_t vd, float vs1, vfloat32m4_t vs2, size_t vl) {367 return __riscv_vfwnmacc_vf_f64m8_m(mask, vd, vs1, vs2, vl);368}369 370// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwnmacc_vv_f32mf2_rm371// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {372// CHECK-RV64-NEXT: entry:373// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)374// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]375//376vfloat32mf2_t test_vfwnmacc_vv_f32mf2_rm(vfloat32mf2_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {377 return __riscv_vfwnmacc_vv_f32mf2_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);378}379 380// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwnmacc_vf_f32mf2_rm381// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], half noundef [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {382// CHECK-RV64-NEXT: entry:383// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> [[VD]], half [[VS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)384// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]385//386vfloat32mf2_t test_vfwnmacc_vf_f32mf2_rm(vfloat32mf2_t vd, _Float16 vs1, vfloat16mf4_t vs2, size_t vl) {387 return __riscv_vfwnmacc_vf_f32mf2_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);388}389 390// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwnmacc_vv_f32m1_rm391// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {392// CHECK-RV64-NEXT: entry:393// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)394// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]395//396vfloat32m1_t test_vfwnmacc_vv_f32m1_rm(vfloat32m1_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {397 return __riscv_vfwnmacc_vv_f32m1_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);398}399 400// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwnmacc_vf_f32m1_rm401// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], half noundef [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {402// CHECK-RV64-NEXT: entry:403// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> [[VD]], half [[VS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)404// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]405//406vfloat32m1_t test_vfwnmacc_vf_f32m1_rm(vfloat32m1_t vd, _Float16 vs1, vfloat16mf2_t vs2, size_t vl) {407 return __riscv_vfwnmacc_vf_f32m1_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);408}409 410// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwnmacc_vv_f32m2_rm411// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {412// CHECK-RV64-NEXT: entry:413// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)414// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]415//416vfloat32m2_t test_vfwnmacc_vv_f32m2_rm(vfloat32m2_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {417 return __riscv_vfwnmacc_vv_f32m2_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);418}419 420// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwnmacc_vf_f32m2_rm421// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], half noundef [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {422// CHECK-RV64-NEXT: entry:423// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> [[VD]], half [[VS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)424// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]425//426vfloat32m2_t test_vfwnmacc_vf_f32m2_rm(vfloat32m2_t vd, _Float16 vs1, vfloat16m1_t vs2, size_t vl) {427 return __riscv_vfwnmacc_vf_f32m2_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);428}429 430// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwnmacc_vv_f32m4_rm431// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {432// CHECK-RV64-NEXT: entry:433// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)434// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]435//436vfloat32m4_t test_vfwnmacc_vv_f32m4_rm(vfloat32m4_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {437 return __riscv_vfwnmacc_vv_f32m4_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);438}439 440// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwnmacc_vf_f32m4_rm441// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], half noundef [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {442// CHECK-RV64-NEXT: entry:443// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> [[VD]], half [[VS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)444// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]445//446vfloat32m4_t test_vfwnmacc_vf_f32m4_rm(vfloat32m4_t vd, _Float16 vs1, vfloat16m2_t vs2, size_t vl) {447 return __riscv_vfwnmacc_vf_f32m4_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);448}449 450// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwnmacc_vv_f32m8_rm451// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {452// CHECK-RV64-NEXT: entry:453// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwnmacc.nxv16f32.nxv16f16.nxv16f16.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)454// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]455//456vfloat32m8_t test_vfwnmacc_vv_f32m8_rm(vfloat32m8_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {457 return __riscv_vfwnmacc_vv_f32m8_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);458}459 460// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwnmacc_vf_f32m8_rm461// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], half noundef [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {462// CHECK-RV64-NEXT: entry:463// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwnmacc.nxv16f32.f16.nxv16f16.i64(<vscale x 16 x float> [[VD]], half [[VS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)464// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]465//466vfloat32m8_t test_vfwnmacc_vf_f32m8_rm(vfloat32m8_t vd, _Float16 vs1, vfloat16m4_t vs2, size_t vl) {467 return __riscv_vfwnmacc_vf_f32m8_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);468}469 470// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwnmacc_vv_f64m1_rm471// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {472// CHECK-RV64-NEXT: entry:473// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwnmacc.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)474// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]475//476vfloat64m1_t test_vfwnmacc_vv_f64m1_rm(vfloat64m1_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {477 return __riscv_vfwnmacc_vv_f64m1_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);478}479 480// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwnmacc_vf_f64m1_rm481// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], float noundef [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {482// CHECK-RV64-NEXT: entry:483// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwnmacc.nxv1f64.f32.nxv1f32.i64(<vscale x 1 x double> [[VD]], float [[VS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)484// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]485//486vfloat64m1_t test_vfwnmacc_vf_f64m1_rm(vfloat64m1_t vd, float vs1, vfloat32mf2_t vs2, size_t vl) {487 return __riscv_vfwnmacc_vf_f64m1_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);488}489 490// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfwnmacc_vv_f64m2_rm491// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {492// CHECK-RV64-NEXT: entry:493// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwnmacc.nxv2f64.nxv2f32.nxv2f32.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)494// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]495//496vfloat64m2_t test_vfwnmacc_vv_f64m2_rm(vfloat64m2_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {497 return __riscv_vfwnmacc_vv_f64m2_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);498}499 500// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfwnmacc_vf_f64m2_rm501// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], float noundef [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {502// CHECK-RV64-NEXT: entry:503// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwnmacc.nxv2f64.f32.nxv2f32.i64(<vscale x 2 x double> [[VD]], float [[VS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)504// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]505//506vfloat64m2_t test_vfwnmacc_vf_f64m2_rm(vfloat64m2_t vd, float vs1, vfloat32m1_t vs2, size_t vl) {507 return __riscv_vfwnmacc_vf_f64m2_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);508}509 510// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfwnmacc_vv_f64m4_rm511// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {512// CHECK-RV64-NEXT: entry:513// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwnmacc.nxv4f64.nxv4f32.nxv4f32.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)514// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]515//516vfloat64m4_t test_vfwnmacc_vv_f64m4_rm(vfloat64m4_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {517 return __riscv_vfwnmacc_vv_f64m4_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);518}519 520// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfwnmacc_vf_f64m4_rm521// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], float noundef [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {522// CHECK-RV64-NEXT: entry:523// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwnmacc.nxv4f64.f32.nxv4f32.i64(<vscale x 4 x double> [[VD]], float [[VS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)524// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]525//526vfloat64m4_t test_vfwnmacc_vf_f64m4_rm(vfloat64m4_t vd, float vs1, vfloat32m2_t vs2, size_t vl) {527 return __riscv_vfwnmacc_vf_f64m4_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);528}529 530// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfwnmacc_vv_f64m8_rm531// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {532// CHECK-RV64-NEXT: entry:533// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwnmacc.nxv8f64.nxv8f32.nxv8f32.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)534// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]535//536vfloat64m8_t test_vfwnmacc_vv_f64m8_rm(vfloat64m8_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {537 return __riscv_vfwnmacc_vv_f64m8_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);538}539 540// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfwnmacc_vf_f64m8_rm541// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], float noundef [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {542// CHECK-RV64-NEXT: entry:543// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwnmacc.nxv8f64.f32.nxv8f32.i64(<vscale x 8 x double> [[VD]], float [[VS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)544// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]545//546vfloat64m8_t test_vfwnmacc_vf_f64m8_rm(vfloat64m8_t vd, float vs1, vfloat32m4_t vs2, size_t vl) {547 return __riscv_vfwnmacc_vf_f64m8_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);548}549 550// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwnmacc_vv_f32mf2_rm_m551// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {552// CHECK-RV64-NEXT: entry:553// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.mask.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)554// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]555//556vfloat32mf2_t test_vfwnmacc_vv_f32mf2_rm_m(vbool64_t mask, vfloat32mf2_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {557 return __riscv_vfwnmacc_vv_f32mf2_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);558}559 560// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwnmacc_vf_f32mf2_rm_m561// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], half noundef [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {562// CHECK-RV64-NEXT: entry:563// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.mask.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> [[VD]], half [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)564// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]565//566vfloat32mf2_t test_vfwnmacc_vf_f32mf2_rm_m(vbool64_t mask, vfloat32mf2_t vd, _Float16 vs1, vfloat16mf4_t vs2, size_t vl) {567 return __riscv_vfwnmacc_vf_f32mf2_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);568}569 570// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwnmacc_vv_f32m1_rm_m571// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {572// CHECK-RV64-NEXT: entry:573// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.mask.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)574// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]575//576vfloat32m1_t test_vfwnmacc_vv_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {577 return __riscv_vfwnmacc_vv_f32m1_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);578}579 580// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwnmacc_vf_f32m1_rm_m581// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], half noundef [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {582// CHECK-RV64-NEXT: entry:583// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.mask.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> [[VD]], half [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)584// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]585//586vfloat32m1_t test_vfwnmacc_vf_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, _Float16 vs1, vfloat16mf2_t vs2, size_t vl) {587 return __riscv_vfwnmacc_vf_f32m1_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);588}589 590// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwnmacc_vv_f32m2_rm_m591// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {592// CHECK-RV64-NEXT: entry:593// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.mask.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)594// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]595//596vfloat32m2_t test_vfwnmacc_vv_f32m2_rm_m(vbool16_t mask, vfloat32m2_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {597 return __riscv_vfwnmacc_vv_f32m2_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);598}599 600// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwnmacc_vf_f32m2_rm_m601// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], half noundef [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {602// CHECK-RV64-NEXT: entry:603// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.mask.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> [[VD]], half [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)604// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]605//606vfloat32m2_t test_vfwnmacc_vf_f32m2_rm_m(vbool16_t mask, vfloat32m2_t vd, _Float16 vs1, vfloat16m1_t vs2, size_t vl) {607 return __riscv_vfwnmacc_vf_f32m2_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);608}609 610// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwnmacc_vv_f32m4_rm_m611// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {612// CHECK-RV64-NEXT: entry:613// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.mask.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)614// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]615//616vfloat32m4_t test_vfwnmacc_vv_f32m4_rm_m(vbool8_t mask, vfloat32m4_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {617 return __riscv_vfwnmacc_vv_f32m4_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);618}619 620// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwnmacc_vf_f32m4_rm_m621// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], half noundef [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {622// CHECK-RV64-NEXT: entry:623// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.mask.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> [[VD]], half [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)624// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]625//626vfloat32m4_t test_vfwnmacc_vf_f32m4_rm_m(vbool8_t mask, vfloat32m4_t vd, _Float16 vs1, vfloat16m2_t vs2, size_t vl) {627 return __riscv_vfwnmacc_vf_f32m4_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);628}629 630// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwnmacc_vv_f32m8_rm_m631// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {632// CHECK-RV64-NEXT: entry:633// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwnmacc.mask.nxv16f32.nxv16f16.nxv16f16.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)634// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]635//636vfloat32m8_t test_vfwnmacc_vv_f32m8_rm_m(vbool4_t mask, vfloat32m8_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {637 return __riscv_vfwnmacc_vv_f32m8_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);638}639 640// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwnmacc_vf_f32m8_rm_m641// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], half noundef [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {642// CHECK-RV64-NEXT: entry:643// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwnmacc.mask.nxv16f32.f16.nxv16f16.i64(<vscale x 16 x float> [[VD]], half [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)644// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]645//646vfloat32m8_t test_vfwnmacc_vf_f32m8_rm_m(vbool4_t mask, vfloat32m8_t vd, _Float16 vs1, vfloat16m4_t vs2, size_t vl) {647 return __riscv_vfwnmacc_vf_f32m8_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);648}649 650// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwnmacc_vv_f64m1_rm_m651// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {652// CHECK-RV64-NEXT: entry:653// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwnmacc.mask.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)654// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]655//656vfloat64m1_t test_vfwnmacc_vv_f64m1_rm_m(vbool64_t mask, vfloat64m1_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {657 return __riscv_vfwnmacc_vv_f64m1_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);658}659 660// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwnmacc_vf_f64m1_rm_m661// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], float noundef [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {662// CHECK-RV64-NEXT: entry:663// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwnmacc.mask.nxv1f64.f32.nxv1f32.i64(<vscale x 1 x double> [[VD]], float [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)664// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]665//666vfloat64m1_t test_vfwnmacc_vf_f64m1_rm_m(vbool64_t mask, vfloat64m1_t vd, float vs1, vfloat32mf2_t vs2, size_t vl) {667 return __riscv_vfwnmacc_vf_f64m1_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);668}669 670// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfwnmacc_vv_f64m2_rm_m671// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {672// CHECK-RV64-NEXT: entry:673// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwnmacc.mask.nxv2f64.nxv2f32.nxv2f32.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)674// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]675//676vfloat64m2_t test_vfwnmacc_vv_f64m2_rm_m(vbool32_t mask, vfloat64m2_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {677 return __riscv_vfwnmacc_vv_f64m2_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);678}679 680// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfwnmacc_vf_f64m2_rm_m681// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], float noundef [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {682// CHECK-RV64-NEXT: entry:683// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwnmacc.mask.nxv2f64.f32.nxv2f32.i64(<vscale x 2 x double> [[VD]], float [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)684// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]685//686vfloat64m2_t test_vfwnmacc_vf_f64m2_rm_m(vbool32_t mask, vfloat64m2_t vd, float vs1, vfloat32m1_t vs2, size_t vl) {687 return __riscv_vfwnmacc_vf_f64m2_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);688}689 690// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfwnmacc_vv_f64m4_rm_m691// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {692// CHECK-RV64-NEXT: entry:693// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwnmacc.mask.nxv4f64.nxv4f32.nxv4f32.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)694// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]695//696vfloat64m4_t test_vfwnmacc_vv_f64m4_rm_m(vbool16_t mask, vfloat64m4_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {697 return __riscv_vfwnmacc_vv_f64m4_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);698}699 700// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfwnmacc_vf_f64m4_rm_m701// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], float noundef [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {702// CHECK-RV64-NEXT: entry:703// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwnmacc.mask.nxv4f64.f32.nxv4f32.i64(<vscale x 4 x double> [[VD]], float [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)704// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]705//706vfloat64m4_t test_vfwnmacc_vf_f64m4_rm_m(vbool16_t mask, vfloat64m4_t vd, float vs1, vfloat32m2_t vs2, size_t vl) {707 return __riscv_vfwnmacc_vf_f64m4_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);708}709 710// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfwnmacc_vv_f64m8_rm_m711// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {712// CHECK-RV64-NEXT: entry:713// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwnmacc.mask.nxv8f64.nxv8f32.nxv8f32.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)714// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]715//716vfloat64m8_t test_vfwnmacc_vv_f64m8_rm_m(vbool8_t mask, vfloat64m8_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {717 return __riscv_vfwnmacc_vv_f64m8_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);718}719 720// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfwnmacc_vf_f64m8_rm_m721// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], float noundef [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {722// CHECK-RV64-NEXT: entry:723// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwnmacc.mask.nxv8f64.f32.nxv8f32.i64(<vscale x 8 x double> [[VD]], float [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)724// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]725//726vfloat64m8_t test_vfwnmacc_vf_f64m8_rm_m(vbool8_t mask, vfloat64m8_t vd, float vs1, vfloat32m4_t vs2, size_t vl) {727 return __riscv_vfwnmacc_vf_f64m8_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);728}729 730