2930 lines · c
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 22// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \4// RUN: -target-feature +zvfhmin -disable-O0-optnone \5// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \6// RUN: FileCheck --check-prefix=CHECK-RV64 %s7 8#include <riscv_vector.h>9 10// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vget_v_f16m2_f16m111// CHECK-RV64-SAME: (<vscale x 8 x half> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0:[0-9]+]] {12// CHECK-RV64-NEXT: entry:13// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half> [[SRC]], i64 0)14// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]15//16vfloat16m1_t test_vget_v_f16m2_f16m1(vfloat16m2_t src, size_t index) {17 return __riscv_vget_v_f16m2_f16m1(src, 0);18}19 20// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vget_v_f16m4_f16m121// CHECK-RV64-SAME: (<vscale x 16 x half> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {22// CHECK-RV64-NEXT: entry:23// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half> [[SRC]], i64 0)24// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]25//26vfloat16m1_t test_vget_v_f16m4_f16m1(vfloat16m4_t src, size_t index) {27 return __riscv_vget_v_f16m4_f16m1(src, 0);28}29 30// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vget_v_f16m8_f16m131// CHECK-RV64-SAME: (<vscale x 32 x half> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {32// CHECK-RV64-NEXT: entry:33// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv32f16(<vscale x 32 x half> [[SRC]], i64 0)34// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]35//36vfloat16m1_t test_vget_v_f16m8_f16m1(vfloat16m8_t src, size_t index) {37 return __riscv_vget_v_f16m8_f16m1(src, 0);38}39 40// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vget_v_f16m4_f16m241// CHECK-RV64-SAME: (<vscale x 16 x half> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {42// CHECK-RV64-NEXT: entry:43// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv16f16(<vscale x 16 x half> [[SRC]], i64 0)44// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]45//46vfloat16m2_t test_vget_v_f16m4_f16m2(vfloat16m4_t src, size_t index) {47 return __riscv_vget_v_f16m4_f16m2(src, 0);48}49 50// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vget_v_f16m8_f16m251// CHECK-RV64-SAME: (<vscale x 32 x half> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {52// CHECK-RV64-NEXT: entry:53// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv32f16(<vscale x 32 x half> [[SRC]], i64 0)54// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]55//56vfloat16m2_t test_vget_v_f16m8_f16m2(vfloat16m8_t src, size_t index) {57 return __riscv_vget_v_f16m8_f16m2(src, 0);58}59 60// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vget_v_f16m8_f16m461// CHECK-RV64-SAME: (<vscale x 32 x half> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {62// CHECK-RV64-NEXT: entry:63// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.vector.extract.nxv16f16.nxv32f16(<vscale x 32 x half> [[SRC]], i64 0)64// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]65//66vfloat16m4_t test_vget_v_f16m8_f16m4(vfloat16m8_t src, size_t index) {67 return __riscv_vget_v_f16m8_f16m4(src, 0);68}69 70// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vget_v_f32m2_f32m171// CHECK-RV64-SAME: (<vscale x 4 x float> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {72// CHECK-RV64-NEXT: entry:73// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv4f32(<vscale x 4 x float> [[SRC]], i64 0)74// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]75//76vfloat32m1_t test_vget_v_f32m2_f32m1(vfloat32m2_t src, size_t index) {77 return __riscv_vget_v_f32m2_f32m1(src, 0);78}79 80// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vget_v_f32m4_f32m181// CHECK-RV64-SAME: (<vscale x 8 x float> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {82// CHECK-RV64-NEXT: entry:83// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv8f32(<vscale x 8 x float> [[SRC]], i64 0)84// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]85//86vfloat32m1_t test_vget_v_f32m4_f32m1(vfloat32m4_t src, size_t index) {87 return __riscv_vget_v_f32m4_f32m1(src, 0);88}89 90// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vget_v_f32m8_f32m191// CHECK-RV64-SAME: (<vscale x 16 x float> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {92// CHECK-RV64-NEXT: entry:93// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv16f32(<vscale x 16 x float> [[SRC]], i64 0)94// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]95//96vfloat32m1_t test_vget_v_f32m8_f32m1(vfloat32m8_t src, size_t index) {97 return __riscv_vget_v_f32m8_f32m1(src, 0);98}99 100// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vget_v_f32m4_f32m2101// CHECK-RV64-SAME: (<vscale x 8 x float> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {102// CHECK-RV64-NEXT: entry:103// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv8f32(<vscale x 8 x float> [[SRC]], i64 0)104// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]105//106vfloat32m2_t test_vget_v_f32m4_f32m2(vfloat32m4_t src, size_t index) {107 return __riscv_vget_v_f32m4_f32m2(src, 0);108}109 110// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vget_v_f32m8_f32m2111// CHECK-RV64-SAME: (<vscale x 16 x float> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {112// CHECK-RV64-NEXT: entry:113// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv16f32(<vscale x 16 x float> [[SRC]], i64 0)114// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]115//116vfloat32m2_t test_vget_v_f32m8_f32m2(vfloat32m8_t src, size_t index) {117 return __riscv_vget_v_f32m8_f32m2(src, 0);118}119 120// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vget_v_f32m8_f32m4121// CHECK-RV64-SAME: (<vscale x 16 x float> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {122// CHECK-RV64-NEXT: entry:123// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.vector.extract.nxv8f32.nxv16f32(<vscale x 16 x float> [[SRC]], i64 0)124// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]125//126vfloat32m4_t test_vget_v_f32m8_f32m4(vfloat32m8_t src, size_t index) {127 return __riscv_vget_v_f32m8_f32m4(src, 0);128}129 130// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vget_v_f64m2_f64m1131// CHECK-RV64-SAME: (<vscale x 2 x double> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {132// CHECK-RV64-NEXT: entry:133// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.vector.extract.nxv1f64.nxv2f64(<vscale x 2 x double> [[SRC]], i64 0)134// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]135//136vfloat64m1_t test_vget_v_f64m2_f64m1(vfloat64m2_t src, size_t index) {137 return __riscv_vget_v_f64m2_f64m1(src, 0);138}139 140// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vget_v_f64m4_f64m1141// CHECK-RV64-SAME: (<vscale x 4 x double> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {142// CHECK-RV64-NEXT: entry:143// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.vector.extract.nxv1f64.nxv4f64(<vscale x 4 x double> [[SRC]], i64 0)144// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]145//146vfloat64m1_t test_vget_v_f64m4_f64m1(vfloat64m4_t src, size_t index) {147 return __riscv_vget_v_f64m4_f64m1(src, 0);148}149 150// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vget_v_f64m8_f64m1151// CHECK-RV64-SAME: (<vscale x 8 x double> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {152// CHECK-RV64-NEXT: entry:153// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.vector.extract.nxv1f64.nxv8f64(<vscale x 8 x double> [[SRC]], i64 0)154// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]155//156vfloat64m1_t test_vget_v_f64m8_f64m1(vfloat64m8_t src, size_t index) {157 return __riscv_vget_v_f64m8_f64m1(src, 0);158}159 160// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vget_v_f64m4_f64m2161// CHECK-RV64-SAME: (<vscale x 4 x double> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {162// CHECK-RV64-NEXT: entry:163// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.vector.extract.nxv2f64.nxv4f64(<vscale x 4 x double> [[SRC]], i64 0)164// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]165//166vfloat64m2_t test_vget_v_f64m4_f64m2(vfloat64m4_t src, size_t index) {167 return __riscv_vget_v_f64m4_f64m2(src, 0);168}169 170// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vget_v_f64m8_f64m2171// CHECK-RV64-SAME: (<vscale x 8 x double> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {172// CHECK-RV64-NEXT: entry:173// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.vector.extract.nxv2f64.nxv8f64(<vscale x 8 x double> [[SRC]], i64 0)174// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]175//176vfloat64m2_t test_vget_v_f64m8_f64m2(vfloat64m8_t src, size_t index) {177 return __riscv_vget_v_f64m8_f64m2(src, 0);178}179 180// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vget_v_f64m8_f64m4181// CHECK-RV64-SAME: (<vscale x 8 x double> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {182// CHECK-RV64-NEXT: entry:183// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.vector.extract.nxv4f64.nxv8f64(<vscale x 8 x double> [[SRC]], i64 0)184// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]185//186vfloat64m4_t test_vget_v_f64m8_f64m4(vfloat64m8_t src, size_t index) {187 return __riscv_vget_v_f64m8_f64m4(src, 0);188}189 190// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vget_v_i8m2_i8m1191// CHECK-RV64-SAME: (<vscale x 16 x i8> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {192// CHECK-RV64-NEXT: entry:193// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8> [[SRC]], i64 0)194// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]195//196vint8m1_t test_vget_v_i8m2_i8m1(vint8m2_t src, size_t index) {197 return __riscv_vget_v_i8m2_i8m1(src, 0);198}199 200// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vget_v_i8m4_i8m1201// CHECK-RV64-SAME: (<vscale x 32 x i8> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {202// CHECK-RV64-NEXT: entry:203// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8> [[SRC]], i64 0)204// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]205//206vint8m1_t test_vget_v_i8m4_i8m1(vint8m4_t src, size_t index) {207 return __riscv_vget_v_i8m4_i8m1(src, 0);208}209 210// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vget_v_i8m8_i8m1211// CHECK-RV64-SAME: (<vscale x 64 x i8> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {212// CHECK-RV64-NEXT: entry:213// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv64i8(<vscale x 64 x i8> [[SRC]], i64 0)214// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]215//216vint8m1_t test_vget_v_i8m8_i8m1(vint8m8_t src, size_t index) {217 return __riscv_vget_v_i8m8_i8m1(src, 0);218}219 220// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vget_v_i8m4_i8m2221// CHECK-RV64-SAME: (<vscale x 32 x i8> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {222// CHECK-RV64-NEXT: entry:223// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> [[SRC]], i64 0)224// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]225//226vint8m2_t test_vget_v_i8m4_i8m2(vint8m4_t src, size_t index) {227 return __riscv_vget_v_i8m4_i8m2(src, 0);228}229 230// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vget_v_i8m8_i8m2231// CHECK-RV64-SAME: (<vscale x 64 x i8> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {232// CHECK-RV64-NEXT: entry:233// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv64i8(<vscale x 64 x i8> [[SRC]], i64 0)234// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]235//236vint8m2_t test_vget_v_i8m8_i8m2(vint8m8_t src, size_t index) {237 return __riscv_vget_v_i8m8_i8m2(src, 0);238}239 240// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vget_v_i8m8_i8m4241// CHECK-RV64-SAME: (<vscale x 64 x i8> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {242// CHECK-RV64-NEXT: entry:243// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.extract.nxv32i8.nxv64i8(<vscale x 64 x i8> [[SRC]], i64 0)244// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]245//246vint8m4_t test_vget_v_i8m8_i8m4(vint8m8_t src, size_t index) {247 return __riscv_vget_v_i8m8_i8m4(src, 0);248}249 250// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vget_v_i16m2_i16m1251// CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {252// CHECK-RV64-NEXT: entry:253// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv8i16(<vscale x 8 x i16> [[SRC]], i64 0)254// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]255//256vint16m1_t test_vget_v_i16m2_i16m1(vint16m2_t src, size_t index) {257 return __riscv_vget_v_i16m2_i16m1(src, 0);258}259 260// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vget_v_i16m4_i16m1261// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {262// CHECK-RV64-NEXT: entry:263// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv16i16(<vscale x 16 x i16> [[SRC]], i64 0)264// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]265//266vint16m1_t test_vget_v_i16m4_i16m1(vint16m4_t src, size_t index) {267 return __riscv_vget_v_i16m4_i16m1(src, 0);268}269 270// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vget_v_i16m8_i16m1271// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {272// CHECK-RV64-NEXT: entry:273// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv32i16(<vscale x 32 x i16> [[SRC]], i64 0)274// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]275//276vint16m1_t test_vget_v_i16m8_i16m1(vint16m8_t src, size_t index) {277 return __riscv_vget_v_i16m8_i16m1(src, 0);278}279 280// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vget_v_i16m4_i16m2281// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {282// CHECK-RV64-NEXT: entry:283// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.extract.nxv8i16.nxv16i16(<vscale x 16 x i16> [[SRC]], i64 0)284// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]285//286vint16m2_t test_vget_v_i16m4_i16m2(vint16m4_t src, size_t index) {287 return __riscv_vget_v_i16m4_i16m2(src, 0);288}289 290// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vget_v_i16m8_i16m2291// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {292// CHECK-RV64-NEXT: entry:293// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.extract.nxv8i16.nxv32i16(<vscale x 32 x i16> [[SRC]], i64 0)294// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]295//296vint16m2_t test_vget_v_i16m8_i16m2(vint16m8_t src, size_t index) {297 return __riscv_vget_v_i16m8_i16m2(src, 0);298}299 300// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vget_v_i16m8_i16m4301// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {302// CHECK-RV64-NEXT: entry:303// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.vector.extract.nxv16i16.nxv32i16(<vscale x 32 x i16> [[SRC]], i64 0)304// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]305//306vint16m4_t test_vget_v_i16m8_i16m4(vint16m8_t src, size_t index) {307 return __riscv_vget_v_i16m8_i16m4(src, 0);308}309 310// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vget_v_i32m2_i32m1311// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {312// CHECK-RV64-NEXT: entry:313// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv4i32(<vscale x 4 x i32> [[SRC]], i64 0)314// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]315//316vint32m1_t test_vget_v_i32m2_i32m1(vint32m2_t src, size_t index) {317 return __riscv_vget_v_i32m2_i32m1(src, 0);318}319 320// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vget_v_i32m4_i32m1321// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {322// CHECK-RV64-NEXT: entry:323// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> [[SRC]], i64 0)324// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]325//326vint32m1_t test_vget_v_i32m4_i32m1(vint32m4_t src, size_t index) {327 return __riscv_vget_v_i32m4_i32m1(src, 0);328}329 330// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vget_v_i32m8_i32m1331// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {332// CHECK-RV64-NEXT: entry:333// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> [[SRC]], i64 0)334// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]335//336vint32m1_t test_vget_v_i32m8_i32m1(vint32m8_t src, size_t index) {337 return __riscv_vget_v_i32m8_i32m1(src, 0);338}339 340// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vget_v_i32m4_i32m2341// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {342// CHECK-RV64-NEXT: entry:343// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> [[SRC]], i64 0)344// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]345//346vint32m2_t test_vget_v_i32m4_i32m2(vint32m4_t src, size_t index) {347 return __riscv_vget_v_i32m4_i32m2(src, 0);348}349 350// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vget_v_i32m8_i32m2351// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {352// CHECK-RV64-NEXT: entry:353// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> [[SRC]], i64 0)354// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]355//356vint32m2_t test_vget_v_i32m8_i32m2(vint32m8_t src, size_t index) {357 return __riscv_vget_v_i32m8_i32m2(src, 0);358}359 360// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vget_v_i32m8_i32m4361// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {362// CHECK-RV64-NEXT: entry:363// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.vector.extract.nxv8i32.nxv16i32(<vscale x 16 x i32> [[SRC]], i64 0)364// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]365//366vint32m4_t test_vget_v_i32m8_i32m4(vint32m8_t src, size_t index) {367 return __riscv_vget_v_i32m8_i32m4(src, 0);368}369 370// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vget_v_i64m2_i64m1371// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {372// CHECK-RV64-NEXT: entry:373// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.vector.extract.nxv1i64.nxv2i64(<vscale x 2 x i64> [[SRC]], i64 0)374// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]375//376vint64m1_t test_vget_v_i64m2_i64m1(vint64m2_t src, size_t index) {377 return __riscv_vget_v_i64m2_i64m1(src, 0);378}379 380// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vget_v_i64m4_i64m1381// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {382// CHECK-RV64-NEXT: entry:383// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.vector.extract.nxv1i64.nxv4i64(<vscale x 4 x i64> [[SRC]], i64 0)384// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]385//386vint64m1_t test_vget_v_i64m4_i64m1(vint64m4_t src, size_t index) {387 return __riscv_vget_v_i64m4_i64m1(src, 0);388}389 390// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vget_v_i64m8_i64m1391// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {392// CHECK-RV64-NEXT: entry:393// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.vector.extract.nxv1i64.nxv8i64(<vscale x 8 x i64> [[SRC]], i64 0)394// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]395//396vint64m1_t test_vget_v_i64m8_i64m1(vint64m8_t src, size_t index) {397 return __riscv_vget_v_i64m8_i64m1(src, 0);398}399 400// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vget_v_i64m4_i64m2401// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {402// CHECK-RV64-NEXT: entry:403// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.vector.extract.nxv2i64.nxv4i64(<vscale x 4 x i64> [[SRC]], i64 0)404// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]405//406vint64m2_t test_vget_v_i64m4_i64m2(vint64m4_t src, size_t index) {407 return __riscv_vget_v_i64m4_i64m2(src, 0);408}409 410// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vget_v_i64m8_i64m2411// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {412// CHECK-RV64-NEXT: entry:413// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.vector.extract.nxv2i64.nxv8i64(<vscale x 8 x i64> [[SRC]], i64 0)414// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]415//416vint64m2_t test_vget_v_i64m8_i64m2(vint64m8_t src, size_t index) {417 return __riscv_vget_v_i64m8_i64m2(src, 0);418}419 420// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vget_v_i64m8_i64m4421// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {422// CHECK-RV64-NEXT: entry:423// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.vector.extract.nxv4i64.nxv8i64(<vscale x 8 x i64> [[SRC]], i64 0)424// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]425//426vint64m4_t test_vget_v_i64m8_i64m4(vint64m8_t src, size_t index) {427 return __riscv_vget_v_i64m8_i64m4(src, 0);428}429 430// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vget_v_u8m2_u8m1431// CHECK-RV64-SAME: (<vscale x 16 x i8> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {432// CHECK-RV64-NEXT: entry:433// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8> [[SRC]], i64 0)434// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]435//436vuint8m1_t test_vget_v_u8m2_u8m1(vuint8m2_t src, size_t index) {437 return __riscv_vget_v_u8m2_u8m1(src, 0);438}439 440// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vget_v_u8m4_u8m1441// CHECK-RV64-SAME: (<vscale x 32 x i8> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {442// CHECK-RV64-NEXT: entry:443// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8> [[SRC]], i64 0)444// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]445//446vuint8m1_t test_vget_v_u8m4_u8m1(vuint8m4_t src, size_t index) {447 return __riscv_vget_v_u8m4_u8m1(src, 0);448}449 450// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vget_v_u8m8_u8m1451// CHECK-RV64-SAME: (<vscale x 64 x i8> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {452// CHECK-RV64-NEXT: entry:453// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv64i8(<vscale x 64 x i8> [[SRC]], i64 0)454// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]455//456vuint8m1_t test_vget_v_u8m8_u8m1(vuint8m8_t src, size_t index) {457 return __riscv_vget_v_u8m8_u8m1(src, 0);458}459 460// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vget_v_u8m4_u8m2461// CHECK-RV64-SAME: (<vscale x 32 x i8> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {462// CHECK-RV64-NEXT: entry:463// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> [[SRC]], i64 0)464// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]465//466vuint8m2_t test_vget_v_u8m4_u8m2(vuint8m4_t src, size_t index) {467 return __riscv_vget_v_u8m4_u8m2(src, 0);468}469 470// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vget_v_u8m8_u8m2471// CHECK-RV64-SAME: (<vscale x 64 x i8> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {472// CHECK-RV64-NEXT: entry:473// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv64i8(<vscale x 64 x i8> [[SRC]], i64 0)474// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]475//476vuint8m2_t test_vget_v_u8m8_u8m2(vuint8m8_t src, size_t index) {477 return __riscv_vget_v_u8m8_u8m2(src, 0);478}479 480// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vget_v_u8m8_u8m4481// CHECK-RV64-SAME: (<vscale x 64 x i8> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {482// CHECK-RV64-NEXT: entry:483// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.extract.nxv32i8.nxv64i8(<vscale x 64 x i8> [[SRC]], i64 0)484// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]485//486vuint8m4_t test_vget_v_u8m8_u8m4(vuint8m8_t src, size_t index) {487 return __riscv_vget_v_u8m8_u8m4(src, 0);488}489 490// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vget_v_u16m2_u16m1491// CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {492// CHECK-RV64-NEXT: entry:493// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv8i16(<vscale x 8 x i16> [[SRC]], i64 0)494// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]495//496vuint16m1_t test_vget_v_u16m2_u16m1(vuint16m2_t src, size_t index) {497 return __riscv_vget_v_u16m2_u16m1(src, 0);498}499 500// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vget_v_u16m4_u16m1501// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {502// CHECK-RV64-NEXT: entry:503// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv16i16(<vscale x 16 x i16> [[SRC]], i64 0)504// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]505//506vuint16m1_t test_vget_v_u16m4_u16m1(vuint16m4_t src, size_t index) {507 return __riscv_vget_v_u16m4_u16m1(src, 0);508}509 510// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vget_v_u16m8_u16m1511// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {512// CHECK-RV64-NEXT: entry:513// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv32i16(<vscale x 32 x i16> [[SRC]], i64 0)514// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]515//516vuint16m1_t test_vget_v_u16m8_u16m1(vuint16m8_t src, size_t index) {517 return __riscv_vget_v_u16m8_u16m1(src, 0);518}519 520// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vget_v_u16m4_u16m2521// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {522// CHECK-RV64-NEXT: entry:523// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.extract.nxv8i16.nxv16i16(<vscale x 16 x i16> [[SRC]], i64 0)524// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]525//526vuint16m2_t test_vget_v_u16m4_u16m2(vuint16m4_t src, size_t index) {527 return __riscv_vget_v_u16m4_u16m2(src, 0);528}529 530// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vget_v_u16m8_u16m2531// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {532// CHECK-RV64-NEXT: entry:533// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.extract.nxv8i16.nxv32i16(<vscale x 32 x i16> [[SRC]], i64 0)534// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]535//536vuint16m2_t test_vget_v_u16m8_u16m2(vuint16m8_t src, size_t index) {537 return __riscv_vget_v_u16m8_u16m2(src, 0);538}539 540// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vget_v_u16m8_u16m4541// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {542// CHECK-RV64-NEXT: entry:543// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.vector.extract.nxv16i16.nxv32i16(<vscale x 32 x i16> [[SRC]], i64 0)544// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]545//546vuint16m4_t test_vget_v_u16m8_u16m4(vuint16m8_t src, size_t index) {547 return __riscv_vget_v_u16m8_u16m4(src, 0);548}549 550// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vget_v_u32m2_u32m1551// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {552// CHECK-RV64-NEXT: entry:553// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv4i32(<vscale x 4 x i32> [[SRC]], i64 0)554// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]555//556vuint32m1_t test_vget_v_u32m2_u32m1(vuint32m2_t src, size_t index) {557 return __riscv_vget_v_u32m2_u32m1(src, 0);558}559 560// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vget_v_u32m4_u32m1561// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {562// CHECK-RV64-NEXT: entry:563// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> [[SRC]], i64 0)564// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]565//566vuint32m1_t test_vget_v_u32m4_u32m1(vuint32m4_t src, size_t index) {567 return __riscv_vget_v_u32m4_u32m1(src, 0);568}569 570// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vget_v_u32m8_u32m1571// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {572// CHECK-RV64-NEXT: entry:573// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> [[SRC]], i64 0)574// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]575//576vuint32m1_t test_vget_v_u32m8_u32m1(vuint32m8_t src, size_t index) {577 return __riscv_vget_v_u32m8_u32m1(src, 0);578}579 580// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vget_v_u32m4_u32m2581// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {582// CHECK-RV64-NEXT: entry:583// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> [[SRC]], i64 0)584// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]585//586vuint32m2_t test_vget_v_u32m4_u32m2(vuint32m4_t src, size_t index) {587 return __riscv_vget_v_u32m4_u32m2(src, 0);588}589 590// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vget_v_u32m8_u32m2591// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {592// CHECK-RV64-NEXT: entry:593// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> [[SRC]], i64 0)594// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]595//596vuint32m2_t test_vget_v_u32m8_u32m2(vuint32m8_t src, size_t index) {597 return __riscv_vget_v_u32m8_u32m2(src, 0);598}599 600// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vget_v_u32m8_u32m4601// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {602// CHECK-RV64-NEXT: entry:603// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.vector.extract.nxv8i32.nxv16i32(<vscale x 16 x i32> [[SRC]], i64 0)604// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]605//606vuint32m4_t test_vget_v_u32m8_u32m4(vuint32m8_t src, size_t index) {607 return __riscv_vget_v_u32m8_u32m4(src, 0);608}609 610// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vget_v_u64m2_u64m1611// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {612// CHECK-RV64-NEXT: entry:613// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.vector.extract.nxv1i64.nxv2i64(<vscale x 2 x i64> [[SRC]], i64 0)614// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]615//616vuint64m1_t test_vget_v_u64m2_u64m1(vuint64m2_t src, size_t index) {617 return __riscv_vget_v_u64m2_u64m1(src, 0);618}619 620// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vget_v_u64m4_u64m1621// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {622// CHECK-RV64-NEXT: entry:623// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.vector.extract.nxv1i64.nxv4i64(<vscale x 4 x i64> [[SRC]], i64 0)624// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]625//626vuint64m1_t test_vget_v_u64m4_u64m1(vuint64m4_t src, size_t index) {627 return __riscv_vget_v_u64m4_u64m1(src, 0);628}629 630// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vget_v_u64m8_u64m1631// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {632// CHECK-RV64-NEXT: entry:633// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.vector.extract.nxv1i64.nxv8i64(<vscale x 8 x i64> [[SRC]], i64 0)634// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]635//636vuint64m1_t test_vget_v_u64m8_u64m1(vuint64m8_t src, size_t index) {637 return __riscv_vget_v_u64m8_u64m1(src, 0);638}639 640// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vget_v_u64m4_u64m2641// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {642// CHECK-RV64-NEXT: entry:643// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.vector.extract.nxv2i64.nxv4i64(<vscale x 4 x i64> [[SRC]], i64 0)644// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]645//646vuint64m2_t test_vget_v_u64m4_u64m2(vuint64m4_t src, size_t index) {647 return __riscv_vget_v_u64m4_u64m2(src, 0);648}649 650// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vget_v_u64m8_u64m2651// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {652// CHECK-RV64-NEXT: entry:653// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.vector.extract.nxv2i64.nxv8i64(<vscale x 8 x i64> [[SRC]], i64 0)654// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]655//656vuint64m2_t test_vget_v_u64m8_u64m2(vuint64m8_t src, size_t index) {657 return __riscv_vget_v_u64m8_u64m2(src, 0);658}659 660// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vget_v_u64m8_u64m4661// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {662// CHECK-RV64-NEXT: entry:663// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.vector.extract.nxv4i64.nxv8i64(<vscale x 8 x i64> [[SRC]], i64 0)664// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]665//666vuint64m4_t test_vget_v_u64m8_u64m4(vuint64m8_t src, size_t index) {667 return __riscv_vget_v_u64m8_u64m4(src, 0);668}669 670// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vget_v_f16mf4x2_f16mf4671// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 2 x i8>, 2) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {672// CHECK-RV64-NEXT: entry:673// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.tuple.extract.nxv1f16.triscv.vector.tuple_nxv2i8_2t(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) [[SRC]], i32 0)674// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]675//676vfloat16mf4_t test_vget_v_f16mf4x2_f16mf4(vfloat16mf4x2_t src, size_t index) {677 return __riscv_vget_v_f16mf4x2_f16mf4(src, 0);678}679 680// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vget_v_f16mf4x3_f16mf4681// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 2 x i8>, 3) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {682// CHECK-RV64-NEXT: entry:683// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.tuple.extract.nxv1f16.triscv.vector.tuple_nxv2i8_3t(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) [[SRC]], i32 0)684// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]685//686vfloat16mf4_t test_vget_v_f16mf4x3_f16mf4(vfloat16mf4x3_t src, size_t index) {687 return __riscv_vget_v_f16mf4x3_f16mf4(src, 0);688}689 690// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vget_v_f16mf4x4_f16mf4691// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 2 x i8>, 4) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {692// CHECK-RV64-NEXT: entry:693// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.tuple.extract.nxv1f16.triscv.vector.tuple_nxv2i8_4t(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) [[SRC]], i32 0)694// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]695//696vfloat16mf4_t test_vget_v_f16mf4x4_f16mf4(vfloat16mf4x4_t src, size_t index) {697 return __riscv_vget_v_f16mf4x4_f16mf4(src, 0);698}699 700// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vget_v_f16mf4x5_f16mf4701// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 2 x i8>, 5) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {702// CHECK-RV64-NEXT: entry:703// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.tuple.extract.nxv1f16.triscv.vector.tuple_nxv2i8_5t(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) [[SRC]], i32 0)704// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]705//706vfloat16mf4_t test_vget_v_f16mf4x5_f16mf4(vfloat16mf4x5_t src, size_t index) {707 return __riscv_vget_v_f16mf4x5_f16mf4(src, 0);708}709 710// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vget_v_f16mf4x6_f16mf4711// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 2 x i8>, 6) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {712// CHECK-RV64-NEXT: entry:713// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.tuple.extract.nxv1f16.triscv.vector.tuple_nxv2i8_6t(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) [[SRC]], i32 0)714// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]715//716vfloat16mf4_t test_vget_v_f16mf4x6_f16mf4(vfloat16mf4x6_t src, size_t index) {717 return __riscv_vget_v_f16mf4x6_f16mf4(src, 0);718}719 720// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vget_v_f16mf4x7_f16mf4721// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 2 x i8>, 7) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {722// CHECK-RV64-NEXT: entry:723// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.tuple.extract.nxv1f16.triscv.vector.tuple_nxv2i8_7t(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) [[SRC]], i32 0)724// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]725//726vfloat16mf4_t test_vget_v_f16mf4x7_f16mf4(vfloat16mf4x7_t src, size_t index) {727 return __riscv_vget_v_f16mf4x7_f16mf4(src, 0);728}729 730// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vget_v_f16mf4x8_f16mf4731// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 2 x i8>, 8) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {732// CHECK-RV64-NEXT: entry:733// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.tuple.extract.nxv1f16.triscv.vector.tuple_nxv2i8_8t(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) [[SRC]], i32 0)734// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]735//736vfloat16mf4_t test_vget_v_f16mf4x8_f16mf4(vfloat16mf4x8_t src, size_t index) {737 return __riscv_vget_v_f16mf4x8_f16mf4(src, 0);738}739 740// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vget_v_f16mf2x2_f16mf2741// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 2) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {742// CHECK-RV64-NEXT: entry:743// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.tuple.extract.nxv2f16.triscv.vector.tuple_nxv4i8_2t(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) [[SRC]], i32 0)744// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]745//746vfloat16mf2_t test_vget_v_f16mf2x2_f16mf2(vfloat16mf2x2_t src, size_t index) {747 return __riscv_vget_v_f16mf2x2_f16mf2(src, 0);748}749 750// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vget_v_f16mf2x3_f16mf2751// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {752// CHECK-RV64-NEXT: entry:753// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.tuple.extract.nxv2f16.triscv.vector.tuple_nxv4i8_3t(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[SRC]], i32 0)754// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]755//756vfloat16mf2_t test_vget_v_f16mf2x3_f16mf2(vfloat16mf2x3_t src, size_t index) {757 return __riscv_vget_v_f16mf2x3_f16mf2(src, 0);758}759 760// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vget_v_f16mf2x4_f16mf2761// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 4) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {762// CHECK-RV64-NEXT: entry:763// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.tuple.extract.nxv2f16.triscv.vector.tuple_nxv4i8_4t(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) [[SRC]], i32 0)764// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]765//766vfloat16mf2_t test_vget_v_f16mf2x4_f16mf2(vfloat16mf2x4_t src, size_t index) {767 return __riscv_vget_v_f16mf2x4_f16mf2(src, 0);768}769 770// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vget_v_f16mf2x5_f16mf2771// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {772// CHECK-RV64-NEXT: entry:773// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.tuple.extract.nxv2f16.triscv.vector.tuple_nxv4i8_5t(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[SRC]], i32 0)774// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]775//776vfloat16mf2_t test_vget_v_f16mf2x5_f16mf2(vfloat16mf2x5_t src, size_t index) {777 return __riscv_vget_v_f16mf2x5_f16mf2(src, 0);778}779 780// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vget_v_f16mf2x6_f16mf2781// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {782// CHECK-RV64-NEXT: entry:783// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.tuple.extract.nxv2f16.triscv.vector.tuple_nxv4i8_6t(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[SRC]], i32 0)784// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]785//786vfloat16mf2_t test_vget_v_f16mf2x6_f16mf2(vfloat16mf2x6_t src, size_t index) {787 return __riscv_vget_v_f16mf2x6_f16mf2(src, 0);788}789 790// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vget_v_f16mf2x7_f16mf2791// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 7) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {792// CHECK-RV64-NEXT: entry:793// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.tuple.extract.nxv2f16.triscv.vector.tuple_nxv4i8_7t(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) [[SRC]], i32 0)794// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]795//796vfloat16mf2_t test_vget_v_f16mf2x7_f16mf2(vfloat16mf2x7_t src, size_t index) {797 return __riscv_vget_v_f16mf2x7_f16mf2(src, 0);798}799 800// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vget_v_f16mf2x8_f16mf2801// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 8) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {802// CHECK-RV64-NEXT: entry:803// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.tuple.extract.nxv2f16.triscv.vector.tuple_nxv4i8_8t(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) [[SRC]], i32 0)804// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]805//806vfloat16mf2_t test_vget_v_f16mf2x8_f16mf2(vfloat16mf2x8_t src, size_t index) {807 return __riscv_vget_v_f16mf2x8_f16mf2(src, 0);808}809 810// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vget_v_f16m1x2_f16m1811// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 2) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {812// CHECK-RV64-NEXT: entry:813// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.tuple.extract.nxv4f16.triscv.vector.tuple_nxv8i8_2t(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) [[SRC]], i32 0)814// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]815//816vfloat16m1_t test_vget_v_f16m1x2_f16m1(vfloat16m1x2_t src, size_t index) {817 return __riscv_vget_v_f16m1x2_f16m1(src, 0);818}819 820// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vget_v_f16m1x3_f16m1821// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 3) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {822// CHECK-RV64-NEXT: entry:823// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.tuple.extract.nxv4f16.triscv.vector.tuple_nxv8i8_3t(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) [[SRC]], i32 0)824// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]825//826vfloat16m1_t test_vget_v_f16m1x3_f16m1(vfloat16m1x3_t src, size_t index) {827 return __riscv_vget_v_f16m1x3_f16m1(src, 0);828}829 830// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vget_v_f16m1x4_f16m1831// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 4) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {832// CHECK-RV64-NEXT: entry:833// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.tuple.extract.nxv4f16.triscv.vector.tuple_nxv8i8_4t(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) [[SRC]], i32 0)834// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]835//836vfloat16m1_t test_vget_v_f16m1x4_f16m1(vfloat16m1x4_t src, size_t index) {837 return __riscv_vget_v_f16m1x4_f16m1(src, 0);838}839 840// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vget_v_f16m1x5_f16m1841// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 5) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {842// CHECK-RV64-NEXT: entry:843// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.tuple.extract.nxv4f16.triscv.vector.tuple_nxv8i8_5t(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) [[SRC]], i32 0)844// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]845//846vfloat16m1_t test_vget_v_f16m1x5_f16m1(vfloat16m1x5_t src, size_t index) {847 return __riscv_vget_v_f16m1x5_f16m1(src, 0);848}849 850// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vget_v_f16m1x6_f16m1851// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 6) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {852// CHECK-RV64-NEXT: entry:853// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.tuple.extract.nxv4f16.triscv.vector.tuple_nxv8i8_6t(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) [[SRC]], i32 0)854// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]855//856vfloat16m1_t test_vget_v_f16m1x6_f16m1(vfloat16m1x6_t src, size_t index) {857 return __riscv_vget_v_f16m1x6_f16m1(src, 0);858}859 860// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vget_v_f16m1x7_f16m1861// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 7) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {862// CHECK-RV64-NEXT: entry:863// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.tuple.extract.nxv4f16.triscv.vector.tuple_nxv8i8_7t(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) [[SRC]], i32 0)864// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]865//866vfloat16m1_t test_vget_v_f16m1x7_f16m1(vfloat16m1x7_t src, size_t index) {867 return __riscv_vget_v_f16m1x7_f16m1(src, 0);868}869 870// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vget_v_f16m1x8_f16m1871// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 8) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {872// CHECK-RV64-NEXT: entry:873// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.tuple.extract.nxv4f16.triscv.vector.tuple_nxv8i8_8t(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) [[SRC]], i32 0)874// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]875//876vfloat16m1_t test_vget_v_f16m1x8_f16m1(vfloat16m1x8_t src, size_t index) {877 return __riscv_vget_v_f16m1x8_f16m1(src, 0);878}879 880// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vget_v_f16m2x2_f16m2881// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 16 x i8>, 2) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {882// CHECK-RV64-NEXT: entry:883// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.tuple.extract.nxv8f16.triscv.vector.tuple_nxv16i8_2t(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) [[SRC]], i32 0)884// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]885//886vfloat16m2_t test_vget_v_f16m2x2_f16m2(vfloat16m2x2_t src, size_t index) {887 return __riscv_vget_v_f16m2x2_f16m2(src, 0);888}889 890// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vget_v_f16m2x3_f16m2891// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 16 x i8>, 3) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {892// CHECK-RV64-NEXT: entry:893// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.tuple.extract.nxv8f16.triscv.vector.tuple_nxv16i8_3t(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) [[SRC]], i32 0)894// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]895//896vfloat16m2_t test_vget_v_f16m2x3_f16m2(vfloat16m2x3_t src, size_t index) {897 return __riscv_vget_v_f16m2x3_f16m2(src, 0);898}899 900// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vget_v_f16m2x4_f16m2901// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 16 x i8>, 4) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {902// CHECK-RV64-NEXT: entry:903// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.tuple.extract.nxv8f16.triscv.vector.tuple_nxv16i8_4t(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) [[SRC]], i32 0)904// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]905//906vfloat16m2_t test_vget_v_f16m2x4_f16m2(vfloat16m2x4_t src, size_t index) {907 return __riscv_vget_v_f16m2x4_f16m2(src, 0);908}909 910// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vget_v_f16m4x2_f16m4911// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 32 x i8>, 2) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {912// CHECK-RV64-NEXT: entry:913// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.tuple.extract.nxv16f16.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) [[SRC]], i32 0)914// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]915//916vfloat16m4_t test_vget_v_f16m4x2_f16m4(vfloat16m4x2_t src, size_t index) {917 return __riscv_vget_v_f16m4x2_f16m4(src, 0);918}919 920// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vget_v_f32mf2x2_f32mf2921// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 2) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {922// CHECK-RV64-NEXT: entry:923// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.tuple.extract.nxv1f32.triscv.vector.tuple_nxv4i8_2t(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) [[SRC]], i32 0)924// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]925//926vfloat32mf2_t test_vget_v_f32mf2x2_f32mf2(vfloat32mf2x2_t src, size_t index) {927 return __riscv_vget_v_f32mf2x2_f32mf2(src, 0);928}929 930// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vget_v_f32mf2x3_f32mf2931// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {932// CHECK-RV64-NEXT: entry:933// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.tuple.extract.nxv1f32.triscv.vector.tuple_nxv4i8_3t(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[SRC]], i32 0)934// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]935//936vfloat32mf2_t test_vget_v_f32mf2x3_f32mf2(vfloat32mf2x3_t src, size_t index) {937 return __riscv_vget_v_f32mf2x3_f32mf2(src, 0);938}939 940// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vget_v_f32mf2x4_f32mf2941// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 4) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {942// CHECK-RV64-NEXT: entry:943// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.tuple.extract.nxv1f32.triscv.vector.tuple_nxv4i8_4t(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) [[SRC]], i32 0)944// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]945//946vfloat32mf2_t test_vget_v_f32mf2x4_f32mf2(vfloat32mf2x4_t src, size_t index) {947 return __riscv_vget_v_f32mf2x4_f32mf2(src, 0);948}949 950// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vget_v_f32mf2x5_f32mf2951// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {952// CHECK-RV64-NEXT: entry:953// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.tuple.extract.nxv1f32.triscv.vector.tuple_nxv4i8_5t(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[SRC]], i32 0)954// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]955//956vfloat32mf2_t test_vget_v_f32mf2x5_f32mf2(vfloat32mf2x5_t src, size_t index) {957 return __riscv_vget_v_f32mf2x5_f32mf2(src, 0);958}959 960// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vget_v_f32mf2x6_f32mf2961// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {962// CHECK-RV64-NEXT: entry:963// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.tuple.extract.nxv1f32.triscv.vector.tuple_nxv4i8_6t(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[SRC]], i32 0)964// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]965//966vfloat32mf2_t test_vget_v_f32mf2x6_f32mf2(vfloat32mf2x6_t src, size_t index) {967 return __riscv_vget_v_f32mf2x6_f32mf2(src, 0);968}969 970// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vget_v_f32mf2x7_f32mf2971// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 7) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {972// CHECK-RV64-NEXT: entry:973// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.tuple.extract.nxv1f32.triscv.vector.tuple_nxv4i8_7t(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) [[SRC]], i32 0)974// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]975//976vfloat32mf2_t test_vget_v_f32mf2x7_f32mf2(vfloat32mf2x7_t src, size_t index) {977 return __riscv_vget_v_f32mf2x7_f32mf2(src, 0);978}979 980// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vget_v_f32mf2x8_f32mf2981// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 8) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {982// CHECK-RV64-NEXT: entry:983// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.tuple.extract.nxv1f32.triscv.vector.tuple_nxv4i8_8t(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) [[SRC]], i32 0)984// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]985//986vfloat32mf2_t test_vget_v_f32mf2x8_f32mf2(vfloat32mf2x8_t src, size_t index) {987 return __riscv_vget_v_f32mf2x8_f32mf2(src, 0);988}989 990// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vget_v_f32m1x2_f32m1991// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 2) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {992// CHECK-RV64-NEXT: entry:993// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.tuple.extract.nxv2f32.triscv.vector.tuple_nxv8i8_2t(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) [[SRC]], i32 0)994// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]995//996vfloat32m1_t test_vget_v_f32m1x2_f32m1(vfloat32m1x2_t src, size_t index) {997 return __riscv_vget_v_f32m1x2_f32m1(src, 0);998}999 1000// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vget_v_f32m1x3_f32m11001// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 3) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1002// CHECK-RV64-NEXT: entry:1003// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.tuple.extract.nxv2f32.triscv.vector.tuple_nxv8i8_3t(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) [[SRC]], i32 0)1004// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]1005//1006vfloat32m1_t test_vget_v_f32m1x3_f32m1(vfloat32m1x3_t src, size_t index) {1007 return __riscv_vget_v_f32m1x3_f32m1(src, 0);1008}1009 1010// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vget_v_f32m1x4_f32m11011// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 4) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1012// CHECK-RV64-NEXT: entry:1013// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.tuple.extract.nxv2f32.triscv.vector.tuple_nxv8i8_4t(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) [[SRC]], i32 0)1014// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]1015//1016vfloat32m1_t test_vget_v_f32m1x4_f32m1(vfloat32m1x4_t src, size_t index) {1017 return __riscv_vget_v_f32m1x4_f32m1(src, 0);1018}1019 1020// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vget_v_f32m1x5_f32m11021// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 5) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1022// CHECK-RV64-NEXT: entry:1023// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.tuple.extract.nxv2f32.triscv.vector.tuple_nxv8i8_5t(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) [[SRC]], i32 0)1024// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]1025//1026vfloat32m1_t test_vget_v_f32m1x5_f32m1(vfloat32m1x5_t src, size_t index) {1027 return __riscv_vget_v_f32m1x5_f32m1(src, 0);1028}1029 1030// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vget_v_f32m1x6_f32m11031// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 6) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1032// CHECK-RV64-NEXT: entry:1033// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.tuple.extract.nxv2f32.triscv.vector.tuple_nxv8i8_6t(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) [[SRC]], i32 0)1034// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]1035//1036vfloat32m1_t test_vget_v_f32m1x6_f32m1(vfloat32m1x6_t src, size_t index) {1037 return __riscv_vget_v_f32m1x6_f32m1(src, 0);1038}1039 1040// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vget_v_f32m1x7_f32m11041// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 7) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1042// CHECK-RV64-NEXT: entry:1043// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.tuple.extract.nxv2f32.triscv.vector.tuple_nxv8i8_7t(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) [[SRC]], i32 0)1044// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]1045//1046vfloat32m1_t test_vget_v_f32m1x7_f32m1(vfloat32m1x7_t src, size_t index) {1047 return __riscv_vget_v_f32m1x7_f32m1(src, 0);1048}1049 1050// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vget_v_f32m1x8_f32m11051// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 8) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1052// CHECK-RV64-NEXT: entry:1053// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.tuple.extract.nxv2f32.triscv.vector.tuple_nxv8i8_8t(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) [[SRC]], i32 0)1054// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]1055//1056vfloat32m1_t test_vget_v_f32m1x8_f32m1(vfloat32m1x8_t src, size_t index) {1057 return __riscv_vget_v_f32m1x8_f32m1(src, 0);1058}1059 1060// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vget_v_f32m2x2_f32m21061// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 16 x i8>, 2) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1062// CHECK-RV64-NEXT: entry:1063// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.tuple.extract.nxv4f32.triscv.vector.tuple_nxv16i8_2t(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) [[SRC]], i32 0)1064// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]1065//1066vfloat32m2_t test_vget_v_f32m2x2_f32m2(vfloat32m2x2_t src, size_t index) {1067 return __riscv_vget_v_f32m2x2_f32m2(src, 0);1068}1069 1070// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vget_v_f32m2x3_f32m21071// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 16 x i8>, 3) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1072// CHECK-RV64-NEXT: entry:1073// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.tuple.extract.nxv4f32.triscv.vector.tuple_nxv16i8_3t(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) [[SRC]], i32 0)1074// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]1075//1076vfloat32m2_t test_vget_v_f32m2x3_f32m2(vfloat32m2x3_t src, size_t index) {1077 return __riscv_vget_v_f32m2x3_f32m2(src, 0);1078}1079 1080// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vget_v_f32m2x4_f32m21081// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 16 x i8>, 4) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1082// CHECK-RV64-NEXT: entry:1083// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.tuple.extract.nxv4f32.triscv.vector.tuple_nxv16i8_4t(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) [[SRC]], i32 0)1084// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]1085//1086vfloat32m2_t test_vget_v_f32m2x4_f32m2(vfloat32m2x4_t src, size_t index) {1087 return __riscv_vget_v_f32m2x4_f32m2(src, 0);1088}1089 1090// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vget_v_f32m4x2_f32m41091// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 32 x i8>, 2) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1092// CHECK-RV64-NEXT: entry:1093// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.tuple.extract.nxv8f32.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) [[SRC]], i32 0)1094// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]1095//1096vfloat32m4_t test_vget_v_f32m4x2_f32m4(vfloat32m4x2_t src, size_t index) {1097 return __riscv_vget_v_f32m4x2_f32m4(src, 0);1098}1099 1100// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vget_v_f64m1x2_f64m11101// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 2) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1102// CHECK-RV64-NEXT: entry:1103// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.tuple.extract.nxv1f64.triscv.vector.tuple_nxv8i8_2t(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) [[SRC]], i32 0)1104// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]1105//1106vfloat64m1_t test_vget_v_f64m1x2_f64m1(vfloat64m1x2_t src, size_t index) {1107 return __riscv_vget_v_f64m1x2_f64m1(src, 0);1108}1109 1110// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vget_v_f64m1x3_f64m11111// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 3) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1112// CHECK-RV64-NEXT: entry:1113// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.tuple.extract.nxv1f64.triscv.vector.tuple_nxv8i8_3t(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) [[SRC]], i32 0)1114// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]1115//1116vfloat64m1_t test_vget_v_f64m1x3_f64m1(vfloat64m1x3_t src, size_t index) {1117 return __riscv_vget_v_f64m1x3_f64m1(src, 0);1118}1119 1120// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vget_v_f64m1x4_f64m11121// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 4) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1122// CHECK-RV64-NEXT: entry:1123// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.tuple.extract.nxv1f64.triscv.vector.tuple_nxv8i8_4t(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) [[SRC]], i32 0)1124// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]1125//1126vfloat64m1_t test_vget_v_f64m1x4_f64m1(vfloat64m1x4_t src, size_t index) {1127 return __riscv_vget_v_f64m1x4_f64m1(src, 0);1128}1129 1130// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vget_v_f64m1x5_f64m11131// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 5) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1132// CHECK-RV64-NEXT: entry:1133// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.tuple.extract.nxv1f64.triscv.vector.tuple_nxv8i8_5t(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) [[SRC]], i32 0)1134// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]1135//1136vfloat64m1_t test_vget_v_f64m1x5_f64m1(vfloat64m1x5_t src, size_t index) {1137 return __riscv_vget_v_f64m1x5_f64m1(src, 0);1138}1139 1140// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vget_v_f64m1x6_f64m11141// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 6) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1142// CHECK-RV64-NEXT: entry:1143// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.tuple.extract.nxv1f64.triscv.vector.tuple_nxv8i8_6t(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) [[SRC]], i32 0)1144// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]1145//1146vfloat64m1_t test_vget_v_f64m1x6_f64m1(vfloat64m1x6_t src, size_t index) {1147 return __riscv_vget_v_f64m1x6_f64m1(src, 0);1148}1149 1150// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vget_v_f64m1x7_f64m11151// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 7) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1152// CHECK-RV64-NEXT: entry:1153// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.tuple.extract.nxv1f64.triscv.vector.tuple_nxv8i8_7t(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) [[SRC]], i32 0)1154// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]1155//1156vfloat64m1_t test_vget_v_f64m1x7_f64m1(vfloat64m1x7_t src, size_t index) {1157 return __riscv_vget_v_f64m1x7_f64m1(src, 0);1158}1159 1160// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vget_v_f64m1x8_f64m11161// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 8) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1162// CHECK-RV64-NEXT: entry:1163// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.tuple.extract.nxv1f64.triscv.vector.tuple_nxv8i8_8t(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) [[SRC]], i32 0)1164// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]1165//1166vfloat64m1_t test_vget_v_f64m1x8_f64m1(vfloat64m1x8_t src, size_t index) {1167 return __riscv_vget_v_f64m1x8_f64m1(src, 0);1168}1169 1170// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vget_v_f64m2x2_f64m21171// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 16 x i8>, 2) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1172// CHECK-RV64-NEXT: entry:1173// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.tuple.extract.nxv2f64.triscv.vector.tuple_nxv16i8_2t(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) [[SRC]], i32 0)1174// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]1175//1176vfloat64m2_t test_vget_v_f64m2x2_f64m2(vfloat64m2x2_t src, size_t index) {1177 return __riscv_vget_v_f64m2x2_f64m2(src, 0);1178}1179 1180// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vget_v_f64m2x3_f64m21181// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 16 x i8>, 3) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1182// CHECK-RV64-NEXT: entry:1183// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.tuple.extract.nxv2f64.triscv.vector.tuple_nxv16i8_3t(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) [[SRC]], i32 0)1184// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]1185//1186vfloat64m2_t test_vget_v_f64m2x3_f64m2(vfloat64m2x3_t src, size_t index) {1187 return __riscv_vget_v_f64m2x3_f64m2(src, 0);1188}1189 1190// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vget_v_f64m2x4_f64m21191// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 16 x i8>, 4) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1192// CHECK-RV64-NEXT: entry:1193// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.tuple.extract.nxv2f64.triscv.vector.tuple_nxv16i8_4t(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) [[SRC]], i32 0)1194// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]1195//1196vfloat64m2_t test_vget_v_f64m2x4_f64m2(vfloat64m2x4_t src, size_t index) {1197 return __riscv_vget_v_f64m2x4_f64m2(src, 0);1198}1199 1200// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vget_v_f64m4x2_f64m41201// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 32 x i8>, 2) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1202// CHECK-RV64-NEXT: entry:1203// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.tuple.extract.nxv4f64.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) [[SRC]], i32 0)1204// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]1205//1206vfloat64m4_t test_vget_v_f64m4x2_f64m4(vfloat64m4x2_t src, size_t index) {1207 return __riscv_vget_v_f64m4x2_f64m4(src, 0);1208}1209 1210// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vget_v_i8mf8x2_i8mf81211// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 1 x i8>, 2) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1212// CHECK-RV64-NEXT: entry:1213// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.tuple.extract.nxv1i8.triscv.vector.tuple_nxv1i8_2t(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) [[SRC]], i32 0)1214// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]1215//1216vint8mf8_t test_vget_v_i8mf8x2_i8mf8(vint8mf8x2_t src, size_t index) {1217 return __riscv_vget_v_i8mf8x2_i8mf8(src, 0);1218}1219 1220// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vget_v_i8mf8x3_i8mf81221// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 1 x i8>, 3) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1222// CHECK-RV64-NEXT: entry:1223// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.tuple.extract.nxv1i8.triscv.vector.tuple_nxv1i8_3t(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) [[SRC]], i32 0)1224// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]1225//1226vint8mf8_t test_vget_v_i8mf8x3_i8mf8(vint8mf8x3_t src, size_t index) {1227 return __riscv_vget_v_i8mf8x3_i8mf8(src, 0);1228}1229 1230// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vget_v_i8mf8x4_i8mf81231// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 1 x i8>, 4) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1232// CHECK-RV64-NEXT: entry:1233// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.tuple.extract.nxv1i8.triscv.vector.tuple_nxv1i8_4t(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) [[SRC]], i32 0)1234// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]1235//1236vint8mf8_t test_vget_v_i8mf8x4_i8mf8(vint8mf8x4_t src, size_t index) {1237 return __riscv_vget_v_i8mf8x4_i8mf8(src, 0);1238}1239 1240// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vget_v_i8mf8x5_i8mf81241// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 1 x i8>, 5) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1242// CHECK-RV64-NEXT: entry:1243// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.tuple.extract.nxv1i8.triscv.vector.tuple_nxv1i8_5t(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) [[SRC]], i32 0)1244// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]1245//1246vint8mf8_t test_vget_v_i8mf8x5_i8mf8(vint8mf8x5_t src, size_t index) {1247 return __riscv_vget_v_i8mf8x5_i8mf8(src, 0);1248}1249 1250// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vget_v_i8mf8x6_i8mf81251// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 1 x i8>, 6) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1252// CHECK-RV64-NEXT: entry:1253// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.tuple.extract.nxv1i8.triscv.vector.tuple_nxv1i8_6t(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) [[SRC]], i32 0)1254// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]1255//1256vint8mf8_t test_vget_v_i8mf8x6_i8mf8(vint8mf8x6_t src, size_t index) {1257 return __riscv_vget_v_i8mf8x6_i8mf8(src, 0);1258}1259 1260// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vget_v_i8mf8x7_i8mf81261// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 1 x i8>, 7) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1262// CHECK-RV64-NEXT: entry:1263// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.tuple.extract.nxv1i8.triscv.vector.tuple_nxv1i8_7t(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) [[SRC]], i32 0)1264// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]1265//1266vint8mf8_t test_vget_v_i8mf8x7_i8mf8(vint8mf8x7_t src, size_t index) {1267 return __riscv_vget_v_i8mf8x7_i8mf8(src, 0);1268}1269 1270// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vget_v_i8mf8x8_i8mf81271// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 1 x i8>, 8) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1272// CHECK-RV64-NEXT: entry:1273// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.tuple.extract.nxv1i8.triscv.vector.tuple_nxv1i8_8t(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) [[SRC]], i32 0)1274// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]1275//1276vint8mf8_t test_vget_v_i8mf8x8_i8mf8(vint8mf8x8_t src, size_t index) {1277 return __riscv_vget_v_i8mf8x8_i8mf8(src, 0);1278}1279 1280// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vget_v_i8mf4x2_i8mf41281// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 2 x i8>, 2) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1282// CHECK-RV64-NEXT: entry:1283// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.tuple.extract.nxv2i8.triscv.vector.tuple_nxv2i8_2t(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) [[SRC]], i32 0)1284// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]1285//1286vint8mf4_t test_vget_v_i8mf4x2_i8mf4(vint8mf4x2_t src, size_t index) {1287 return __riscv_vget_v_i8mf4x2_i8mf4(src, 0);1288}1289 1290// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vget_v_i8mf4x3_i8mf41291// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 2 x i8>, 3) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1292// CHECK-RV64-NEXT: entry:1293// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.tuple.extract.nxv2i8.triscv.vector.tuple_nxv2i8_3t(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) [[SRC]], i32 0)1294// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]1295//1296vint8mf4_t test_vget_v_i8mf4x3_i8mf4(vint8mf4x3_t src, size_t index) {1297 return __riscv_vget_v_i8mf4x3_i8mf4(src, 0);1298}1299 1300// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vget_v_i8mf4x4_i8mf41301// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 2 x i8>, 4) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1302// CHECK-RV64-NEXT: entry:1303// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.tuple.extract.nxv2i8.triscv.vector.tuple_nxv2i8_4t(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) [[SRC]], i32 0)1304// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]1305//1306vint8mf4_t test_vget_v_i8mf4x4_i8mf4(vint8mf4x4_t src, size_t index) {1307 return __riscv_vget_v_i8mf4x4_i8mf4(src, 0);1308}1309 1310// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vget_v_i8mf4x5_i8mf41311// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 2 x i8>, 5) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1312// CHECK-RV64-NEXT: entry:1313// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.tuple.extract.nxv2i8.triscv.vector.tuple_nxv2i8_5t(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) [[SRC]], i32 0)1314// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]1315//1316vint8mf4_t test_vget_v_i8mf4x5_i8mf4(vint8mf4x5_t src, size_t index) {1317 return __riscv_vget_v_i8mf4x5_i8mf4(src, 0);1318}1319 1320// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vget_v_i8mf4x6_i8mf41321// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 2 x i8>, 6) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1322// CHECK-RV64-NEXT: entry:1323// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.tuple.extract.nxv2i8.triscv.vector.tuple_nxv2i8_6t(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) [[SRC]], i32 0)1324// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]1325//1326vint8mf4_t test_vget_v_i8mf4x6_i8mf4(vint8mf4x6_t src, size_t index) {1327 return __riscv_vget_v_i8mf4x6_i8mf4(src, 0);1328}1329 1330// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vget_v_i8mf4x7_i8mf41331// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 2 x i8>, 7) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1332// CHECK-RV64-NEXT: entry:1333// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.tuple.extract.nxv2i8.triscv.vector.tuple_nxv2i8_7t(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) [[SRC]], i32 0)1334// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]1335//1336vint8mf4_t test_vget_v_i8mf4x7_i8mf4(vint8mf4x7_t src, size_t index) {1337 return __riscv_vget_v_i8mf4x7_i8mf4(src, 0);1338}1339 1340// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vget_v_i8mf4x8_i8mf41341// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 2 x i8>, 8) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1342// CHECK-RV64-NEXT: entry:1343// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.tuple.extract.nxv2i8.triscv.vector.tuple_nxv2i8_8t(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) [[SRC]], i32 0)1344// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]1345//1346vint8mf4_t test_vget_v_i8mf4x8_i8mf4(vint8mf4x8_t src, size_t index) {1347 return __riscv_vget_v_i8mf4x8_i8mf4(src, 0);1348}1349 1350// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vget_v_i8mf2x2_i8mf21351// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 2) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1352// CHECK-RV64-NEXT: entry:1353// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.tuple.extract.nxv4i8.triscv.vector.tuple_nxv4i8_2t(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) [[SRC]], i32 0)1354// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]1355//1356vint8mf2_t test_vget_v_i8mf2x2_i8mf2(vint8mf2x2_t src, size_t index) {1357 return __riscv_vget_v_i8mf2x2_i8mf2(src, 0);1358}1359 1360// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vget_v_i8mf2x3_i8mf21361// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1362// CHECK-RV64-NEXT: entry:1363// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.tuple.extract.nxv4i8.triscv.vector.tuple_nxv4i8_3t(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[SRC]], i32 0)1364// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]1365//1366vint8mf2_t test_vget_v_i8mf2x3_i8mf2(vint8mf2x3_t src, size_t index) {1367 return __riscv_vget_v_i8mf2x3_i8mf2(src, 0);1368}1369 1370// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vget_v_i8mf2x4_i8mf21371// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 4) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1372// CHECK-RV64-NEXT: entry:1373// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.tuple.extract.nxv4i8.triscv.vector.tuple_nxv4i8_4t(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) [[SRC]], i32 0)1374// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]1375//1376vint8mf2_t test_vget_v_i8mf2x4_i8mf2(vint8mf2x4_t src, size_t index) {1377 return __riscv_vget_v_i8mf2x4_i8mf2(src, 0);1378}1379 1380// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vget_v_i8mf2x5_i8mf21381// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1382// CHECK-RV64-NEXT: entry:1383// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.tuple.extract.nxv4i8.triscv.vector.tuple_nxv4i8_5t(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[SRC]], i32 0)1384// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]1385//1386vint8mf2_t test_vget_v_i8mf2x5_i8mf2(vint8mf2x5_t src, size_t index) {1387 return __riscv_vget_v_i8mf2x5_i8mf2(src, 0);1388}1389 1390// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vget_v_i8mf2x6_i8mf21391// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1392// CHECK-RV64-NEXT: entry:1393// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.tuple.extract.nxv4i8.triscv.vector.tuple_nxv4i8_6t(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[SRC]], i32 0)1394// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]1395//1396vint8mf2_t test_vget_v_i8mf2x6_i8mf2(vint8mf2x6_t src, size_t index) {1397 return __riscv_vget_v_i8mf2x6_i8mf2(src, 0);1398}1399 1400// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vget_v_i8mf2x7_i8mf21401// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 7) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1402// CHECK-RV64-NEXT: entry:1403// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.tuple.extract.nxv4i8.triscv.vector.tuple_nxv4i8_7t(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) [[SRC]], i32 0)1404// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]1405//1406vint8mf2_t test_vget_v_i8mf2x7_i8mf2(vint8mf2x7_t src, size_t index) {1407 return __riscv_vget_v_i8mf2x7_i8mf2(src, 0);1408}1409 1410// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vget_v_i8mf2x8_i8mf21411// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 8) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1412// CHECK-RV64-NEXT: entry:1413// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.tuple.extract.nxv4i8.triscv.vector.tuple_nxv4i8_8t(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) [[SRC]], i32 0)1414// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]1415//1416vint8mf2_t test_vget_v_i8mf2x8_i8mf2(vint8mf2x8_t src, size_t index) {1417 return __riscv_vget_v_i8mf2x8_i8mf2(src, 0);1418}1419 1420// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vget_v_i8m1x2_i8m11421// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 2) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1422// CHECK-RV64-NEXT: entry:1423// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.tuple.extract.nxv8i8.triscv.vector.tuple_nxv8i8_2t(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) [[SRC]], i32 0)1424// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]1425//1426vint8m1_t test_vget_v_i8m1x2_i8m1(vint8m1x2_t src, size_t index) {1427 return __riscv_vget_v_i8m1x2_i8m1(src, 0);1428}1429 1430// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vget_v_i8m1x3_i8m11431// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 3) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1432// CHECK-RV64-NEXT: entry:1433// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.tuple.extract.nxv8i8.triscv.vector.tuple_nxv8i8_3t(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) [[SRC]], i32 0)1434// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]1435//1436vint8m1_t test_vget_v_i8m1x3_i8m1(vint8m1x3_t src, size_t index) {1437 return __riscv_vget_v_i8m1x3_i8m1(src, 0);1438}1439 1440// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vget_v_i8m1x4_i8m11441// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 4) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1442// CHECK-RV64-NEXT: entry:1443// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.tuple.extract.nxv8i8.triscv.vector.tuple_nxv8i8_4t(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) [[SRC]], i32 0)1444// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]1445//1446vint8m1_t test_vget_v_i8m1x4_i8m1(vint8m1x4_t src, size_t index) {1447 return __riscv_vget_v_i8m1x4_i8m1(src, 0);1448}1449 1450// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vget_v_i8m1x5_i8m11451// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 5) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1452// CHECK-RV64-NEXT: entry:1453// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.tuple.extract.nxv8i8.triscv.vector.tuple_nxv8i8_5t(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) [[SRC]], i32 0)1454// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]1455//1456vint8m1_t test_vget_v_i8m1x5_i8m1(vint8m1x5_t src, size_t index) {1457 return __riscv_vget_v_i8m1x5_i8m1(src, 0);1458}1459 1460// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vget_v_i8m1x6_i8m11461// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 6) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1462// CHECK-RV64-NEXT: entry:1463// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.tuple.extract.nxv8i8.triscv.vector.tuple_nxv8i8_6t(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) [[SRC]], i32 0)1464// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]1465//1466vint8m1_t test_vget_v_i8m1x6_i8m1(vint8m1x6_t src, size_t index) {1467 return __riscv_vget_v_i8m1x6_i8m1(src, 0);1468}1469 1470// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vget_v_i8m1x7_i8m11471// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 7) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1472// CHECK-RV64-NEXT: entry:1473// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.tuple.extract.nxv8i8.triscv.vector.tuple_nxv8i8_7t(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) [[SRC]], i32 0)1474// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]1475//1476vint8m1_t test_vget_v_i8m1x7_i8m1(vint8m1x7_t src, size_t index) {1477 return __riscv_vget_v_i8m1x7_i8m1(src, 0);1478}1479 1480// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vget_v_i8m1x8_i8m11481// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 8) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1482// CHECK-RV64-NEXT: entry:1483// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.tuple.extract.nxv8i8.triscv.vector.tuple_nxv8i8_8t(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) [[SRC]], i32 0)1484// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]1485//1486vint8m1_t test_vget_v_i8m1x8_i8m1(vint8m1x8_t src, size_t index) {1487 return __riscv_vget_v_i8m1x8_i8m1(src, 0);1488}1489 1490// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vget_v_i8m2x2_i8m21491// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 16 x i8>, 2) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1492// CHECK-RV64-NEXT: entry:1493// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.tuple.extract.nxv16i8.triscv.vector.tuple_nxv16i8_2t(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) [[SRC]], i32 0)1494// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]1495//1496vint8m2_t test_vget_v_i8m2x2_i8m2(vint8m2x2_t src, size_t index) {1497 return __riscv_vget_v_i8m2x2_i8m2(src, 0);1498}1499 1500// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vget_v_i8m2x3_i8m21501// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 16 x i8>, 3) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1502// CHECK-RV64-NEXT: entry:1503// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.tuple.extract.nxv16i8.triscv.vector.tuple_nxv16i8_3t(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) [[SRC]], i32 0)1504// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]1505//1506vint8m2_t test_vget_v_i8m2x3_i8m2(vint8m2x3_t src, size_t index) {1507 return __riscv_vget_v_i8m2x3_i8m2(src, 0);1508}1509 1510// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vget_v_i8m2x4_i8m21511// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 16 x i8>, 4) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1512// CHECK-RV64-NEXT: entry:1513// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.tuple.extract.nxv16i8.triscv.vector.tuple_nxv16i8_4t(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) [[SRC]], i32 0)1514// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]1515//1516vint8m2_t test_vget_v_i8m2x4_i8m2(vint8m2x4_t src, size_t index) {1517 return __riscv_vget_v_i8m2x4_i8m2(src, 0);1518}1519 1520// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vget_v_i8m4x2_i8m41521// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 32 x i8>, 2) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1522// CHECK-RV64-NEXT: entry:1523// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.tuple.extract.nxv32i8.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) [[SRC]], i32 0)1524// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]1525//1526vint8m4_t test_vget_v_i8m4x2_i8m4(vint8m4x2_t src, size_t index) {1527 return __riscv_vget_v_i8m4x2_i8m4(src, 0);1528}1529 1530// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vget_v_i16mf4x2_i16mf41531// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 2 x i8>, 2) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1532// CHECK-RV64-NEXT: entry:1533// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.tuple.extract.nxv1i16.triscv.vector.tuple_nxv2i8_2t(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) [[SRC]], i32 0)1534// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]1535//1536vint16mf4_t test_vget_v_i16mf4x2_i16mf4(vint16mf4x2_t src, size_t index) {1537 return __riscv_vget_v_i16mf4x2_i16mf4(src, 0);1538}1539 1540// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vget_v_i16mf4x3_i16mf41541// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 2 x i8>, 3) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1542// CHECK-RV64-NEXT: entry:1543// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.tuple.extract.nxv1i16.triscv.vector.tuple_nxv2i8_3t(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) [[SRC]], i32 0)1544// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]1545//1546vint16mf4_t test_vget_v_i16mf4x3_i16mf4(vint16mf4x3_t src, size_t index) {1547 return __riscv_vget_v_i16mf4x3_i16mf4(src, 0);1548}1549 1550// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vget_v_i16mf4x4_i16mf41551// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 2 x i8>, 4) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1552// CHECK-RV64-NEXT: entry:1553// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.tuple.extract.nxv1i16.triscv.vector.tuple_nxv2i8_4t(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) [[SRC]], i32 0)1554// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]1555//1556vint16mf4_t test_vget_v_i16mf4x4_i16mf4(vint16mf4x4_t src, size_t index) {1557 return __riscv_vget_v_i16mf4x4_i16mf4(src, 0);1558}1559 1560// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vget_v_i16mf4x5_i16mf41561// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 2 x i8>, 5) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1562// CHECK-RV64-NEXT: entry:1563// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.tuple.extract.nxv1i16.triscv.vector.tuple_nxv2i8_5t(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) [[SRC]], i32 0)1564// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]1565//1566vint16mf4_t test_vget_v_i16mf4x5_i16mf4(vint16mf4x5_t src, size_t index) {1567 return __riscv_vget_v_i16mf4x5_i16mf4(src, 0);1568}1569 1570// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vget_v_i16mf4x6_i16mf41571// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 2 x i8>, 6) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1572// CHECK-RV64-NEXT: entry:1573// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.tuple.extract.nxv1i16.triscv.vector.tuple_nxv2i8_6t(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) [[SRC]], i32 0)1574// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]1575//1576vint16mf4_t test_vget_v_i16mf4x6_i16mf4(vint16mf4x6_t src, size_t index) {1577 return __riscv_vget_v_i16mf4x6_i16mf4(src, 0);1578}1579 1580// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vget_v_i16mf4x7_i16mf41581// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 2 x i8>, 7) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1582// CHECK-RV64-NEXT: entry:1583// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.tuple.extract.nxv1i16.triscv.vector.tuple_nxv2i8_7t(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) [[SRC]], i32 0)1584// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]1585//1586vint16mf4_t test_vget_v_i16mf4x7_i16mf4(vint16mf4x7_t src, size_t index) {1587 return __riscv_vget_v_i16mf4x7_i16mf4(src, 0);1588}1589 1590// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vget_v_i16mf4x8_i16mf41591// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 2 x i8>, 8) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1592// CHECK-RV64-NEXT: entry:1593// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.tuple.extract.nxv1i16.triscv.vector.tuple_nxv2i8_8t(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) [[SRC]], i32 0)1594// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]1595//1596vint16mf4_t test_vget_v_i16mf4x8_i16mf4(vint16mf4x8_t src, size_t index) {1597 return __riscv_vget_v_i16mf4x8_i16mf4(src, 0);1598}1599 1600// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vget_v_i16mf2x2_i16mf21601// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 2) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1602// CHECK-RV64-NEXT: entry:1603// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.tuple.extract.nxv2i16.triscv.vector.tuple_nxv4i8_2t(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) [[SRC]], i32 0)1604// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]1605//1606vint16mf2_t test_vget_v_i16mf2x2_i16mf2(vint16mf2x2_t src, size_t index) {1607 return __riscv_vget_v_i16mf2x2_i16mf2(src, 0);1608}1609 1610// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vget_v_i16mf2x3_i16mf21611// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1612// CHECK-RV64-NEXT: entry:1613// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.tuple.extract.nxv2i16.triscv.vector.tuple_nxv4i8_3t(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[SRC]], i32 0)1614// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]1615//1616vint16mf2_t test_vget_v_i16mf2x3_i16mf2(vint16mf2x3_t src, size_t index) {1617 return __riscv_vget_v_i16mf2x3_i16mf2(src, 0);1618}1619 1620// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vget_v_i16mf2x4_i16mf21621// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 4) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1622// CHECK-RV64-NEXT: entry:1623// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.tuple.extract.nxv2i16.triscv.vector.tuple_nxv4i8_4t(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) [[SRC]], i32 0)1624// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]1625//1626vint16mf2_t test_vget_v_i16mf2x4_i16mf2(vint16mf2x4_t src, size_t index) {1627 return __riscv_vget_v_i16mf2x4_i16mf2(src, 0);1628}1629 1630// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vget_v_i16mf2x5_i16mf21631// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1632// CHECK-RV64-NEXT: entry:1633// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.tuple.extract.nxv2i16.triscv.vector.tuple_nxv4i8_5t(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[SRC]], i32 0)1634// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]1635//1636vint16mf2_t test_vget_v_i16mf2x5_i16mf2(vint16mf2x5_t src, size_t index) {1637 return __riscv_vget_v_i16mf2x5_i16mf2(src, 0);1638}1639 1640// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vget_v_i16mf2x6_i16mf21641// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1642// CHECK-RV64-NEXT: entry:1643// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.tuple.extract.nxv2i16.triscv.vector.tuple_nxv4i8_6t(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[SRC]], i32 0)1644// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]1645//1646vint16mf2_t test_vget_v_i16mf2x6_i16mf2(vint16mf2x6_t src, size_t index) {1647 return __riscv_vget_v_i16mf2x6_i16mf2(src, 0);1648}1649 1650// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vget_v_i16mf2x7_i16mf21651// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 7) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1652// CHECK-RV64-NEXT: entry:1653// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.tuple.extract.nxv2i16.triscv.vector.tuple_nxv4i8_7t(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) [[SRC]], i32 0)1654// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]1655//1656vint16mf2_t test_vget_v_i16mf2x7_i16mf2(vint16mf2x7_t src, size_t index) {1657 return __riscv_vget_v_i16mf2x7_i16mf2(src, 0);1658}1659 1660// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vget_v_i16mf2x8_i16mf21661// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 8) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1662// CHECK-RV64-NEXT: entry:1663// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.tuple.extract.nxv2i16.triscv.vector.tuple_nxv4i8_8t(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) [[SRC]], i32 0)1664// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]1665//1666vint16mf2_t test_vget_v_i16mf2x8_i16mf2(vint16mf2x8_t src, size_t index) {1667 return __riscv_vget_v_i16mf2x8_i16mf2(src, 0);1668}1669 1670// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vget_v_i16m1x2_i16m11671// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 2) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1672// CHECK-RV64-NEXT: entry:1673// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.tuple.extract.nxv4i16.triscv.vector.tuple_nxv8i8_2t(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) [[SRC]], i32 0)1674// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]1675//1676vint16m1_t test_vget_v_i16m1x2_i16m1(vint16m1x2_t src, size_t index) {1677 return __riscv_vget_v_i16m1x2_i16m1(src, 0);1678}1679 1680// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vget_v_i16m1x3_i16m11681// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 3) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1682// CHECK-RV64-NEXT: entry:1683// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.tuple.extract.nxv4i16.triscv.vector.tuple_nxv8i8_3t(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) [[SRC]], i32 0)1684// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]1685//1686vint16m1_t test_vget_v_i16m1x3_i16m1(vint16m1x3_t src, size_t index) {1687 return __riscv_vget_v_i16m1x3_i16m1(src, 0);1688}1689 1690// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vget_v_i16m1x4_i16m11691// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 4) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1692// CHECK-RV64-NEXT: entry:1693// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.tuple.extract.nxv4i16.triscv.vector.tuple_nxv8i8_4t(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) [[SRC]], i32 0)1694// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]1695//1696vint16m1_t test_vget_v_i16m1x4_i16m1(vint16m1x4_t src, size_t index) {1697 return __riscv_vget_v_i16m1x4_i16m1(src, 0);1698}1699 1700// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vget_v_i16m1x5_i16m11701// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 5) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1702// CHECK-RV64-NEXT: entry:1703// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.tuple.extract.nxv4i16.triscv.vector.tuple_nxv8i8_5t(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) [[SRC]], i32 0)1704// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]1705//1706vint16m1_t test_vget_v_i16m1x5_i16m1(vint16m1x5_t src, size_t index) {1707 return __riscv_vget_v_i16m1x5_i16m1(src, 0);1708}1709 1710// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vget_v_i16m1x6_i16m11711// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 6) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1712// CHECK-RV64-NEXT: entry:1713// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.tuple.extract.nxv4i16.triscv.vector.tuple_nxv8i8_6t(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) [[SRC]], i32 0)1714// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]1715//1716vint16m1_t test_vget_v_i16m1x6_i16m1(vint16m1x6_t src, size_t index) {1717 return __riscv_vget_v_i16m1x6_i16m1(src, 0);1718}1719 1720// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vget_v_i16m1x7_i16m11721// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 7) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1722// CHECK-RV64-NEXT: entry:1723// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.tuple.extract.nxv4i16.triscv.vector.tuple_nxv8i8_7t(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) [[SRC]], i32 0)1724// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]1725//1726vint16m1_t test_vget_v_i16m1x7_i16m1(vint16m1x7_t src, size_t index) {1727 return __riscv_vget_v_i16m1x7_i16m1(src, 0);1728}1729 1730// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vget_v_i16m1x8_i16m11731// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 8) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1732// CHECK-RV64-NEXT: entry:1733// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.tuple.extract.nxv4i16.triscv.vector.tuple_nxv8i8_8t(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) [[SRC]], i32 0)1734// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]1735//1736vint16m1_t test_vget_v_i16m1x8_i16m1(vint16m1x8_t src, size_t index) {1737 return __riscv_vget_v_i16m1x8_i16m1(src, 0);1738}1739 1740// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vget_v_i16m2x2_i16m21741// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 16 x i8>, 2) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1742// CHECK-RV64-NEXT: entry:1743// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.tuple.extract.nxv8i16.triscv.vector.tuple_nxv16i8_2t(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) [[SRC]], i32 0)1744// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]1745//1746vint16m2_t test_vget_v_i16m2x2_i16m2(vint16m2x2_t src, size_t index) {1747 return __riscv_vget_v_i16m2x2_i16m2(src, 0);1748}1749 1750// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vget_v_i16m2x3_i16m21751// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 16 x i8>, 3) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1752// CHECK-RV64-NEXT: entry:1753// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.tuple.extract.nxv8i16.triscv.vector.tuple_nxv16i8_3t(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) [[SRC]], i32 0)1754// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]1755//1756vint16m2_t test_vget_v_i16m2x3_i16m2(vint16m2x3_t src, size_t index) {1757 return __riscv_vget_v_i16m2x3_i16m2(src, 0);1758}1759 1760// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vget_v_i16m2x4_i16m21761// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 16 x i8>, 4) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1762// CHECK-RV64-NEXT: entry:1763// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.tuple.extract.nxv8i16.triscv.vector.tuple_nxv16i8_4t(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) [[SRC]], i32 0)1764// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]1765//1766vint16m2_t test_vget_v_i16m2x4_i16m2(vint16m2x4_t src, size_t index) {1767 return __riscv_vget_v_i16m2x4_i16m2(src, 0);1768}1769 1770// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vget_v_i16m4x2_i16m41771// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 32 x i8>, 2) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1772// CHECK-RV64-NEXT: entry:1773// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.tuple.extract.nxv16i16.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) [[SRC]], i32 0)1774// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]1775//1776vint16m4_t test_vget_v_i16m4x2_i16m4(vint16m4x2_t src, size_t index) {1777 return __riscv_vget_v_i16m4x2_i16m4(src, 0);1778}1779 1780// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vget_v_i32mf2x2_i32mf21781// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 2) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1782// CHECK-RV64-NEXT: entry:1783// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_2t(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) [[SRC]], i32 0)1784// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]1785//1786vint32mf2_t test_vget_v_i32mf2x2_i32mf2(vint32mf2x2_t src, size_t index) {1787 return __riscv_vget_v_i32mf2x2_i32mf2(src, 0);1788}1789 1790// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vget_v_i32mf2x3_i32mf21791// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1792// CHECK-RV64-NEXT: entry:1793// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_3t(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[SRC]], i32 0)1794// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]1795//1796vint32mf2_t test_vget_v_i32mf2x3_i32mf2(vint32mf2x3_t src, size_t index) {1797 return __riscv_vget_v_i32mf2x3_i32mf2(src, 0);1798}1799 1800// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vget_v_i32mf2x4_i32mf21801// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 4) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1802// CHECK-RV64-NEXT: entry:1803// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_4t(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) [[SRC]], i32 0)1804// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]1805//1806vint32mf2_t test_vget_v_i32mf2x4_i32mf2(vint32mf2x4_t src, size_t index) {1807 return __riscv_vget_v_i32mf2x4_i32mf2(src, 0);1808}1809 1810// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vget_v_i32mf2x5_i32mf21811// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1812// CHECK-RV64-NEXT: entry:1813// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_5t(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[SRC]], i32 0)1814// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]1815//1816vint32mf2_t test_vget_v_i32mf2x5_i32mf2(vint32mf2x5_t src, size_t index) {1817 return __riscv_vget_v_i32mf2x5_i32mf2(src, 0);1818}1819 1820// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vget_v_i32mf2x6_i32mf21821// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1822// CHECK-RV64-NEXT: entry:1823// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_6t(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[SRC]], i32 0)1824// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]1825//1826vint32mf2_t test_vget_v_i32mf2x6_i32mf2(vint32mf2x6_t src, size_t index) {1827 return __riscv_vget_v_i32mf2x6_i32mf2(src, 0);1828}1829 1830// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vget_v_i32mf2x7_i32mf21831// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 7) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1832// CHECK-RV64-NEXT: entry:1833// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_7t(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) [[SRC]], i32 0)1834// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]1835//1836vint32mf2_t test_vget_v_i32mf2x7_i32mf2(vint32mf2x7_t src, size_t index) {1837 return __riscv_vget_v_i32mf2x7_i32mf2(src, 0);1838}1839 1840// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vget_v_i32mf2x8_i32mf21841// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 8) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1842// CHECK-RV64-NEXT: entry:1843// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_8t(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) [[SRC]], i32 0)1844// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]1845//1846vint32mf2_t test_vget_v_i32mf2x8_i32mf2(vint32mf2x8_t src, size_t index) {1847 return __riscv_vget_v_i32mf2x8_i32mf2(src, 0);1848}1849 1850// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vget_v_i32m1x2_i32m11851// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 2) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1852// CHECK-RV64-NEXT: entry:1853// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.tuple.extract.nxv2i32.triscv.vector.tuple_nxv8i8_2t(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) [[SRC]], i32 0)1854// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]1855//1856vint32m1_t test_vget_v_i32m1x2_i32m1(vint32m1x2_t src, size_t index) {1857 return __riscv_vget_v_i32m1x2_i32m1(src, 0);1858}1859 1860// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vget_v_i32m1x3_i32m11861// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 3) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1862// CHECK-RV64-NEXT: entry:1863// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.tuple.extract.nxv2i32.triscv.vector.tuple_nxv8i8_3t(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) [[SRC]], i32 0)1864// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]1865//1866vint32m1_t test_vget_v_i32m1x3_i32m1(vint32m1x3_t src, size_t index) {1867 return __riscv_vget_v_i32m1x3_i32m1(src, 0);1868}1869 1870// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vget_v_i32m1x4_i32m11871// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 4) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1872// CHECK-RV64-NEXT: entry:1873// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.tuple.extract.nxv2i32.triscv.vector.tuple_nxv8i8_4t(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) [[SRC]], i32 0)1874// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]1875//1876vint32m1_t test_vget_v_i32m1x4_i32m1(vint32m1x4_t src, size_t index) {1877 return __riscv_vget_v_i32m1x4_i32m1(src, 0);1878}1879 1880// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vget_v_i32m1x5_i32m11881// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 5) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1882// CHECK-RV64-NEXT: entry:1883// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.tuple.extract.nxv2i32.triscv.vector.tuple_nxv8i8_5t(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) [[SRC]], i32 0)1884// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]1885//1886vint32m1_t test_vget_v_i32m1x5_i32m1(vint32m1x5_t src, size_t index) {1887 return __riscv_vget_v_i32m1x5_i32m1(src, 0);1888}1889 1890// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vget_v_i32m1x6_i32m11891// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 6) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1892// CHECK-RV64-NEXT: entry:1893// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.tuple.extract.nxv2i32.triscv.vector.tuple_nxv8i8_6t(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) [[SRC]], i32 0)1894// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]1895//1896vint32m1_t test_vget_v_i32m1x6_i32m1(vint32m1x6_t src, size_t index) {1897 return __riscv_vget_v_i32m1x6_i32m1(src, 0);1898}1899 1900// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vget_v_i32m1x7_i32m11901// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 7) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1902// CHECK-RV64-NEXT: entry:1903// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.tuple.extract.nxv2i32.triscv.vector.tuple_nxv8i8_7t(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) [[SRC]], i32 0)1904// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]1905//1906vint32m1_t test_vget_v_i32m1x7_i32m1(vint32m1x7_t src, size_t index) {1907 return __riscv_vget_v_i32m1x7_i32m1(src, 0);1908}1909 1910// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vget_v_i32m1x8_i32m11911// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 8) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1912// CHECK-RV64-NEXT: entry:1913// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.tuple.extract.nxv2i32.triscv.vector.tuple_nxv8i8_8t(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) [[SRC]], i32 0)1914// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]1915//1916vint32m1_t test_vget_v_i32m1x8_i32m1(vint32m1x8_t src, size_t index) {1917 return __riscv_vget_v_i32m1x8_i32m1(src, 0);1918}1919 1920// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vget_v_i32m2x2_i32m21921// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 16 x i8>, 2) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1922// CHECK-RV64-NEXT: entry:1923// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.tuple.extract.nxv4i32.triscv.vector.tuple_nxv16i8_2t(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) [[SRC]], i32 0)1924// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]1925//1926vint32m2_t test_vget_v_i32m2x2_i32m2(vint32m2x2_t src, size_t index) {1927 return __riscv_vget_v_i32m2x2_i32m2(src, 0);1928}1929 1930// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vget_v_i32m2x3_i32m21931// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 16 x i8>, 3) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1932// CHECK-RV64-NEXT: entry:1933// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.tuple.extract.nxv4i32.triscv.vector.tuple_nxv16i8_3t(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) [[SRC]], i32 0)1934// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]1935//1936vint32m2_t test_vget_v_i32m2x3_i32m2(vint32m2x3_t src, size_t index) {1937 return __riscv_vget_v_i32m2x3_i32m2(src, 0);1938}1939 1940// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vget_v_i32m2x4_i32m21941// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 16 x i8>, 4) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1942// CHECK-RV64-NEXT: entry:1943// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.tuple.extract.nxv4i32.triscv.vector.tuple_nxv16i8_4t(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) [[SRC]], i32 0)1944// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]1945//1946vint32m2_t test_vget_v_i32m2x4_i32m2(vint32m2x4_t src, size_t index) {1947 return __riscv_vget_v_i32m2x4_i32m2(src, 0);1948}1949 1950// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vget_v_i32m4x2_i32m41951// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 32 x i8>, 2) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1952// CHECK-RV64-NEXT: entry:1953// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.tuple.extract.nxv8i32.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) [[SRC]], i32 0)1954// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]1955//1956vint32m4_t test_vget_v_i32m4x2_i32m4(vint32m4x2_t src, size_t index) {1957 return __riscv_vget_v_i32m4x2_i32m4(src, 0);1958}1959 1960// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vget_v_i64m1x2_i64m11961// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 2) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1962// CHECK-RV64-NEXT: entry:1963// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.tuple.extract.nxv1i64.triscv.vector.tuple_nxv8i8_2t(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) [[SRC]], i32 0)1964// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]1965//1966vint64m1_t test_vget_v_i64m1x2_i64m1(vint64m1x2_t src, size_t index) {1967 return __riscv_vget_v_i64m1x2_i64m1(src, 0);1968}1969 1970// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vget_v_i64m1x3_i64m11971// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 3) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1972// CHECK-RV64-NEXT: entry:1973// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.tuple.extract.nxv1i64.triscv.vector.tuple_nxv8i8_3t(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) [[SRC]], i32 0)1974// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]1975//1976vint64m1_t test_vget_v_i64m1x3_i64m1(vint64m1x3_t src, size_t index) {1977 return __riscv_vget_v_i64m1x3_i64m1(src, 0);1978}1979 1980// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vget_v_i64m1x4_i64m11981// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 4) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1982// CHECK-RV64-NEXT: entry:1983// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.tuple.extract.nxv1i64.triscv.vector.tuple_nxv8i8_4t(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) [[SRC]], i32 0)1984// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]1985//1986vint64m1_t test_vget_v_i64m1x4_i64m1(vint64m1x4_t src, size_t index) {1987 return __riscv_vget_v_i64m1x4_i64m1(src, 0);1988}1989 1990// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vget_v_i64m1x5_i64m11991// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 5) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {1992// CHECK-RV64-NEXT: entry:1993// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.tuple.extract.nxv1i64.triscv.vector.tuple_nxv8i8_5t(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) [[SRC]], i32 0)1994// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]1995//1996vint64m1_t test_vget_v_i64m1x5_i64m1(vint64m1x5_t src, size_t index) {1997 return __riscv_vget_v_i64m1x5_i64m1(src, 0);1998}1999 2000// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vget_v_i64m1x6_i64m12001// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 6) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2002// CHECK-RV64-NEXT: entry:2003// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.tuple.extract.nxv1i64.triscv.vector.tuple_nxv8i8_6t(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) [[SRC]], i32 0)2004// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]2005//2006vint64m1_t test_vget_v_i64m1x6_i64m1(vint64m1x6_t src, size_t index) {2007 return __riscv_vget_v_i64m1x6_i64m1(src, 0);2008}2009 2010// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vget_v_i64m1x7_i64m12011// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 7) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2012// CHECK-RV64-NEXT: entry:2013// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.tuple.extract.nxv1i64.triscv.vector.tuple_nxv8i8_7t(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) [[SRC]], i32 0)2014// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]2015//2016vint64m1_t test_vget_v_i64m1x7_i64m1(vint64m1x7_t src, size_t index) {2017 return __riscv_vget_v_i64m1x7_i64m1(src, 0);2018}2019 2020// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vget_v_i64m1x8_i64m12021// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 8) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2022// CHECK-RV64-NEXT: entry:2023// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.tuple.extract.nxv1i64.triscv.vector.tuple_nxv8i8_8t(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) [[SRC]], i32 0)2024// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]2025//2026vint64m1_t test_vget_v_i64m1x8_i64m1(vint64m1x8_t src, size_t index) {2027 return __riscv_vget_v_i64m1x8_i64m1(src, 0);2028}2029 2030// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vget_v_i64m2x2_i64m22031// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 16 x i8>, 2) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2032// CHECK-RV64-NEXT: entry:2033// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.tuple.extract.nxv2i64.triscv.vector.tuple_nxv16i8_2t(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) [[SRC]], i32 0)2034// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]2035//2036vint64m2_t test_vget_v_i64m2x2_i64m2(vint64m2x2_t src, size_t index) {2037 return __riscv_vget_v_i64m2x2_i64m2(src, 0);2038}2039 2040// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vget_v_i64m2x3_i64m22041// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 16 x i8>, 3) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2042// CHECK-RV64-NEXT: entry:2043// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.tuple.extract.nxv2i64.triscv.vector.tuple_nxv16i8_3t(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) [[SRC]], i32 0)2044// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]2045//2046vint64m2_t test_vget_v_i64m2x3_i64m2(vint64m2x3_t src, size_t index) {2047 return __riscv_vget_v_i64m2x3_i64m2(src, 0);2048}2049 2050// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vget_v_i64m2x4_i64m22051// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 16 x i8>, 4) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2052// CHECK-RV64-NEXT: entry:2053// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.tuple.extract.nxv2i64.triscv.vector.tuple_nxv16i8_4t(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) [[SRC]], i32 0)2054// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]2055//2056vint64m2_t test_vget_v_i64m2x4_i64m2(vint64m2x4_t src, size_t index) {2057 return __riscv_vget_v_i64m2x4_i64m2(src, 0);2058}2059 2060// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vget_v_i64m4x2_i64m42061// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 32 x i8>, 2) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2062// CHECK-RV64-NEXT: entry:2063// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.tuple.extract.nxv4i64.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) [[SRC]], i32 0)2064// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]2065//2066vint64m4_t test_vget_v_i64m4x2_i64m4(vint64m4x2_t src, size_t index) {2067 return __riscv_vget_v_i64m4x2_i64m4(src, 0);2068}2069 2070// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vget_v_u8mf8x2_u8mf82071// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 1 x i8>, 2) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2072// CHECK-RV64-NEXT: entry:2073// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.tuple.extract.nxv1i8.triscv.vector.tuple_nxv1i8_2t(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) [[SRC]], i32 0)2074// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]2075//2076vuint8mf8_t test_vget_v_u8mf8x2_u8mf8(vuint8mf8x2_t src, size_t index) {2077 return __riscv_vget_v_u8mf8x2_u8mf8(src, 0);2078}2079 2080// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vget_v_u8mf8x3_u8mf82081// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 1 x i8>, 3) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2082// CHECK-RV64-NEXT: entry:2083// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.tuple.extract.nxv1i8.triscv.vector.tuple_nxv1i8_3t(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) [[SRC]], i32 0)2084// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]2085//2086vuint8mf8_t test_vget_v_u8mf8x3_u8mf8(vuint8mf8x3_t src, size_t index) {2087 return __riscv_vget_v_u8mf8x3_u8mf8(src, 0);2088}2089 2090// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vget_v_u8mf8x4_u8mf82091// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 1 x i8>, 4) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2092// CHECK-RV64-NEXT: entry:2093// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.tuple.extract.nxv1i8.triscv.vector.tuple_nxv1i8_4t(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) [[SRC]], i32 0)2094// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]2095//2096vuint8mf8_t test_vget_v_u8mf8x4_u8mf8(vuint8mf8x4_t src, size_t index) {2097 return __riscv_vget_v_u8mf8x4_u8mf8(src, 0);2098}2099 2100// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vget_v_u8mf8x5_u8mf82101// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 1 x i8>, 5) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2102// CHECK-RV64-NEXT: entry:2103// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.tuple.extract.nxv1i8.triscv.vector.tuple_nxv1i8_5t(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) [[SRC]], i32 0)2104// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]2105//2106vuint8mf8_t test_vget_v_u8mf8x5_u8mf8(vuint8mf8x5_t src, size_t index) {2107 return __riscv_vget_v_u8mf8x5_u8mf8(src, 0);2108}2109 2110// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vget_v_u8mf8x6_u8mf82111// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 1 x i8>, 6) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2112// CHECK-RV64-NEXT: entry:2113// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.tuple.extract.nxv1i8.triscv.vector.tuple_nxv1i8_6t(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) [[SRC]], i32 0)2114// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]2115//2116vuint8mf8_t test_vget_v_u8mf8x6_u8mf8(vuint8mf8x6_t src, size_t index) {2117 return __riscv_vget_v_u8mf8x6_u8mf8(src, 0);2118}2119 2120// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vget_v_u8mf8x7_u8mf82121// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 1 x i8>, 7) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2122// CHECK-RV64-NEXT: entry:2123// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.tuple.extract.nxv1i8.triscv.vector.tuple_nxv1i8_7t(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) [[SRC]], i32 0)2124// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]2125//2126vuint8mf8_t test_vget_v_u8mf8x7_u8mf8(vuint8mf8x7_t src, size_t index) {2127 return __riscv_vget_v_u8mf8x7_u8mf8(src, 0);2128}2129 2130// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vget_v_u8mf8x8_u8mf82131// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 1 x i8>, 8) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2132// CHECK-RV64-NEXT: entry:2133// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.tuple.extract.nxv1i8.triscv.vector.tuple_nxv1i8_8t(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) [[SRC]], i32 0)2134// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]2135//2136vuint8mf8_t test_vget_v_u8mf8x8_u8mf8(vuint8mf8x8_t src, size_t index) {2137 return __riscv_vget_v_u8mf8x8_u8mf8(src, 0);2138}2139 2140// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vget_v_u8mf4x2_u8mf42141// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 2 x i8>, 2) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2142// CHECK-RV64-NEXT: entry:2143// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.tuple.extract.nxv2i8.triscv.vector.tuple_nxv2i8_2t(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) [[SRC]], i32 0)2144// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]2145//2146vuint8mf4_t test_vget_v_u8mf4x2_u8mf4(vuint8mf4x2_t src, size_t index) {2147 return __riscv_vget_v_u8mf4x2_u8mf4(src, 0);2148}2149 2150// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vget_v_u8mf4x3_u8mf42151// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 2 x i8>, 3) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2152// CHECK-RV64-NEXT: entry:2153// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.tuple.extract.nxv2i8.triscv.vector.tuple_nxv2i8_3t(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) [[SRC]], i32 0)2154// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]2155//2156vuint8mf4_t test_vget_v_u8mf4x3_u8mf4(vuint8mf4x3_t src, size_t index) {2157 return __riscv_vget_v_u8mf4x3_u8mf4(src, 0);2158}2159 2160// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vget_v_u8mf4x4_u8mf42161// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 2 x i8>, 4) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2162// CHECK-RV64-NEXT: entry:2163// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.tuple.extract.nxv2i8.triscv.vector.tuple_nxv2i8_4t(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) [[SRC]], i32 0)2164// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]2165//2166vuint8mf4_t test_vget_v_u8mf4x4_u8mf4(vuint8mf4x4_t src, size_t index) {2167 return __riscv_vget_v_u8mf4x4_u8mf4(src, 0);2168}2169 2170// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vget_v_u8mf4x5_u8mf42171// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 2 x i8>, 5) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2172// CHECK-RV64-NEXT: entry:2173// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.tuple.extract.nxv2i8.triscv.vector.tuple_nxv2i8_5t(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) [[SRC]], i32 0)2174// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]2175//2176vuint8mf4_t test_vget_v_u8mf4x5_u8mf4(vuint8mf4x5_t src, size_t index) {2177 return __riscv_vget_v_u8mf4x5_u8mf4(src, 0);2178}2179 2180// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vget_v_u8mf4x6_u8mf42181// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 2 x i8>, 6) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2182// CHECK-RV64-NEXT: entry:2183// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.tuple.extract.nxv2i8.triscv.vector.tuple_nxv2i8_6t(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) [[SRC]], i32 0)2184// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]2185//2186vuint8mf4_t test_vget_v_u8mf4x6_u8mf4(vuint8mf4x6_t src, size_t index) {2187 return __riscv_vget_v_u8mf4x6_u8mf4(src, 0);2188}2189 2190// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vget_v_u8mf4x7_u8mf42191// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 2 x i8>, 7) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2192// CHECK-RV64-NEXT: entry:2193// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.tuple.extract.nxv2i8.triscv.vector.tuple_nxv2i8_7t(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) [[SRC]], i32 0)2194// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]2195//2196vuint8mf4_t test_vget_v_u8mf4x7_u8mf4(vuint8mf4x7_t src, size_t index) {2197 return __riscv_vget_v_u8mf4x7_u8mf4(src, 0);2198}2199 2200// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vget_v_u8mf4x8_u8mf42201// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 2 x i8>, 8) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2202// CHECK-RV64-NEXT: entry:2203// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.tuple.extract.nxv2i8.triscv.vector.tuple_nxv2i8_8t(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) [[SRC]], i32 0)2204// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]2205//2206vuint8mf4_t test_vget_v_u8mf4x8_u8mf4(vuint8mf4x8_t src, size_t index) {2207 return __riscv_vget_v_u8mf4x8_u8mf4(src, 0);2208}2209 2210// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vget_v_u8mf2x2_u8mf22211// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 2) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2212// CHECK-RV64-NEXT: entry:2213// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.tuple.extract.nxv4i8.triscv.vector.tuple_nxv4i8_2t(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) [[SRC]], i32 0)2214// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]2215//2216vuint8mf2_t test_vget_v_u8mf2x2_u8mf2(vuint8mf2x2_t src, size_t index) {2217 return __riscv_vget_v_u8mf2x2_u8mf2(src, 0);2218}2219 2220// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vget_v_u8mf2x3_u8mf22221// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2222// CHECK-RV64-NEXT: entry:2223// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.tuple.extract.nxv4i8.triscv.vector.tuple_nxv4i8_3t(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[SRC]], i32 0)2224// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]2225//2226vuint8mf2_t test_vget_v_u8mf2x3_u8mf2(vuint8mf2x3_t src, size_t index) {2227 return __riscv_vget_v_u8mf2x3_u8mf2(src, 0);2228}2229 2230// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vget_v_u8mf2x4_u8mf22231// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 4) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2232// CHECK-RV64-NEXT: entry:2233// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.tuple.extract.nxv4i8.triscv.vector.tuple_nxv4i8_4t(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) [[SRC]], i32 0)2234// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]2235//2236vuint8mf2_t test_vget_v_u8mf2x4_u8mf2(vuint8mf2x4_t src, size_t index) {2237 return __riscv_vget_v_u8mf2x4_u8mf2(src, 0);2238}2239 2240// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vget_v_u8mf2x5_u8mf22241// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2242// CHECK-RV64-NEXT: entry:2243// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.tuple.extract.nxv4i8.triscv.vector.tuple_nxv4i8_5t(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[SRC]], i32 0)2244// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]2245//2246vuint8mf2_t test_vget_v_u8mf2x5_u8mf2(vuint8mf2x5_t src, size_t index) {2247 return __riscv_vget_v_u8mf2x5_u8mf2(src, 0);2248}2249 2250// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vget_v_u8mf2x6_u8mf22251// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2252// CHECK-RV64-NEXT: entry:2253// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.tuple.extract.nxv4i8.triscv.vector.tuple_nxv4i8_6t(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[SRC]], i32 0)2254// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]2255//2256vuint8mf2_t test_vget_v_u8mf2x6_u8mf2(vuint8mf2x6_t src, size_t index) {2257 return __riscv_vget_v_u8mf2x6_u8mf2(src, 0);2258}2259 2260// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vget_v_u8mf2x7_u8mf22261// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 7) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2262// CHECK-RV64-NEXT: entry:2263// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.tuple.extract.nxv4i8.triscv.vector.tuple_nxv4i8_7t(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) [[SRC]], i32 0)2264// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]2265//2266vuint8mf2_t test_vget_v_u8mf2x7_u8mf2(vuint8mf2x7_t src, size_t index) {2267 return __riscv_vget_v_u8mf2x7_u8mf2(src, 0);2268}2269 2270// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vget_v_u8mf2x8_u8mf22271// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 8) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2272// CHECK-RV64-NEXT: entry:2273// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.tuple.extract.nxv4i8.triscv.vector.tuple_nxv4i8_8t(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) [[SRC]], i32 0)2274// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]2275//2276vuint8mf2_t test_vget_v_u8mf2x8_u8mf2(vuint8mf2x8_t src, size_t index) {2277 return __riscv_vget_v_u8mf2x8_u8mf2(src, 0);2278}2279 2280// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vget_v_u8m1x2_u8m12281// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 2) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2282// CHECK-RV64-NEXT: entry:2283// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.tuple.extract.nxv8i8.triscv.vector.tuple_nxv8i8_2t(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) [[SRC]], i32 0)2284// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]2285//2286vuint8m1_t test_vget_v_u8m1x2_u8m1(vuint8m1x2_t src, size_t index) {2287 return __riscv_vget_v_u8m1x2_u8m1(src, 0);2288}2289 2290// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vget_v_u8m1x3_u8m12291// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 3) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2292// CHECK-RV64-NEXT: entry:2293// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.tuple.extract.nxv8i8.triscv.vector.tuple_nxv8i8_3t(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) [[SRC]], i32 0)2294// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]2295//2296vuint8m1_t test_vget_v_u8m1x3_u8m1(vuint8m1x3_t src, size_t index) {2297 return __riscv_vget_v_u8m1x3_u8m1(src, 0);2298}2299 2300// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vget_v_u8m1x4_u8m12301// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 4) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2302// CHECK-RV64-NEXT: entry:2303// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.tuple.extract.nxv8i8.triscv.vector.tuple_nxv8i8_4t(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) [[SRC]], i32 0)2304// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]2305//2306vuint8m1_t test_vget_v_u8m1x4_u8m1(vuint8m1x4_t src, size_t index) {2307 return __riscv_vget_v_u8m1x4_u8m1(src, 0);2308}2309 2310// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vget_v_u8m1x5_u8m12311// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 5) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2312// CHECK-RV64-NEXT: entry:2313// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.tuple.extract.nxv8i8.triscv.vector.tuple_nxv8i8_5t(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) [[SRC]], i32 0)2314// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]2315//2316vuint8m1_t test_vget_v_u8m1x5_u8m1(vuint8m1x5_t src, size_t index) {2317 return __riscv_vget_v_u8m1x5_u8m1(src, 0);2318}2319 2320// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vget_v_u8m1x6_u8m12321// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 6) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2322// CHECK-RV64-NEXT: entry:2323// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.tuple.extract.nxv8i8.triscv.vector.tuple_nxv8i8_6t(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) [[SRC]], i32 0)2324// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]2325//2326vuint8m1_t test_vget_v_u8m1x6_u8m1(vuint8m1x6_t src, size_t index) {2327 return __riscv_vget_v_u8m1x6_u8m1(src, 0);2328}2329 2330// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vget_v_u8m1x7_u8m12331// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 7) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2332// CHECK-RV64-NEXT: entry:2333// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.tuple.extract.nxv8i8.triscv.vector.tuple_nxv8i8_7t(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) [[SRC]], i32 0)2334// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]2335//2336vuint8m1_t test_vget_v_u8m1x7_u8m1(vuint8m1x7_t src, size_t index) {2337 return __riscv_vget_v_u8m1x7_u8m1(src, 0);2338}2339 2340// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vget_v_u8m1x8_u8m12341// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 8) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2342// CHECK-RV64-NEXT: entry:2343// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.tuple.extract.nxv8i8.triscv.vector.tuple_nxv8i8_8t(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) [[SRC]], i32 0)2344// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]2345//2346vuint8m1_t test_vget_v_u8m1x8_u8m1(vuint8m1x8_t src, size_t index) {2347 return __riscv_vget_v_u8m1x8_u8m1(src, 0);2348}2349 2350// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vget_v_u8m2x2_u8m22351// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 16 x i8>, 2) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2352// CHECK-RV64-NEXT: entry:2353// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.tuple.extract.nxv16i8.triscv.vector.tuple_nxv16i8_2t(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) [[SRC]], i32 0)2354// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]2355//2356vuint8m2_t test_vget_v_u8m2x2_u8m2(vuint8m2x2_t src, size_t index) {2357 return __riscv_vget_v_u8m2x2_u8m2(src, 0);2358}2359 2360// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vget_v_u8m2x3_u8m22361// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 16 x i8>, 3) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2362// CHECK-RV64-NEXT: entry:2363// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.tuple.extract.nxv16i8.triscv.vector.tuple_nxv16i8_3t(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) [[SRC]], i32 0)2364// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]2365//2366vuint8m2_t test_vget_v_u8m2x3_u8m2(vuint8m2x3_t src, size_t index) {2367 return __riscv_vget_v_u8m2x3_u8m2(src, 0);2368}2369 2370// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vget_v_u8m2x4_u8m22371// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 16 x i8>, 4) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2372// CHECK-RV64-NEXT: entry:2373// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.tuple.extract.nxv16i8.triscv.vector.tuple_nxv16i8_4t(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) [[SRC]], i32 0)2374// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]2375//2376vuint8m2_t test_vget_v_u8m2x4_u8m2(vuint8m2x4_t src, size_t index) {2377 return __riscv_vget_v_u8m2x4_u8m2(src, 0);2378}2379 2380// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vget_v_u8m4x2_u8m42381// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 32 x i8>, 2) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2382// CHECK-RV64-NEXT: entry:2383// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.tuple.extract.nxv32i8.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) [[SRC]], i32 0)2384// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]2385//2386vuint8m4_t test_vget_v_u8m4x2_u8m4(vuint8m4x2_t src, size_t index) {2387 return __riscv_vget_v_u8m4x2_u8m4(src, 0);2388}2389 2390// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vget_v_u16mf4x2_u16mf42391// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 2 x i8>, 2) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2392// CHECK-RV64-NEXT: entry:2393// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.tuple.extract.nxv1i16.triscv.vector.tuple_nxv2i8_2t(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) [[SRC]], i32 0)2394// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]2395//2396vuint16mf4_t test_vget_v_u16mf4x2_u16mf4(vuint16mf4x2_t src, size_t index) {2397 return __riscv_vget_v_u16mf4x2_u16mf4(src, 0);2398}2399 2400// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vget_v_u16mf4x3_u16mf42401// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 2 x i8>, 3) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2402// CHECK-RV64-NEXT: entry:2403// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.tuple.extract.nxv1i16.triscv.vector.tuple_nxv2i8_3t(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) [[SRC]], i32 0)2404// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]2405//2406vuint16mf4_t test_vget_v_u16mf4x3_u16mf4(vuint16mf4x3_t src, size_t index) {2407 return __riscv_vget_v_u16mf4x3_u16mf4(src, 0);2408}2409 2410// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vget_v_u16mf4x4_u16mf42411// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 2 x i8>, 4) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2412// CHECK-RV64-NEXT: entry:2413// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.tuple.extract.nxv1i16.triscv.vector.tuple_nxv2i8_4t(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) [[SRC]], i32 0)2414// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]2415//2416vuint16mf4_t test_vget_v_u16mf4x4_u16mf4(vuint16mf4x4_t src, size_t index) {2417 return __riscv_vget_v_u16mf4x4_u16mf4(src, 0);2418}2419 2420// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vget_v_u16mf4x5_u16mf42421// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 2 x i8>, 5) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2422// CHECK-RV64-NEXT: entry:2423// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.tuple.extract.nxv1i16.triscv.vector.tuple_nxv2i8_5t(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) [[SRC]], i32 0)2424// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]2425//2426vuint16mf4_t test_vget_v_u16mf4x5_u16mf4(vuint16mf4x5_t src, size_t index) {2427 return __riscv_vget_v_u16mf4x5_u16mf4(src, 0);2428}2429 2430// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vget_v_u16mf4x6_u16mf42431// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 2 x i8>, 6) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2432// CHECK-RV64-NEXT: entry:2433// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.tuple.extract.nxv1i16.triscv.vector.tuple_nxv2i8_6t(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) [[SRC]], i32 0)2434// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]2435//2436vuint16mf4_t test_vget_v_u16mf4x6_u16mf4(vuint16mf4x6_t src, size_t index) {2437 return __riscv_vget_v_u16mf4x6_u16mf4(src, 0);2438}2439 2440// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vget_v_u16mf4x7_u16mf42441// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 2 x i8>, 7) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2442// CHECK-RV64-NEXT: entry:2443// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.tuple.extract.nxv1i16.triscv.vector.tuple_nxv2i8_7t(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) [[SRC]], i32 0)2444// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]2445//2446vuint16mf4_t test_vget_v_u16mf4x7_u16mf4(vuint16mf4x7_t src, size_t index) {2447 return __riscv_vget_v_u16mf4x7_u16mf4(src, 0);2448}2449 2450// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vget_v_u16mf4x8_u16mf42451// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 2 x i8>, 8) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2452// CHECK-RV64-NEXT: entry:2453// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.tuple.extract.nxv1i16.triscv.vector.tuple_nxv2i8_8t(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) [[SRC]], i32 0)2454// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]2455//2456vuint16mf4_t test_vget_v_u16mf4x8_u16mf4(vuint16mf4x8_t src, size_t index) {2457 return __riscv_vget_v_u16mf4x8_u16mf4(src, 0);2458}2459 2460// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vget_v_u16mf2x2_u16mf22461// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 2) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2462// CHECK-RV64-NEXT: entry:2463// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.tuple.extract.nxv2i16.triscv.vector.tuple_nxv4i8_2t(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) [[SRC]], i32 0)2464// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]2465//2466vuint16mf2_t test_vget_v_u16mf2x2_u16mf2(vuint16mf2x2_t src, size_t index) {2467 return __riscv_vget_v_u16mf2x2_u16mf2(src, 0);2468}2469 2470// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vget_v_u16mf2x3_u16mf22471// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2472// CHECK-RV64-NEXT: entry:2473// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.tuple.extract.nxv2i16.triscv.vector.tuple_nxv4i8_3t(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[SRC]], i32 0)2474// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]2475//2476vuint16mf2_t test_vget_v_u16mf2x3_u16mf2(vuint16mf2x3_t src, size_t index) {2477 return __riscv_vget_v_u16mf2x3_u16mf2(src, 0);2478}2479 2480// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vget_v_u16mf2x4_u16mf22481// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 4) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2482// CHECK-RV64-NEXT: entry:2483// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.tuple.extract.nxv2i16.triscv.vector.tuple_nxv4i8_4t(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) [[SRC]], i32 0)2484// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]2485//2486vuint16mf2_t test_vget_v_u16mf2x4_u16mf2(vuint16mf2x4_t src, size_t index) {2487 return __riscv_vget_v_u16mf2x4_u16mf2(src, 0);2488}2489 2490// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vget_v_u16mf2x5_u16mf22491// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2492// CHECK-RV64-NEXT: entry:2493// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.tuple.extract.nxv2i16.triscv.vector.tuple_nxv4i8_5t(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[SRC]], i32 0)2494// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]2495//2496vuint16mf2_t test_vget_v_u16mf2x5_u16mf2(vuint16mf2x5_t src, size_t index) {2497 return __riscv_vget_v_u16mf2x5_u16mf2(src, 0);2498}2499 2500// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vget_v_u16mf2x6_u16mf22501// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2502// CHECK-RV64-NEXT: entry:2503// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.tuple.extract.nxv2i16.triscv.vector.tuple_nxv4i8_6t(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[SRC]], i32 0)2504// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]2505//2506vuint16mf2_t test_vget_v_u16mf2x6_u16mf2(vuint16mf2x6_t src, size_t index) {2507 return __riscv_vget_v_u16mf2x6_u16mf2(src, 0);2508}2509 2510// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vget_v_u16mf2x7_u16mf22511// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 7) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2512// CHECK-RV64-NEXT: entry:2513// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.tuple.extract.nxv2i16.triscv.vector.tuple_nxv4i8_7t(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) [[SRC]], i32 0)2514// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]2515//2516vuint16mf2_t test_vget_v_u16mf2x7_u16mf2(vuint16mf2x7_t src, size_t index) {2517 return __riscv_vget_v_u16mf2x7_u16mf2(src, 0);2518}2519 2520// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vget_v_u16mf2x8_u16mf22521// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 8) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2522// CHECK-RV64-NEXT: entry:2523// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.tuple.extract.nxv2i16.triscv.vector.tuple_nxv4i8_8t(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) [[SRC]], i32 0)2524// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]2525//2526vuint16mf2_t test_vget_v_u16mf2x8_u16mf2(vuint16mf2x8_t src, size_t index) {2527 return __riscv_vget_v_u16mf2x8_u16mf2(src, 0);2528}2529 2530// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vget_v_u16m1x2_u16m12531// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 2) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2532// CHECK-RV64-NEXT: entry:2533// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.tuple.extract.nxv4i16.triscv.vector.tuple_nxv8i8_2t(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) [[SRC]], i32 0)2534// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]2535//2536vuint16m1_t test_vget_v_u16m1x2_u16m1(vuint16m1x2_t src, size_t index) {2537 return __riscv_vget_v_u16m1x2_u16m1(src, 0);2538}2539 2540// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vget_v_u16m1x3_u16m12541// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 3) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2542// CHECK-RV64-NEXT: entry:2543// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.tuple.extract.nxv4i16.triscv.vector.tuple_nxv8i8_3t(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) [[SRC]], i32 0)2544// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]2545//2546vuint16m1_t test_vget_v_u16m1x3_u16m1(vuint16m1x3_t src, size_t index) {2547 return __riscv_vget_v_u16m1x3_u16m1(src, 0);2548}2549 2550// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vget_v_u16m1x4_u16m12551// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 4) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2552// CHECK-RV64-NEXT: entry:2553// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.tuple.extract.nxv4i16.triscv.vector.tuple_nxv8i8_4t(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) [[SRC]], i32 0)2554// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]2555//2556vuint16m1_t test_vget_v_u16m1x4_u16m1(vuint16m1x4_t src, size_t index) {2557 return __riscv_vget_v_u16m1x4_u16m1(src, 0);2558}2559 2560// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vget_v_u16m1x5_u16m12561// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 5) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2562// CHECK-RV64-NEXT: entry:2563// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.tuple.extract.nxv4i16.triscv.vector.tuple_nxv8i8_5t(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) [[SRC]], i32 0)2564// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]2565//2566vuint16m1_t test_vget_v_u16m1x5_u16m1(vuint16m1x5_t src, size_t index) {2567 return __riscv_vget_v_u16m1x5_u16m1(src, 0);2568}2569 2570// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vget_v_u16m1x6_u16m12571// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 6) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2572// CHECK-RV64-NEXT: entry:2573// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.tuple.extract.nxv4i16.triscv.vector.tuple_nxv8i8_6t(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) [[SRC]], i32 0)2574// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]2575//2576vuint16m1_t test_vget_v_u16m1x6_u16m1(vuint16m1x6_t src, size_t index) {2577 return __riscv_vget_v_u16m1x6_u16m1(src, 0);2578}2579 2580// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vget_v_u16m1x7_u16m12581// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 7) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2582// CHECK-RV64-NEXT: entry:2583// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.tuple.extract.nxv4i16.triscv.vector.tuple_nxv8i8_7t(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) [[SRC]], i32 0)2584// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]2585//2586vuint16m1_t test_vget_v_u16m1x7_u16m1(vuint16m1x7_t src, size_t index) {2587 return __riscv_vget_v_u16m1x7_u16m1(src, 0);2588}2589 2590// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vget_v_u16m1x8_u16m12591// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 8) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2592// CHECK-RV64-NEXT: entry:2593// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.tuple.extract.nxv4i16.triscv.vector.tuple_nxv8i8_8t(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) [[SRC]], i32 0)2594// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]2595//2596vuint16m1_t test_vget_v_u16m1x8_u16m1(vuint16m1x8_t src, size_t index) {2597 return __riscv_vget_v_u16m1x8_u16m1(src, 0);2598}2599 2600// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vget_v_u16m2x2_u16m22601// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 16 x i8>, 2) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2602// CHECK-RV64-NEXT: entry:2603// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.tuple.extract.nxv8i16.triscv.vector.tuple_nxv16i8_2t(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) [[SRC]], i32 0)2604// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]2605//2606vuint16m2_t test_vget_v_u16m2x2_u16m2(vuint16m2x2_t src, size_t index) {2607 return __riscv_vget_v_u16m2x2_u16m2(src, 0);2608}2609 2610// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vget_v_u16m2x3_u16m22611// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 16 x i8>, 3) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2612// CHECK-RV64-NEXT: entry:2613// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.tuple.extract.nxv8i16.triscv.vector.tuple_nxv16i8_3t(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) [[SRC]], i32 0)2614// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]2615//2616vuint16m2_t test_vget_v_u16m2x3_u16m2(vuint16m2x3_t src, size_t index) {2617 return __riscv_vget_v_u16m2x3_u16m2(src, 0);2618}2619 2620// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vget_v_u16m2x4_u16m22621// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 16 x i8>, 4) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2622// CHECK-RV64-NEXT: entry:2623// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.tuple.extract.nxv8i16.triscv.vector.tuple_nxv16i8_4t(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) [[SRC]], i32 0)2624// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]2625//2626vuint16m2_t test_vget_v_u16m2x4_u16m2(vuint16m2x4_t src, size_t index) {2627 return __riscv_vget_v_u16m2x4_u16m2(src, 0);2628}2629 2630// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vget_v_u16m4x2_u16m42631// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 32 x i8>, 2) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2632// CHECK-RV64-NEXT: entry:2633// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.tuple.extract.nxv16i16.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) [[SRC]], i32 0)2634// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]2635//2636vuint16m4_t test_vget_v_u16m4x2_u16m4(vuint16m4x2_t src, size_t index) {2637 return __riscv_vget_v_u16m4x2_u16m4(src, 0);2638}2639 2640// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vget_v_u32mf2x2_u32mf22641// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 2) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2642// CHECK-RV64-NEXT: entry:2643// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_2t(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) [[SRC]], i32 0)2644// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]2645//2646vuint32mf2_t test_vget_v_u32mf2x2_u32mf2(vuint32mf2x2_t src, size_t index) {2647 return __riscv_vget_v_u32mf2x2_u32mf2(src, 0);2648}2649 2650// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vget_v_u32mf2x3_u32mf22651// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2652// CHECK-RV64-NEXT: entry:2653// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_3t(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[SRC]], i32 0)2654// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]2655//2656vuint32mf2_t test_vget_v_u32mf2x3_u32mf2(vuint32mf2x3_t src, size_t index) {2657 return __riscv_vget_v_u32mf2x3_u32mf2(src, 0);2658}2659 2660// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vget_v_u32mf2x4_u32mf22661// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 4) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2662// CHECK-RV64-NEXT: entry:2663// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_4t(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) [[SRC]], i32 0)2664// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]2665//2666vuint32mf2_t test_vget_v_u32mf2x4_u32mf2(vuint32mf2x4_t src, size_t index) {2667 return __riscv_vget_v_u32mf2x4_u32mf2(src, 0);2668}2669 2670// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vget_v_u32mf2x5_u32mf22671// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2672// CHECK-RV64-NEXT: entry:2673// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_5t(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[SRC]], i32 0)2674// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]2675//2676vuint32mf2_t test_vget_v_u32mf2x5_u32mf2(vuint32mf2x5_t src, size_t index) {2677 return __riscv_vget_v_u32mf2x5_u32mf2(src, 0);2678}2679 2680// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vget_v_u32mf2x6_u32mf22681// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2682// CHECK-RV64-NEXT: entry:2683// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_6t(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[SRC]], i32 0)2684// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]2685//2686vuint32mf2_t test_vget_v_u32mf2x6_u32mf2(vuint32mf2x6_t src, size_t index) {2687 return __riscv_vget_v_u32mf2x6_u32mf2(src, 0);2688}2689 2690// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vget_v_u32mf2x7_u32mf22691// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 7) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2692// CHECK-RV64-NEXT: entry:2693// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_7t(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) [[SRC]], i32 0)2694// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]2695//2696vuint32mf2_t test_vget_v_u32mf2x7_u32mf2(vuint32mf2x7_t src, size_t index) {2697 return __riscv_vget_v_u32mf2x7_u32mf2(src, 0);2698}2699 2700// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vget_v_u32mf2x8_u32mf22701// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 4 x i8>, 8) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2702// CHECK-RV64-NEXT: entry:2703// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_8t(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) [[SRC]], i32 0)2704// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]2705//2706vuint32mf2_t test_vget_v_u32mf2x8_u32mf2(vuint32mf2x8_t src, size_t index) {2707 return __riscv_vget_v_u32mf2x8_u32mf2(src, 0);2708}2709 2710// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vget_v_u32m1x2_u32m12711// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 2) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2712// CHECK-RV64-NEXT: entry:2713// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.tuple.extract.nxv2i32.triscv.vector.tuple_nxv8i8_2t(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) [[SRC]], i32 0)2714// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]2715//2716vuint32m1_t test_vget_v_u32m1x2_u32m1(vuint32m1x2_t src, size_t index) {2717 return __riscv_vget_v_u32m1x2_u32m1(src, 0);2718}2719 2720// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vget_v_u32m1x3_u32m12721// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 3) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2722// CHECK-RV64-NEXT: entry:2723// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.tuple.extract.nxv2i32.triscv.vector.tuple_nxv8i8_3t(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) [[SRC]], i32 0)2724// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]2725//2726vuint32m1_t test_vget_v_u32m1x3_u32m1(vuint32m1x3_t src, size_t index) {2727 return __riscv_vget_v_u32m1x3_u32m1(src, 0);2728}2729 2730// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vget_v_u32m1x4_u32m12731// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 4) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2732// CHECK-RV64-NEXT: entry:2733// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.tuple.extract.nxv2i32.triscv.vector.tuple_nxv8i8_4t(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) [[SRC]], i32 0)2734// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]2735//2736vuint32m1_t test_vget_v_u32m1x4_u32m1(vuint32m1x4_t src, size_t index) {2737 return __riscv_vget_v_u32m1x4_u32m1(src, 0);2738}2739 2740// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vget_v_u32m1x5_u32m12741// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 5) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2742// CHECK-RV64-NEXT: entry:2743// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.tuple.extract.nxv2i32.triscv.vector.tuple_nxv8i8_5t(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) [[SRC]], i32 0)2744// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]2745//2746vuint32m1_t test_vget_v_u32m1x5_u32m1(vuint32m1x5_t src, size_t index) {2747 return __riscv_vget_v_u32m1x5_u32m1(src, 0);2748}2749 2750// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vget_v_u32m1x6_u32m12751// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 6) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2752// CHECK-RV64-NEXT: entry:2753// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.tuple.extract.nxv2i32.triscv.vector.tuple_nxv8i8_6t(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) [[SRC]], i32 0)2754// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]2755//2756vuint32m1_t test_vget_v_u32m1x6_u32m1(vuint32m1x6_t src, size_t index) {2757 return __riscv_vget_v_u32m1x6_u32m1(src, 0);2758}2759 2760// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vget_v_u32m1x7_u32m12761// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 7) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2762// CHECK-RV64-NEXT: entry:2763// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.tuple.extract.nxv2i32.triscv.vector.tuple_nxv8i8_7t(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) [[SRC]], i32 0)2764// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]2765//2766vuint32m1_t test_vget_v_u32m1x7_u32m1(vuint32m1x7_t src, size_t index) {2767 return __riscv_vget_v_u32m1x7_u32m1(src, 0);2768}2769 2770// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vget_v_u32m1x8_u32m12771// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 8) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2772// CHECK-RV64-NEXT: entry:2773// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.tuple.extract.nxv2i32.triscv.vector.tuple_nxv8i8_8t(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) [[SRC]], i32 0)2774// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]2775//2776vuint32m1_t test_vget_v_u32m1x8_u32m1(vuint32m1x8_t src, size_t index) {2777 return __riscv_vget_v_u32m1x8_u32m1(src, 0);2778}2779 2780// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vget_v_u32m2x2_u32m22781// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 16 x i8>, 2) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2782// CHECK-RV64-NEXT: entry:2783// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.tuple.extract.nxv4i32.triscv.vector.tuple_nxv16i8_2t(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) [[SRC]], i32 0)2784// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]2785//2786vuint32m2_t test_vget_v_u32m2x2_u32m2(vuint32m2x2_t src, size_t index) {2787 return __riscv_vget_v_u32m2x2_u32m2(src, 0);2788}2789 2790// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vget_v_u32m2x3_u32m22791// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 16 x i8>, 3) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2792// CHECK-RV64-NEXT: entry:2793// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.tuple.extract.nxv4i32.triscv.vector.tuple_nxv16i8_3t(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) [[SRC]], i32 0)2794// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]2795//2796vuint32m2_t test_vget_v_u32m2x3_u32m2(vuint32m2x3_t src, size_t index) {2797 return __riscv_vget_v_u32m2x3_u32m2(src, 0);2798}2799 2800// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vget_v_u32m2x4_u32m22801// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 16 x i8>, 4) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2802// CHECK-RV64-NEXT: entry:2803// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.tuple.extract.nxv4i32.triscv.vector.tuple_nxv16i8_4t(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) [[SRC]], i32 0)2804// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]2805//2806vuint32m2_t test_vget_v_u32m2x4_u32m2(vuint32m2x4_t src, size_t index) {2807 return __riscv_vget_v_u32m2x4_u32m2(src, 0);2808}2809 2810// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vget_v_u32m4x2_u32m42811// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 32 x i8>, 2) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2812// CHECK-RV64-NEXT: entry:2813// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.tuple.extract.nxv8i32.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) [[SRC]], i32 0)2814// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]2815//2816vuint32m4_t test_vget_v_u32m4x2_u32m4(vuint32m4x2_t src, size_t index) {2817 return __riscv_vget_v_u32m4x2_u32m4(src, 0);2818}2819 2820// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vget_v_u64m1x2_u64m12821// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 2) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2822// CHECK-RV64-NEXT: entry:2823// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.tuple.extract.nxv1i64.triscv.vector.tuple_nxv8i8_2t(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) [[SRC]], i32 0)2824// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]2825//2826vuint64m1_t test_vget_v_u64m1x2_u64m1(vuint64m1x2_t src, size_t index) {2827 return __riscv_vget_v_u64m1x2_u64m1(src, 0);2828}2829 2830// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vget_v_u64m1x3_u64m12831// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 3) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2832// CHECK-RV64-NEXT: entry:2833// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.tuple.extract.nxv1i64.triscv.vector.tuple_nxv8i8_3t(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) [[SRC]], i32 0)2834// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]2835//2836vuint64m1_t test_vget_v_u64m1x3_u64m1(vuint64m1x3_t src, size_t index) {2837 return __riscv_vget_v_u64m1x3_u64m1(src, 0);2838}2839 2840// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vget_v_u64m1x4_u64m12841// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 4) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2842// CHECK-RV64-NEXT: entry:2843// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.tuple.extract.nxv1i64.triscv.vector.tuple_nxv8i8_4t(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) [[SRC]], i32 0)2844// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]2845//2846vuint64m1_t test_vget_v_u64m1x4_u64m1(vuint64m1x4_t src, size_t index) {2847 return __riscv_vget_v_u64m1x4_u64m1(src, 0);2848}2849 2850// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vget_v_u64m1x5_u64m12851// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 5) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2852// CHECK-RV64-NEXT: entry:2853// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.tuple.extract.nxv1i64.triscv.vector.tuple_nxv8i8_5t(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) [[SRC]], i32 0)2854// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]2855//2856vuint64m1_t test_vget_v_u64m1x5_u64m1(vuint64m1x5_t src, size_t index) {2857 return __riscv_vget_v_u64m1x5_u64m1(src, 0);2858}2859 2860// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vget_v_u64m1x6_u64m12861// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 6) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2862// CHECK-RV64-NEXT: entry:2863// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.tuple.extract.nxv1i64.triscv.vector.tuple_nxv8i8_6t(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) [[SRC]], i32 0)2864// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]2865//2866vuint64m1_t test_vget_v_u64m1x6_u64m1(vuint64m1x6_t src, size_t index) {2867 return __riscv_vget_v_u64m1x6_u64m1(src, 0);2868}2869 2870// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vget_v_u64m1x7_u64m12871// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 7) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2872// CHECK-RV64-NEXT: entry:2873// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.tuple.extract.nxv1i64.triscv.vector.tuple_nxv8i8_7t(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) [[SRC]], i32 0)2874// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]2875//2876vuint64m1_t test_vget_v_u64m1x7_u64m1(vuint64m1x7_t src, size_t index) {2877 return __riscv_vget_v_u64m1x7_u64m1(src, 0);2878}2879 2880// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vget_v_u64m1x8_u64m12881// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 8 x i8>, 8) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2882// CHECK-RV64-NEXT: entry:2883// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.tuple.extract.nxv1i64.triscv.vector.tuple_nxv8i8_8t(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) [[SRC]], i32 0)2884// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]2885//2886vuint64m1_t test_vget_v_u64m1x8_u64m1(vuint64m1x8_t src, size_t index) {2887 return __riscv_vget_v_u64m1x8_u64m1(src, 0);2888}2889 2890// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vget_v_u64m2x2_u64m22891// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 16 x i8>, 2) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2892// CHECK-RV64-NEXT: entry:2893// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.tuple.extract.nxv2i64.triscv.vector.tuple_nxv16i8_2t(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) [[SRC]], i32 0)2894// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]2895//2896vuint64m2_t test_vget_v_u64m2x2_u64m2(vuint64m2x2_t src, size_t index) {2897 return __riscv_vget_v_u64m2x2_u64m2(src, 0);2898}2899 2900// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vget_v_u64m2x3_u64m22901// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 16 x i8>, 3) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2902// CHECK-RV64-NEXT: entry:2903// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.tuple.extract.nxv2i64.triscv.vector.tuple_nxv16i8_3t(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) [[SRC]], i32 0)2904// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]2905//2906vuint64m2_t test_vget_v_u64m2x3_u64m2(vuint64m2x3_t src, size_t index) {2907 return __riscv_vget_v_u64m2x3_u64m2(src, 0);2908}2909 2910// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vget_v_u64m2x4_u64m22911// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 16 x i8>, 4) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2912// CHECK-RV64-NEXT: entry:2913// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.tuple.extract.nxv2i64.triscv.vector.tuple_nxv16i8_4t(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) [[SRC]], i32 0)2914// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]2915//2916vuint64m2_t test_vget_v_u64m2x4_u64m2(vuint64m2x4_t src, size_t index) {2917 return __riscv_vget_v_u64m2x4_u64m2(src, 0);2918}2919 2920// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vget_v_u64m4x2_u64m42921// CHECK-RV64-SAME: (target("riscv.vector.tuple", <vscale x 32 x i8>, 2) [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] {2922// CHECK-RV64-NEXT: entry:2923// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.tuple.extract.nxv4i64.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) [[SRC]], i32 0)2924// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]2925//2926vuint64m4_t test_vget_v_u64m4x2_u64m4(vuint64m4x2_t src, size_t index) {2927 return __riscv_vget_v_u64m4x2_u64m4(src, 0);2928}2929 2930