400 lines · c
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 22// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \4// RUN: -target-feature +zvfh -disable-O0-optnone \5// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \6// RUN: FileCheck --check-prefix=CHECK-RV64 %s7 8#include <riscv_vector.h>9 10// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vle32ff_v_f32mf211// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {12// CHECK-RV64-NEXT: entry:13// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.nxv1f32.i64.p0(<vscale x 1 x float> poison, ptr [[BASE]], i64 [[VL]])14// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x float>, i64 } [[TMP0]], 015// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x float>, i64 } [[TMP0]], 116// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 817// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]18//19vfloat32mf2_t test_vle32ff_v_f32mf2(const float *base, size_t *new_vl, size_t vl) {20 return __riscv_vle32ff_v_f32mf2(base, new_vl, vl);21}22 23// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vle32ff_v_f32m124// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {25// CHECK-RV64-NEXT: entry:26// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 2 x float>, i64 } @llvm.riscv.vleff.nxv2f32.i64.p0(<vscale x 2 x float> poison, ptr [[BASE]], i64 [[VL]])27// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 2 x float>, i64 } [[TMP0]], 028// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x float>, i64 } [[TMP0]], 129// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 830// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP1]]31//32vfloat32m1_t test_vle32ff_v_f32m1(const float *base, size_t *new_vl, size_t vl) {33 return __riscv_vle32ff_v_f32m1(base, new_vl, vl);34}35 36// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vle32ff_v_f32m237// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {38// CHECK-RV64-NEXT: entry:39// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 4 x float>, i64 } @llvm.riscv.vleff.nxv4f32.i64.p0(<vscale x 4 x float> poison, ptr [[BASE]], i64 [[VL]])40// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 4 x float>, i64 } [[TMP0]], 041// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x float>, i64 } [[TMP0]], 142// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 843// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP1]]44//45vfloat32m2_t test_vle32ff_v_f32m2(const float *base, size_t *new_vl, size_t vl) {46 return __riscv_vle32ff_v_f32m2(base, new_vl, vl);47}48 49// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vle32ff_v_f32m450// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {51// CHECK-RV64-NEXT: entry:52// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 8 x float>, i64 } @llvm.riscv.vleff.nxv8f32.i64.p0(<vscale x 8 x float> poison, ptr [[BASE]], i64 [[VL]])53// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 8 x float>, i64 } [[TMP0]], 054// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x float>, i64 } [[TMP0]], 155// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 856// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP1]]57//58vfloat32m4_t test_vle32ff_v_f32m4(const float *base, size_t *new_vl, size_t vl) {59 return __riscv_vle32ff_v_f32m4(base, new_vl, vl);60}61 62// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vle32ff_v_f32m863// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {64// CHECK-RV64-NEXT: entry:65// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 16 x float>, i64 } @llvm.riscv.vleff.nxv16f32.i64.p0(<vscale x 16 x float> poison, ptr [[BASE]], i64 [[VL]])66// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 16 x float>, i64 } [[TMP0]], 067// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 16 x float>, i64 } [[TMP0]], 168// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 869// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP1]]70//71vfloat32m8_t test_vle32ff_v_f32m8(const float *base, size_t *new_vl, size_t vl) {72 return __riscv_vle32ff_v_f32m8(base, new_vl, vl);73}74 75// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vle32ff_v_i32mf276// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {77// CHECK-RV64-NEXT: entry:78// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.nxv1i32.i64.p0(<vscale x 1 x i32> poison, ptr [[BASE]], i64 [[VL]])79// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, i64 } [[TMP0]], 080// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x i32>, i64 } [[TMP0]], 181// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 882// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]83//84vint32mf2_t test_vle32ff_v_i32mf2(const int32_t *base, size_t *new_vl, size_t vl) {85 return __riscv_vle32ff_v_i32mf2(base, new_vl, vl);86}87 88// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vle32ff_v_i32m189// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {90// CHECK-RV64-NEXT: entry:91// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.nxv2i32.i64.p0(<vscale x 2 x i32> poison, ptr [[BASE]], i64 [[VL]])92// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 2 x i32>, i64 } [[TMP0]], 093// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x i32>, i64 } [[TMP0]], 194// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 895// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]96//97vint32m1_t test_vle32ff_v_i32m1(const int32_t *base, size_t *new_vl, size_t vl) {98 return __riscv_vle32ff_v_i32m1(base, new_vl, vl);99}100 101// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vle32ff_v_i32m2102// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {103// CHECK-RV64-NEXT: entry:104// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 4 x i32>, i64 } @llvm.riscv.vleff.nxv4i32.i64.p0(<vscale x 4 x i32> poison, ptr [[BASE]], i64 [[VL]])105// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 4 x i32>, i64 } [[TMP0]], 0106// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x i32>, i64 } [[TMP0]], 1107// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8108// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]109//110vint32m2_t test_vle32ff_v_i32m2(const int32_t *base, size_t *new_vl, size_t vl) {111 return __riscv_vle32ff_v_i32m2(base, new_vl, vl);112}113 114// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vle32ff_v_i32m4115// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {116// CHECK-RV64-NEXT: entry:117// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 8 x i32>, i64 } @llvm.riscv.vleff.nxv8i32.i64.p0(<vscale x 8 x i32> poison, ptr [[BASE]], i64 [[VL]])118// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 8 x i32>, i64 } [[TMP0]], 0119// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x i32>, i64 } [[TMP0]], 1120// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8121// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]122//123vint32m4_t test_vle32ff_v_i32m4(const int32_t *base, size_t *new_vl, size_t vl) {124 return __riscv_vle32ff_v_i32m4(base, new_vl, vl);125}126 127// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vle32ff_v_i32m8128// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {129// CHECK-RV64-NEXT: entry:130// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 16 x i32>, i64 } @llvm.riscv.vleff.nxv16i32.i64.p0(<vscale x 16 x i32> poison, ptr [[BASE]], i64 [[VL]])131// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 16 x i32>, i64 } [[TMP0]], 0132// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 16 x i32>, i64 } [[TMP0]], 1133// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8134// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]]135//136vint32m8_t test_vle32ff_v_i32m8(const int32_t *base, size_t *new_vl, size_t vl) {137 return __riscv_vle32ff_v_i32m8(base, new_vl, vl);138}139 140// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vle32ff_v_u32mf2141// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {142// CHECK-RV64-NEXT: entry:143// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.nxv1i32.i64.p0(<vscale x 1 x i32> poison, ptr [[BASE]], i64 [[VL]])144// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, i64 } [[TMP0]], 0145// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x i32>, i64 } [[TMP0]], 1146// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8147// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]148//149vuint32mf2_t test_vle32ff_v_u32mf2(const uint32_t *base, size_t *new_vl, size_t vl) {150 return __riscv_vle32ff_v_u32mf2(base, new_vl, vl);151}152 153// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vle32ff_v_u32m1154// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {155// CHECK-RV64-NEXT: entry:156// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.nxv2i32.i64.p0(<vscale x 2 x i32> poison, ptr [[BASE]], i64 [[VL]])157// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 2 x i32>, i64 } [[TMP0]], 0158// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x i32>, i64 } [[TMP0]], 1159// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8160// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]161//162vuint32m1_t test_vle32ff_v_u32m1(const uint32_t *base, size_t *new_vl, size_t vl) {163 return __riscv_vle32ff_v_u32m1(base, new_vl, vl);164}165 166// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vle32ff_v_u32m2167// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {168// CHECK-RV64-NEXT: entry:169// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 4 x i32>, i64 } @llvm.riscv.vleff.nxv4i32.i64.p0(<vscale x 4 x i32> poison, ptr [[BASE]], i64 [[VL]])170// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 4 x i32>, i64 } [[TMP0]], 0171// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x i32>, i64 } [[TMP0]], 1172// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8173// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]174//175vuint32m2_t test_vle32ff_v_u32m2(const uint32_t *base, size_t *new_vl, size_t vl) {176 return __riscv_vle32ff_v_u32m2(base, new_vl, vl);177}178 179// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vle32ff_v_u32m4180// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {181// CHECK-RV64-NEXT: entry:182// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 8 x i32>, i64 } @llvm.riscv.vleff.nxv8i32.i64.p0(<vscale x 8 x i32> poison, ptr [[BASE]], i64 [[VL]])183// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 8 x i32>, i64 } [[TMP0]], 0184// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x i32>, i64 } [[TMP0]], 1185// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8186// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]187//188vuint32m4_t test_vle32ff_v_u32m4(const uint32_t *base, size_t *new_vl, size_t vl) {189 return __riscv_vle32ff_v_u32m4(base, new_vl, vl);190}191 192// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vle32ff_v_u32m8193// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {194// CHECK-RV64-NEXT: entry:195// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 16 x i32>, i64 } @llvm.riscv.vleff.nxv16i32.i64.p0(<vscale x 16 x i32> poison, ptr [[BASE]], i64 [[VL]])196// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 16 x i32>, i64 } [[TMP0]], 0197// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 16 x i32>, i64 } [[TMP0]], 1198// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8199// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]]200//201vuint32m8_t test_vle32ff_v_u32m8(const uint32_t *base, size_t *new_vl, size_t vl) {202 return __riscv_vle32ff_v_u32m8(base, new_vl, vl);203}204 205// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vle32ff_v_f32mf2_m206// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {207// CHECK-RV64-NEXT: entry:208// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.mask.nxv1f32.i64.p0(<vscale x 1 x float> poison, ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)209// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x float>, i64 } [[TMP0]], 0210// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x float>, i64 } [[TMP0]], 1211// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8212// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]213//214vfloat32mf2_t test_vle32ff_v_f32mf2_m(vbool64_t mask, const float *base, size_t *new_vl, size_t vl) {215 return __riscv_vle32ff_v_f32mf2_m(mask, base, new_vl, vl);216}217 218// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vle32ff_v_f32m1_m219// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {220// CHECK-RV64-NEXT: entry:221// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 2 x float>, i64 } @llvm.riscv.vleff.mask.nxv2f32.i64.p0(<vscale x 2 x float> poison, ptr [[BASE]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)222// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 2 x float>, i64 } [[TMP0]], 0223// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x float>, i64 } [[TMP0]], 1224// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8225// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP1]]226//227vfloat32m1_t test_vle32ff_v_f32m1_m(vbool32_t mask, const float *base, size_t *new_vl, size_t vl) {228 return __riscv_vle32ff_v_f32m1_m(mask, base, new_vl, vl);229}230 231// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vle32ff_v_f32m2_m232// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {233// CHECK-RV64-NEXT: entry:234// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 4 x float>, i64 } @llvm.riscv.vleff.mask.nxv4f32.i64.p0(<vscale x 4 x float> poison, ptr [[BASE]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)235// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 4 x float>, i64 } [[TMP0]], 0236// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x float>, i64 } [[TMP0]], 1237// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8238// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP1]]239//240vfloat32m2_t test_vle32ff_v_f32m2_m(vbool16_t mask, const float *base, size_t *new_vl, size_t vl) {241 return __riscv_vle32ff_v_f32m2_m(mask, base, new_vl, vl);242}243 244// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vle32ff_v_f32m4_m245// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {246// CHECK-RV64-NEXT: entry:247// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 8 x float>, i64 } @llvm.riscv.vleff.mask.nxv8f32.i64.p0(<vscale x 8 x float> poison, ptr [[BASE]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)248// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 8 x float>, i64 } [[TMP0]], 0249// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x float>, i64 } [[TMP0]], 1250// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8251// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP1]]252//253vfloat32m4_t test_vle32ff_v_f32m4_m(vbool8_t mask, const float *base, size_t *new_vl, size_t vl) {254 return __riscv_vle32ff_v_f32m4_m(mask, base, new_vl, vl);255}256 257// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vle32ff_v_f32m8_m258// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {259// CHECK-RV64-NEXT: entry:260// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 16 x float>, i64 } @llvm.riscv.vleff.mask.nxv16f32.i64.p0(<vscale x 16 x float> poison, ptr [[BASE]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3)261// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 16 x float>, i64 } [[TMP0]], 0262// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 16 x float>, i64 } [[TMP0]], 1263// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8264// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP1]]265//266vfloat32m8_t test_vle32ff_v_f32m8_m(vbool4_t mask, const float *base, size_t *new_vl, size_t vl) {267 return __riscv_vle32ff_v_f32m8_m(mask, base, new_vl, vl);268}269 270// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vle32ff_v_i32mf2_m271// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {272// CHECK-RV64-NEXT: entry:273// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.mask.nxv1i32.i64.p0(<vscale x 1 x i32> poison, ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)274// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, i64 } [[TMP0]], 0275// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x i32>, i64 } [[TMP0]], 1276// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8277// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]278//279vint32mf2_t test_vle32ff_v_i32mf2_m(vbool64_t mask, const int32_t *base, size_t *new_vl, size_t vl) {280 return __riscv_vle32ff_v_i32mf2_m(mask, base, new_vl, vl);281}282 283// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vle32ff_v_i32m1_m284// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {285// CHECK-RV64-NEXT: entry:286// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.mask.nxv2i32.i64.p0(<vscale x 2 x i32> poison, ptr [[BASE]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)287// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 2 x i32>, i64 } [[TMP0]], 0288// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x i32>, i64 } [[TMP0]], 1289// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8290// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]291//292vint32m1_t test_vle32ff_v_i32m1_m(vbool32_t mask, const int32_t *base, size_t *new_vl, size_t vl) {293 return __riscv_vle32ff_v_i32m1_m(mask, base, new_vl, vl);294}295 296// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vle32ff_v_i32m2_m297// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {298// CHECK-RV64-NEXT: entry:299// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 4 x i32>, i64 } @llvm.riscv.vleff.mask.nxv4i32.i64.p0(<vscale x 4 x i32> poison, ptr [[BASE]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)300// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 4 x i32>, i64 } [[TMP0]], 0301// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x i32>, i64 } [[TMP0]], 1302// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8303// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]304//305vint32m2_t test_vle32ff_v_i32m2_m(vbool16_t mask, const int32_t *base, size_t *new_vl, size_t vl) {306 return __riscv_vle32ff_v_i32m2_m(mask, base, new_vl, vl);307}308 309// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vle32ff_v_i32m4_m310// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {311// CHECK-RV64-NEXT: entry:312// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 8 x i32>, i64 } @llvm.riscv.vleff.mask.nxv8i32.i64.p0(<vscale x 8 x i32> poison, ptr [[BASE]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)313// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 8 x i32>, i64 } [[TMP0]], 0314// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x i32>, i64 } [[TMP0]], 1315// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8316// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]317//318vint32m4_t test_vle32ff_v_i32m4_m(vbool8_t mask, const int32_t *base, size_t *new_vl, size_t vl) {319 return __riscv_vle32ff_v_i32m4_m(mask, base, new_vl, vl);320}321 322// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vle32ff_v_i32m8_m323// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {324// CHECK-RV64-NEXT: entry:325// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 16 x i32>, i64 } @llvm.riscv.vleff.mask.nxv16i32.i64.p0(<vscale x 16 x i32> poison, ptr [[BASE]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3)326// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 16 x i32>, i64 } [[TMP0]], 0327// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 16 x i32>, i64 } [[TMP0]], 1328// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8329// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]]330//331vint32m8_t test_vle32ff_v_i32m8_m(vbool4_t mask, const int32_t *base, size_t *new_vl, size_t vl) {332 return __riscv_vle32ff_v_i32m8_m(mask, base, new_vl, vl);333}334 335// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vle32ff_v_u32mf2_m336// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {337// CHECK-RV64-NEXT: entry:338// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.mask.nxv1i32.i64.p0(<vscale x 1 x i32> poison, ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)339// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, i64 } [[TMP0]], 0340// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x i32>, i64 } [[TMP0]], 1341// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8342// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]343//344vuint32mf2_t test_vle32ff_v_u32mf2_m(vbool64_t mask, const uint32_t *base, size_t *new_vl, size_t vl) {345 return __riscv_vle32ff_v_u32mf2_m(mask, base, new_vl, vl);346}347 348// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vle32ff_v_u32m1_m349// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {350// CHECK-RV64-NEXT: entry:351// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.mask.nxv2i32.i64.p0(<vscale x 2 x i32> poison, ptr [[BASE]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)352// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 2 x i32>, i64 } [[TMP0]], 0353// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x i32>, i64 } [[TMP0]], 1354// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8355// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]356//357vuint32m1_t test_vle32ff_v_u32m1_m(vbool32_t mask, const uint32_t *base, size_t *new_vl, size_t vl) {358 return __riscv_vle32ff_v_u32m1_m(mask, base, new_vl, vl);359}360 361// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vle32ff_v_u32m2_m362// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {363// CHECK-RV64-NEXT: entry:364// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 4 x i32>, i64 } @llvm.riscv.vleff.mask.nxv4i32.i64.p0(<vscale x 4 x i32> poison, ptr [[BASE]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)365// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 4 x i32>, i64 } [[TMP0]], 0366// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x i32>, i64 } [[TMP0]], 1367// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8368// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]369//370vuint32m2_t test_vle32ff_v_u32m2_m(vbool16_t mask, const uint32_t *base, size_t *new_vl, size_t vl) {371 return __riscv_vle32ff_v_u32m2_m(mask, base, new_vl, vl);372}373 374// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vle32ff_v_u32m4_m375// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {376// CHECK-RV64-NEXT: entry:377// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 8 x i32>, i64 } @llvm.riscv.vleff.mask.nxv8i32.i64.p0(<vscale x 8 x i32> poison, ptr [[BASE]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)378// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 8 x i32>, i64 } [[TMP0]], 0379// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x i32>, i64 } [[TMP0]], 1380// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8381// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]382//383vuint32m4_t test_vle32ff_v_u32m4_m(vbool8_t mask, const uint32_t *base, size_t *new_vl, size_t vl) {384 return __riscv_vle32ff_v_u32m4_m(mask, base, new_vl, vl);385}386 387// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vle32ff_v_u32m8_m388// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {389// CHECK-RV64-NEXT: entry:390// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 16 x i32>, i64 } @llvm.riscv.vleff.mask.nxv16i32.i64.p0(<vscale x 16 x i32> poison, ptr [[BASE]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3)391// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 16 x i32>, i64 } [[TMP0]], 0392// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 16 x i32>, i64 } [[TMP0]], 1393// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8394// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]]395//396vuint32m8_t test_vle32ff_v_u32m8_m(vbool4_t mask, const uint32_t *base, size_t *new_vl, size_t vl) {397 return __riscv_vle32ff_v_u32m8_m(mask, base, new_vl, vl);398}399 400