190 lines · c
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 22// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \4// RUN: -target-feature +zvfh -disable-O0-optnone \5// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \6// RUN: FileCheck --check-prefix=CHECK-RV64 %s7 8#include <riscv_vector.h>9 10// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_f32mf2x311// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {12// CHECK-RV64-NEXT: entry:13// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr [[BASE]], i64 [[BSTRIDE]], i64 [[VL]], i64 5)14// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[TMP0]]15//16vfloat32mf2x3_t test_vlsseg3e32_v_f32mf2x3(const float *base, ptrdiff_t bstride, size_t vl) {17 return __riscv_vlsseg3e32_v_f32mf2x3(base, bstride, vl);18}19 20// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_f32m1x321// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {22// CHECK-RV64-NEXT: entry:23// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr [[BASE]], i64 [[BSTRIDE]], i64 [[VL]], i64 5)24// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) [[TMP0]]25//26vfloat32m1x3_t test_vlsseg3e32_v_f32m1x3(const float *base, ptrdiff_t bstride, size_t vl) {27 return __riscv_vlsseg3e32_v_f32m1x3(base, bstride, vl);28}29 30// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_f32m2x331// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {32// CHECK-RV64-NEXT: entry:33// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr [[BASE]], i64 [[BSTRIDE]], i64 [[VL]], i64 5)34// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) [[TMP0]]35//36vfloat32m2x3_t test_vlsseg3e32_v_f32m2x3(const float *base, ptrdiff_t bstride, size_t vl) {37 return __riscv_vlsseg3e32_v_f32m2x3(base, bstride, vl);38}39 40// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_i32mf2x341// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {42// CHECK-RV64-NEXT: entry:43// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr [[BASE]], i64 [[BSTRIDE]], i64 [[VL]], i64 5)44// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[TMP0]]45//46vint32mf2x3_t test_vlsseg3e32_v_i32mf2x3(const int32_t *base, ptrdiff_t bstride, size_t vl) {47 return __riscv_vlsseg3e32_v_i32mf2x3(base, bstride, vl);48}49 50// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_i32m1x351// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {52// CHECK-RV64-NEXT: entry:53// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr [[BASE]], i64 [[BSTRIDE]], i64 [[VL]], i64 5)54// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) [[TMP0]]55//56vint32m1x3_t test_vlsseg3e32_v_i32m1x3(const int32_t *base, ptrdiff_t bstride, size_t vl) {57 return __riscv_vlsseg3e32_v_i32m1x3(base, bstride, vl);58}59 60// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_i32m2x361// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {62// CHECK-RV64-NEXT: entry:63// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr [[BASE]], i64 [[BSTRIDE]], i64 [[VL]], i64 5)64// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) [[TMP0]]65//66vint32m2x3_t test_vlsseg3e32_v_i32m2x3(const int32_t *base, ptrdiff_t bstride, size_t vl) {67 return __riscv_vlsseg3e32_v_i32m2x3(base, bstride, vl);68}69 70// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_u32mf2x371// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {72// CHECK-RV64-NEXT: entry:73// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr [[BASE]], i64 [[BSTRIDE]], i64 [[VL]], i64 5)74// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[TMP0]]75//76vuint32mf2x3_t test_vlsseg3e32_v_u32mf2x3(const uint32_t *base, ptrdiff_t bstride, size_t vl) {77 return __riscv_vlsseg3e32_v_u32mf2x3(base, bstride, vl);78}79 80// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_u32m1x381// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {82// CHECK-RV64-NEXT: entry:83// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr [[BASE]], i64 [[BSTRIDE]], i64 [[VL]], i64 5)84// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) [[TMP0]]85//86vuint32m1x3_t test_vlsseg3e32_v_u32m1x3(const uint32_t *base, ptrdiff_t bstride, size_t vl) {87 return __riscv_vlsseg3e32_v_u32m1x3(base, bstride, vl);88}89 90// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_u32m2x391// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {92// CHECK-RV64-NEXT: entry:93// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr [[BASE]], i64 [[BSTRIDE]], i64 [[VL]], i64 5)94// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) [[TMP0]]95//96vuint32m2x3_t test_vlsseg3e32_v_u32m2x3(const uint32_t *base, ptrdiff_t bstride, size_t vl) {97 return __riscv_vlsseg3e32_v_u32m2x3(base, bstride, vl);98}99 100// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_f32mf2x3_m101// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {102// CHECK-RV64-NEXT: entry:103// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr [[BASE]], i64 [[BSTRIDE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3, i64 5)104// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[TMP0]]105//106vfloat32mf2x3_t test_vlsseg3e32_v_f32mf2x3_m(vbool64_t mask, const float *base, ptrdiff_t bstride, size_t vl) {107 return __riscv_vlsseg3e32_v_f32mf2x3_m(mask, base, bstride, vl);108}109 110// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_f32m1x3_m111// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {112// CHECK-RV64-NEXT: entry:113// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr [[BASE]], i64 [[BSTRIDE]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3, i64 5)114// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) [[TMP0]]115//116vfloat32m1x3_t test_vlsseg3e32_v_f32m1x3_m(vbool32_t mask, const float *base, ptrdiff_t bstride, size_t vl) {117 return __riscv_vlsseg3e32_v_f32m1x3_m(mask, base, bstride, vl);118}119 120// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_f32m2x3_m121// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {122// CHECK-RV64-NEXT: entry:123// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr [[BASE]], i64 [[BSTRIDE]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3, i64 5)124// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) [[TMP0]]125//126vfloat32m2x3_t test_vlsseg3e32_v_f32m2x3_m(vbool16_t mask, const float *base, ptrdiff_t bstride, size_t vl) {127 return __riscv_vlsseg3e32_v_f32m2x3_m(mask, base, bstride, vl);128}129 130// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_i32mf2x3_m131// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {132// CHECK-RV64-NEXT: entry:133// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr [[BASE]], i64 [[BSTRIDE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3, i64 5)134// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[TMP0]]135//136vint32mf2x3_t test_vlsseg3e32_v_i32mf2x3_m(vbool64_t mask, const int32_t *base, ptrdiff_t bstride, size_t vl) {137 return __riscv_vlsseg3e32_v_i32mf2x3_m(mask, base, bstride, vl);138}139 140// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_i32m1x3_m141// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {142// CHECK-RV64-NEXT: entry:143// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr [[BASE]], i64 [[BSTRIDE]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3, i64 5)144// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) [[TMP0]]145//146vint32m1x3_t test_vlsseg3e32_v_i32m1x3_m(vbool32_t mask, const int32_t *base, ptrdiff_t bstride, size_t vl) {147 return __riscv_vlsseg3e32_v_i32m1x3_m(mask, base, bstride, vl);148}149 150// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_i32m2x3_m151// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {152// CHECK-RV64-NEXT: entry:153// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr [[BASE]], i64 [[BSTRIDE]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3, i64 5)154// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) [[TMP0]]155//156vint32m2x3_t test_vlsseg3e32_v_i32m2x3_m(vbool16_t mask, const int32_t *base, ptrdiff_t bstride, size_t vl) {157 return __riscv_vlsseg3e32_v_i32m2x3_m(mask, base, bstride, vl);158}159 160// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_u32mf2x3_m161// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {162// CHECK-RV64-NEXT: entry:163// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr [[BASE]], i64 [[BSTRIDE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3, i64 5)164// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[TMP0]]165//166vuint32mf2x3_t test_vlsseg3e32_v_u32mf2x3_m(vbool64_t mask, const uint32_t *base, ptrdiff_t bstride, size_t vl) {167 return __riscv_vlsseg3e32_v_u32mf2x3_m(mask, base, bstride, vl);168}169 170// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_u32m1x3_m171// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {172// CHECK-RV64-NEXT: entry:173// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr [[BASE]], i64 [[BSTRIDE]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3, i64 5)174// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) [[TMP0]]175//176vuint32m1x3_t test_vlsseg3e32_v_u32m1x3_m(vbool32_t mask, const uint32_t *base, ptrdiff_t bstride, size_t vl) {177 return __riscv_vlsseg3e32_v_u32m1x3_m(mask, base, bstride, vl);178}179 180// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_u32m2x3_m181// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {182// CHECK-RV64-NEXT: entry:183// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr [[BASE]], i64 [[BSTRIDE]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3, i64 5)184// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) [[TMP0]]185//186vuint32m2x3_t test_vlsseg3e32_v_u32m2x3_m(vbool16_t mask, const uint32_t *base, ptrdiff_t bstride, size_t vl) {187 return __riscv_vlsseg3e32_v_u32m2x3_m(mask, base, bstride, vl);188}189 190