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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 22// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone \4// RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \5// RUN:   FileCheck --check-prefix=CHECK-RV64 %s6 7#include <riscv_vector.h>8 9// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmadc_vvm_i8mf8_b6410// CHECK-RV64-SAME: (<vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {11// CHECK-RV64-NEXT:  entry:12// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1]], <vscale x 1 x i8> [[OP2]], <vscale x 1 x i1> [[CARRYIN]], i64 [[VL]])13// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]14//15vbool64_t test_vmadc_vvm_i8mf8_b64(vint8mf8_t op1, vint8mf8_t op2, vbool64_t carryin, size_t vl) {16  return __riscv_vmadc_vvm_i8mf8_b64(op1, op2, carryin, vl);17}18 19// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmadc_vxm_i8mf8_b6420// CHECK-RV64-SAME: (<vscale x 1 x i8> [[OP1:%.*]], i8 noundef signext [[OP2:%.*]], <vscale x 1 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {21// CHECK-RV64-NEXT:  entry:22// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.i8.i64(<vscale x 1 x i8> [[OP1]], i8 [[OP2]], <vscale x 1 x i1> [[CARRYIN]], i64 [[VL]])23// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]24//25vbool64_t test_vmadc_vxm_i8mf8_b64(vint8mf8_t op1, int8_t op2, vbool64_t carryin, size_t vl) {26  return __riscv_vmadc_vxm_i8mf8_b64(op1, op2, carryin, vl);27}28 29// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmadc_vv_i8mf8_b6430// CHECK-RV64-SAME: (<vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {31// CHECK-RV64-NEXT:  entry:32// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1]], <vscale x 1 x i8> [[OP2]], i64 [[VL]])33// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]34//35vbool64_t test_vmadc_vv_i8mf8_b64(vint8mf8_t op1, vint8mf8_t op2, size_t vl) {36  return __riscv_vmadc_vv_i8mf8_b64(op1, op2, vl);37}38 39// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmadc_vx_i8mf8_b6440// CHECK-RV64-SAME: (<vscale x 1 x i8> [[OP1:%.*]], i8 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {41// CHECK-RV64-NEXT:  entry:42// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i8.i8.i64(<vscale x 1 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])43// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]44//45vbool64_t test_vmadc_vx_i8mf8_b64(vint8mf8_t op1, int8_t op2, size_t vl) {46  return __riscv_vmadc_vx_i8mf8_b64(op1, op2, vl);47}48 49// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmadc_vvm_i8mf4_b3250// CHECK-RV64-SAME: (<vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {51// CHECK-RV64-NEXT:  entry:52// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[OP1]], <vscale x 2 x i8> [[OP2]], <vscale x 2 x i1> [[CARRYIN]], i64 [[VL]])53// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]54//55vbool32_t test_vmadc_vvm_i8mf4_b32(vint8mf4_t op1, vint8mf4_t op2, vbool32_t carryin, size_t vl) {56  return __riscv_vmadc_vvm_i8mf4_b32(op1, op2, carryin, vl);57}58 59// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmadc_vxm_i8mf4_b3260// CHECK-RV64-SAME: (<vscale x 2 x i8> [[OP1:%.*]], i8 noundef signext [[OP2:%.*]], <vscale x 2 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {61// CHECK-RV64-NEXT:  entry:62// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i8.i8.i64(<vscale x 2 x i8> [[OP1]], i8 [[OP2]], <vscale x 2 x i1> [[CARRYIN]], i64 [[VL]])63// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]64//65vbool32_t test_vmadc_vxm_i8mf4_b32(vint8mf4_t op1, int8_t op2, vbool32_t carryin, size_t vl) {66  return __riscv_vmadc_vxm_i8mf4_b32(op1, op2, carryin, vl);67}68 69// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmadc_vv_i8mf4_b3270// CHECK-RV64-SAME: (<vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {71// CHECK-RV64-NEXT:  entry:72// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[OP1]], <vscale x 2 x i8> [[OP2]], i64 [[VL]])73// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]74//75vbool32_t test_vmadc_vv_i8mf4_b32(vint8mf4_t op1, vint8mf4_t op2, size_t vl) {76  return __riscv_vmadc_vv_i8mf4_b32(op1, op2, vl);77}78 79// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmadc_vx_i8mf4_b3280// CHECK-RV64-SAME: (<vscale x 2 x i8> [[OP1:%.*]], i8 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {81// CHECK-RV64-NEXT:  entry:82// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i8.i8.i64(<vscale x 2 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])83// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]84//85vbool32_t test_vmadc_vx_i8mf4_b32(vint8mf4_t op1, int8_t op2, size_t vl) {86  return __riscv_vmadc_vx_i8mf4_b32(op1, op2, vl);87}88 89// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmadc_vvm_i8mf2_b1690// CHECK-RV64-SAME: (<vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {91// CHECK-RV64-NEXT:  entry:92// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[OP1]], <vscale x 4 x i8> [[OP2]], <vscale x 4 x i1> [[CARRYIN]], i64 [[VL]])93// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]94//95vbool16_t test_vmadc_vvm_i8mf2_b16(vint8mf2_t op1, vint8mf2_t op2, vbool16_t carryin, size_t vl) {96  return __riscv_vmadc_vvm_i8mf2_b16(op1, op2, carryin, vl);97}98 99// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmadc_vxm_i8mf2_b16100// CHECK-RV64-SAME: (<vscale x 4 x i8> [[OP1:%.*]], i8 noundef signext [[OP2:%.*]], <vscale x 4 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {101// CHECK-RV64-NEXT:  entry:102// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i8.i8.i64(<vscale x 4 x i8> [[OP1]], i8 [[OP2]], <vscale x 4 x i1> [[CARRYIN]], i64 [[VL]])103// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]104//105vbool16_t test_vmadc_vxm_i8mf2_b16(vint8mf2_t op1, int8_t op2, vbool16_t carryin, size_t vl) {106  return __riscv_vmadc_vxm_i8mf2_b16(op1, op2, carryin, vl);107}108 109// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmadc_vv_i8mf2_b16110// CHECK-RV64-SAME: (<vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {111// CHECK-RV64-NEXT:  entry:112// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmadc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[OP1]], <vscale x 4 x i8> [[OP2]], i64 [[VL]])113// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]114//115vbool16_t test_vmadc_vv_i8mf2_b16(vint8mf2_t op1, vint8mf2_t op2, size_t vl) {116  return __riscv_vmadc_vv_i8mf2_b16(op1, op2, vl);117}118 119// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmadc_vx_i8mf2_b16120// CHECK-RV64-SAME: (<vscale x 4 x i8> [[OP1:%.*]], i8 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {121// CHECK-RV64-NEXT:  entry:122// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmadc.nxv4i8.i8.i64(<vscale x 4 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])123// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]124//125vbool16_t test_vmadc_vx_i8mf2_b16(vint8mf2_t op1, int8_t op2, size_t vl) {126  return __riscv_vmadc_vx_i8mf2_b16(op1, op2, vl);127}128 129// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmadc_vvm_i8m1_b8130// CHECK-RV64-SAME: (<vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {131// CHECK-RV64-NEXT:  entry:132// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmadc.carry.in.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[OP1]], <vscale x 8 x i8> [[OP2]], <vscale x 8 x i1> [[CARRYIN]], i64 [[VL]])133// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]134//135vbool8_t test_vmadc_vvm_i8m1_b8(vint8m1_t op1, vint8m1_t op2, vbool8_t carryin, size_t vl) {136  return __riscv_vmadc_vvm_i8m1_b8(op1, op2, carryin, vl);137}138 139// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmadc_vxm_i8m1_b8140// CHECK-RV64-SAME: (<vscale x 8 x i8> [[OP1:%.*]], i8 noundef signext [[OP2:%.*]], <vscale x 8 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {141// CHECK-RV64-NEXT:  entry:142// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmadc.carry.in.nxv8i8.i8.i64(<vscale x 8 x i8> [[OP1]], i8 [[OP2]], <vscale x 8 x i1> [[CARRYIN]], i64 [[VL]])143// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]144//145vbool8_t test_vmadc_vxm_i8m1_b8(vint8m1_t op1, int8_t op2, vbool8_t carryin, size_t vl) {146  return __riscv_vmadc_vxm_i8m1_b8(op1, op2, carryin, vl);147}148 149// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmadc_vv_i8m1_b8150// CHECK-RV64-SAME: (<vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {151// CHECK-RV64-NEXT:  entry:152// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmadc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[OP1]], <vscale x 8 x i8> [[OP2]], i64 [[VL]])153// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]154//155vbool8_t test_vmadc_vv_i8m1_b8(vint8m1_t op1, vint8m1_t op2, size_t vl) {156  return __riscv_vmadc_vv_i8m1_b8(op1, op2, vl);157}158 159// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmadc_vx_i8m1_b8160// CHECK-RV64-SAME: (<vscale x 8 x i8> [[OP1:%.*]], i8 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {161// CHECK-RV64-NEXT:  entry:162// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmadc.nxv8i8.i8.i64(<vscale x 8 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])163// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]164//165vbool8_t test_vmadc_vx_i8m1_b8(vint8m1_t op1, int8_t op2, size_t vl) {166  return __riscv_vmadc_vx_i8m1_b8(op1, op2, vl);167}168 169// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmadc_vvm_i8m2_b4170// CHECK-RV64-SAME: (<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {171// CHECK-RV64-NEXT:  entry:172// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmadc.carry.in.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[OP1]], <vscale x 16 x i8> [[OP2]], <vscale x 16 x i1> [[CARRYIN]], i64 [[VL]])173// CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP0]]174//175vbool4_t test_vmadc_vvm_i8m2_b4(vint8m2_t op1, vint8m2_t op2, vbool4_t carryin, size_t vl) {176  return __riscv_vmadc_vvm_i8m2_b4(op1, op2, carryin, vl);177}178 179// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmadc_vxm_i8m2_b4180// CHECK-RV64-SAME: (<vscale x 16 x i8> [[OP1:%.*]], i8 noundef signext [[OP2:%.*]], <vscale x 16 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {181// CHECK-RV64-NEXT:  entry:182// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmadc.carry.in.nxv16i8.i8.i64(<vscale x 16 x i8> [[OP1]], i8 [[OP2]], <vscale x 16 x i1> [[CARRYIN]], i64 [[VL]])183// CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP0]]184//185vbool4_t test_vmadc_vxm_i8m2_b4(vint8m2_t op1, int8_t op2, vbool4_t carryin, size_t vl) {186  return __riscv_vmadc_vxm_i8m2_b4(op1, op2, carryin, vl);187}188 189// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmadc_vv_i8m2_b4190// CHECK-RV64-SAME: (<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {191// CHECK-RV64-NEXT:  entry:192// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmadc.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[OP1]], <vscale x 16 x i8> [[OP2]], i64 [[VL]])193// CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP0]]194//195vbool4_t test_vmadc_vv_i8m2_b4(vint8m2_t op1, vint8m2_t op2, size_t vl) {196  return __riscv_vmadc_vv_i8m2_b4(op1, op2, vl);197}198 199// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmadc_vx_i8m2_b4200// CHECK-RV64-SAME: (<vscale x 16 x i8> [[OP1:%.*]], i8 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {201// CHECK-RV64-NEXT:  entry:202// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmadc.nxv16i8.i8.i64(<vscale x 16 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])203// CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP0]]204//205vbool4_t test_vmadc_vx_i8m2_b4(vint8m2_t op1, int8_t op2, size_t vl) {206  return __riscv_vmadc_vx_i8m2_b4(op1, op2, vl);207}208 209// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vmadc_vvm_i8m4_b2210// CHECK-RV64-SAME: (<vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {211// CHECK-RV64-NEXT:  entry:212// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmadc.carry.in.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[OP1]], <vscale x 32 x i8> [[OP2]], <vscale x 32 x i1> [[CARRYIN]], i64 [[VL]])213// CHECK-RV64-NEXT:    ret <vscale x 32 x i1> [[TMP0]]214//215vbool2_t test_vmadc_vvm_i8m4_b2(vint8m4_t op1, vint8m4_t op2, vbool2_t carryin, size_t vl) {216  return __riscv_vmadc_vvm_i8m4_b2(op1, op2, carryin, vl);217}218 219// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vmadc_vxm_i8m4_b2220// CHECK-RV64-SAME: (<vscale x 32 x i8> [[OP1:%.*]], i8 noundef signext [[OP2:%.*]], <vscale x 32 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {221// CHECK-RV64-NEXT:  entry:222// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmadc.carry.in.nxv32i8.i8.i64(<vscale x 32 x i8> [[OP1]], i8 [[OP2]], <vscale x 32 x i1> [[CARRYIN]], i64 [[VL]])223// CHECK-RV64-NEXT:    ret <vscale x 32 x i1> [[TMP0]]224//225vbool2_t test_vmadc_vxm_i8m4_b2(vint8m4_t op1, int8_t op2, vbool2_t carryin, size_t vl) {226  return __riscv_vmadc_vxm_i8m4_b2(op1, op2, carryin, vl);227}228 229// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vmadc_vv_i8m4_b2230// CHECK-RV64-SAME: (<vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {231// CHECK-RV64-NEXT:  entry:232// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmadc.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[OP1]], <vscale x 32 x i8> [[OP2]], i64 [[VL]])233// CHECK-RV64-NEXT:    ret <vscale x 32 x i1> [[TMP0]]234//235vbool2_t test_vmadc_vv_i8m4_b2(vint8m4_t op1, vint8m4_t op2, size_t vl) {236  return __riscv_vmadc_vv_i8m4_b2(op1, op2, vl);237}238 239// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vmadc_vx_i8m4_b2240// CHECK-RV64-SAME: (<vscale x 32 x i8> [[OP1:%.*]], i8 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {241// CHECK-RV64-NEXT:  entry:242// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmadc.nxv32i8.i8.i64(<vscale x 32 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])243// CHECK-RV64-NEXT:    ret <vscale x 32 x i1> [[TMP0]]244//245vbool2_t test_vmadc_vx_i8m4_b2(vint8m4_t op1, int8_t op2, size_t vl) {246  return __riscv_vmadc_vx_i8m4_b2(op1, op2, vl);247}248 249// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i1> @test_vmadc_vvm_i8m8_b1250// CHECK-RV64-SAME: (<vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {251// CHECK-RV64-NEXT:  entry:252// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmadc.carry.in.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[OP1]], <vscale x 64 x i8> [[OP2]], <vscale x 64 x i1> [[CARRYIN]], i64 [[VL]])253// CHECK-RV64-NEXT:    ret <vscale x 64 x i1> [[TMP0]]254//255vbool1_t test_vmadc_vvm_i8m8_b1(vint8m8_t op1, vint8m8_t op2, vbool1_t carryin, size_t vl) {256  return __riscv_vmadc_vvm_i8m8_b1(op1, op2, carryin, vl);257}258 259// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i1> @test_vmadc_vxm_i8m8_b1260// CHECK-RV64-SAME: (<vscale x 64 x i8> [[OP1:%.*]], i8 noundef signext [[OP2:%.*]], <vscale x 64 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {261// CHECK-RV64-NEXT:  entry:262// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmadc.carry.in.nxv64i8.i8.i64(<vscale x 64 x i8> [[OP1]], i8 [[OP2]], <vscale x 64 x i1> [[CARRYIN]], i64 [[VL]])263// CHECK-RV64-NEXT:    ret <vscale x 64 x i1> [[TMP0]]264//265vbool1_t test_vmadc_vxm_i8m8_b1(vint8m8_t op1, int8_t op2, vbool1_t carryin, size_t vl) {266  return __riscv_vmadc_vxm_i8m8_b1(op1, op2, carryin, vl);267}268 269// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i1> @test_vmadc_vv_i8m8_b1270// CHECK-RV64-SAME: (<vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {271// CHECK-RV64-NEXT:  entry:272// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmadc.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[OP1]], <vscale x 64 x i8> [[OP2]], i64 [[VL]])273// CHECK-RV64-NEXT:    ret <vscale x 64 x i1> [[TMP0]]274//275vbool1_t test_vmadc_vv_i8m8_b1(vint8m8_t op1, vint8m8_t op2, size_t vl) {276  return __riscv_vmadc_vv_i8m8_b1(op1, op2, vl);277}278 279// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i1> @test_vmadc_vx_i8m8_b1280// CHECK-RV64-SAME: (<vscale x 64 x i8> [[OP1:%.*]], i8 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {281// CHECK-RV64-NEXT:  entry:282// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmadc.nxv64i8.i8.i64(<vscale x 64 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])283// CHECK-RV64-NEXT:    ret <vscale x 64 x i1> [[TMP0]]284//285vbool1_t test_vmadc_vx_i8m8_b1(vint8m8_t op1, int8_t op2, size_t vl) {286  return __riscv_vmadc_vx_i8m8_b1(op1, op2, vl);287}288 289// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmadc_vvm_i16mf4_b64290// CHECK-RV64-SAME: (<vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {291// CHECK-RV64-NEXT:  entry:292// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[OP1]], <vscale x 1 x i16> [[OP2]], <vscale x 1 x i1> [[CARRYIN]], i64 [[VL]])293// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]294//295vbool64_t test_vmadc_vvm_i16mf4_b64(vint16mf4_t op1, vint16mf4_t op2, vbool64_t carryin, size_t vl) {296  return __riscv_vmadc_vvm_i16mf4_b64(op1, op2, carryin, vl);297}298 299// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmadc_vxm_i16mf4_b64300// CHECK-RV64-SAME: (<vscale x 1 x i16> [[OP1:%.*]], i16 noundef signext [[OP2:%.*]], <vscale x 1 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {301// CHECK-RV64-NEXT:  entry:302// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i16.i16.i64(<vscale x 1 x i16> [[OP1]], i16 [[OP2]], <vscale x 1 x i1> [[CARRYIN]], i64 [[VL]])303// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]304//305vbool64_t test_vmadc_vxm_i16mf4_b64(vint16mf4_t op1, int16_t op2, vbool64_t carryin, size_t vl) {306  return __riscv_vmadc_vxm_i16mf4_b64(op1, op2, carryin, vl);307}308 309// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmadc_vv_i16mf4_b64310// CHECK-RV64-SAME: (<vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {311// CHECK-RV64-NEXT:  entry:312// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[OP1]], <vscale x 1 x i16> [[OP2]], i64 [[VL]])313// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]314//315vbool64_t test_vmadc_vv_i16mf4_b64(vint16mf4_t op1, vint16mf4_t op2, size_t vl) {316  return __riscv_vmadc_vv_i16mf4_b64(op1, op2, vl);317}318 319// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmadc_vx_i16mf4_b64320// CHECK-RV64-SAME: (<vscale x 1 x i16> [[OP1:%.*]], i16 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {321// CHECK-RV64-NEXT:  entry:322// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i16.i16.i64(<vscale x 1 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])323// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]324//325vbool64_t test_vmadc_vx_i16mf4_b64(vint16mf4_t op1, int16_t op2, size_t vl) {326  return __riscv_vmadc_vx_i16mf4_b64(op1, op2, vl);327}328 329// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmadc_vvm_i16mf2_b32330// CHECK-RV64-SAME: (<vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {331// CHECK-RV64-NEXT:  entry:332// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[OP1]], <vscale x 2 x i16> [[OP2]], <vscale x 2 x i1> [[CARRYIN]], i64 [[VL]])333// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]334//335vbool32_t test_vmadc_vvm_i16mf2_b32(vint16mf2_t op1, vint16mf2_t op2, vbool32_t carryin, size_t vl) {336  return __riscv_vmadc_vvm_i16mf2_b32(op1, op2, carryin, vl);337}338 339// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmadc_vxm_i16mf2_b32340// CHECK-RV64-SAME: (<vscale x 2 x i16> [[OP1:%.*]], i16 noundef signext [[OP2:%.*]], <vscale x 2 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {341// CHECK-RV64-NEXT:  entry:342// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i16.i16.i64(<vscale x 2 x i16> [[OP1]], i16 [[OP2]], <vscale x 2 x i1> [[CARRYIN]], i64 [[VL]])343// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]344//345vbool32_t test_vmadc_vxm_i16mf2_b32(vint16mf2_t op1, int16_t op2, vbool32_t carryin, size_t vl) {346  return __riscv_vmadc_vxm_i16mf2_b32(op1, op2, carryin, vl);347}348 349// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmadc_vv_i16mf2_b32350// CHECK-RV64-SAME: (<vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {351// CHECK-RV64-NEXT:  entry:352// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[OP1]], <vscale x 2 x i16> [[OP2]], i64 [[VL]])353// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]354//355vbool32_t test_vmadc_vv_i16mf2_b32(vint16mf2_t op1, vint16mf2_t op2, size_t vl) {356  return __riscv_vmadc_vv_i16mf2_b32(op1, op2, vl);357}358 359// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmadc_vx_i16mf2_b32360// CHECK-RV64-SAME: (<vscale x 2 x i16> [[OP1:%.*]], i16 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {361// CHECK-RV64-NEXT:  entry:362// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i16.i16.i64(<vscale x 2 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])363// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]364//365vbool32_t test_vmadc_vx_i16mf2_b32(vint16mf2_t op1, int16_t op2, size_t vl) {366  return __riscv_vmadc_vx_i16mf2_b32(op1, op2, vl);367}368 369// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmadc_vvm_i16m1_b16370// CHECK-RV64-SAME: (<vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {371// CHECK-RV64-NEXT:  entry:372// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[OP1]], <vscale x 4 x i16> [[OP2]], <vscale x 4 x i1> [[CARRYIN]], i64 [[VL]])373// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]374//375vbool16_t test_vmadc_vvm_i16m1_b16(vint16m1_t op1, vint16m1_t op2, vbool16_t carryin, size_t vl) {376  return __riscv_vmadc_vvm_i16m1_b16(op1, op2, carryin, vl);377}378 379// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmadc_vxm_i16m1_b16380// CHECK-RV64-SAME: (<vscale x 4 x i16> [[OP1:%.*]], i16 noundef signext [[OP2:%.*]], <vscale x 4 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {381// CHECK-RV64-NEXT:  entry:382// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i16.i16.i64(<vscale x 4 x i16> [[OP1]], i16 [[OP2]], <vscale x 4 x i1> [[CARRYIN]], i64 [[VL]])383// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]384//385vbool16_t test_vmadc_vxm_i16m1_b16(vint16m1_t op1, int16_t op2, vbool16_t carryin, size_t vl) {386  return __riscv_vmadc_vxm_i16m1_b16(op1, op2, carryin, vl);387}388 389// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmadc_vv_i16m1_b16390// CHECK-RV64-SAME: (<vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {391// CHECK-RV64-NEXT:  entry:392// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmadc.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[OP1]], <vscale x 4 x i16> [[OP2]], i64 [[VL]])393// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]394//395vbool16_t test_vmadc_vv_i16m1_b16(vint16m1_t op1, vint16m1_t op2, size_t vl) {396  return __riscv_vmadc_vv_i16m1_b16(op1, op2, vl);397}398 399// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmadc_vx_i16m1_b16400// CHECK-RV64-SAME: (<vscale x 4 x i16> [[OP1:%.*]], i16 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {401// CHECK-RV64-NEXT:  entry:402// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmadc.nxv4i16.i16.i64(<vscale x 4 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])403// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]404//405vbool16_t test_vmadc_vx_i16m1_b16(vint16m1_t op1, int16_t op2, size_t vl) {406  return __riscv_vmadc_vx_i16m1_b16(op1, op2, vl);407}408 409// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmadc_vvm_i16m2_b8410// CHECK-RV64-SAME: (<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {411// CHECK-RV64-NEXT:  entry:412// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmadc.carry.in.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[OP1]], <vscale x 8 x i16> [[OP2]], <vscale x 8 x i1> [[CARRYIN]], i64 [[VL]])413// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]414//415vbool8_t test_vmadc_vvm_i16m2_b8(vint16m2_t op1, vint16m2_t op2, vbool8_t carryin, size_t vl) {416  return __riscv_vmadc_vvm_i16m2_b8(op1, op2, carryin, vl);417}418 419// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmadc_vxm_i16m2_b8420// CHECK-RV64-SAME: (<vscale x 8 x i16> [[OP1:%.*]], i16 noundef signext [[OP2:%.*]], <vscale x 8 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {421// CHECK-RV64-NEXT:  entry:422// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmadc.carry.in.nxv8i16.i16.i64(<vscale x 8 x i16> [[OP1]], i16 [[OP2]], <vscale x 8 x i1> [[CARRYIN]], i64 [[VL]])423// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]424//425vbool8_t test_vmadc_vxm_i16m2_b8(vint16m2_t op1, int16_t op2, vbool8_t carryin, size_t vl) {426  return __riscv_vmadc_vxm_i16m2_b8(op1, op2, carryin, vl);427}428 429// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmadc_vv_i16m2_b8430// CHECK-RV64-SAME: (<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {431// CHECK-RV64-NEXT:  entry:432// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmadc.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[OP1]], <vscale x 8 x i16> [[OP2]], i64 [[VL]])433// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]434//435vbool8_t test_vmadc_vv_i16m2_b8(vint16m2_t op1, vint16m2_t op2, size_t vl) {436  return __riscv_vmadc_vv_i16m2_b8(op1, op2, vl);437}438 439// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmadc_vx_i16m2_b8440// CHECK-RV64-SAME: (<vscale x 8 x i16> [[OP1:%.*]], i16 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {441// CHECK-RV64-NEXT:  entry:442// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmadc.nxv8i16.i16.i64(<vscale x 8 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])443// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]444//445vbool8_t test_vmadc_vx_i16m2_b8(vint16m2_t op1, int16_t op2, size_t vl) {446  return __riscv_vmadc_vx_i16m2_b8(op1, op2, vl);447}448 449// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmadc_vvm_i16m4_b4450// CHECK-RV64-SAME: (<vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {451// CHECK-RV64-NEXT:  entry:452// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmadc.carry.in.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[OP1]], <vscale x 16 x i16> [[OP2]], <vscale x 16 x i1> [[CARRYIN]], i64 [[VL]])453// CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP0]]454//455vbool4_t test_vmadc_vvm_i16m4_b4(vint16m4_t op1, vint16m4_t op2, vbool4_t carryin, size_t vl) {456  return __riscv_vmadc_vvm_i16m4_b4(op1, op2, carryin, vl);457}458 459// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmadc_vxm_i16m4_b4460// CHECK-RV64-SAME: (<vscale x 16 x i16> [[OP1:%.*]], i16 noundef signext [[OP2:%.*]], <vscale x 16 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {461// CHECK-RV64-NEXT:  entry:462// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmadc.carry.in.nxv16i16.i16.i64(<vscale x 16 x i16> [[OP1]], i16 [[OP2]], <vscale x 16 x i1> [[CARRYIN]], i64 [[VL]])463// CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP0]]464//465vbool4_t test_vmadc_vxm_i16m4_b4(vint16m4_t op1, int16_t op2, vbool4_t carryin, size_t vl) {466  return __riscv_vmadc_vxm_i16m4_b4(op1, op2, carryin, vl);467}468 469// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmadc_vv_i16m4_b4470// CHECK-RV64-SAME: (<vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {471// CHECK-RV64-NEXT:  entry:472// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmadc.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[OP1]], <vscale x 16 x i16> [[OP2]], i64 [[VL]])473// CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP0]]474//475vbool4_t test_vmadc_vv_i16m4_b4(vint16m4_t op1, vint16m4_t op2, size_t vl) {476  return __riscv_vmadc_vv_i16m4_b4(op1, op2, vl);477}478 479// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmadc_vx_i16m4_b4480// CHECK-RV64-SAME: (<vscale x 16 x i16> [[OP1:%.*]], i16 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {481// CHECK-RV64-NEXT:  entry:482// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmadc.nxv16i16.i16.i64(<vscale x 16 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])483// CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP0]]484//485vbool4_t test_vmadc_vx_i16m4_b4(vint16m4_t op1, int16_t op2, size_t vl) {486  return __riscv_vmadc_vx_i16m4_b4(op1, op2, vl);487}488 489// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vmadc_vvm_i16m8_b2490// CHECK-RV64-SAME: (<vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {491// CHECK-RV64-NEXT:  entry:492// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmadc.carry.in.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[OP1]], <vscale x 32 x i16> [[OP2]], <vscale x 32 x i1> [[CARRYIN]], i64 [[VL]])493// CHECK-RV64-NEXT:    ret <vscale x 32 x i1> [[TMP0]]494//495vbool2_t test_vmadc_vvm_i16m8_b2(vint16m8_t op1, vint16m8_t op2, vbool2_t carryin, size_t vl) {496  return __riscv_vmadc_vvm_i16m8_b2(op1, op2, carryin, vl);497}498 499// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vmadc_vxm_i16m8_b2500// CHECK-RV64-SAME: (<vscale x 32 x i16> [[OP1:%.*]], i16 noundef signext [[OP2:%.*]], <vscale x 32 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {501// CHECK-RV64-NEXT:  entry:502// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmadc.carry.in.nxv32i16.i16.i64(<vscale x 32 x i16> [[OP1]], i16 [[OP2]], <vscale x 32 x i1> [[CARRYIN]], i64 [[VL]])503// CHECK-RV64-NEXT:    ret <vscale x 32 x i1> [[TMP0]]504//505vbool2_t test_vmadc_vxm_i16m8_b2(vint16m8_t op1, int16_t op2, vbool2_t carryin, size_t vl) {506  return __riscv_vmadc_vxm_i16m8_b2(op1, op2, carryin, vl);507}508 509// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vmadc_vv_i16m8_b2510// CHECK-RV64-SAME: (<vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {511// CHECK-RV64-NEXT:  entry:512// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmadc.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[OP1]], <vscale x 32 x i16> [[OP2]], i64 [[VL]])513// CHECK-RV64-NEXT:    ret <vscale x 32 x i1> [[TMP0]]514//515vbool2_t test_vmadc_vv_i16m8_b2(vint16m8_t op1, vint16m8_t op2, size_t vl) {516  return __riscv_vmadc_vv_i16m8_b2(op1, op2, vl);517}518 519// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vmadc_vx_i16m8_b2520// CHECK-RV64-SAME: (<vscale x 32 x i16> [[OP1:%.*]], i16 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {521// CHECK-RV64-NEXT:  entry:522// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmadc.nxv32i16.i16.i64(<vscale x 32 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])523// CHECK-RV64-NEXT:    ret <vscale x 32 x i1> [[TMP0]]524//525vbool2_t test_vmadc_vx_i16m8_b2(vint16m8_t op1, int16_t op2, size_t vl) {526  return __riscv_vmadc_vx_i16m8_b2(op1, op2, vl);527}528 529// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmadc_vvm_i32mf2_b64530// CHECK-RV64-SAME: (<vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {531// CHECK-RV64-NEXT:  entry:532// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[OP1]], <vscale x 1 x i32> [[OP2]], <vscale x 1 x i1> [[CARRYIN]], i64 [[VL]])533// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]534//535vbool64_t test_vmadc_vvm_i32mf2_b64(vint32mf2_t op1, vint32mf2_t op2, vbool64_t carryin, size_t vl) {536  return __riscv_vmadc_vvm_i32mf2_b64(op1, op2, carryin, vl);537}538 539// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmadc_vxm_i32mf2_b64540// CHECK-RV64-SAME: (<vscale x 1 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], <vscale x 1 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {541// CHECK-RV64-NEXT:  entry:542// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i32.i32.i64(<vscale x 1 x i32> [[OP1]], i32 [[OP2]], <vscale x 1 x i1> [[CARRYIN]], i64 [[VL]])543// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]544//545vbool64_t test_vmadc_vxm_i32mf2_b64(vint32mf2_t op1, int32_t op2, vbool64_t carryin, size_t vl) {546  return __riscv_vmadc_vxm_i32mf2_b64(op1, op2, carryin, vl);547}548 549// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmadc_vv_i32mf2_b64550// CHECK-RV64-SAME: (<vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {551// CHECK-RV64-NEXT:  entry:552// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[OP1]], <vscale x 1 x i32> [[OP2]], i64 [[VL]])553// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]554//555vbool64_t test_vmadc_vv_i32mf2_b64(vint32mf2_t op1, vint32mf2_t op2, size_t vl) {556  return __riscv_vmadc_vv_i32mf2_b64(op1, op2, vl);557}558 559// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmadc_vx_i32mf2_b64560// CHECK-RV64-SAME: (<vscale x 1 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {561// CHECK-RV64-NEXT:  entry:562// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i32.i32.i64(<vscale x 1 x i32> [[OP1]], i32 [[OP2]], i64 [[VL]])563// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]564//565vbool64_t test_vmadc_vx_i32mf2_b64(vint32mf2_t op1, int32_t op2, size_t vl) {566  return __riscv_vmadc_vx_i32mf2_b64(op1, op2, vl);567}568 569// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmadc_vvm_i32m1_b32570// CHECK-RV64-SAME: (<vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {571// CHECK-RV64-NEXT:  entry:572// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[OP1]], <vscale x 2 x i32> [[OP2]], <vscale x 2 x i1> [[CARRYIN]], i64 [[VL]])573// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]574//575vbool32_t test_vmadc_vvm_i32m1_b32(vint32m1_t op1, vint32m1_t op2, vbool32_t carryin, size_t vl) {576  return __riscv_vmadc_vvm_i32m1_b32(op1, op2, carryin, vl);577}578 579// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmadc_vxm_i32m1_b32580// CHECK-RV64-SAME: (<vscale x 2 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], <vscale x 2 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {581// CHECK-RV64-NEXT:  entry:582// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i32.i32.i64(<vscale x 2 x i32> [[OP1]], i32 [[OP2]], <vscale x 2 x i1> [[CARRYIN]], i64 [[VL]])583// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]584//585vbool32_t test_vmadc_vxm_i32m1_b32(vint32m1_t op1, int32_t op2, vbool32_t carryin, size_t vl) {586  return __riscv_vmadc_vxm_i32m1_b32(op1, op2, carryin, vl);587}588 589// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmadc_vv_i32m1_b32590// CHECK-RV64-SAME: (<vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {591// CHECK-RV64-NEXT:  entry:592// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[OP1]], <vscale x 2 x i32> [[OP2]], i64 [[VL]])593// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]594//595vbool32_t test_vmadc_vv_i32m1_b32(vint32m1_t op1, vint32m1_t op2, size_t vl) {596  return __riscv_vmadc_vv_i32m1_b32(op1, op2, vl);597}598 599// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmadc_vx_i32m1_b32600// CHECK-RV64-SAME: (<vscale x 2 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {601// CHECK-RV64-NEXT:  entry:602// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i32.i32.i64(<vscale x 2 x i32> [[OP1]], i32 [[OP2]], i64 [[VL]])603// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]604//605vbool32_t test_vmadc_vx_i32m1_b32(vint32m1_t op1, int32_t op2, size_t vl) {606  return __riscv_vmadc_vx_i32m1_b32(op1, op2, vl);607}608 609// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmadc_vvm_i32m2_b16610// CHECK-RV64-SAME: (<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {611// CHECK-RV64-NEXT:  entry:612// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[OP1]], <vscale x 4 x i32> [[OP2]], <vscale x 4 x i1> [[CARRYIN]], i64 [[VL]])613// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]614//615vbool16_t test_vmadc_vvm_i32m2_b16(vint32m2_t op1, vint32m2_t op2, vbool16_t carryin, size_t vl) {616  return __riscv_vmadc_vvm_i32m2_b16(op1, op2, carryin, vl);617}618 619// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmadc_vxm_i32m2_b16620// CHECK-RV64-SAME: (<vscale x 4 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], <vscale x 4 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {621// CHECK-RV64-NEXT:  entry:622// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i32.i32.i64(<vscale x 4 x i32> [[OP1]], i32 [[OP2]], <vscale x 4 x i1> [[CARRYIN]], i64 [[VL]])623// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]624//625vbool16_t test_vmadc_vxm_i32m2_b16(vint32m2_t op1, int32_t op2, vbool16_t carryin, size_t vl) {626  return __riscv_vmadc_vxm_i32m2_b16(op1, op2, carryin, vl);627}628 629// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmadc_vv_i32m2_b16630// CHECK-RV64-SAME: (<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {631// CHECK-RV64-NEXT:  entry:632// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmadc.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[OP1]], <vscale x 4 x i32> [[OP2]], i64 [[VL]])633// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]634//635vbool16_t test_vmadc_vv_i32m2_b16(vint32m2_t op1, vint32m2_t op2, size_t vl) {636  return __riscv_vmadc_vv_i32m2_b16(op1, op2, vl);637}638 639// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmadc_vx_i32m2_b16640// CHECK-RV64-SAME: (<vscale x 4 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {641// CHECK-RV64-NEXT:  entry:642// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmadc.nxv4i32.i32.i64(<vscale x 4 x i32> [[OP1]], i32 [[OP2]], i64 [[VL]])643// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]644//645vbool16_t test_vmadc_vx_i32m2_b16(vint32m2_t op1, int32_t op2, size_t vl) {646  return __riscv_vmadc_vx_i32m2_b16(op1, op2, vl);647}648 649// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmadc_vvm_i32m4_b8650// CHECK-RV64-SAME: (<vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {651// CHECK-RV64-NEXT:  entry:652// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmadc.carry.in.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[OP1]], <vscale x 8 x i32> [[OP2]], <vscale x 8 x i1> [[CARRYIN]], i64 [[VL]])653// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]654//655vbool8_t test_vmadc_vvm_i32m4_b8(vint32m4_t op1, vint32m4_t op2, vbool8_t carryin, size_t vl) {656  return __riscv_vmadc_vvm_i32m4_b8(op1, op2, carryin, vl);657}658 659// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmadc_vxm_i32m4_b8660// CHECK-RV64-SAME: (<vscale x 8 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], <vscale x 8 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {661// CHECK-RV64-NEXT:  entry:662// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmadc.carry.in.nxv8i32.i32.i64(<vscale x 8 x i32> [[OP1]], i32 [[OP2]], <vscale x 8 x i1> [[CARRYIN]], i64 [[VL]])663// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]664//665vbool8_t test_vmadc_vxm_i32m4_b8(vint32m4_t op1, int32_t op2, vbool8_t carryin, size_t vl) {666  return __riscv_vmadc_vxm_i32m4_b8(op1, op2, carryin, vl);667}668 669// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmadc_vv_i32m4_b8670// CHECK-RV64-SAME: (<vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {671// CHECK-RV64-NEXT:  entry:672// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmadc.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[OP1]], <vscale x 8 x i32> [[OP2]], i64 [[VL]])673// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]674//675vbool8_t test_vmadc_vv_i32m4_b8(vint32m4_t op1, vint32m4_t op2, size_t vl) {676  return __riscv_vmadc_vv_i32m4_b8(op1, op2, vl);677}678 679// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmadc_vx_i32m4_b8680// CHECK-RV64-SAME: (<vscale x 8 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {681// CHECK-RV64-NEXT:  entry:682// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmadc.nxv8i32.i32.i64(<vscale x 8 x i32> [[OP1]], i32 [[OP2]], i64 [[VL]])683// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]684//685vbool8_t test_vmadc_vx_i32m4_b8(vint32m4_t op1, int32_t op2, size_t vl) {686  return __riscv_vmadc_vx_i32m4_b8(op1, op2, vl);687}688 689// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmadc_vvm_i32m8_b4690// CHECK-RV64-SAME: (<vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {691// CHECK-RV64-NEXT:  entry:692// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmadc.carry.in.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[OP1]], <vscale x 16 x i32> [[OP2]], <vscale x 16 x i1> [[CARRYIN]], i64 [[VL]])693// CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP0]]694//695vbool4_t test_vmadc_vvm_i32m8_b4(vint32m8_t op1, vint32m8_t op2, vbool4_t carryin, size_t vl) {696  return __riscv_vmadc_vvm_i32m8_b4(op1, op2, carryin, vl);697}698 699// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmadc_vxm_i32m8_b4700// CHECK-RV64-SAME: (<vscale x 16 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], <vscale x 16 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {701// CHECK-RV64-NEXT:  entry:702// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmadc.carry.in.nxv16i32.i32.i64(<vscale x 16 x i32> [[OP1]], i32 [[OP2]], <vscale x 16 x i1> [[CARRYIN]], i64 [[VL]])703// CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP0]]704//705vbool4_t test_vmadc_vxm_i32m8_b4(vint32m8_t op1, int32_t op2, vbool4_t carryin, size_t vl) {706  return __riscv_vmadc_vxm_i32m8_b4(op1, op2, carryin, vl);707}708 709// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmadc_vv_i32m8_b4710// CHECK-RV64-SAME: (<vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {711// CHECK-RV64-NEXT:  entry:712// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmadc.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[OP1]], <vscale x 16 x i32> [[OP2]], i64 [[VL]])713// CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP0]]714//715vbool4_t test_vmadc_vv_i32m8_b4(vint32m8_t op1, vint32m8_t op2, size_t vl) {716  return __riscv_vmadc_vv_i32m8_b4(op1, op2, vl);717}718 719// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmadc_vx_i32m8_b4720// CHECK-RV64-SAME: (<vscale x 16 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {721// CHECK-RV64-NEXT:  entry:722// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmadc.nxv16i32.i32.i64(<vscale x 16 x i32> [[OP1]], i32 [[OP2]], i64 [[VL]])723// CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP0]]724//725vbool4_t test_vmadc_vx_i32m8_b4(vint32m8_t op1, int32_t op2, size_t vl) {726  return __riscv_vmadc_vx_i32m8_b4(op1, op2, vl);727}728 729// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmadc_vvm_i64m1_b64730// CHECK-RV64-SAME: (<vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {731// CHECK-RV64-NEXT:  entry:732// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[OP1]], <vscale x 1 x i64> [[OP2]], <vscale x 1 x i1> [[CARRYIN]], i64 [[VL]])733// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]734//735vbool64_t test_vmadc_vvm_i64m1_b64(vint64m1_t op1, vint64m1_t op2, vbool64_t carryin, size_t vl) {736  return __riscv_vmadc_vvm_i64m1_b64(op1, op2, carryin, vl);737}738 739// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmadc_vxm_i64m1_b64740// CHECK-RV64-SAME: (<vscale x 1 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], <vscale x 1 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {741// CHECK-RV64-NEXT:  entry:742// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i64.i64.i64(<vscale x 1 x i64> [[OP1]], i64 [[OP2]], <vscale x 1 x i1> [[CARRYIN]], i64 [[VL]])743// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]744//745vbool64_t test_vmadc_vxm_i64m1_b64(vint64m1_t op1, int64_t op2, vbool64_t carryin, size_t vl) {746  return __riscv_vmadc_vxm_i64m1_b64(op1, op2, carryin, vl);747}748 749// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmadc_vv_i64m1_b64750// CHECK-RV64-SAME: (<vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {751// CHECK-RV64-NEXT:  entry:752// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[OP1]], <vscale x 1 x i64> [[OP2]], i64 [[VL]])753// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]754//755vbool64_t test_vmadc_vv_i64m1_b64(vint64m1_t op1, vint64m1_t op2, size_t vl) {756  return __riscv_vmadc_vv_i64m1_b64(op1, op2, vl);757}758 759// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmadc_vx_i64m1_b64760// CHECK-RV64-SAME: (<vscale x 1 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {761// CHECK-RV64-NEXT:  entry:762// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i64.i64.i64(<vscale x 1 x i64> [[OP1]], i64 [[OP2]], i64 [[VL]])763// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]764//765vbool64_t test_vmadc_vx_i64m1_b64(vint64m1_t op1, int64_t op2, size_t vl) {766  return __riscv_vmadc_vx_i64m1_b64(op1, op2, vl);767}768 769// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmadc_vvm_i64m2_b32770// CHECK-RV64-SAME: (<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {771// CHECK-RV64-NEXT:  entry:772// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[OP1]], <vscale x 2 x i64> [[OP2]], <vscale x 2 x i1> [[CARRYIN]], i64 [[VL]])773// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]774//775vbool32_t test_vmadc_vvm_i64m2_b32(vint64m2_t op1, vint64m2_t op2, vbool32_t carryin, size_t vl) {776  return __riscv_vmadc_vvm_i64m2_b32(op1, op2, carryin, vl);777}778 779// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmadc_vxm_i64m2_b32780// CHECK-RV64-SAME: (<vscale x 2 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], <vscale x 2 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {781// CHECK-RV64-NEXT:  entry:782// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i64.i64.i64(<vscale x 2 x i64> [[OP1]], i64 [[OP2]], <vscale x 2 x i1> [[CARRYIN]], i64 [[VL]])783// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]784//785vbool32_t test_vmadc_vxm_i64m2_b32(vint64m2_t op1, int64_t op2, vbool32_t carryin, size_t vl) {786  return __riscv_vmadc_vxm_i64m2_b32(op1, op2, carryin, vl);787}788 789// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmadc_vv_i64m2_b32790// CHECK-RV64-SAME: (<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {791// CHECK-RV64-NEXT:  entry:792// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[OP1]], <vscale x 2 x i64> [[OP2]], i64 [[VL]])793// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]794//795vbool32_t test_vmadc_vv_i64m2_b32(vint64m2_t op1, vint64m2_t op2, size_t vl) {796  return __riscv_vmadc_vv_i64m2_b32(op1, op2, vl);797}798 799// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmadc_vx_i64m2_b32800// CHECK-RV64-SAME: (<vscale x 2 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {801// CHECK-RV64-NEXT:  entry:802// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i64.i64.i64(<vscale x 2 x i64> [[OP1]], i64 [[OP2]], i64 [[VL]])803// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]804//805vbool32_t test_vmadc_vx_i64m2_b32(vint64m2_t op1, int64_t op2, size_t vl) {806  return __riscv_vmadc_vx_i64m2_b32(op1, op2, vl);807}808 809// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmadc_vvm_i64m4_b16810// CHECK-RV64-SAME: (<vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {811// CHECK-RV64-NEXT:  entry:812// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[OP1]], <vscale x 4 x i64> [[OP2]], <vscale x 4 x i1> [[CARRYIN]], i64 [[VL]])813// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]814//815vbool16_t test_vmadc_vvm_i64m4_b16(vint64m4_t op1, vint64m4_t op2, vbool16_t carryin, size_t vl) {816  return __riscv_vmadc_vvm_i64m4_b16(op1, op2, carryin, vl);817}818 819// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmadc_vxm_i64m4_b16820// CHECK-RV64-SAME: (<vscale x 4 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], <vscale x 4 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {821// CHECK-RV64-NEXT:  entry:822// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i64.i64.i64(<vscale x 4 x i64> [[OP1]], i64 [[OP2]], <vscale x 4 x i1> [[CARRYIN]], i64 [[VL]])823// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]824//825vbool16_t test_vmadc_vxm_i64m4_b16(vint64m4_t op1, int64_t op2, vbool16_t carryin, size_t vl) {826  return __riscv_vmadc_vxm_i64m4_b16(op1, op2, carryin, vl);827}828 829// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmadc_vv_i64m4_b16830// CHECK-RV64-SAME: (<vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {831// CHECK-RV64-NEXT:  entry:832// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmadc.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[OP1]], <vscale x 4 x i64> [[OP2]], i64 [[VL]])833// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]834//835vbool16_t test_vmadc_vv_i64m4_b16(vint64m4_t op1, vint64m4_t op2, size_t vl) {836  return __riscv_vmadc_vv_i64m4_b16(op1, op2, vl);837}838 839// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmadc_vx_i64m4_b16840// CHECK-RV64-SAME: (<vscale x 4 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {841// CHECK-RV64-NEXT:  entry:842// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmadc.nxv4i64.i64.i64(<vscale x 4 x i64> [[OP1]], i64 [[OP2]], i64 [[VL]])843// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]844//845vbool16_t test_vmadc_vx_i64m4_b16(vint64m4_t op1, int64_t op2, size_t vl) {846  return __riscv_vmadc_vx_i64m4_b16(op1, op2, vl);847}848 849// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmadc_vvm_i64m8_b8850// CHECK-RV64-SAME: (<vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {851// CHECK-RV64-NEXT:  entry:852// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmadc.carry.in.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[OP1]], <vscale x 8 x i64> [[OP2]], <vscale x 8 x i1> [[CARRYIN]], i64 [[VL]])853// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]854//855vbool8_t test_vmadc_vvm_i64m8_b8(vint64m8_t op1, vint64m8_t op2, vbool8_t carryin, size_t vl) {856  return __riscv_vmadc_vvm_i64m8_b8(op1, op2, carryin, vl);857}858 859// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmadc_vxm_i64m8_b8860// CHECK-RV64-SAME: (<vscale x 8 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], <vscale x 8 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {861// CHECK-RV64-NEXT:  entry:862// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmadc.carry.in.nxv8i64.i64.i64(<vscale x 8 x i64> [[OP1]], i64 [[OP2]], <vscale x 8 x i1> [[CARRYIN]], i64 [[VL]])863// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]864//865vbool8_t test_vmadc_vxm_i64m8_b8(vint64m8_t op1, int64_t op2, vbool8_t carryin, size_t vl) {866  return __riscv_vmadc_vxm_i64m8_b8(op1, op2, carryin, vl);867}868 869// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmadc_vv_i64m8_b8870// CHECK-RV64-SAME: (<vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {871// CHECK-RV64-NEXT:  entry:872// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmadc.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[OP1]], <vscale x 8 x i64> [[OP2]], i64 [[VL]])873// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]874//875vbool8_t test_vmadc_vv_i64m8_b8(vint64m8_t op1, vint64m8_t op2, size_t vl) {876  return __riscv_vmadc_vv_i64m8_b8(op1, op2, vl);877}878 879// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmadc_vx_i64m8_b8880// CHECK-RV64-SAME: (<vscale x 8 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {881// CHECK-RV64-NEXT:  entry:882// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmadc.nxv8i64.i64.i64(<vscale x 8 x i64> [[OP1]], i64 [[OP2]], i64 [[VL]])883// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]884//885vbool8_t test_vmadc_vx_i64m8_b8(vint64m8_t op1, int64_t op2, size_t vl) {886  return __riscv_vmadc_vx_i64m8_b8(op1, op2, vl);887}888 889// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmadc_vvm_u8mf8_b64890// CHECK-RV64-SAME: (<vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {891// CHECK-RV64-NEXT:  entry:892// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1]], <vscale x 1 x i8> [[OP2]], <vscale x 1 x i1> [[CARRYIN]], i64 [[VL]])893// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]894//895vbool64_t test_vmadc_vvm_u8mf8_b64(vuint8mf8_t op1, vuint8mf8_t op2, vbool64_t carryin, size_t vl) {896  return __riscv_vmadc_vvm_u8mf8_b64(op1, op2, carryin, vl);897}898 899// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmadc_vxm_u8mf8_b64900// CHECK-RV64-SAME: (<vscale x 1 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], <vscale x 1 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {901// CHECK-RV64-NEXT:  entry:902// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.i8.i64(<vscale x 1 x i8> [[OP1]], i8 [[OP2]], <vscale x 1 x i1> [[CARRYIN]], i64 [[VL]])903// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]904//905vbool64_t test_vmadc_vxm_u8mf8_b64(vuint8mf8_t op1, uint8_t op2, vbool64_t carryin, size_t vl) {906  return __riscv_vmadc_vxm_u8mf8_b64(op1, op2, carryin, vl);907}908 909// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmadc_vv_u8mf8_b64910// CHECK-RV64-SAME: (<vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {911// CHECK-RV64-NEXT:  entry:912// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1]], <vscale x 1 x i8> [[OP2]], i64 [[VL]])913// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]914//915vbool64_t test_vmadc_vv_u8mf8_b64(vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) {916  return __riscv_vmadc_vv_u8mf8_b64(op1, op2, vl);917}918 919// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmadc_vx_u8mf8_b64920// CHECK-RV64-SAME: (<vscale x 1 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {921// CHECK-RV64-NEXT:  entry:922// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i8.i8.i64(<vscale x 1 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])923// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]924//925vbool64_t test_vmadc_vx_u8mf8_b64(vuint8mf8_t op1, uint8_t op2, size_t vl) {926  return __riscv_vmadc_vx_u8mf8_b64(op1, op2, vl);927}928 929// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmadc_vvm_u8mf4_b32930// CHECK-RV64-SAME: (<vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {931// CHECK-RV64-NEXT:  entry:932// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[OP1]], <vscale x 2 x i8> [[OP2]], <vscale x 2 x i1> [[CARRYIN]], i64 [[VL]])933// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]934//935vbool32_t test_vmadc_vvm_u8mf4_b32(vuint8mf4_t op1, vuint8mf4_t op2, vbool32_t carryin, size_t vl) {936  return __riscv_vmadc_vvm_u8mf4_b32(op1, op2, carryin, vl);937}938 939// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmadc_vxm_u8mf4_b32940// CHECK-RV64-SAME: (<vscale x 2 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], <vscale x 2 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {941// CHECK-RV64-NEXT:  entry:942// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i8.i8.i64(<vscale x 2 x i8> [[OP1]], i8 [[OP2]], <vscale x 2 x i1> [[CARRYIN]], i64 [[VL]])943// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]944//945vbool32_t test_vmadc_vxm_u8mf4_b32(vuint8mf4_t op1, uint8_t op2, vbool32_t carryin, size_t vl) {946  return __riscv_vmadc_vxm_u8mf4_b32(op1, op2, carryin, vl);947}948 949// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmadc_vv_u8mf4_b32950// CHECK-RV64-SAME: (<vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {951// CHECK-RV64-NEXT:  entry:952// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[OP1]], <vscale x 2 x i8> [[OP2]], i64 [[VL]])953// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]954//955vbool32_t test_vmadc_vv_u8mf4_b32(vuint8mf4_t op1, vuint8mf4_t op2, size_t vl) {956  return __riscv_vmadc_vv_u8mf4_b32(op1, op2, vl);957}958 959// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmadc_vx_u8mf4_b32960// CHECK-RV64-SAME: (<vscale x 2 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {961// CHECK-RV64-NEXT:  entry:962// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i8.i8.i64(<vscale x 2 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])963// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]964//965vbool32_t test_vmadc_vx_u8mf4_b32(vuint8mf4_t op1, uint8_t op2, size_t vl) {966  return __riscv_vmadc_vx_u8mf4_b32(op1, op2, vl);967}968 969// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmadc_vvm_u8mf2_b16970// CHECK-RV64-SAME: (<vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {971// CHECK-RV64-NEXT:  entry:972// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[OP1]], <vscale x 4 x i8> [[OP2]], <vscale x 4 x i1> [[CARRYIN]], i64 [[VL]])973// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]974//975vbool16_t test_vmadc_vvm_u8mf2_b16(vuint8mf2_t op1, vuint8mf2_t op2, vbool16_t carryin, size_t vl) {976  return __riscv_vmadc_vvm_u8mf2_b16(op1, op2, carryin, vl);977}978 979// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmadc_vxm_u8mf2_b16980// CHECK-RV64-SAME: (<vscale x 4 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], <vscale x 4 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {981// CHECK-RV64-NEXT:  entry:982// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i8.i8.i64(<vscale x 4 x i8> [[OP1]], i8 [[OP2]], <vscale x 4 x i1> [[CARRYIN]], i64 [[VL]])983// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]984//985vbool16_t test_vmadc_vxm_u8mf2_b16(vuint8mf2_t op1, uint8_t op2, vbool16_t carryin, size_t vl) {986  return __riscv_vmadc_vxm_u8mf2_b16(op1, op2, carryin, vl);987}988 989// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmadc_vv_u8mf2_b16990// CHECK-RV64-SAME: (<vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {991// CHECK-RV64-NEXT:  entry:992// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmadc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[OP1]], <vscale x 4 x i8> [[OP2]], i64 [[VL]])993// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]994//995vbool16_t test_vmadc_vv_u8mf2_b16(vuint8mf2_t op1, vuint8mf2_t op2, size_t vl) {996  return __riscv_vmadc_vv_u8mf2_b16(op1, op2, vl);997}998 999// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmadc_vx_u8mf2_b161000// CHECK-RV64-SAME: (<vscale x 4 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1001// CHECK-RV64-NEXT:  entry:1002// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmadc.nxv4i8.i8.i64(<vscale x 4 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])1003// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]1004//1005vbool16_t test_vmadc_vx_u8mf2_b16(vuint8mf2_t op1, uint8_t op2, size_t vl) {1006  return __riscv_vmadc_vx_u8mf2_b16(op1, op2, vl);1007}1008 1009// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmadc_vvm_u8m1_b81010// CHECK-RV64-SAME: (<vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1011// CHECK-RV64-NEXT:  entry:1012// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmadc.carry.in.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[OP1]], <vscale x 8 x i8> [[OP2]], <vscale x 8 x i1> [[CARRYIN]], i64 [[VL]])1013// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]1014//1015vbool8_t test_vmadc_vvm_u8m1_b8(vuint8m1_t op1, vuint8m1_t op2, vbool8_t carryin, size_t vl) {1016  return __riscv_vmadc_vvm_u8m1_b8(op1, op2, carryin, vl);1017}1018 1019// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmadc_vxm_u8m1_b81020// CHECK-RV64-SAME: (<vscale x 8 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], <vscale x 8 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1021// CHECK-RV64-NEXT:  entry:1022// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmadc.carry.in.nxv8i8.i8.i64(<vscale x 8 x i8> [[OP1]], i8 [[OP2]], <vscale x 8 x i1> [[CARRYIN]], i64 [[VL]])1023// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]1024//1025vbool8_t test_vmadc_vxm_u8m1_b8(vuint8m1_t op1, uint8_t op2, vbool8_t carryin, size_t vl) {1026  return __riscv_vmadc_vxm_u8m1_b8(op1, op2, carryin, vl);1027}1028 1029// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmadc_vv_u8m1_b81030// CHECK-RV64-SAME: (<vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1031// CHECK-RV64-NEXT:  entry:1032// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmadc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[OP1]], <vscale x 8 x i8> [[OP2]], i64 [[VL]])1033// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]1034//1035vbool8_t test_vmadc_vv_u8m1_b8(vuint8m1_t op1, vuint8m1_t op2, size_t vl) {1036  return __riscv_vmadc_vv_u8m1_b8(op1, op2, vl);1037}1038 1039// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmadc_vx_u8m1_b81040// CHECK-RV64-SAME: (<vscale x 8 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1041// CHECK-RV64-NEXT:  entry:1042// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmadc.nxv8i8.i8.i64(<vscale x 8 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])1043// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]1044//1045vbool8_t test_vmadc_vx_u8m1_b8(vuint8m1_t op1, uint8_t op2, size_t vl) {1046  return __riscv_vmadc_vx_u8m1_b8(op1, op2, vl);1047}1048 1049// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmadc_vvm_u8m2_b41050// CHECK-RV64-SAME: (<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1051// CHECK-RV64-NEXT:  entry:1052// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmadc.carry.in.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[OP1]], <vscale x 16 x i8> [[OP2]], <vscale x 16 x i1> [[CARRYIN]], i64 [[VL]])1053// CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP0]]1054//1055vbool4_t test_vmadc_vvm_u8m2_b4(vuint8m2_t op1, vuint8m2_t op2, vbool4_t carryin, size_t vl) {1056  return __riscv_vmadc_vvm_u8m2_b4(op1, op2, carryin, vl);1057}1058 1059// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmadc_vxm_u8m2_b41060// CHECK-RV64-SAME: (<vscale x 16 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], <vscale x 16 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1061// CHECK-RV64-NEXT:  entry:1062// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmadc.carry.in.nxv16i8.i8.i64(<vscale x 16 x i8> [[OP1]], i8 [[OP2]], <vscale x 16 x i1> [[CARRYIN]], i64 [[VL]])1063// CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP0]]1064//1065vbool4_t test_vmadc_vxm_u8m2_b4(vuint8m2_t op1, uint8_t op2, vbool4_t carryin, size_t vl) {1066  return __riscv_vmadc_vxm_u8m2_b4(op1, op2, carryin, vl);1067}1068 1069// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmadc_vv_u8m2_b41070// CHECK-RV64-SAME: (<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1071// CHECK-RV64-NEXT:  entry:1072// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmadc.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[OP1]], <vscale x 16 x i8> [[OP2]], i64 [[VL]])1073// CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP0]]1074//1075vbool4_t test_vmadc_vv_u8m2_b4(vuint8m2_t op1, vuint8m2_t op2, size_t vl) {1076  return __riscv_vmadc_vv_u8m2_b4(op1, op2, vl);1077}1078 1079// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmadc_vx_u8m2_b41080// CHECK-RV64-SAME: (<vscale x 16 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1081// CHECK-RV64-NEXT:  entry:1082// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmadc.nxv16i8.i8.i64(<vscale x 16 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])1083// CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP0]]1084//1085vbool4_t test_vmadc_vx_u8m2_b4(vuint8m2_t op1, uint8_t op2, size_t vl) {1086  return __riscv_vmadc_vx_u8m2_b4(op1, op2, vl);1087}1088 1089// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vmadc_vvm_u8m4_b21090// CHECK-RV64-SAME: (<vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1091// CHECK-RV64-NEXT:  entry:1092// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmadc.carry.in.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[OP1]], <vscale x 32 x i8> [[OP2]], <vscale x 32 x i1> [[CARRYIN]], i64 [[VL]])1093// CHECK-RV64-NEXT:    ret <vscale x 32 x i1> [[TMP0]]1094//1095vbool2_t test_vmadc_vvm_u8m4_b2(vuint8m4_t op1, vuint8m4_t op2, vbool2_t carryin, size_t vl) {1096  return __riscv_vmadc_vvm_u8m4_b2(op1, op2, carryin, vl);1097}1098 1099// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vmadc_vxm_u8m4_b21100// CHECK-RV64-SAME: (<vscale x 32 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], <vscale x 32 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1101// CHECK-RV64-NEXT:  entry:1102// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmadc.carry.in.nxv32i8.i8.i64(<vscale x 32 x i8> [[OP1]], i8 [[OP2]], <vscale x 32 x i1> [[CARRYIN]], i64 [[VL]])1103// CHECK-RV64-NEXT:    ret <vscale x 32 x i1> [[TMP0]]1104//1105vbool2_t test_vmadc_vxm_u8m4_b2(vuint8m4_t op1, uint8_t op2, vbool2_t carryin, size_t vl) {1106  return __riscv_vmadc_vxm_u8m4_b2(op1, op2, carryin, vl);1107}1108 1109// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vmadc_vv_u8m4_b21110// CHECK-RV64-SAME: (<vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1111// CHECK-RV64-NEXT:  entry:1112// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmadc.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[OP1]], <vscale x 32 x i8> [[OP2]], i64 [[VL]])1113// CHECK-RV64-NEXT:    ret <vscale x 32 x i1> [[TMP0]]1114//1115vbool2_t test_vmadc_vv_u8m4_b2(vuint8m4_t op1, vuint8m4_t op2, size_t vl) {1116  return __riscv_vmadc_vv_u8m4_b2(op1, op2, vl);1117}1118 1119// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vmadc_vx_u8m4_b21120// CHECK-RV64-SAME: (<vscale x 32 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1121// CHECK-RV64-NEXT:  entry:1122// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmadc.nxv32i8.i8.i64(<vscale x 32 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])1123// CHECK-RV64-NEXT:    ret <vscale x 32 x i1> [[TMP0]]1124//1125vbool2_t test_vmadc_vx_u8m4_b2(vuint8m4_t op1, uint8_t op2, size_t vl) {1126  return __riscv_vmadc_vx_u8m4_b2(op1, op2, vl);1127}1128 1129// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i1> @test_vmadc_vvm_u8m8_b11130// CHECK-RV64-SAME: (<vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1131// CHECK-RV64-NEXT:  entry:1132// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmadc.carry.in.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[OP1]], <vscale x 64 x i8> [[OP2]], <vscale x 64 x i1> [[CARRYIN]], i64 [[VL]])1133// CHECK-RV64-NEXT:    ret <vscale x 64 x i1> [[TMP0]]1134//1135vbool1_t test_vmadc_vvm_u8m8_b1(vuint8m8_t op1, vuint8m8_t op2, vbool1_t carryin, size_t vl) {1136  return __riscv_vmadc_vvm_u8m8_b1(op1, op2, carryin, vl);1137}1138 1139// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i1> @test_vmadc_vxm_u8m8_b11140// CHECK-RV64-SAME: (<vscale x 64 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], <vscale x 64 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1141// CHECK-RV64-NEXT:  entry:1142// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmadc.carry.in.nxv64i8.i8.i64(<vscale x 64 x i8> [[OP1]], i8 [[OP2]], <vscale x 64 x i1> [[CARRYIN]], i64 [[VL]])1143// CHECK-RV64-NEXT:    ret <vscale x 64 x i1> [[TMP0]]1144//1145vbool1_t test_vmadc_vxm_u8m8_b1(vuint8m8_t op1, uint8_t op2, vbool1_t carryin, size_t vl) {1146  return __riscv_vmadc_vxm_u8m8_b1(op1, op2, carryin, vl);1147}1148 1149// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i1> @test_vmadc_vv_u8m8_b11150// CHECK-RV64-SAME: (<vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1151// CHECK-RV64-NEXT:  entry:1152// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmadc.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[OP1]], <vscale x 64 x i8> [[OP2]], i64 [[VL]])1153// CHECK-RV64-NEXT:    ret <vscale x 64 x i1> [[TMP0]]1154//1155vbool1_t test_vmadc_vv_u8m8_b1(vuint8m8_t op1, vuint8m8_t op2, size_t vl) {1156  return __riscv_vmadc_vv_u8m8_b1(op1, op2, vl);1157}1158 1159// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i1> @test_vmadc_vx_u8m8_b11160// CHECK-RV64-SAME: (<vscale x 64 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1161// CHECK-RV64-NEXT:  entry:1162// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmadc.nxv64i8.i8.i64(<vscale x 64 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])1163// CHECK-RV64-NEXT:    ret <vscale x 64 x i1> [[TMP0]]1164//1165vbool1_t test_vmadc_vx_u8m8_b1(vuint8m8_t op1, uint8_t op2, size_t vl) {1166  return __riscv_vmadc_vx_u8m8_b1(op1, op2, vl);1167}1168 1169// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmadc_vvm_u16mf4_b641170// CHECK-RV64-SAME: (<vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1171// CHECK-RV64-NEXT:  entry:1172// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[OP1]], <vscale x 1 x i16> [[OP2]], <vscale x 1 x i1> [[CARRYIN]], i64 [[VL]])1173// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]1174//1175vbool64_t test_vmadc_vvm_u16mf4_b64(vuint16mf4_t op1, vuint16mf4_t op2, vbool64_t carryin, size_t vl) {1176  return __riscv_vmadc_vvm_u16mf4_b64(op1, op2, carryin, vl);1177}1178 1179// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmadc_vxm_u16mf4_b641180// CHECK-RV64-SAME: (<vscale x 1 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], <vscale x 1 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1181// CHECK-RV64-NEXT:  entry:1182// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i16.i16.i64(<vscale x 1 x i16> [[OP1]], i16 [[OP2]], <vscale x 1 x i1> [[CARRYIN]], i64 [[VL]])1183// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]1184//1185vbool64_t test_vmadc_vxm_u16mf4_b64(vuint16mf4_t op1, uint16_t op2, vbool64_t carryin, size_t vl) {1186  return __riscv_vmadc_vxm_u16mf4_b64(op1, op2, carryin, vl);1187}1188 1189// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmadc_vv_u16mf4_b641190// CHECK-RV64-SAME: (<vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1191// CHECK-RV64-NEXT:  entry:1192// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[OP1]], <vscale x 1 x i16> [[OP2]], i64 [[VL]])1193// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]1194//1195vbool64_t test_vmadc_vv_u16mf4_b64(vuint16mf4_t op1, vuint16mf4_t op2, size_t vl) {1196  return __riscv_vmadc_vv_u16mf4_b64(op1, op2, vl);1197}1198 1199// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmadc_vx_u16mf4_b641200// CHECK-RV64-SAME: (<vscale x 1 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1201// CHECK-RV64-NEXT:  entry:1202// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i16.i16.i64(<vscale x 1 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])1203// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]1204//1205vbool64_t test_vmadc_vx_u16mf4_b64(vuint16mf4_t op1, uint16_t op2, size_t vl) {1206  return __riscv_vmadc_vx_u16mf4_b64(op1, op2, vl);1207}1208 1209// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmadc_vvm_u16mf2_b321210// CHECK-RV64-SAME: (<vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1211// CHECK-RV64-NEXT:  entry:1212// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[OP1]], <vscale x 2 x i16> [[OP2]], <vscale x 2 x i1> [[CARRYIN]], i64 [[VL]])1213// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]1214//1215vbool32_t test_vmadc_vvm_u16mf2_b32(vuint16mf2_t op1, vuint16mf2_t op2, vbool32_t carryin, size_t vl) {1216  return __riscv_vmadc_vvm_u16mf2_b32(op1, op2, carryin, vl);1217}1218 1219// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmadc_vxm_u16mf2_b321220// CHECK-RV64-SAME: (<vscale x 2 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], <vscale x 2 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1221// CHECK-RV64-NEXT:  entry:1222// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i16.i16.i64(<vscale x 2 x i16> [[OP1]], i16 [[OP2]], <vscale x 2 x i1> [[CARRYIN]], i64 [[VL]])1223// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]1224//1225vbool32_t test_vmadc_vxm_u16mf2_b32(vuint16mf2_t op1, uint16_t op2, vbool32_t carryin, size_t vl) {1226  return __riscv_vmadc_vxm_u16mf2_b32(op1, op2, carryin, vl);1227}1228 1229// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmadc_vv_u16mf2_b321230// CHECK-RV64-SAME: (<vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1231// CHECK-RV64-NEXT:  entry:1232// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[OP1]], <vscale x 2 x i16> [[OP2]], i64 [[VL]])1233// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]1234//1235vbool32_t test_vmadc_vv_u16mf2_b32(vuint16mf2_t op1, vuint16mf2_t op2, size_t vl) {1236  return __riscv_vmadc_vv_u16mf2_b32(op1, op2, vl);1237}1238 1239// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmadc_vx_u16mf2_b321240// CHECK-RV64-SAME: (<vscale x 2 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1241// CHECK-RV64-NEXT:  entry:1242// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i16.i16.i64(<vscale x 2 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])1243// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]1244//1245vbool32_t test_vmadc_vx_u16mf2_b32(vuint16mf2_t op1, uint16_t op2, size_t vl) {1246  return __riscv_vmadc_vx_u16mf2_b32(op1, op2, vl);1247}1248 1249// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmadc_vvm_u16m1_b161250// CHECK-RV64-SAME: (<vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1251// CHECK-RV64-NEXT:  entry:1252// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[OP1]], <vscale x 4 x i16> [[OP2]], <vscale x 4 x i1> [[CARRYIN]], i64 [[VL]])1253// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]1254//1255vbool16_t test_vmadc_vvm_u16m1_b16(vuint16m1_t op1, vuint16m1_t op2, vbool16_t carryin, size_t vl) {1256  return __riscv_vmadc_vvm_u16m1_b16(op1, op2, carryin, vl);1257}1258 1259// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmadc_vxm_u16m1_b161260// CHECK-RV64-SAME: (<vscale x 4 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], <vscale x 4 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1261// CHECK-RV64-NEXT:  entry:1262// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i16.i16.i64(<vscale x 4 x i16> [[OP1]], i16 [[OP2]], <vscale x 4 x i1> [[CARRYIN]], i64 [[VL]])1263// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]1264//1265vbool16_t test_vmadc_vxm_u16m1_b16(vuint16m1_t op1, uint16_t op2, vbool16_t carryin, size_t vl) {1266  return __riscv_vmadc_vxm_u16m1_b16(op1, op2, carryin, vl);1267}1268 1269// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmadc_vv_u16m1_b161270// CHECK-RV64-SAME: (<vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1271// CHECK-RV64-NEXT:  entry:1272// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmadc.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[OP1]], <vscale x 4 x i16> [[OP2]], i64 [[VL]])1273// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]1274//1275vbool16_t test_vmadc_vv_u16m1_b16(vuint16m1_t op1, vuint16m1_t op2, size_t vl) {1276  return __riscv_vmadc_vv_u16m1_b16(op1, op2, vl);1277}1278 1279// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmadc_vx_u16m1_b161280// CHECK-RV64-SAME: (<vscale x 4 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1281// CHECK-RV64-NEXT:  entry:1282// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmadc.nxv4i16.i16.i64(<vscale x 4 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])1283// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]1284//1285vbool16_t test_vmadc_vx_u16m1_b16(vuint16m1_t op1, uint16_t op2, size_t vl) {1286  return __riscv_vmadc_vx_u16m1_b16(op1, op2, vl);1287}1288 1289// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmadc_vvm_u16m2_b81290// CHECK-RV64-SAME: (<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1291// CHECK-RV64-NEXT:  entry:1292// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmadc.carry.in.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[OP1]], <vscale x 8 x i16> [[OP2]], <vscale x 8 x i1> [[CARRYIN]], i64 [[VL]])1293// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]1294//1295vbool8_t test_vmadc_vvm_u16m2_b8(vuint16m2_t op1, vuint16m2_t op2, vbool8_t carryin, size_t vl) {1296  return __riscv_vmadc_vvm_u16m2_b8(op1, op2, carryin, vl);1297}1298 1299// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmadc_vxm_u16m2_b81300// CHECK-RV64-SAME: (<vscale x 8 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], <vscale x 8 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1301// CHECK-RV64-NEXT:  entry:1302// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmadc.carry.in.nxv8i16.i16.i64(<vscale x 8 x i16> [[OP1]], i16 [[OP2]], <vscale x 8 x i1> [[CARRYIN]], i64 [[VL]])1303// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]1304//1305vbool8_t test_vmadc_vxm_u16m2_b8(vuint16m2_t op1, uint16_t op2, vbool8_t carryin, size_t vl) {1306  return __riscv_vmadc_vxm_u16m2_b8(op1, op2, carryin, vl);1307}1308 1309// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmadc_vv_u16m2_b81310// CHECK-RV64-SAME: (<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1311// CHECK-RV64-NEXT:  entry:1312// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmadc.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[OP1]], <vscale x 8 x i16> [[OP2]], i64 [[VL]])1313// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]1314//1315vbool8_t test_vmadc_vv_u16m2_b8(vuint16m2_t op1, vuint16m2_t op2, size_t vl) {1316  return __riscv_vmadc_vv_u16m2_b8(op1, op2, vl);1317}1318 1319// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmadc_vx_u16m2_b81320// CHECK-RV64-SAME: (<vscale x 8 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1321// CHECK-RV64-NEXT:  entry:1322// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmadc.nxv8i16.i16.i64(<vscale x 8 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])1323// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]1324//1325vbool8_t test_vmadc_vx_u16m2_b8(vuint16m2_t op1, uint16_t op2, size_t vl) {1326  return __riscv_vmadc_vx_u16m2_b8(op1, op2, vl);1327}1328 1329// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmadc_vvm_u16m4_b41330// CHECK-RV64-SAME: (<vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1331// CHECK-RV64-NEXT:  entry:1332// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmadc.carry.in.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[OP1]], <vscale x 16 x i16> [[OP2]], <vscale x 16 x i1> [[CARRYIN]], i64 [[VL]])1333// CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP0]]1334//1335vbool4_t test_vmadc_vvm_u16m4_b4(vuint16m4_t op1, vuint16m4_t op2, vbool4_t carryin, size_t vl) {1336  return __riscv_vmadc_vvm_u16m4_b4(op1, op2, carryin, vl);1337}1338 1339// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmadc_vxm_u16m4_b41340// CHECK-RV64-SAME: (<vscale x 16 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], <vscale x 16 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1341// CHECK-RV64-NEXT:  entry:1342// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmadc.carry.in.nxv16i16.i16.i64(<vscale x 16 x i16> [[OP1]], i16 [[OP2]], <vscale x 16 x i1> [[CARRYIN]], i64 [[VL]])1343// CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP0]]1344//1345vbool4_t test_vmadc_vxm_u16m4_b4(vuint16m4_t op1, uint16_t op2, vbool4_t carryin, size_t vl) {1346  return __riscv_vmadc_vxm_u16m4_b4(op1, op2, carryin, vl);1347}1348 1349// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmadc_vv_u16m4_b41350// CHECK-RV64-SAME: (<vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1351// CHECK-RV64-NEXT:  entry:1352// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmadc.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[OP1]], <vscale x 16 x i16> [[OP2]], i64 [[VL]])1353// CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP0]]1354//1355vbool4_t test_vmadc_vv_u16m4_b4(vuint16m4_t op1, vuint16m4_t op2, size_t vl) {1356  return __riscv_vmadc_vv_u16m4_b4(op1, op2, vl);1357}1358 1359// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmadc_vx_u16m4_b41360// CHECK-RV64-SAME: (<vscale x 16 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1361// CHECK-RV64-NEXT:  entry:1362// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmadc.nxv16i16.i16.i64(<vscale x 16 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])1363// CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP0]]1364//1365vbool4_t test_vmadc_vx_u16m4_b4(vuint16m4_t op1, uint16_t op2, size_t vl) {1366  return __riscv_vmadc_vx_u16m4_b4(op1, op2, vl);1367}1368 1369// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vmadc_vvm_u16m8_b21370// CHECK-RV64-SAME: (<vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1371// CHECK-RV64-NEXT:  entry:1372// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmadc.carry.in.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[OP1]], <vscale x 32 x i16> [[OP2]], <vscale x 32 x i1> [[CARRYIN]], i64 [[VL]])1373// CHECK-RV64-NEXT:    ret <vscale x 32 x i1> [[TMP0]]1374//1375vbool2_t test_vmadc_vvm_u16m8_b2(vuint16m8_t op1, vuint16m8_t op2, vbool2_t carryin, size_t vl) {1376  return __riscv_vmadc_vvm_u16m8_b2(op1, op2, carryin, vl);1377}1378 1379// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vmadc_vxm_u16m8_b21380// CHECK-RV64-SAME: (<vscale x 32 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], <vscale x 32 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1381// CHECK-RV64-NEXT:  entry:1382// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmadc.carry.in.nxv32i16.i16.i64(<vscale x 32 x i16> [[OP1]], i16 [[OP2]], <vscale x 32 x i1> [[CARRYIN]], i64 [[VL]])1383// CHECK-RV64-NEXT:    ret <vscale x 32 x i1> [[TMP0]]1384//1385vbool2_t test_vmadc_vxm_u16m8_b2(vuint16m8_t op1, uint16_t op2, vbool2_t carryin, size_t vl) {1386  return __riscv_vmadc_vxm_u16m8_b2(op1, op2, carryin, vl);1387}1388 1389// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vmadc_vv_u16m8_b21390// CHECK-RV64-SAME: (<vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1391// CHECK-RV64-NEXT:  entry:1392// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmadc.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[OP1]], <vscale x 32 x i16> [[OP2]], i64 [[VL]])1393// CHECK-RV64-NEXT:    ret <vscale x 32 x i1> [[TMP0]]1394//1395vbool2_t test_vmadc_vv_u16m8_b2(vuint16m8_t op1, vuint16m8_t op2, size_t vl) {1396  return __riscv_vmadc_vv_u16m8_b2(op1, op2, vl);1397}1398 1399// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vmadc_vx_u16m8_b21400// CHECK-RV64-SAME: (<vscale x 32 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1401// CHECK-RV64-NEXT:  entry:1402// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmadc.nxv32i16.i16.i64(<vscale x 32 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])1403// CHECK-RV64-NEXT:    ret <vscale x 32 x i1> [[TMP0]]1404//1405vbool2_t test_vmadc_vx_u16m8_b2(vuint16m8_t op1, uint16_t op2, size_t vl) {1406  return __riscv_vmadc_vx_u16m8_b2(op1, op2, vl);1407}1408 1409// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmadc_vvm_u32mf2_b641410// CHECK-RV64-SAME: (<vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1411// CHECK-RV64-NEXT:  entry:1412// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[OP1]], <vscale x 1 x i32> [[OP2]], <vscale x 1 x i1> [[CARRYIN]], i64 [[VL]])1413// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]1414//1415vbool64_t test_vmadc_vvm_u32mf2_b64(vuint32mf2_t op1, vuint32mf2_t op2, vbool64_t carryin, size_t vl) {1416  return __riscv_vmadc_vvm_u32mf2_b64(op1, op2, carryin, vl);1417}1418 1419// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmadc_vxm_u32mf2_b641420// CHECK-RV64-SAME: (<vscale x 1 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], <vscale x 1 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1421// CHECK-RV64-NEXT:  entry:1422// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i32.i32.i64(<vscale x 1 x i32> [[OP1]], i32 [[OP2]], <vscale x 1 x i1> [[CARRYIN]], i64 [[VL]])1423// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]1424//1425vbool64_t test_vmadc_vxm_u32mf2_b64(vuint32mf2_t op1, uint32_t op2, vbool64_t carryin, size_t vl) {1426  return __riscv_vmadc_vxm_u32mf2_b64(op1, op2, carryin, vl);1427}1428 1429// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmadc_vv_u32mf2_b641430// CHECK-RV64-SAME: (<vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1431// CHECK-RV64-NEXT:  entry:1432// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[OP1]], <vscale x 1 x i32> [[OP2]], i64 [[VL]])1433// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]1434//1435vbool64_t test_vmadc_vv_u32mf2_b64(vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {1436  return __riscv_vmadc_vv_u32mf2_b64(op1, op2, vl);1437}1438 1439// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmadc_vx_u32mf2_b641440// CHECK-RV64-SAME: (<vscale x 1 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1441// CHECK-RV64-NEXT:  entry:1442// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i32.i32.i64(<vscale x 1 x i32> [[OP1]], i32 [[OP2]], i64 [[VL]])1443// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]1444//1445vbool64_t test_vmadc_vx_u32mf2_b64(vuint32mf2_t op1, uint32_t op2, size_t vl) {1446  return __riscv_vmadc_vx_u32mf2_b64(op1, op2, vl);1447}1448 1449// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmadc_vvm_u32m1_b321450// CHECK-RV64-SAME: (<vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1451// CHECK-RV64-NEXT:  entry:1452// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[OP1]], <vscale x 2 x i32> [[OP2]], <vscale x 2 x i1> [[CARRYIN]], i64 [[VL]])1453// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]1454//1455vbool32_t test_vmadc_vvm_u32m1_b32(vuint32m1_t op1, vuint32m1_t op2, vbool32_t carryin, size_t vl) {1456  return __riscv_vmadc_vvm_u32m1_b32(op1, op2, carryin, vl);1457}1458 1459// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmadc_vxm_u32m1_b321460// CHECK-RV64-SAME: (<vscale x 2 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], <vscale x 2 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1461// CHECK-RV64-NEXT:  entry:1462// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i32.i32.i64(<vscale x 2 x i32> [[OP1]], i32 [[OP2]], <vscale x 2 x i1> [[CARRYIN]], i64 [[VL]])1463// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]1464//1465vbool32_t test_vmadc_vxm_u32m1_b32(vuint32m1_t op1, uint32_t op2, vbool32_t carryin, size_t vl) {1466  return __riscv_vmadc_vxm_u32m1_b32(op1, op2, carryin, vl);1467}1468 1469// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmadc_vv_u32m1_b321470// CHECK-RV64-SAME: (<vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1471// CHECK-RV64-NEXT:  entry:1472// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[OP1]], <vscale x 2 x i32> [[OP2]], i64 [[VL]])1473// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]1474//1475vbool32_t test_vmadc_vv_u32m1_b32(vuint32m1_t op1, vuint32m1_t op2, size_t vl) {1476  return __riscv_vmadc_vv_u32m1_b32(op1, op2, vl);1477}1478 1479// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmadc_vx_u32m1_b321480// CHECK-RV64-SAME: (<vscale x 2 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1481// CHECK-RV64-NEXT:  entry:1482// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i32.i32.i64(<vscale x 2 x i32> [[OP1]], i32 [[OP2]], i64 [[VL]])1483// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]1484//1485vbool32_t test_vmadc_vx_u32m1_b32(vuint32m1_t op1, uint32_t op2, size_t vl) {1486  return __riscv_vmadc_vx_u32m1_b32(op1, op2, vl);1487}1488 1489// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmadc_vvm_u32m2_b161490// CHECK-RV64-SAME: (<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1491// CHECK-RV64-NEXT:  entry:1492// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[OP1]], <vscale x 4 x i32> [[OP2]], <vscale x 4 x i1> [[CARRYIN]], i64 [[VL]])1493// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]1494//1495vbool16_t test_vmadc_vvm_u32m2_b16(vuint32m2_t op1, vuint32m2_t op2, vbool16_t carryin, size_t vl) {1496  return __riscv_vmadc_vvm_u32m2_b16(op1, op2, carryin, vl);1497}1498 1499// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmadc_vxm_u32m2_b161500// CHECK-RV64-SAME: (<vscale x 4 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], <vscale x 4 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1501// CHECK-RV64-NEXT:  entry:1502// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i32.i32.i64(<vscale x 4 x i32> [[OP1]], i32 [[OP2]], <vscale x 4 x i1> [[CARRYIN]], i64 [[VL]])1503// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]1504//1505vbool16_t test_vmadc_vxm_u32m2_b16(vuint32m2_t op1, uint32_t op2, vbool16_t carryin, size_t vl) {1506  return __riscv_vmadc_vxm_u32m2_b16(op1, op2, carryin, vl);1507}1508 1509// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmadc_vv_u32m2_b161510// CHECK-RV64-SAME: (<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1511// CHECK-RV64-NEXT:  entry:1512// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmadc.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[OP1]], <vscale x 4 x i32> [[OP2]], i64 [[VL]])1513// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]1514//1515vbool16_t test_vmadc_vv_u32m2_b16(vuint32m2_t op1, vuint32m2_t op2, size_t vl) {1516  return __riscv_vmadc_vv_u32m2_b16(op1, op2, vl);1517}1518 1519// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmadc_vx_u32m2_b161520// CHECK-RV64-SAME: (<vscale x 4 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1521// CHECK-RV64-NEXT:  entry:1522// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmadc.nxv4i32.i32.i64(<vscale x 4 x i32> [[OP1]], i32 [[OP2]], i64 [[VL]])1523// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]1524//1525vbool16_t test_vmadc_vx_u32m2_b16(vuint32m2_t op1, uint32_t op2, size_t vl) {1526  return __riscv_vmadc_vx_u32m2_b16(op1, op2, vl);1527}1528 1529// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmadc_vvm_u32m4_b81530// CHECK-RV64-SAME: (<vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1531// CHECK-RV64-NEXT:  entry:1532// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmadc.carry.in.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[OP1]], <vscale x 8 x i32> [[OP2]], <vscale x 8 x i1> [[CARRYIN]], i64 [[VL]])1533// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]1534//1535vbool8_t test_vmadc_vvm_u32m4_b8(vuint32m4_t op1, vuint32m4_t op2, vbool8_t carryin, size_t vl) {1536  return __riscv_vmadc_vvm_u32m4_b8(op1, op2, carryin, vl);1537}1538 1539// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmadc_vxm_u32m4_b81540// CHECK-RV64-SAME: (<vscale x 8 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], <vscale x 8 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1541// CHECK-RV64-NEXT:  entry:1542// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmadc.carry.in.nxv8i32.i32.i64(<vscale x 8 x i32> [[OP1]], i32 [[OP2]], <vscale x 8 x i1> [[CARRYIN]], i64 [[VL]])1543// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]1544//1545vbool8_t test_vmadc_vxm_u32m4_b8(vuint32m4_t op1, uint32_t op2, vbool8_t carryin, size_t vl) {1546  return __riscv_vmadc_vxm_u32m4_b8(op1, op2, carryin, vl);1547}1548 1549// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmadc_vv_u32m4_b81550// CHECK-RV64-SAME: (<vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1551// CHECK-RV64-NEXT:  entry:1552// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmadc.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[OP1]], <vscale x 8 x i32> [[OP2]], i64 [[VL]])1553// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]1554//1555vbool8_t test_vmadc_vv_u32m4_b8(vuint32m4_t op1, vuint32m4_t op2, size_t vl) {1556  return __riscv_vmadc_vv_u32m4_b8(op1, op2, vl);1557}1558 1559// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmadc_vx_u32m4_b81560// CHECK-RV64-SAME: (<vscale x 8 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1561// CHECK-RV64-NEXT:  entry:1562// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmadc.nxv8i32.i32.i64(<vscale x 8 x i32> [[OP1]], i32 [[OP2]], i64 [[VL]])1563// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]1564//1565vbool8_t test_vmadc_vx_u32m4_b8(vuint32m4_t op1, uint32_t op2, size_t vl) {1566  return __riscv_vmadc_vx_u32m4_b8(op1, op2, vl);1567}1568 1569// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmadc_vvm_u32m8_b41570// CHECK-RV64-SAME: (<vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1571// CHECK-RV64-NEXT:  entry:1572// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmadc.carry.in.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[OP1]], <vscale x 16 x i32> [[OP2]], <vscale x 16 x i1> [[CARRYIN]], i64 [[VL]])1573// CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP0]]1574//1575vbool4_t test_vmadc_vvm_u32m8_b4(vuint32m8_t op1, vuint32m8_t op2, vbool4_t carryin, size_t vl) {1576  return __riscv_vmadc_vvm_u32m8_b4(op1, op2, carryin, vl);1577}1578 1579// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmadc_vxm_u32m8_b41580// CHECK-RV64-SAME: (<vscale x 16 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], <vscale x 16 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1581// CHECK-RV64-NEXT:  entry:1582// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmadc.carry.in.nxv16i32.i32.i64(<vscale x 16 x i32> [[OP1]], i32 [[OP2]], <vscale x 16 x i1> [[CARRYIN]], i64 [[VL]])1583// CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP0]]1584//1585vbool4_t test_vmadc_vxm_u32m8_b4(vuint32m8_t op1, uint32_t op2, vbool4_t carryin, size_t vl) {1586  return __riscv_vmadc_vxm_u32m8_b4(op1, op2, carryin, vl);1587}1588 1589// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmadc_vv_u32m8_b41590// CHECK-RV64-SAME: (<vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1591// CHECK-RV64-NEXT:  entry:1592// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmadc.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[OP1]], <vscale x 16 x i32> [[OP2]], i64 [[VL]])1593// CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP0]]1594//1595vbool4_t test_vmadc_vv_u32m8_b4(vuint32m8_t op1, vuint32m8_t op2, size_t vl) {1596  return __riscv_vmadc_vv_u32m8_b4(op1, op2, vl);1597}1598 1599// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmadc_vx_u32m8_b41600// CHECK-RV64-SAME: (<vscale x 16 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1601// CHECK-RV64-NEXT:  entry:1602// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmadc.nxv16i32.i32.i64(<vscale x 16 x i32> [[OP1]], i32 [[OP2]], i64 [[VL]])1603// CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP0]]1604//1605vbool4_t test_vmadc_vx_u32m8_b4(vuint32m8_t op1, uint32_t op2, size_t vl) {1606  return __riscv_vmadc_vx_u32m8_b4(op1, op2, vl);1607}1608 1609// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmadc_vvm_u64m1_b641610// CHECK-RV64-SAME: (<vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1611// CHECK-RV64-NEXT:  entry:1612// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[OP1]], <vscale x 1 x i64> [[OP2]], <vscale x 1 x i1> [[CARRYIN]], i64 [[VL]])1613// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]1614//1615vbool64_t test_vmadc_vvm_u64m1_b64(vuint64m1_t op1, vuint64m1_t op2, vbool64_t carryin, size_t vl) {1616  return __riscv_vmadc_vvm_u64m1_b64(op1, op2, carryin, vl);1617}1618 1619// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmadc_vxm_u64m1_b641620// CHECK-RV64-SAME: (<vscale x 1 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], <vscale x 1 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1621// CHECK-RV64-NEXT:  entry:1622// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i64.i64.i64(<vscale x 1 x i64> [[OP1]], i64 [[OP2]], <vscale x 1 x i1> [[CARRYIN]], i64 [[VL]])1623// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]1624//1625vbool64_t test_vmadc_vxm_u64m1_b64(vuint64m1_t op1, uint64_t op2, vbool64_t carryin, size_t vl) {1626  return __riscv_vmadc_vxm_u64m1_b64(op1, op2, carryin, vl);1627}1628 1629// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmadc_vv_u64m1_b641630// CHECK-RV64-SAME: (<vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1631// CHECK-RV64-NEXT:  entry:1632// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[OP1]], <vscale x 1 x i64> [[OP2]], i64 [[VL]])1633// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]1634//1635vbool64_t test_vmadc_vv_u64m1_b64(vuint64m1_t op1, vuint64m1_t op2, size_t vl) {1636  return __riscv_vmadc_vv_u64m1_b64(op1, op2, vl);1637}1638 1639// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmadc_vx_u64m1_b641640// CHECK-RV64-SAME: (<vscale x 1 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1641// CHECK-RV64-NEXT:  entry:1642// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i64.i64.i64(<vscale x 1 x i64> [[OP1]], i64 [[OP2]], i64 [[VL]])1643// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]1644//1645vbool64_t test_vmadc_vx_u64m1_b64(vuint64m1_t op1, uint64_t op2, size_t vl) {1646  return __riscv_vmadc_vx_u64m1_b64(op1, op2, vl);1647}1648 1649// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmadc_vvm_u64m2_b321650// CHECK-RV64-SAME: (<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1651// CHECK-RV64-NEXT:  entry:1652// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[OP1]], <vscale x 2 x i64> [[OP2]], <vscale x 2 x i1> [[CARRYIN]], i64 [[VL]])1653// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]1654//1655vbool32_t test_vmadc_vvm_u64m2_b32(vuint64m2_t op1, vuint64m2_t op2, vbool32_t carryin, size_t vl) {1656  return __riscv_vmadc_vvm_u64m2_b32(op1, op2, carryin, vl);1657}1658 1659// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmadc_vxm_u64m2_b321660// CHECK-RV64-SAME: (<vscale x 2 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], <vscale x 2 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1661// CHECK-RV64-NEXT:  entry:1662// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i64.i64.i64(<vscale x 2 x i64> [[OP1]], i64 [[OP2]], <vscale x 2 x i1> [[CARRYIN]], i64 [[VL]])1663// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]1664//1665vbool32_t test_vmadc_vxm_u64m2_b32(vuint64m2_t op1, uint64_t op2, vbool32_t carryin, size_t vl) {1666  return __riscv_vmadc_vxm_u64m2_b32(op1, op2, carryin, vl);1667}1668 1669// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmadc_vv_u64m2_b321670// CHECK-RV64-SAME: (<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1671// CHECK-RV64-NEXT:  entry:1672// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[OP1]], <vscale x 2 x i64> [[OP2]], i64 [[VL]])1673// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]1674//1675vbool32_t test_vmadc_vv_u64m2_b32(vuint64m2_t op1, vuint64m2_t op2, size_t vl) {1676  return __riscv_vmadc_vv_u64m2_b32(op1, op2, vl);1677}1678 1679// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmadc_vx_u64m2_b321680// CHECK-RV64-SAME: (<vscale x 2 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1681// CHECK-RV64-NEXT:  entry:1682// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i64.i64.i64(<vscale x 2 x i64> [[OP1]], i64 [[OP2]], i64 [[VL]])1683// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]1684//1685vbool32_t test_vmadc_vx_u64m2_b32(vuint64m2_t op1, uint64_t op2, size_t vl) {1686  return __riscv_vmadc_vx_u64m2_b32(op1, op2, vl);1687}1688 1689// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmadc_vvm_u64m4_b161690// CHECK-RV64-SAME: (<vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1691// CHECK-RV64-NEXT:  entry:1692// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[OP1]], <vscale x 4 x i64> [[OP2]], <vscale x 4 x i1> [[CARRYIN]], i64 [[VL]])1693// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]1694//1695vbool16_t test_vmadc_vvm_u64m4_b16(vuint64m4_t op1, vuint64m4_t op2, vbool16_t carryin, size_t vl) {1696  return __riscv_vmadc_vvm_u64m4_b16(op1, op2, carryin, vl);1697}1698 1699// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmadc_vxm_u64m4_b161700// CHECK-RV64-SAME: (<vscale x 4 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], <vscale x 4 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1701// CHECK-RV64-NEXT:  entry:1702// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i64.i64.i64(<vscale x 4 x i64> [[OP1]], i64 [[OP2]], <vscale x 4 x i1> [[CARRYIN]], i64 [[VL]])1703// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]1704//1705vbool16_t test_vmadc_vxm_u64m4_b16(vuint64m4_t op1, uint64_t op2, vbool16_t carryin, size_t vl) {1706  return __riscv_vmadc_vxm_u64m4_b16(op1, op2, carryin, vl);1707}1708 1709// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmadc_vv_u64m4_b161710// CHECK-RV64-SAME: (<vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1711// CHECK-RV64-NEXT:  entry:1712// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmadc.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[OP1]], <vscale x 4 x i64> [[OP2]], i64 [[VL]])1713// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]1714//1715vbool16_t test_vmadc_vv_u64m4_b16(vuint64m4_t op1, vuint64m4_t op2, size_t vl) {1716  return __riscv_vmadc_vv_u64m4_b16(op1, op2, vl);1717}1718 1719// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmadc_vx_u64m4_b161720// CHECK-RV64-SAME: (<vscale x 4 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1721// CHECK-RV64-NEXT:  entry:1722// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmadc.nxv4i64.i64.i64(<vscale x 4 x i64> [[OP1]], i64 [[OP2]], i64 [[VL]])1723// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]1724//1725vbool16_t test_vmadc_vx_u64m4_b16(vuint64m4_t op1, uint64_t op2, size_t vl) {1726  return __riscv_vmadc_vx_u64m4_b16(op1, op2, vl);1727}1728 1729// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmadc_vvm_u64m8_b81730// CHECK-RV64-SAME: (<vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1731// CHECK-RV64-NEXT:  entry:1732// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmadc.carry.in.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[OP1]], <vscale x 8 x i64> [[OP2]], <vscale x 8 x i1> [[CARRYIN]], i64 [[VL]])1733// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]1734//1735vbool8_t test_vmadc_vvm_u64m8_b8(vuint64m8_t op1, vuint64m8_t op2, vbool8_t carryin, size_t vl) {1736  return __riscv_vmadc_vvm_u64m8_b8(op1, op2, carryin, vl);1737}1738 1739// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmadc_vxm_u64m8_b81740// CHECK-RV64-SAME: (<vscale x 8 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], <vscale x 8 x i1> [[CARRYIN:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1741// CHECK-RV64-NEXT:  entry:1742// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmadc.carry.in.nxv8i64.i64.i64(<vscale x 8 x i64> [[OP1]], i64 [[OP2]], <vscale x 8 x i1> [[CARRYIN]], i64 [[VL]])1743// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]1744//1745vbool8_t test_vmadc_vxm_u64m8_b8(vuint64m8_t op1, uint64_t op2, vbool8_t carryin, size_t vl) {1746  return __riscv_vmadc_vxm_u64m8_b8(op1, op2, carryin, vl);1747}1748 1749// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmadc_vv_u64m8_b81750// CHECK-RV64-SAME: (<vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1751// CHECK-RV64-NEXT:  entry:1752// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmadc.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[OP1]], <vscale x 8 x i64> [[OP2]], i64 [[VL]])1753// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]1754//1755vbool8_t test_vmadc_vv_u64m8_b8(vuint64m8_t op1, vuint64m8_t op2, size_t vl) {1756  return __riscv_vmadc_vv_u64m8_b8(op1, op2, vl);1757}1758 1759// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmadc_vx_u64m8_b81760// CHECK-RV64-SAME: (<vscale x 8 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1761// CHECK-RV64-NEXT:  entry:1762// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmadc.nxv8i64.i64.i64(<vscale x 8 x i64> [[OP1]], i64 [[OP2]], i64 [[VL]])1763// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]1764//1765vbool8_t test_vmadc_vx_u64m8_b8(vuint64m8_t op1, uint64_t op2, size_t vl) {1766  return __riscv_vmadc_vx_u64m8_b8(op1, op2, vl);1767}1768 1769