890 lines · c
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 22// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \4// RUN: -target-feature +zvfh -disable-O0-optnone \5// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \6// RUN: FileCheck --check-prefix=CHECK-RV64 %s7 8#include <riscv_vector.h>9 10// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmsgeu_vv_u8mf8_b6411// CHECK-RV64-SAME: (<vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {12// CHECK-RV64-NEXT: entry:13// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1]], <vscale x 1 x i8> [[OP2]], i64 [[VL]])14// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]15//16vbool64_t test_vmsgeu_vv_u8mf8_b64(vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) {17 return __riscv_vmsgeu_vv_u8mf8_b64(op1, op2, vl);18}19 20// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmsgeu_vx_u8mf8_b6421// CHECK-RV64-SAME: (<vscale x 1 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {22// CHECK-RV64-NEXT: entry:23// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.i8.i64(<vscale x 1 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])24// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]25//26vbool64_t test_vmsgeu_vx_u8mf8_b64(vuint8mf8_t op1, uint8_t op2, size_t vl) {27 return __riscv_vmsgeu_vx_u8mf8_b64(op1, op2, vl);28}29 30// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmsgeu_vv_u8mf4_b3231// CHECK-RV64-SAME: (<vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {32// CHECK-RV64-NEXT: entry:33// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[OP1]], <vscale x 2 x i8> [[OP2]], i64 [[VL]])34// CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]35//36vbool32_t test_vmsgeu_vv_u8mf4_b32(vuint8mf4_t op1, vuint8mf4_t op2, size_t vl) {37 return __riscv_vmsgeu_vv_u8mf4_b32(op1, op2, vl);38}39 40// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmsgeu_vx_u8mf4_b3241// CHECK-RV64-SAME: (<vscale x 2 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {42// CHECK-RV64-NEXT: entry:43// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.i8.i64(<vscale x 2 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])44// CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]45//46vbool32_t test_vmsgeu_vx_u8mf4_b32(vuint8mf4_t op1, uint8_t op2, size_t vl) {47 return __riscv_vmsgeu_vx_u8mf4_b32(op1, op2, vl);48}49 50// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmsgeu_vv_u8mf2_b1651// CHECK-RV64-SAME: (<vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {52// CHECK-RV64-NEXT: entry:53// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[OP1]], <vscale x 4 x i8> [[OP2]], i64 [[VL]])54// CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]55//56vbool16_t test_vmsgeu_vv_u8mf2_b16(vuint8mf2_t op1, vuint8mf2_t op2, size_t vl) {57 return __riscv_vmsgeu_vv_u8mf2_b16(op1, op2, vl);58}59 60// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmsgeu_vx_u8mf2_b1661// CHECK-RV64-SAME: (<vscale x 4 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {62// CHECK-RV64-NEXT: entry:63// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.i8.i64(<vscale x 4 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])64// CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]65//66vbool16_t test_vmsgeu_vx_u8mf2_b16(vuint8mf2_t op1, uint8_t op2, size_t vl) {67 return __riscv_vmsgeu_vx_u8mf2_b16(op1, op2, vl);68}69 70// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmsgeu_vv_u8m1_b871// CHECK-RV64-SAME: (<vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {72// CHECK-RV64-NEXT: entry:73// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[OP1]], <vscale x 8 x i8> [[OP2]], i64 [[VL]])74// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]75//76vbool8_t test_vmsgeu_vv_u8m1_b8(vuint8m1_t op1, vuint8m1_t op2, size_t vl) {77 return __riscv_vmsgeu_vv_u8m1_b8(op1, op2, vl);78}79 80// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmsgeu_vx_u8m1_b881// CHECK-RV64-SAME: (<vscale x 8 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {82// CHECK-RV64-NEXT: entry:83// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.i8.i64(<vscale x 8 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])84// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]85//86vbool8_t test_vmsgeu_vx_u8m1_b8(vuint8m1_t op1, uint8_t op2, size_t vl) {87 return __riscv_vmsgeu_vx_u8m1_b8(op1, op2, vl);88}89 90// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmsgeu_vv_u8m2_b491// CHECK-RV64-SAME: (<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {92// CHECK-RV64-NEXT: entry:93// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[OP1]], <vscale x 16 x i8> [[OP2]], i64 [[VL]])94// CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]95//96vbool4_t test_vmsgeu_vv_u8m2_b4(vuint8m2_t op1, vuint8m2_t op2, size_t vl) {97 return __riscv_vmsgeu_vv_u8m2_b4(op1, op2, vl);98}99 100// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmsgeu_vx_u8m2_b4101// CHECK-RV64-SAME: (<vscale x 16 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {102// CHECK-RV64-NEXT: entry:103// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.i8.i64(<vscale x 16 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])104// CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]105//106vbool4_t test_vmsgeu_vx_u8m2_b4(vuint8m2_t op1, uint8_t op2, size_t vl) {107 return __riscv_vmsgeu_vx_u8m2_b4(op1, op2, vl);108}109 110// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vmsgeu_vv_u8m4_b2111// CHECK-RV64-SAME: (<vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {112// CHECK-RV64-NEXT: entry:113// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[OP1]], <vscale x 32 x i8> [[OP2]], i64 [[VL]])114// CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]115//116vbool2_t test_vmsgeu_vv_u8m4_b2(vuint8m4_t op1, vuint8m4_t op2, size_t vl) {117 return __riscv_vmsgeu_vv_u8m4_b2(op1, op2, vl);118}119 120// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vmsgeu_vx_u8m4_b2121// CHECK-RV64-SAME: (<vscale x 32 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {122// CHECK-RV64-NEXT: entry:123// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.nxv32i8.i8.i64(<vscale x 32 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])124// CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]125//126vbool2_t test_vmsgeu_vx_u8m4_b2(vuint8m4_t op1, uint8_t op2, size_t vl) {127 return __riscv_vmsgeu_vx_u8m4_b2(op1, op2, vl);128}129 130// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i1> @test_vmsgeu_vv_u8m8_b1131// CHECK-RV64-SAME: (<vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {132// CHECK-RV64-NEXT: entry:133// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmsgeu.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[OP1]], <vscale x 64 x i8> [[OP2]], i64 [[VL]])134// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]135//136vbool1_t test_vmsgeu_vv_u8m8_b1(vuint8m8_t op1, vuint8m8_t op2, size_t vl) {137 return __riscv_vmsgeu_vv_u8m8_b1(op1, op2, vl);138}139 140// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i1> @test_vmsgeu_vx_u8m8_b1141// CHECK-RV64-SAME: (<vscale x 64 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {142// CHECK-RV64-NEXT: entry:143// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmsgeu.nxv64i8.i8.i64(<vscale x 64 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])144// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]145//146vbool1_t test_vmsgeu_vx_u8m8_b1(vuint8m8_t op1, uint8_t op2, size_t vl) {147 return __riscv_vmsgeu_vx_u8m8_b1(op1, op2, vl);148}149 150// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmsgeu_vv_u16mf4_b64151// CHECK-RV64-SAME: (<vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {152// CHECK-RV64-NEXT: entry:153// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[OP1]], <vscale x 1 x i16> [[OP2]], i64 [[VL]])154// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]155//156vbool64_t test_vmsgeu_vv_u16mf4_b64(vuint16mf4_t op1, vuint16mf4_t op2, size_t vl) {157 return __riscv_vmsgeu_vv_u16mf4_b64(op1, op2, vl);158}159 160// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmsgeu_vx_u16mf4_b64161// CHECK-RV64-SAME: (<vscale x 1 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {162// CHECK-RV64-NEXT: entry:163// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i16.i16.i64(<vscale x 1 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])164// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]165//166vbool64_t test_vmsgeu_vx_u16mf4_b64(vuint16mf4_t op1, uint16_t op2, size_t vl) {167 return __riscv_vmsgeu_vx_u16mf4_b64(op1, op2, vl);168}169 170// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmsgeu_vv_u16mf2_b32171// CHECK-RV64-SAME: (<vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {172// CHECK-RV64-NEXT: entry:173// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[OP1]], <vscale x 2 x i16> [[OP2]], i64 [[VL]])174// CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]175//176vbool32_t test_vmsgeu_vv_u16mf2_b32(vuint16mf2_t op1, vuint16mf2_t op2, size_t vl) {177 return __riscv_vmsgeu_vv_u16mf2_b32(op1, op2, vl);178}179 180// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmsgeu_vx_u16mf2_b32181// CHECK-RV64-SAME: (<vscale x 2 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {182// CHECK-RV64-NEXT: entry:183// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i16.i16.i64(<vscale x 2 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])184// CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]185//186vbool32_t test_vmsgeu_vx_u16mf2_b32(vuint16mf2_t op1, uint16_t op2, size_t vl) {187 return __riscv_vmsgeu_vx_u16mf2_b32(op1, op2, vl);188}189 190// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmsgeu_vv_u16m1_b16191// CHECK-RV64-SAME: (<vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {192// CHECK-RV64-NEXT: entry:193// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[OP1]], <vscale x 4 x i16> [[OP2]], i64 [[VL]])194// CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]195//196vbool16_t test_vmsgeu_vv_u16m1_b16(vuint16m1_t op1, vuint16m1_t op2, size_t vl) {197 return __riscv_vmsgeu_vv_u16m1_b16(op1, op2, vl);198}199 200// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmsgeu_vx_u16m1_b16201// CHECK-RV64-SAME: (<vscale x 4 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {202// CHECK-RV64-NEXT: entry:203// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i16.i16.i64(<vscale x 4 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])204// CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]205//206vbool16_t test_vmsgeu_vx_u16m1_b16(vuint16m1_t op1, uint16_t op2, size_t vl) {207 return __riscv_vmsgeu_vx_u16m1_b16(op1, op2, vl);208}209 210// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmsgeu_vv_u16m2_b8211// CHECK-RV64-SAME: (<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {212// CHECK-RV64-NEXT: entry:213// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[OP1]], <vscale x 8 x i16> [[OP2]], i64 [[VL]])214// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]215//216vbool8_t test_vmsgeu_vv_u16m2_b8(vuint16m2_t op1, vuint16m2_t op2, size_t vl) {217 return __riscv_vmsgeu_vv_u16m2_b8(op1, op2, vl);218}219 220// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmsgeu_vx_u16m2_b8221// CHECK-RV64-SAME: (<vscale x 8 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {222// CHECK-RV64-NEXT: entry:223// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i16.i16.i64(<vscale x 8 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])224// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]225//226vbool8_t test_vmsgeu_vx_u16m2_b8(vuint16m2_t op1, uint16_t op2, size_t vl) {227 return __riscv_vmsgeu_vx_u16m2_b8(op1, op2, vl);228}229 230// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmsgeu_vv_u16m4_b4231// CHECK-RV64-SAME: (<vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {232// CHECK-RV64-NEXT: entry:233// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[OP1]], <vscale x 16 x i16> [[OP2]], i64 [[VL]])234// CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]235//236vbool4_t test_vmsgeu_vv_u16m4_b4(vuint16m4_t op1, vuint16m4_t op2, size_t vl) {237 return __riscv_vmsgeu_vv_u16m4_b4(op1, op2, vl);238}239 240// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmsgeu_vx_u16m4_b4241// CHECK-RV64-SAME: (<vscale x 16 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {242// CHECK-RV64-NEXT: entry:243// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i16.i16.i64(<vscale x 16 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])244// CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]245//246vbool4_t test_vmsgeu_vx_u16m4_b4(vuint16m4_t op1, uint16_t op2, size_t vl) {247 return __riscv_vmsgeu_vx_u16m4_b4(op1, op2, vl);248}249 250// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vmsgeu_vv_u16m8_b2251// CHECK-RV64-SAME: (<vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {252// CHECK-RV64-NEXT: entry:253// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[OP1]], <vscale x 32 x i16> [[OP2]], i64 [[VL]])254// CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]255//256vbool2_t test_vmsgeu_vv_u16m8_b2(vuint16m8_t op1, vuint16m8_t op2, size_t vl) {257 return __riscv_vmsgeu_vv_u16m8_b2(op1, op2, vl);258}259 260// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vmsgeu_vx_u16m8_b2261// CHECK-RV64-SAME: (<vscale x 32 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {262// CHECK-RV64-NEXT: entry:263// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.nxv32i16.i16.i64(<vscale x 32 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])264// CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]265//266vbool2_t test_vmsgeu_vx_u16m8_b2(vuint16m8_t op1, uint16_t op2, size_t vl) {267 return __riscv_vmsgeu_vx_u16m8_b2(op1, op2, vl);268}269 270// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmsgeu_vv_u32mf2_b64271// CHECK-RV64-SAME: (<vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {272// CHECK-RV64-NEXT: entry:273// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[OP1]], <vscale x 1 x i32> [[OP2]], i64 [[VL]])274// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]275//276vbool64_t test_vmsgeu_vv_u32mf2_b64(vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {277 return __riscv_vmsgeu_vv_u32mf2_b64(op1, op2, vl);278}279 280// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmsgeu_vx_u32mf2_b64281// CHECK-RV64-SAME: (<vscale x 1 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {282// CHECK-RV64-NEXT: entry:283// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i32.i32.i64(<vscale x 1 x i32> [[OP1]], i32 [[OP2]], i64 [[VL]])284// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]285//286vbool64_t test_vmsgeu_vx_u32mf2_b64(vuint32mf2_t op1, uint32_t op2, size_t vl) {287 return __riscv_vmsgeu_vx_u32mf2_b64(op1, op2, vl);288}289 290// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmsgeu_vv_u32m1_b32291// CHECK-RV64-SAME: (<vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {292// CHECK-RV64-NEXT: entry:293// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[OP1]], <vscale x 2 x i32> [[OP2]], i64 [[VL]])294// CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]295//296vbool32_t test_vmsgeu_vv_u32m1_b32(vuint32m1_t op1, vuint32m1_t op2, size_t vl) {297 return __riscv_vmsgeu_vv_u32m1_b32(op1, op2, vl);298}299 300// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmsgeu_vx_u32m1_b32301// CHECK-RV64-SAME: (<vscale x 2 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {302// CHECK-RV64-NEXT: entry:303// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i32.i32.i64(<vscale x 2 x i32> [[OP1]], i32 [[OP2]], i64 [[VL]])304// CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]305//306vbool32_t test_vmsgeu_vx_u32m1_b32(vuint32m1_t op1, uint32_t op2, size_t vl) {307 return __riscv_vmsgeu_vx_u32m1_b32(op1, op2, vl);308}309 310// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmsgeu_vv_u32m2_b16311// CHECK-RV64-SAME: (<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {312// CHECK-RV64-NEXT: entry:313// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[OP1]], <vscale x 4 x i32> [[OP2]], i64 [[VL]])314// CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]315//316vbool16_t test_vmsgeu_vv_u32m2_b16(vuint32m2_t op1, vuint32m2_t op2, size_t vl) {317 return __riscv_vmsgeu_vv_u32m2_b16(op1, op2, vl);318}319 320// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmsgeu_vx_u32m2_b16321// CHECK-RV64-SAME: (<vscale x 4 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {322// CHECK-RV64-NEXT: entry:323// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i32.i32.i64(<vscale x 4 x i32> [[OP1]], i32 [[OP2]], i64 [[VL]])324// CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]325//326vbool16_t test_vmsgeu_vx_u32m2_b16(vuint32m2_t op1, uint32_t op2, size_t vl) {327 return __riscv_vmsgeu_vx_u32m2_b16(op1, op2, vl);328}329 330// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmsgeu_vv_u32m4_b8331// CHECK-RV64-SAME: (<vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {332// CHECK-RV64-NEXT: entry:333// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[OP1]], <vscale x 8 x i32> [[OP2]], i64 [[VL]])334// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]335//336vbool8_t test_vmsgeu_vv_u32m4_b8(vuint32m4_t op1, vuint32m4_t op2, size_t vl) {337 return __riscv_vmsgeu_vv_u32m4_b8(op1, op2, vl);338}339 340// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmsgeu_vx_u32m4_b8341// CHECK-RV64-SAME: (<vscale x 8 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {342// CHECK-RV64-NEXT: entry:343// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i32.i32.i64(<vscale x 8 x i32> [[OP1]], i32 [[OP2]], i64 [[VL]])344// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]345//346vbool8_t test_vmsgeu_vx_u32m4_b8(vuint32m4_t op1, uint32_t op2, size_t vl) {347 return __riscv_vmsgeu_vx_u32m4_b8(op1, op2, vl);348}349 350// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmsgeu_vv_u32m8_b4351// CHECK-RV64-SAME: (<vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {352// CHECK-RV64-NEXT: entry:353// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[OP1]], <vscale x 16 x i32> [[OP2]], i64 [[VL]])354// CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]355//356vbool4_t test_vmsgeu_vv_u32m8_b4(vuint32m8_t op1, vuint32m8_t op2, size_t vl) {357 return __riscv_vmsgeu_vv_u32m8_b4(op1, op2, vl);358}359 360// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmsgeu_vx_u32m8_b4361// CHECK-RV64-SAME: (<vscale x 16 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {362// CHECK-RV64-NEXT: entry:363// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i32.i32.i64(<vscale x 16 x i32> [[OP1]], i32 [[OP2]], i64 [[VL]])364// CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]365//366vbool4_t test_vmsgeu_vx_u32m8_b4(vuint32m8_t op1, uint32_t op2, size_t vl) {367 return __riscv_vmsgeu_vx_u32m8_b4(op1, op2, vl);368}369 370// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmsgeu_vv_u64m1_b64371// CHECK-RV64-SAME: (<vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {372// CHECK-RV64-NEXT: entry:373// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[OP1]], <vscale x 1 x i64> [[OP2]], i64 [[VL]])374// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]375//376vbool64_t test_vmsgeu_vv_u64m1_b64(vuint64m1_t op1, vuint64m1_t op2, size_t vl) {377 return __riscv_vmsgeu_vv_u64m1_b64(op1, op2, vl);378}379 380// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmsgeu_vx_u64m1_b64381// CHECK-RV64-SAME: (<vscale x 1 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {382// CHECK-RV64-NEXT: entry:383// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i64.i64.i64(<vscale x 1 x i64> [[OP1]], i64 [[OP2]], i64 [[VL]])384// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]385//386vbool64_t test_vmsgeu_vx_u64m1_b64(vuint64m1_t op1, uint64_t op2, size_t vl) {387 return __riscv_vmsgeu_vx_u64m1_b64(op1, op2, vl);388}389 390// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmsgeu_vv_u64m2_b32391// CHECK-RV64-SAME: (<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {392// CHECK-RV64-NEXT: entry:393// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[OP1]], <vscale x 2 x i64> [[OP2]], i64 [[VL]])394// CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]395//396vbool32_t test_vmsgeu_vv_u64m2_b32(vuint64m2_t op1, vuint64m2_t op2, size_t vl) {397 return __riscv_vmsgeu_vv_u64m2_b32(op1, op2, vl);398}399 400// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmsgeu_vx_u64m2_b32401// CHECK-RV64-SAME: (<vscale x 2 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {402// CHECK-RV64-NEXT: entry:403// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i64.i64.i64(<vscale x 2 x i64> [[OP1]], i64 [[OP2]], i64 [[VL]])404// CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]405//406vbool32_t test_vmsgeu_vx_u64m2_b32(vuint64m2_t op1, uint64_t op2, size_t vl) {407 return __riscv_vmsgeu_vx_u64m2_b32(op1, op2, vl);408}409 410// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmsgeu_vv_u64m4_b16411// CHECK-RV64-SAME: (<vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {412// CHECK-RV64-NEXT: entry:413// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[OP1]], <vscale x 4 x i64> [[OP2]], i64 [[VL]])414// CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]415//416vbool16_t test_vmsgeu_vv_u64m4_b16(vuint64m4_t op1, vuint64m4_t op2, size_t vl) {417 return __riscv_vmsgeu_vv_u64m4_b16(op1, op2, vl);418}419 420// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmsgeu_vx_u64m4_b16421// CHECK-RV64-SAME: (<vscale x 4 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {422// CHECK-RV64-NEXT: entry:423// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i64.i64.i64(<vscale x 4 x i64> [[OP1]], i64 [[OP2]], i64 [[VL]])424// CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]425//426vbool16_t test_vmsgeu_vx_u64m4_b16(vuint64m4_t op1, uint64_t op2, size_t vl) {427 return __riscv_vmsgeu_vx_u64m4_b16(op1, op2, vl);428}429 430// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmsgeu_vv_u64m8_b8431// CHECK-RV64-SAME: (<vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {432// CHECK-RV64-NEXT: entry:433// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[OP1]], <vscale x 8 x i64> [[OP2]], i64 [[VL]])434// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]435//436vbool8_t test_vmsgeu_vv_u64m8_b8(vuint64m8_t op1, vuint64m8_t op2, size_t vl) {437 return __riscv_vmsgeu_vv_u64m8_b8(op1, op2, vl);438}439 440// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmsgeu_vx_u64m8_b8441// CHECK-RV64-SAME: (<vscale x 8 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {442// CHECK-RV64-NEXT: entry:443// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i64.i64.i64(<vscale x 8 x i64> [[OP1]], i64 [[OP2]], i64 [[VL]])444// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]445//446vbool8_t test_vmsgeu_vx_u64m8_b8(vuint64m8_t op1, uint64_t op2, size_t vl) {447 return __riscv_vmsgeu_vx_u64m8_b8(op1, op2, vl);448}449 450// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmsgeu_vv_u8mf8_b64_m451// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {452// CHECK-RV64-NEXT: entry:453// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> poison, <vscale x 1 x i8> [[OP1]], <vscale x 1 x i8> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])454// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]455//456vbool64_t test_vmsgeu_vv_u8mf8_b64_m(vbool64_t mask, vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) {457 return __riscv_vmsgeu_vv_u8mf8_b64_m(mask, op1, op2, vl);458}459 460// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmsgeu_vx_u8mf8_b64_m461// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {462// CHECK-RV64-NEXT: entry:463// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8.i64(<vscale x 1 x i1> poison, <vscale x 1 x i8> [[OP1]], i8 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])464// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]465//466vbool64_t test_vmsgeu_vx_u8mf8_b64_m(vbool64_t mask, vuint8mf8_t op1, uint8_t op2, size_t vl) {467 return __riscv_vmsgeu_vx_u8mf8_b64_m(mask, op1, op2, vl);468}469 470// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmsgeu_vv_u8mf4_b32_m471// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {472// CHECK-RV64-NEXT: entry:473// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> poison, <vscale x 2 x i8> [[OP1]], <vscale x 2 x i8> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])474// CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]475//476vbool32_t test_vmsgeu_vv_u8mf4_b32_m(vbool32_t mask, vuint8mf4_t op1, vuint8mf4_t op2, size_t vl) {477 return __riscv_vmsgeu_vv_u8mf4_b32_m(mask, op1, op2, vl);478}479 480// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmsgeu_vx_u8mf4_b32_m481// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {482// CHECK-RV64-NEXT: entry:483// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8.i64(<vscale x 2 x i1> poison, <vscale x 2 x i8> [[OP1]], i8 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])484// CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]485//486vbool32_t test_vmsgeu_vx_u8mf4_b32_m(vbool32_t mask, vuint8mf4_t op1, uint8_t op2, size_t vl) {487 return __riscv_vmsgeu_vx_u8mf4_b32_m(mask, op1, op2, vl);488}489 490// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmsgeu_vv_u8mf2_b16_m491// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {492// CHECK-RV64-NEXT: entry:493// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> poison, <vscale x 4 x i8> [[OP1]], <vscale x 4 x i8> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])494// CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]495//496vbool16_t test_vmsgeu_vv_u8mf2_b16_m(vbool16_t mask, vuint8mf2_t op1, vuint8mf2_t op2, size_t vl) {497 return __riscv_vmsgeu_vv_u8mf2_b16_m(mask, op1, op2, vl);498}499 500// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmsgeu_vx_u8mf2_b16_m501// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {502// CHECK-RV64-NEXT: entry:503// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8.i64(<vscale x 4 x i1> poison, <vscale x 4 x i8> [[OP1]], i8 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])504// CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]505//506vbool16_t test_vmsgeu_vx_u8mf2_b16_m(vbool16_t mask, vuint8mf2_t op1, uint8_t op2, size_t vl) {507 return __riscv_vmsgeu_vx_u8mf2_b16_m(mask, op1, op2, vl);508}509 510// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmsgeu_vv_u8m1_b8_m511// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {512// CHECK-RV64-NEXT: entry:513// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> poison, <vscale x 8 x i8> [[OP1]], <vscale x 8 x i8> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])514// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]515//516vbool8_t test_vmsgeu_vv_u8m1_b8_m(vbool8_t mask, vuint8m1_t op1, vuint8m1_t op2, size_t vl) {517 return __riscv_vmsgeu_vv_u8m1_b8_m(mask, op1, op2, vl);518}519 520// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmsgeu_vx_u8m1_b8_m521// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {522// CHECK-RV64-NEXT: entry:523// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.i8.i64(<vscale x 8 x i1> poison, <vscale x 8 x i8> [[OP1]], i8 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])524// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]525//526vbool8_t test_vmsgeu_vx_u8m1_b8_m(vbool8_t mask, vuint8m1_t op1, uint8_t op2, size_t vl) {527 return __riscv_vmsgeu_vx_u8m1_b8_m(mask, op1, op2, vl);528}529 530// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmsgeu_vv_u8m2_b4_m531// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {532// CHECK-RV64-NEXT: entry:533// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i1> poison, <vscale x 16 x i8> [[OP1]], <vscale x 16 x i8> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])534// CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]535//536vbool4_t test_vmsgeu_vv_u8m2_b4_m(vbool4_t mask, vuint8m2_t op1, vuint8m2_t op2, size_t vl) {537 return __riscv_vmsgeu_vv_u8m2_b4_m(mask, op1, op2, vl);538}539 540// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmsgeu_vx_u8m2_b4_m541// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {542// CHECK-RV64-NEXT: entry:543// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8.i8.i64(<vscale x 16 x i1> poison, <vscale x 16 x i8> [[OP1]], i8 [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])544// CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]545//546vbool4_t test_vmsgeu_vx_u8m2_b4_m(vbool4_t mask, vuint8m2_t op1, uint8_t op2, size_t vl) {547 return __riscv_vmsgeu_vx_u8m2_b4_m(mask, op1, op2, vl);548}549 550// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vmsgeu_vv_u8m4_b2_m551// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {552// CHECK-RV64-NEXT: entry:553// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i1> poison, <vscale x 32 x i8> [[OP1]], <vscale x 32 x i8> [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]])554// CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]555//556vbool2_t test_vmsgeu_vv_u8m4_b2_m(vbool2_t mask, vuint8m4_t op1, vuint8m4_t op2, size_t vl) {557 return __riscv_vmsgeu_vv_u8m4_b2_m(mask, op1, op2, vl);558}559 560// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vmsgeu_vx_u8m4_b2_m561// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {562// CHECK-RV64-NEXT: entry:563// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8.i8.i64(<vscale x 32 x i1> poison, <vscale x 32 x i8> [[OP1]], i8 [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]])564// CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]565//566vbool2_t test_vmsgeu_vx_u8m4_b2_m(vbool2_t mask, vuint8m4_t op1, uint8_t op2, size_t vl) {567 return __riscv_vmsgeu_vx_u8m4_b2_m(mask, op1, op2, vl);568}569 570// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i1> @test_vmsgeu_vv_u8m8_b1_m571// CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {572// CHECK-RV64-NEXT: entry:573// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmsgeu.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i1> poison, <vscale x 64 x i8> [[OP1]], <vscale x 64 x i8> [[OP2]], <vscale x 64 x i1> [[MASK]], i64 [[VL]])574// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]575//576vbool1_t test_vmsgeu_vv_u8m8_b1_m(vbool1_t mask, vuint8m8_t op1, vuint8m8_t op2, size_t vl) {577 return __riscv_vmsgeu_vv_u8m8_b1_m(mask, op1, op2, vl);578}579 580// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i1> @test_vmsgeu_vx_u8m8_b1_m581// CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {582// CHECK-RV64-NEXT: entry:583// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmsgeu.mask.nxv64i8.i8.i64(<vscale x 64 x i1> poison, <vscale x 64 x i8> [[OP1]], i8 [[OP2]], <vscale x 64 x i1> [[MASK]], i64 [[VL]])584// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]585//586vbool1_t test_vmsgeu_vx_u8m8_b1_m(vbool1_t mask, vuint8m8_t op1, uint8_t op2, size_t vl) {587 return __riscv_vmsgeu_vx_u8m8_b1_m(mask, op1, op2, vl);588}589 590// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmsgeu_vv_u16mf4_b64_m591// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {592// CHECK-RV64-NEXT: entry:593// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i1> poison, <vscale x 1 x i16> [[OP1]], <vscale x 1 x i16> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])594// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]595//596vbool64_t test_vmsgeu_vv_u16mf4_b64_m(vbool64_t mask, vuint16mf4_t op1, vuint16mf4_t op2, size_t vl) {597 return __riscv_vmsgeu_vv_u16mf4_b64_m(mask, op1, op2, vl);598}599 600// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmsgeu_vx_u16mf4_b64_m601// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {602// CHECK-RV64-NEXT: entry:603// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16.i16.i64(<vscale x 1 x i1> poison, <vscale x 1 x i16> [[OP1]], i16 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])604// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]605//606vbool64_t test_vmsgeu_vx_u16mf4_b64_m(vbool64_t mask, vuint16mf4_t op1, uint16_t op2, size_t vl) {607 return __riscv_vmsgeu_vx_u16mf4_b64_m(mask, op1, op2, vl);608}609 610// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmsgeu_vv_u16mf2_b32_m611// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {612// CHECK-RV64-NEXT: entry:613// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i1> poison, <vscale x 2 x i16> [[OP1]], <vscale x 2 x i16> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])614// CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]615//616vbool32_t test_vmsgeu_vv_u16mf2_b32_m(vbool32_t mask, vuint16mf2_t op1, vuint16mf2_t op2, size_t vl) {617 return __riscv_vmsgeu_vv_u16mf2_b32_m(mask, op1, op2, vl);618}619 620// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmsgeu_vx_u16mf2_b32_m621// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {622// CHECK-RV64-NEXT: entry:623// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16.i16.i64(<vscale x 2 x i1> poison, <vscale x 2 x i16> [[OP1]], i16 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])624// CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]625//626vbool32_t test_vmsgeu_vx_u16mf2_b32_m(vbool32_t mask, vuint16mf2_t op1, uint16_t op2, size_t vl) {627 return __riscv_vmsgeu_vx_u16mf2_b32_m(mask, op1, op2, vl);628}629 630// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmsgeu_vv_u16m1_b16_m631// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {632// CHECK-RV64-NEXT: entry:633// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i1> poison, <vscale x 4 x i16> [[OP1]], <vscale x 4 x i16> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])634// CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]635//636vbool16_t test_vmsgeu_vv_u16m1_b16_m(vbool16_t mask, vuint16m1_t op1, vuint16m1_t op2, size_t vl) {637 return __riscv_vmsgeu_vv_u16m1_b16_m(mask, op1, op2, vl);638}639 640// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmsgeu_vx_u16m1_b16_m641// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {642// CHECK-RV64-NEXT: entry:643// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16.i16.i64(<vscale x 4 x i1> poison, <vscale x 4 x i16> [[OP1]], i16 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])644// CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]645//646vbool16_t test_vmsgeu_vx_u16m1_b16_m(vbool16_t mask, vuint16m1_t op1, uint16_t op2, size_t vl) {647 return __riscv_vmsgeu_vx_u16m1_b16_m(mask, op1, op2, vl);648}649 650// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmsgeu_vv_u16m2_b8_m651// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {652// CHECK-RV64-NEXT: entry:653// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i1> poison, <vscale x 8 x i16> [[OP1]], <vscale x 8 x i16> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])654// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]655//656vbool8_t test_vmsgeu_vv_u16m2_b8_m(vbool8_t mask, vuint16m2_t op1, vuint16m2_t op2, size_t vl) {657 return __riscv_vmsgeu_vv_u16m2_b8_m(mask, op1, op2, vl);658}659 660// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmsgeu_vx_u16m2_b8_m661// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {662// CHECK-RV64-NEXT: entry:663// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16.i16.i64(<vscale x 8 x i1> poison, <vscale x 8 x i16> [[OP1]], i16 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])664// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]665//666vbool8_t test_vmsgeu_vx_u16m2_b8_m(vbool8_t mask, vuint16m2_t op1, uint16_t op2, size_t vl) {667 return __riscv_vmsgeu_vx_u16m2_b8_m(mask, op1, op2, vl);668}669 670// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmsgeu_vv_u16m4_b4_m671// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {672// CHECK-RV64-NEXT: entry:673// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i1> poison, <vscale x 16 x i16> [[OP1]], <vscale x 16 x i16> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])674// CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]675//676vbool4_t test_vmsgeu_vv_u16m4_b4_m(vbool4_t mask, vuint16m4_t op1, vuint16m4_t op2, size_t vl) {677 return __riscv_vmsgeu_vv_u16m4_b4_m(mask, op1, op2, vl);678}679 680// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmsgeu_vx_u16m4_b4_m681// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {682// CHECK-RV64-NEXT: entry:683// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16.i16.i64(<vscale x 16 x i1> poison, <vscale x 16 x i16> [[OP1]], i16 [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])684// CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]685//686vbool4_t test_vmsgeu_vx_u16m4_b4_m(vbool4_t mask, vuint16m4_t op1, uint16_t op2, size_t vl) {687 return __riscv_vmsgeu_vx_u16m4_b4_m(mask, op1, op2, vl);688}689 690// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vmsgeu_vv_u16m8_b2_m691// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {692// CHECK-RV64-NEXT: entry:693// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i1> poison, <vscale x 32 x i16> [[OP1]], <vscale x 32 x i16> [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]])694// CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]695//696vbool2_t test_vmsgeu_vv_u16m8_b2_m(vbool2_t mask, vuint16m8_t op1, vuint16m8_t op2, size_t vl) {697 return __riscv_vmsgeu_vv_u16m8_b2_m(mask, op1, op2, vl);698}699 700// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vmsgeu_vx_u16m8_b2_m701// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {702// CHECK-RV64-NEXT: entry:703// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i16.i16.i64(<vscale x 32 x i1> poison, <vscale x 32 x i16> [[OP1]], i16 [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]])704// CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]705//706vbool2_t test_vmsgeu_vx_u16m8_b2_m(vbool2_t mask, vuint16m8_t op1, uint16_t op2, size_t vl) {707 return __riscv_vmsgeu_vx_u16m8_b2_m(mask, op1, op2, vl);708}709 710// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmsgeu_vv_u32mf2_b64_m711// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {712// CHECK-RV64-NEXT: entry:713// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> poison, <vscale x 1 x i32> [[OP1]], <vscale x 1 x i32> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])714// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]715//716vbool64_t test_vmsgeu_vv_u32mf2_b64_m(vbool64_t mask, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {717 return __riscv_vmsgeu_vv_u32mf2_b64_m(mask, op1, op2, vl);718}719 720// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmsgeu_vx_u32mf2_b64_m721// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {722// CHECK-RV64-NEXT: entry:723// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32.i32.i64(<vscale x 1 x i1> poison, <vscale x 1 x i32> [[OP1]], i32 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])724// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]725//726vbool64_t test_vmsgeu_vx_u32mf2_b64_m(vbool64_t mask, vuint32mf2_t op1, uint32_t op2, size_t vl) {727 return __riscv_vmsgeu_vx_u32mf2_b64_m(mask, op1, op2, vl);728}729 730// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmsgeu_vv_u32m1_b32_m731// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {732// CHECK-RV64-NEXT: entry:733// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i1> poison, <vscale x 2 x i32> [[OP1]], <vscale x 2 x i32> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])734// CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]735//736vbool32_t test_vmsgeu_vv_u32m1_b32_m(vbool32_t mask, vuint32m1_t op1, vuint32m1_t op2, size_t vl) {737 return __riscv_vmsgeu_vv_u32m1_b32_m(mask, op1, op2, vl);738}739 740// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmsgeu_vx_u32m1_b32_m741// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {742// CHECK-RV64-NEXT: entry:743// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32.i32.i64(<vscale x 2 x i1> poison, <vscale x 2 x i32> [[OP1]], i32 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])744// CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]745//746vbool32_t test_vmsgeu_vx_u32m1_b32_m(vbool32_t mask, vuint32m1_t op1, uint32_t op2, size_t vl) {747 return __riscv_vmsgeu_vx_u32m1_b32_m(mask, op1, op2, vl);748}749 750// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmsgeu_vv_u32m2_b16_m751// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {752// CHECK-RV64-NEXT: entry:753// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i1> poison, <vscale x 4 x i32> [[OP1]], <vscale x 4 x i32> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])754// CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]755//756vbool16_t test_vmsgeu_vv_u32m2_b16_m(vbool16_t mask, vuint32m2_t op1, vuint32m2_t op2, size_t vl) {757 return __riscv_vmsgeu_vv_u32m2_b16_m(mask, op1, op2, vl);758}759 760// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmsgeu_vx_u32m2_b16_m761// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {762// CHECK-RV64-NEXT: entry:763// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32.i32.i64(<vscale x 4 x i1> poison, <vscale x 4 x i32> [[OP1]], i32 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])764// CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]765//766vbool16_t test_vmsgeu_vx_u32m2_b16_m(vbool16_t mask, vuint32m2_t op1, uint32_t op2, size_t vl) {767 return __riscv_vmsgeu_vx_u32m2_b16_m(mask, op1, op2, vl);768}769 770// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmsgeu_vv_u32m4_b8_m771// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {772// CHECK-RV64-NEXT: entry:773// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i1> poison, <vscale x 8 x i32> [[OP1]], <vscale x 8 x i32> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])774// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]775//776vbool8_t test_vmsgeu_vv_u32m4_b8_m(vbool8_t mask, vuint32m4_t op1, vuint32m4_t op2, size_t vl) {777 return __riscv_vmsgeu_vv_u32m4_b8_m(mask, op1, op2, vl);778}779 780// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmsgeu_vx_u32m4_b8_m781// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {782// CHECK-RV64-NEXT: entry:783// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32.i32.i64(<vscale x 8 x i1> poison, <vscale x 8 x i32> [[OP1]], i32 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])784// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]785//786vbool8_t test_vmsgeu_vx_u32m4_b8_m(vbool8_t mask, vuint32m4_t op1, uint32_t op2, size_t vl) {787 return __riscv_vmsgeu_vx_u32m4_b8_m(mask, op1, op2, vl);788}789 790// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmsgeu_vv_u32m8_b4_m791// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {792// CHECK-RV64-NEXT: entry:793// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i1> poison, <vscale x 16 x i32> [[OP1]], <vscale x 16 x i32> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])794// CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]795//796vbool4_t test_vmsgeu_vv_u32m8_b4_m(vbool4_t mask, vuint32m8_t op1, vuint32m8_t op2, size_t vl) {797 return __riscv_vmsgeu_vv_u32m8_b4_m(mask, op1, op2, vl);798}799 800// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmsgeu_vx_u32m8_b4_m801// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {802// CHECK-RV64-NEXT: entry:803// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i32.i32.i64(<vscale x 16 x i1> poison, <vscale x 16 x i32> [[OP1]], i32 [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])804// CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]805//806vbool4_t test_vmsgeu_vx_u32m8_b4_m(vbool4_t mask, vuint32m8_t op1, uint32_t op2, size_t vl) {807 return __riscv_vmsgeu_vx_u32m8_b4_m(mask, op1, op2, vl);808}809 810// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmsgeu_vv_u64m1_b64_m811// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {812// CHECK-RV64-NEXT: entry:813// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i1> poison, <vscale x 1 x i64> [[OP1]], <vscale x 1 x i64> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])814// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]815//816vbool64_t test_vmsgeu_vv_u64m1_b64_m(vbool64_t mask, vuint64m1_t op1, vuint64m1_t op2, size_t vl) {817 return __riscv_vmsgeu_vv_u64m1_b64_m(mask, op1, op2, vl);818}819 820// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmsgeu_vx_u64m1_b64_m821// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {822// CHECK-RV64-NEXT: entry:823// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64.i64.i64(<vscale x 1 x i1> poison, <vscale x 1 x i64> [[OP1]], i64 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])824// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]825//826vbool64_t test_vmsgeu_vx_u64m1_b64_m(vbool64_t mask, vuint64m1_t op1, uint64_t op2, size_t vl) {827 return __riscv_vmsgeu_vx_u64m1_b64_m(mask, op1, op2, vl);828}829 830// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmsgeu_vv_u64m2_b32_m831// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {832// CHECK-RV64-NEXT: entry:833// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i1> poison, <vscale x 2 x i64> [[OP1]], <vscale x 2 x i64> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])834// CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]835//836vbool32_t test_vmsgeu_vv_u64m2_b32_m(vbool32_t mask, vuint64m2_t op1, vuint64m2_t op2, size_t vl) {837 return __riscv_vmsgeu_vv_u64m2_b32_m(mask, op1, op2, vl);838}839 840// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmsgeu_vx_u64m2_b32_m841// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {842// CHECK-RV64-NEXT: entry:843// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64.i64.i64(<vscale x 2 x i1> poison, <vscale x 2 x i64> [[OP1]], i64 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])844// CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]845//846vbool32_t test_vmsgeu_vx_u64m2_b32_m(vbool32_t mask, vuint64m2_t op1, uint64_t op2, size_t vl) {847 return __riscv_vmsgeu_vx_u64m2_b32_m(mask, op1, op2, vl);848}849 850// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmsgeu_vv_u64m4_b16_m851// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {852// CHECK-RV64-NEXT: entry:853// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i1> poison, <vscale x 4 x i64> [[OP1]], <vscale x 4 x i64> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])854// CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]855//856vbool16_t test_vmsgeu_vv_u64m4_b16_m(vbool16_t mask, vuint64m4_t op1, vuint64m4_t op2, size_t vl) {857 return __riscv_vmsgeu_vv_u64m4_b16_m(mask, op1, op2, vl);858}859 860// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmsgeu_vx_u64m4_b16_m861// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {862// CHECK-RV64-NEXT: entry:863// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64.i64.i64(<vscale x 4 x i1> poison, <vscale x 4 x i64> [[OP1]], i64 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])864// CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]865//866vbool16_t test_vmsgeu_vx_u64m4_b16_m(vbool16_t mask, vuint64m4_t op1, uint64_t op2, size_t vl) {867 return __riscv_vmsgeu_vx_u64m4_b16_m(mask, op1, op2, vl);868}869 870// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmsgeu_vv_u64m8_b8_m871// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {872// CHECK-RV64-NEXT: entry:873// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i1> poison, <vscale x 8 x i64> [[OP1]], <vscale x 8 x i64> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])874// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]875//876vbool8_t test_vmsgeu_vv_u64m8_b8_m(vbool8_t mask, vuint64m8_t op1, vuint64m8_t op2, size_t vl) {877 return __riscv_vmsgeu_vv_u64m8_b8_m(mask, op1, op2, vl);878}879 880// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmsgeu_vx_u64m8_b8_m881// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {882// CHECK-RV64-NEXT: entry:883// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i64.i64.i64(<vscale x 8 x i1> poison, <vscale x 8 x i64> [[OP1]], i64 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])884// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]885//886vbool8_t test_vmsgeu_vx_u64m8_b8_m(vbool8_t mask, vuint64m8_t op1, uint64_t op2, size_t vl) {887 return __riscv_vmsgeu_vx_u64m8_b8_m(mask, op1, op2, vl);888}889 890