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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 22// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \4// RUN: -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone \5// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \6// RUN: FileCheck --check-prefix=CHECK-RV64 %s7 8#include <riscv_vector.h>9 10// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vmv_v_v_i8mf811// CHECK-RV64-SAME: (<vscale x 1 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {12// CHECK-RV64-NEXT: entry:13// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> [[SRC]], i64 [[VL]])14// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]15//16vint8mf8_t test_vmv_v_v_i8mf8(vint8mf8_t src, size_t vl) {17 return __riscv_vmv_v_v_i8mf8(src, vl);18}19 20// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vmv_v_x_i8mf821// CHECK-RV64-SAME: (i8 noundef signext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {22// CHECK-RV64-NEXT: entry:23// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8.i64(<vscale x 1 x i8> poison, i8 [[SRC]], i64 [[VL]])24// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]25//26vint8mf8_t test_vmv_v_x_i8mf8(int8_t src, size_t vl) {27 return __riscv_vmv_v_x_i8mf8(src, vl);28}29 30// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vmv_v_v_i8mf431// CHECK-RV64-SAME: (<vscale x 2 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {32// CHECK-RV64-NEXT: entry:33// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> [[SRC]], i64 [[VL]])34// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]35//36vint8mf4_t test_vmv_v_v_i8mf4(vint8mf4_t src, size_t vl) {37 return __riscv_vmv_v_v_i8mf4(src, vl);38}39 40// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vmv_v_x_i8mf441// CHECK-RV64-SAME: (i8 noundef signext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {42// CHECK-RV64-NEXT: entry:43// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8.i64(<vscale x 2 x i8> poison, i8 [[SRC]], i64 [[VL]])44// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]45//46vint8mf4_t test_vmv_v_x_i8mf4(int8_t src, size_t vl) {47 return __riscv_vmv_v_x_i8mf4(src, vl);48}49 50// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vmv_v_v_i8mf251// CHECK-RV64-SAME: (<vscale x 4 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {52// CHECK-RV64-NEXT: entry:53// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> [[SRC]], i64 [[VL]])54// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]55//56vint8mf2_t test_vmv_v_v_i8mf2(vint8mf2_t src, size_t vl) {57 return __riscv_vmv_v_v_i8mf2(src, vl);58}59 60// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vmv_v_x_i8mf261// CHECK-RV64-SAME: (i8 noundef signext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {62// CHECK-RV64-NEXT: entry:63// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8.i64(<vscale x 4 x i8> poison, i8 [[SRC]], i64 [[VL]])64// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]65//66vint8mf2_t test_vmv_v_x_i8mf2(int8_t src, size_t vl) {67 return __riscv_vmv_v_x_i8mf2(src, vl);68}69 70// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vmv_v_v_i8m171// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {72// CHECK-RV64-NEXT: entry:73// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> [[SRC]], i64 [[VL]])74// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]75//76vint8m1_t test_vmv_v_v_i8m1(vint8m1_t src, size_t vl) {77 return __riscv_vmv_v_v_i8m1(src, vl);78}79 80// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vmv_v_x_i8m181// CHECK-RV64-SAME: (i8 noundef signext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {82// CHECK-RV64-NEXT: entry:83// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i64(<vscale x 8 x i8> poison, i8 [[SRC]], i64 [[VL]])84// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]85//86vint8m1_t test_vmv_v_x_i8m1(int8_t src, size_t vl) {87 return __riscv_vmv_v_x_i8m1(src, vl);88}89 90// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vmv_v_v_i8m291// CHECK-RV64-SAME: (<vscale x 16 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {92// CHECK-RV64-NEXT: entry:93// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> [[SRC]], i64 [[VL]])94// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]95//96vint8m2_t test_vmv_v_v_i8m2(vint8m2_t src, size_t vl) {97 return __riscv_vmv_v_v_i8m2(src, vl);98}99 100// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vmv_v_x_i8m2101// CHECK-RV64-SAME: (i8 noundef signext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {102// CHECK-RV64-NEXT: entry:103// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8.i64(<vscale x 16 x i8> poison, i8 [[SRC]], i64 [[VL]])104// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]105//106vint8m2_t test_vmv_v_x_i8m2(int8_t src, size_t vl) {107 return __riscv_vmv_v_x_i8m2(src, vl);108}109 110// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vmv_v_v_i8m4111// CHECK-RV64-SAME: (<vscale x 32 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {112// CHECK-RV64-NEXT: entry:113// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmv.v.v.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> [[SRC]], i64 [[VL]])114// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]115//116vint8m4_t test_vmv_v_v_i8m4(vint8m4_t src, size_t vl) {117 return __riscv_vmv_v_v_i8m4(src, vl);118}119 120// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vmv_v_x_i8m4121// CHECK-RV64-SAME: (i8 noundef signext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {122// CHECK-RV64-NEXT: entry:123// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmv.v.x.nxv32i8.i64(<vscale x 32 x i8> poison, i8 [[SRC]], i64 [[VL]])124// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]125//126vint8m4_t test_vmv_v_x_i8m4(int8_t src, size_t vl) {127 return __riscv_vmv_v_x_i8m4(src, vl);128}129 130// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vmv_v_v_i8m8131// CHECK-RV64-SAME: (<vscale x 64 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {132// CHECK-RV64-NEXT: entry:133// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmv.v.v.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> [[SRC]], i64 [[VL]])134// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]135//136vint8m8_t test_vmv_v_v_i8m8(vint8m8_t src, size_t vl) {137 return __riscv_vmv_v_v_i8m8(src, vl);138}139 140// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vmv_v_x_i8m8141// CHECK-RV64-SAME: (i8 noundef signext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {142// CHECK-RV64-NEXT: entry:143// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmv.v.x.nxv64i8.i64(<vscale x 64 x i8> poison, i8 [[SRC]], i64 [[VL]])144// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]145//146vint8m8_t test_vmv_v_x_i8m8(int8_t src, size_t vl) {147 return __riscv_vmv_v_x_i8m8(src, vl);148}149 150// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vmv_v_v_i16mf4151// CHECK-RV64-SAME: (<vscale x 1 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {152// CHECK-RV64-NEXT: entry:153// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmv.v.v.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[SRC]], i64 [[VL]])154// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]155//156vint16mf4_t test_vmv_v_v_i16mf4(vint16mf4_t src, size_t vl) {157 return __riscv_vmv_v_v_i16mf4(src, vl);158}159 160// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vmv_v_x_i16mf4161// CHECK-RV64-SAME: (i16 noundef signext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {162// CHECK-RV64-NEXT: entry:163// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmv.v.x.nxv1i16.i64(<vscale x 1 x i16> poison, i16 [[SRC]], i64 [[VL]])164// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]165//166vint16mf4_t test_vmv_v_x_i16mf4(int16_t src, size_t vl) {167 return __riscv_vmv_v_x_i16mf4(src, vl);168}169 170// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vmv_v_v_i16mf2171// CHECK-RV64-SAME: (<vscale x 2 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {172// CHECK-RV64-NEXT: entry:173// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmv.v.v.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> [[SRC]], i64 [[VL]])174// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]175//176vint16mf2_t test_vmv_v_v_i16mf2(vint16mf2_t src, size_t vl) {177 return __riscv_vmv_v_v_i16mf2(src, vl);178}179 180// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vmv_v_x_i16mf2181// CHECK-RV64-SAME: (i16 noundef signext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {182// CHECK-RV64-NEXT: entry:183// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmv.v.x.nxv2i16.i64(<vscale x 2 x i16> poison, i16 [[SRC]], i64 [[VL]])184// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]185//186vint16mf2_t test_vmv_v_x_i16mf2(int16_t src, size_t vl) {187 return __riscv_vmv_v_x_i16mf2(src, vl);188}189 190// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vmv_v_v_i16m1191// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {192// CHECK-RV64-NEXT: entry:193// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmv.v.v.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> [[SRC]], i64 [[VL]])194// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]195//196vint16m1_t test_vmv_v_v_i16m1(vint16m1_t src, size_t vl) {197 return __riscv_vmv_v_v_i16m1(src, vl);198}199 200// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vmv_v_x_i16m1201// CHECK-RV64-SAME: (i16 noundef signext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {202// CHECK-RV64-NEXT: entry:203// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmv.v.x.nxv4i16.i64(<vscale x 4 x i16> poison, i16 [[SRC]], i64 [[VL]])204// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]205//206vint16m1_t test_vmv_v_x_i16m1(int16_t src, size_t vl) {207 return __riscv_vmv_v_x_i16m1(src, vl);208}209 210// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vmv_v_v_i16m2211// CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {212// CHECK-RV64-NEXT: entry:213// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmv.v.v.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> [[SRC]], i64 [[VL]])214// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]215//216vint16m2_t test_vmv_v_v_i16m2(vint16m2_t src, size_t vl) {217 return __riscv_vmv_v_v_i16m2(src, vl);218}219 220// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vmv_v_x_i16m2221// CHECK-RV64-SAME: (i16 noundef signext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {222// CHECK-RV64-NEXT: entry:223// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmv.v.x.nxv8i16.i64(<vscale x 8 x i16> poison, i16 [[SRC]], i64 [[VL]])224// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]225//226vint16m2_t test_vmv_v_x_i16m2(int16_t src, size_t vl) {227 return __riscv_vmv_v_x_i16m2(src, vl);228}229 230// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vmv_v_v_i16m4231// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {232// CHECK-RV64-NEXT: entry:233// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmv.v.v.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> [[SRC]], i64 [[VL]])234// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]235//236vint16m4_t test_vmv_v_v_i16m4(vint16m4_t src, size_t vl) {237 return __riscv_vmv_v_v_i16m4(src, vl);238}239 240// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vmv_v_x_i16m4241// CHECK-RV64-SAME: (i16 noundef signext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {242// CHECK-RV64-NEXT: entry:243// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmv.v.x.nxv16i16.i64(<vscale x 16 x i16> poison, i16 [[SRC]], i64 [[VL]])244// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]245//246vint16m4_t test_vmv_v_x_i16m4(int16_t src, size_t vl) {247 return __riscv_vmv_v_x_i16m4(src, vl);248}249 250// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vmv_v_v_i16m8251// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {252// CHECK-RV64-NEXT: entry:253// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmv.v.v.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> [[SRC]], i64 [[VL]])254// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]255//256vint16m8_t test_vmv_v_v_i16m8(vint16m8_t src, size_t vl) {257 return __riscv_vmv_v_v_i16m8(src, vl);258}259 260// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vmv_v_x_i16m8261// CHECK-RV64-SAME: (i16 noundef signext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {262// CHECK-RV64-NEXT: entry:263// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmv.v.x.nxv32i16.i64(<vscale x 32 x i16> poison, i16 [[SRC]], i64 [[VL]])264// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]265//266vint16m8_t test_vmv_v_x_i16m8(int16_t src, size_t vl) {267 return __riscv_vmv_v_x_i16m8(src, vl);268}269 270// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vmv_v_v_i32mf2271// CHECK-RV64-SAME: (<vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {272// CHECK-RV64-NEXT: entry:273// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmv.v.v.nxv1i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[SRC]], i64 [[VL]])274// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]275//276vint32mf2_t test_vmv_v_v_i32mf2(vint32mf2_t src, size_t vl) {277 return __riscv_vmv_v_v_i32mf2(src, vl);278}279 280// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vmv_v_x_i32mf2281// CHECK-RV64-SAME: (i32 noundef signext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {282// CHECK-RV64-NEXT: entry:283// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmv.v.x.nxv1i32.i64(<vscale x 1 x i32> poison, i32 [[SRC]], i64 [[VL]])284// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]285//286vint32mf2_t test_vmv_v_x_i32mf2(int32_t src, size_t vl) {287 return __riscv_vmv_v_x_i32mf2(src, vl);288}289 290// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vmv_v_v_i32m1291// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {292// CHECK-RV64-NEXT: entry:293// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmv.v.v.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[SRC]], i64 [[VL]])294// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]295//296vint32m1_t test_vmv_v_v_i32m1(vint32m1_t src, size_t vl) {297 return __riscv_vmv_v_v_i32m1(src, vl);298}299 300// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vmv_v_x_i32m1301// CHECK-RV64-SAME: (i32 noundef signext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {302// CHECK-RV64-NEXT: entry:303// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmv.v.x.nxv2i32.i64(<vscale x 2 x i32> poison, i32 [[SRC]], i64 [[VL]])304// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]305//306vint32m1_t test_vmv_v_x_i32m1(int32_t src, size_t vl) {307 return __riscv_vmv_v_x_i32m1(src, vl);308}309 310// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vmv_v_v_i32m2311// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {312// CHECK-RV64-NEXT: entry:313// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmv.v.v.nxv4i32.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> [[SRC]], i64 [[VL]])314// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]315//316vint32m2_t test_vmv_v_v_i32m2(vint32m2_t src, size_t vl) {317 return __riscv_vmv_v_v_i32m2(src, vl);318}319 320// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vmv_v_x_i32m2321// CHECK-RV64-SAME: (i32 noundef signext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {322// CHECK-RV64-NEXT: entry:323// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmv.v.x.nxv4i32.i64(<vscale x 4 x i32> poison, i32 [[SRC]], i64 [[VL]])324// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]325//326vint32m2_t test_vmv_v_x_i32m2(int32_t src, size_t vl) {327 return __riscv_vmv_v_x_i32m2(src, vl);328}329 330// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vmv_v_v_i32m4331// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {332// CHECK-RV64-NEXT: entry:333// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmv.v.v.nxv8i32.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> [[SRC]], i64 [[VL]])334// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]335//336vint32m4_t test_vmv_v_v_i32m4(vint32m4_t src, size_t vl) {337 return __riscv_vmv_v_v_i32m4(src, vl);338}339 340// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vmv_v_x_i32m4341// CHECK-RV64-SAME: (i32 noundef signext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {342// CHECK-RV64-NEXT: entry:343// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmv.v.x.nxv8i32.i64(<vscale x 8 x i32> poison, i32 [[SRC]], i64 [[VL]])344// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]345//346vint32m4_t test_vmv_v_x_i32m4(int32_t src, size_t vl) {347 return __riscv_vmv_v_x_i32m4(src, vl);348}349 350// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vmv_v_v_i32m8351// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {352// CHECK-RV64-NEXT: entry:353// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmv.v.v.nxv16i32.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> [[SRC]], i64 [[VL]])354// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]355//356vint32m8_t test_vmv_v_v_i32m8(vint32m8_t src, size_t vl) {357 return __riscv_vmv_v_v_i32m8(src, vl);358}359 360// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vmv_v_x_i32m8361// CHECK-RV64-SAME: (i32 noundef signext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {362// CHECK-RV64-NEXT: entry:363// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmv.v.x.nxv16i32.i64(<vscale x 16 x i32> poison, i32 [[SRC]], i64 [[VL]])364// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]365//366vint32m8_t test_vmv_v_x_i32m8(int32_t src, size_t vl) {367 return __riscv_vmv_v_x_i32m8(src, vl);368}369 370// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vmv_v_v_i64m1371// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {372// CHECK-RV64-NEXT: entry:373// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmv.v.v.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> [[SRC]], i64 [[VL]])374// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]375//376vint64m1_t test_vmv_v_v_i64m1(vint64m1_t src, size_t vl) {377 return __riscv_vmv_v_v_i64m1(src, vl);378}379 380// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vmv_v_x_i64m1381// CHECK-RV64-SAME: (i64 noundef [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {382// CHECK-RV64-NEXT: entry:383// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmv.v.x.nxv1i64.i64(<vscale x 1 x i64> poison, i64 [[SRC]], i64 [[VL]])384// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]385//386vint64m1_t test_vmv_v_x_i64m1(int64_t src, size_t vl) {387 return __riscv_vmv_v_x_i64m1(src, vl);388}389 390// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vmv_v_v_i64m2391// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {392// CHECK-RV64-NEXT: entry:393// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmv.v.v.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> [[SRC]], i64 [[VL]])394// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]395//396vint64m2_t test_vmv_v_v_i64m2(vint64m2_t src, size_t vl) {397 return __riscv_vmv_v_v_i64m2(src, vl);398}399 400// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vmv_v_x_i64m2401// CHECK-RV64-SAME: (i64 noundef [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {402// CHECK-RV64-NEXT: entry:403// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmv.v.x.nxv2i64.i64(<vscale x 2 x i64> poison, i64 [[SRC]], i64 [[VL]])404// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]405//406vint64m2_t test_vmv_v_x_i64m2(int64_t src, size_t vl) {407 return __riscv_vmv_v_x_i64m2(src, vl);408}409 410// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vmv_v_v_i64m4411// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {412// CHECK-RV64-NEXT: entry:413// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmv.v.v.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> [[SRC]], i64 [[VL]])414// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]415//416vint64m4_t test_vmv_v_v_i64m4(vint64m4_t src, size_t vl) {417 return __riscv_vmv_v_v_i64m4(src, vl);418}419 420// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vmv_v_x_i64m4421// CHECK-RV64-SAME: (i64 noundef [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {422// CHECK-RV64-NEXT: entry:423// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmv.v.x.nxv4i64.i64(<vscale x 4 x i64> poison, i64 [[SRC]], i64 [[VL]])424// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]425//426vint64m4_t test_vmv_v_x_i64m4(int64_t src, size_t vl) {427 return __riscv_vmv_v_x_i64m4(src, vl);428}429 430// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vmv_v_v_i64m8431// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {432// CHECK-RV64-NEXT: entry:433// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmv.v.v.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> [[SRC]], i64 [[VL]])434// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]435//436vint64m8_t test_vmv_v_v_i64m8(vint64m8_t src, size_t vl) {437 return __riscv_vmv_v_v_i64m8(src, vl);438}439 440// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vmv_v_x_i64m8441// CHECK-RV64-SAME: (i64 noundef [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {442// CHECK-RV64-NEXT: entry:443// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmv.v.x.nxv8i64.i64(<vscale x 8 x i64> poison, i64 [[SRC]], i64 [[VL]])444// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]445//446vint64m8_t test_vmv_v_x_i64m8(int64_t src, size_t vl) {447 return __riscv_vmv_v_x_i64m8(src, vl);448}449 450// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vmv_v_v_u8mf8451// CHECK-RV64-SAME: (<vscale x 1 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {452// CHECK-RV64-NEXT: entry:453// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> [[SRC]], i64 [[VL]])454// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]455//456vuint8mf8_t test_vmv_v_v_u8mf8(vuint8mf8_t src, size_t vl) {457 return __riscv_vmv_v_v_u8mf8(src, vl);458}459 460// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vmv_v_x_u8mf8461// CHECK-RV64-SAME: (i8 noundef zeroext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {462// CHECK-RV64-NEXT: entry:463// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8.i64(<vscale x 1 x i8> poison, i8 [[SRC]], i64 [[VL]])464// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]465//466vuint8mf8_t test_vmv_v_x_u8mf8(uint8_t src, size_t vl) {467 return __riscv_vmv_v_x_u8mf8(src, vl);468}469 470// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vmv_v_v_u8mf4471// CHECK-RV64-SAME: (<vscale x 2 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {472// CHECK-RV64-NEXT: entry:473// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> [[SRC]], i64 [[VL]])474// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]475//476vuint8mf4_t test_vmv_v_v_u8mf4(vuint8mf4_t src, size_t vl) {477 return __riscv_vmv_v_v_u8mf4(src, vl);478}479 480// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vmv_v_x_u8mf4481// CHECK-RV64-SAME: (i8 noundef zeroext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {482// CHECK-RV64-NEXT: entry:483// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8.i64(<vscale x 2 x i8> poison, i8 [[SRC]], i64 [[VL]])484// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]485//486vuint8mf4_t test_vmv_v_x_u8mf4(uint8_t src, size_t vl) {487 return __riscv_vmv_v_x_u8mf4(src, vl);488}489 490// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vmv_v_v_u8mf2491// CHECK-RV64-SAME: (<vscale x 4 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {492// CHECK-RV64-NEXT: entry:493// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> [[SRC]], i64 [[VL]])494// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]495//496vuint8mf2_t test_vmv_v_v_u8mf2(vuint8mf2_t src, size_t vl) {497 return __riscv_vmv_v_v_u8mf2(src, vl);498}499 500// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vmv_v_x_u8mf2501// CHECK-RV64-SAME: (i8 noundef zeroext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {502// CHECK-RV64-NEXT: entry:503// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8.i64(<vscale x 4 x i8> poison, i8 [[SRC]], i64 [[VL]])504// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]505//506vuint8mf2_t test_vmv_v_x_u8mf2(uint8_t src, size_t vl) {507 return __riscv_vmv_v_x_u8mf2(src, vl);508}509 510// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vmv_v_v_u8m1511// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {512// CHECK-RV64-NEXT: entry:513// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> [[SRC]], i64 [[VL]])514// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]515//516vuint8m1_t test_vmv_v_v_u8m1(vuint8m1_t src, size_t vl) {517 return __riscv_vmv_v_v_u8m1(src, vl);518}519 520// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vmv_v_x_u8m1521// CHECK-RV64-SAME: (i8 noundef zeroext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {522// CHECK-RV64-NEXT: entry:523// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i64(<vscale x 8 x i8> poison, i8 [[SRC]], i64 [[VL]])524// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]525//526vuint8m1_t test_vmv_v_x_u8m1(uint8_t src, size_t vl) {527 return __riscv_vmv_v_x_u8m1(src, vl);528}529 530// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vmv_v_v_u8m2531// CHECK-RV64-SAME: (<vscale x 16 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {532// CHECK-RV64-NEXT: entry:533// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> [[SRC]], i64 [[VL]])534// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]535//536vuint8m2_t test_vmv_v_v_u8m2(vuint8m2_t src, size_t vl) {537 return __riscv_vmv_v_v_u8m2(src, vl);538}539 540// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vmv_v_x_u8m2541// CHECK-RV64-SAME: (i8 noundef zeroext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {542// CHECK-RV64-NEXT: entry:543// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8.i64(<vscale x 16 x i8> poison, i8 [[SRC]], i64 [[VL]])544// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]545//546vuint8m2_t test_vmv_v_x_u8m2(uint8_t src, size_t vl) {547 return __riscv_vmv_v_x_u8m2(src, vl);548}549 550// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vmv_v_v_u8m4551// CHECK-RV64-SAME: (<vscale x 32 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {552// CHECK-RV64-NEXT: entry:553// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmv.v.v.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> [[SRC]], i64 [[VL]])554// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]555//556vuint8m4_t test_vmv_v_v_u8m4(vuint8m4_t src, size_t vl) {557 return __riscv_vmv_v_v_u8m4(src, vl);558}559 560// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vmv_v_x_u8m4561// CHECK-RV64-SAME: (i8 noundef zeroext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {562// CHECK-RV64-NEXT: entry:563// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmv.v.x.nxv32i8.i64(<vscale x 32 x i8> poison, i8 [[SRC]], i64 [[VL]])564// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]565//566vuint8m4_t test_vmv_v_x_u8m4(uint8_t src, size_t vl) {567 return __riscv_vmv_v_x_u8m4(src, vl);568}569 570// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vmv_v_v_u8m8571// CHECK-RV64-SAME: (<vscale x 64 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {572// CHECK-RV64-NEXT: entry:573// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmv.v.v.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> [[SRC]], i64 [[VL]])574// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]575//576vuint8m8_t test_vmv_v_v_u8m8(vuint8m8_t src, size_t vl) {577 return __riscv_vmv_v_v_u8m8(src, vl);578}579 580// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vmv_v_x_u8m8581// CHECK-RV64-SAME: (i8 noundef zeroext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {582// CHECK-RV64-NEXT: entry:583// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmv.v.x.nxv64i8.i64(<vscale x 64 x i8> poison, i8 [[SRC]], i64 [[VL]])584// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]585//586vuint8m8_t test_vmv_v_x_u8m8(uint8_t src, size_t vl) {587 return __riscv_vmv_v_x_u8m8(src, vl);588}589 590// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vmv_v_v_u16mf4591// CHECK-RV64-SAME: (<vscale x 1 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {592// CHECK-RV64-NEXT: entry:593// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmv.v.v.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[SRC]], i64 [[VL]])594// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]595//596vuint16mf4_t test_vmv_v_v_u16mf4(vuint16mf4_t src, size_t vl) {597 return __riscv_vmv_v_v_u16mf4(src, vl);598}599 600// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vmv_v_x_u16mf4601// CHECK-RV64-SAME: (i16 noundef zeroext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {602// CHECK-RV64-NEXT: entry:603// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmv.v.x.nxv1i16.i64(<vscale x 1 x i16> poison, i16 [[SRC]], i64 [[VL]])604// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]605//606vuint16mf4_t test_vmv_v_x_u16mf4(uint16_t src, size_t vl) {607 return __riscv_vmv_v_x_u16mf4(src, vl);608}609 610// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vmv_v_v_u16mf2611// CHECK-RV64-SAME: (<vscale x 2 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {612// CHECK-RV64-NEXT: entry:613// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmv.v.v.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> [[SRC]], i64 [[VL]])614// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]615//616vuint16mf2_t test_vmv_v_v_u16mf2(vuint16mf2_t src, size_t vl) {617 return __riscv_vmv_v_v_u16mf2(src, vl);618}619 620// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vmv_v_x_u16mf2621// CHECK-RV64-SAME: (i16 noundef zeroext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {622// CHECK-RV64-NEXT: entry:623// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmv.v.x.nxv2i16.i64(<vscale x 2 x i16> poison, i16 [[SRC]], i64 [[VL]])624// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]625//626vuint16mf2_t test_vmv_v_x_u16mf2(uint16_t src, size_t vl) {627 return __riscv_vmv_v_x_u16mf2(src, vl);628}629 630// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vmv_v_v_u16m1631// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {632// CHECK-RV64-NEXT: entry:633// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmv.v.v.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> [[SRC]], i64 [[VL]])634// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]635//636vuint16m1_t test_vmv_v_v_u16m1(vuint16m1_t src, size_t vl) {637 return __riscv_vmv_v_v_u16m1(src, vl);638}639 640// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vmv_v_x_u16m1641// CHECK-RV64-SAME: (i16 noundef zeroext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {642// CHECK-RV64-NEXT: entry:643// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmv.v.x.nxv4i16.i64(<vscale x 4 x i16> poison, i16 [[SRC]], i64 [[VL]])644// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]645//646vuint16m1_t test_vmv_v_x_u16m1(uint16_t src, size_t vl) {647 return __riscv_vmv_v_x_u16m1(src, vl);648}649 650// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vmv_v_v_u16m2651// CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {652// CHECK-RV64-NEXT: entry:653// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmv.v.v.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> [[SRC]], i64 [[VL]])654// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]655//656vuint16m2_t test_vmv_v_v_u16m2(vuint16m2_t src, size_t vl) {657 return __riscv_vmv_v_v_u16m2(src, vl);658}659 660// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vmv_v_x_u16m2661// CHECK-RV64-SAME: (i16 noundef zeroext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {662// CHECK-RV64-NEXT: entry:663// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmv.v.x.nxv8i16.i64(<vscale x 8 x i16> poison, i16 [[SRC]], i64 [[VL]])664// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]665//666vuint16m2_t test_vmv_v_x_u16m2(uint16_t src, size_t vl) {667 return __riscv_vmv_v_x_u16m2(src, vl);668}669 670// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vmv_v_v_u16m4671// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {672// CHECK-RV64-NEXT: entry:673// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmv.v.v.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> [[SRC]], i64 [[VL]])674// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]675//676vuint16m4_t test_vmv_v_v_u16m4(vuint16m4_t src, size_t vl) {677 return __riscv_vmv_v_v_u16m4(src, vl);678}679 680// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vmv_v_x_u16m4681// CHECK-RV64-SAME: (i16 noundef zeroext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {682// CHECK-RV64-NEXT: entry:683// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmv.v.x.nxv16i16.i64(<vscale x 16 x i16> poison, i16 [[SRC]], i64 [[VL]])684// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]685//686vuint16m4_t test_vmv_v_x_u16m4(uint16_t src, size_t vl) {687 return __riscv_vmv_v_x_u16m4(src, vl);688}689 690// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vmv_v_v_u16m8691// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {692// CHECK-RV64-NEXT: entry:693// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmv.v.v.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> [[SRC]], i64 [[VL]])694// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]695//696vuint16m8_t test_vmv_v_v_u16m8(vuint16m8_t src, size_t vl) {697 return __riscv_vmv_v_v_u16m8(src, vl);698}699 700// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vmv_v_x_u16m8701// CHECK-RV64-SAME: (i16 noundef zeroext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {702// CHECK-RV64-NEXT: entry:703// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmv.v.x.nxv32i16.i64(<vscale x 32 x i16> poison, i16 [[SRC]], i64 [[VL]])704// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]705//706vuint16m8_t test_vmv_v_x_u16m8(uint16_t src, size_t vl) {707 return __riscv_vmv_v_x_u16m8(src, vl);708}709 710// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vmv_v_v_u32mf2711// CHECK-RV64-SAME: (<vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {712// CHECK-RV64-NEXT: entry:713// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmv.v.v.nxv1i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[SRC]], i64 [[VL]])714// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]715//716vuint32mf2_t test_vmv_v_v_u32mf2(vuint32mf2_t src, size_t vl) {717 return __riscv_vmv_v_v_u32mf2(src, vl);718}719 720// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vmv_v_x_u32mf2721// CHECK-RV64-SAME: (i32 noundef signext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {722// CHECK-RV64-NEXT: entry:723// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmv.v.x.nxv1i32.i64(<vscale x 1 x i32> poison, i32 [[SRC]], i64 [[VL]])724// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]725//726vuint32mf2_t test_vmv_v_x_u32mf2(uint32_t src, size_t vl) {727 return __riscv_vmv_v_x_u32mf2(src, vl);728}729 730// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vmv_v_v_u32m1731// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {732// CHECK-RV64-NEXT: entry:733// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmv.v.v.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[SRC]], i64 [[VL]])734// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]735//736vuint32m1_t test_vmv_v_v_u32m1(vuint32m1_t src, size_t vl) {737 return __riscv_vmv_v_v_u32m1(src, vl);738}739 740// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vmv_v_x_u32m1741// CHECK-RV64-SAME: (i32 noundef signext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {742// CHECK-RV64-NEXT: entry:743// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmv.v.x.nxv2i32.i64(<vscale x 2 x i32> poison, i32 [[SRC]], i64 [[VL]])744// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]745//746vuint32m1_t test_vmv_v_x_u32m1(uint32_t src, size_t vl) {747 return __riscv_vmv_v_x_u32m1(src, vl);748}749 750// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vmv_v_v_u32m2751// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {752// CHECK-RV64-NEXT: entry:753// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmv.v.v.nxv4i32.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> [[SRC]], i64 [[VL]])754// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]755//756vuint32m2_t test_vmv_v_v_u32m2(vuint32m2_t src, size_t vl) {757 return __riscv_vmv_v_v_u32m2(src, vl);758}759 760// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vmv_v_x_u32m2761// CHECK-RV64-SAME: (i32 noundef signext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {762// CHECK-RV64-NEXT: entry:763// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmv.v.x.nxv4i32.i64(<vscale x 4 x i32> poison, i32 [[SRC]], i64 [[VL]])764// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]765//766vuint32m2_t test_vmv_v_x_u32m2(uint32_t src, size_t vl) {767 return __riscv_vmv_v_x_u32m2(src, vl);768}769 770// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vmv_v_v_u32m4771// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {772// CHECK-RV64-NEXT: entry:773// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmv.v.v.nxv8i32.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> [[SRC]], i64 [[VL]])774// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]775//776vuint32m4_t test_vmv_v_v_u32m4(vuint32m4_t src, size_t vl) {777 return __riscv_vmv_v_v_u32m4(src, vl);778}779 780// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vmv_v_x_u32m4781// CHECK-RV64-SAME: (i32 noundef signext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {782// CHECK-RV64-NEXT: entry:783// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmv.v.x.nxv8i32.i64(<vscale x 8 x i32> poison, i32 [[SRC]], i64 [[VL]])784// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]785//786vuint32m4_t test_vmv_v_x_u32m4(uint32_t src, size_t vl) {787 return __riscv_vmv_v_x_u32m4(src, vl);788}789 790// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vmv_v_v_u32m8791// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {792// CHECK-RV64-NEXT: entry:793// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmv.v.v.nxv16i32.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> [[SRC]], i64 [[VL]])794// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]795//796vuint32m8_t test_vmv_v_v_u32m8(vuint32m8_t src, size_t vl) {797 return __riscv_vmv_v_v_u32m8(src, vl);798}799 800// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vmv_v_x_u32m8801// CHECK-RV64-SAME: (i32 noundef signext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {802// CHECK-RV64-NEXT: entry:803// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmv.v.x.nxv16i32.i64(<vscale x 16 x i32> poison, i32 [[SRC]], i64 [[VL]])804// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]805//806vuint32m8_t test_vmv_v_x_u32m8(uint32_t src, size_t vl) {807 return __riscv_vmv_v_x_u32m8(src, vl);808}809 810// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vmv_v_v_u64m1811// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {812// CHECK-RV64-NEXT: entry:813// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmv.v.v.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> [[SRC]], i64 [[VL]])814// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]815//816vuint64m1_t test_vmv_v_v_u64m1(vuint64m1_t src, size_t vl) {817 return __riscv_vmv_v_v_u64m1(src, vl);818}819 820// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vmv_v_x_u64m1821// CHECK-RV64-SAME: (i64 noundef [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {822// CHECK-RV64-NEXT: entry:823// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmv.v.x.nxv1i64.i64(<vscale x 1 x i64> poison, i64 [[SRC]], i64 [[VL]])824// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]825//826vuint64m1_t test_vmv_v_x_u64m1(uint64_t src, size_t vl) {827 return __riscv_vmv_v_x_u64m1(src, vl);828}829 830// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vmv_v_v_u64m2831// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {832// CHECK-RV64-NEXT: entry:833// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmv.v.v.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> [[SRC]], i64 [[VL]])834// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]835//836vuint64m2_t test_vmv_v_v_u64m2(vuint64m2_t src, size_t vl) {837 return __riscv_vmv_v_v_u64m2(src, vl);838}839 840// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vmv_v_x_u64m2841// CHECK-RV64-SAME: (i64 noundef [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {842// CHECK-RV64-NEXT: entry:843// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmv.v.x.nxv2i64.i64(<vscale x 2 x i64> poison, i64 [[SRC]], i64 [[VL]])844// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]845//846vuint64m2_t test_vmv_v_x_u64m2(uint64_t src, size_t vl) {847 return __riscv_vmv_v_x_u64m2(src, vl);848}849 850// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vmv_v_v_u64m4851// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {852// CHECK-RV64-NEXT: entry:853// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmv.v.v.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> [[SRC]], i64 [[VL]])854// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]855//856vuint64m4_t test_vmv_v_v_u64m4(vuint64m4_t src, size_t vl) {857 return __riscv_vmv_v_v_u64m4(src, vl);858}859 860// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vmv_v_x_u64m4861// CHECK-RV64-SAME: (i64 noundef [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {862// CHECK-RV64-NEXT: entry:863// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmv.v.x.nxv4i64.i64(<vscale x 4 x i64> poison, i64 [[SRC]], i64 [[VL]])864// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]865//866vuint64m4_t test_vmv_v_x_u64m4(uint64_t src, size_t vl) {867 return __riscv_vmv_v_x_u64m4(src, vl);868}869 870// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vmv_v_v_u64m8871// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {872// CHECK-RV64-NEXT: entry:873// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmv.v.v.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> [[SRC]], i64 [[VL]])874// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]875//876vuint64m8_t test_vmv_v_v_u64m8(vuint64m8_t src, size_t vl) {877 return __riscv_vmv_v_v_u64m8(src, vl);878}879 880// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vmv_v_x_u64m8881// CHECK-RV64-SAME: (i64 noundef [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {882// CHECK-RV64-NEXT: entry:883// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmv.v.x.nxv8i64.i64(<vscale x 8 x i64> poison, i64 [[SRC]], i64 [[VL]])884// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]885//886vuint64m8_t test_vmv_v_x_u64m8(uint64_t src, size_t vl) {887 return __riscv_vmv_v_x_u64m8(src, vl);888}889 890// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vmv_v_v_f16mf4891// CHECK-RV64-SAME: (<vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {892// CHECK-RV64-NEXT: entry:893// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vmv.v.v.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> [[SRC]], i64 [[VL]])894// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]895//896vfloat16mf4_t test_vmv_v_v_f16mf4(vfloat16mf4_t src, size_t vl) {897 return __riscv_vmv_v_v_f16mf4(src, vl);898}899 900// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vmv_v_v_f16mf2901// CHECK-RV64-SAME: (<vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {902// CHECK-RV64-NEXT: entry:903// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vmv.v.v.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> [[SRC]], i64 [[VL]])904// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]905//906vfloat16mf2_t test_vmv_v_v_f16mf2(vfloat16mf2_t src, size_t vl) {907 return __riscv_vmv_v_v_f16mf2(src, vl);908}909 910// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vmv_v_v_f16m1911// CHECK-RV64-SAME: (<vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {912// CHECK-RV64-NEXT: entry:913// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vmv.v.v.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> [[SRC]], i64 [[VL]])914// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]915//916vfloat16m1_t test_vmv_v_v_f16m1(vfloat16m1_t src, size_t vl) {917 return __riscv_vmv_v_v_f16m1(src, vl);918}919 920// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vmv_v_v_f16m2921// CHECK-RV64-SAME: (<vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {922// CHECK-RV64-NEXT: entry:923// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vmv.v.v.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> [[SRC]], i64 [[VL]])924// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]925//926vfloat16m2_t test_vmv_v_v_f16m2(vfloat16m2_t src, size_t vl) {927 return __riscv_vmv_v_v_f16m2(src, vl);928}929 930// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vmv_v_v_f16m4931// CHECK-RV64-SAME: (<vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {932// CHECK-RV64-NEXT: entry:933// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vmv.v.v.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> [[SRC]], i64 [[VL]])934// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]935//936vfloat16m4_t test_vmv_v_v_f16m4(vfloat16m4_t src, size_t vl) {937 return __riscv_vmv_v_v_f16m4(src, vl);938}939 940// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vmv_v_v_f16m8941// CHECK-RV64-SAME: (<vscale x 32 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {942// CHECK-RV64-NEXT: entry:943// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vmv.v.v.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> [[SRC]], i64 [[VL]])944// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]945//946vfloat16m8_t test_vmv_v_v_f16m8(vfloat16m8_t src, size_t vl) {947 return __riscv_vmv_v_v_f16m8(src, vl);948}949 950// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vmv_v_v_f32mf2951// CHECK-RV64-SAME: (<vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {952// CHECK-RV64-NEXT: entry:953// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vmv.v.v.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> [[SRC]], i64 [[VL]])954// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]955//956vfloat32mf2_t test_vmv_v_v_f32mf2(vfloat32mf2_t src, size_t vl) {957 return __riscv_vmv_v_v_f32mf2(src, vl);958}959 960// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vmv_v_v_f32m1961// CHECK-RV64-SAME: (<vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {962// CHECK-RV64-NEXT: entry:963// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vmv.v.v.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> [[SRC]], i64 [[VL]])964// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]965//966vfloat32m1_t test_vmv_v_v_f32m1(vfloat32m1_t src, size_t vl) {967 return __riscv_vmv_v_v_f32m1(src, vl);968}969 970// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vmv_v_v_f32m2971// CHECK-RV64-SAME: (<vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {972// CHECK-RV64-NEXT: entry:973// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vmv.v.v.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> [[SRC]], i64 [[VL]])974// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]975//976vfloat32m2_t test_vmv_v_v_f32m2(vfloat32m2_t src, size_t vl) {977 return __riscv_vmv_v_v_f32m2(src, vl);978}979 980// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vmv_v_v_f32m4981// CHECK-RV64-SAME: (<vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {982// CHECK-RV64-NEXT: entry:983// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vmv.v.v.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> [[SRC]], i64 [[VL]])984// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]985//986vfloat32m4_t test_vmv_v_v_f32m4(vfloat32m4_t src, size_t vl) {987 return __riscv_vmv_v_v_f32m4(src, vl);988}989 990// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vmv_v_v_f32m8991// CHECK-RV64-SAME: (<vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {992// CHECK-RV64-NEXT: entry:993// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vmv.v.v.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> [[SRC]], i64 [[VL]])994// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]995//996vfloat32m8_t test_vmv_v_v_f32m8(vfloat32m8_t src, size_t vl) {997 return __riscv_vmv_v_v_f32m8(src, vl);998}999 1000// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vmv_v_v_f64m11001// CHECK-RV64-SAME: (<vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1002// CHECK-RV64-NEXT: entry:1003// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vmv.v.v.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> [[SRC]], i64 [[VL]])1004// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]1005//1006vfloat64m1_t test_vmv_v_v_f64m1(vfloat64m1_t src, size_t vl) {1007 return __riscv_vmv_v_v_f64m1(src, vl);1008}1009 1010// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vmv_v_v_f64m21011// CHECK-RV64-SAME: (<vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1012// CHECK-RV64-NEXT: entry:1013// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vmv.v.v.nxv2f64.i64(<vscale x 2 x double> poison, <vscale x 2 x double> [[SRC]], i64 [[VL]])1014// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]1015//1016vfloat64m2_t test_vmv_v_v_f64m2(vfloat64m2_t src, size_t vl) {1017 return __riscv_vmv_v_v_f64m2(src, vl);1018}1019 1020// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vmv_v_v_f64m41021// CHECK-RV64-SAME: (<vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1022// CHECK-RV64-NEXT: entry:1023// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vmv.v.v.nxv4f64.i64(<vscale x 4 x double> poison, <vscale x 4 x double> [[SRC]], i64 [[VL]])1024// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]1025//1026vfloat64m4_t test_vmv_v_v_f64m4(vfloat64m4_t src, size_t vl) {1027 return __riscv_vmv_v_v_f64m4(src, vl);1028}1029 1030// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vmv_v_v_f64m81031// CHECK-RV64-SAME: (<vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1032// CHECK-RV64-NEXT: entry:1033// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vmv.v.v.nxv8f64.i64(<vscale x 8 x double> poison, <vscale x 8 x double> [[SRC]], i64 [[VL]])1034// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]1035//1036vfloat64m8_t test_vmv_v_v_f64m8(vfloat64m8_t src, size_t vl) {1037 return __riscv_vmv_v_v_f64m8(src, vl);1038}1039 1040// CHECK-RV64-LABEL: define dso_local signext i8 @test_vmv_x_s_i8mf8_i81041// CHECK-RV64-SAME: (<vscale x 1 x i8> [[SRC:%.*]]) #[[ATTR0]] {1042// CHECK-RV64-NEXT: entry:1043// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv1i8(<vscale x 1 x i8> [[SRC]])1044// CHECK-RV64-NEXT: ret i8 [[TMP0]]1045//1046int8_t test_vmv_x_s_i8mf8_i8(vint8mf8_t src) {1047 return __riscv_vmv_x_s_i8mf8_i8(src);1048}1049 1050// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vmv_s_x_i8mf81051// CHECK-RV64-SAME: (i8 noundef signext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1052// CHECK-RV64-NEXT: entry:1053// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmv.s.x.nxv1i8.i64(<vscale x 1 x i8> poison, i8 [[SRC]], i64 [[VL]])1054// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]1055//1056vint8mf8_t test_vmv_s_x_i8mf8(int8_t src, size_t vl) {1057 return __riscv_vmv_s_x_i8mf8(src, vl);1058}1059 1060// CHECK-RV64-LABEL: define dso_local signext i8 @test_vmv_x_s_i8mf4_i81061// CHECK-RV64-SAME: (<vscale x 2 x i8> [[SRC:%.*]]) #[[ATTR0]] {1062// CHECK-RV64-NEXT: entry:1063// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv2i8(<vscale x 2 x i8> [[SRC]])1064// CHECK-RV64-NEXT: ret i8 [[TMP0]]1065//1066int8_t test_vmv_x_s_i8mf4_i8(vint8mf4_t src) {1067 return __riscv_vmv_x_s_i8mf4_i8(src);1068}1069 1070// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vmv_s_x_i8mf41071// CHECK-RV64-SAME: (i8 noundef signext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1072// CHECK-RV64-NEXT: entry:1073// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmv.s.x.nxv2i8.i64(<vscale x 2 x i8> poison, i8 [[SRC]], i64 [[VL]])1074// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]1075//1076vint8mf4_t test_vmv_s_x_i8mf4(int8_t src, size_t vl) {1077 return __riscv_vmv_s_x_i8mf4(src, vl);1078}1079 1080// CHECK-RV64-LABEL: define dso_local signext i8 @test_vmv_x_s_i8mf2_i81081// CHECK-RV64-SAME: (<vscale x 4 x i8> [[SRC:%.*]]) #[[ATTR0]] {1082// CHECK-RV64-NEXT: entry:1083// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv4i8(<vscale x 4 x i8> [[SRC]])1084// CHECK-RV64-NEXT: ret i8 [[TMP0]]1085//1086int8_t test_vmv_x_s_i8mf2_i8(vint8mf2_t src) {1087 return __riscv_vmv_x_s_i8mf2_i8(src);1088}1089 1090// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vmv_s_x_i8mf21091// CHECK-RV64-SAME: (i8 noundef signext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1092// CHECK-RV64-NEXT: entry:1093// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmv.s.x.nxv4i8.i64(<vscale x 4 x i8> poison, i8 [[SRC]], i64 [[VL]])1094// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]1095//1096vint8mf2_t test_vmv_s_x_i8mf2(int8_t src, size_t vl) {1097 return __riscv_vmv_s_x_i8mf2(src, vl);1098}1099 1100// CHECK-RV64-LABEL: define dso_local signext i8 @test_vmv_x_s_i8m1_i81101// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {1102// CHECK-RV64-NEXT: entry:1103// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv8i8(<vscale x 8 x i8> [[SRC]])1104// CHECK-RV64-NEXT: ret i8 [[TMP0]]1105//1106int8_t test_vmv_x_s_i8m1_i8(vint8m1_t src) {1107 return __riscv_vmv_x_s_i8m1_i8(src);1108}1109 1110// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vmv_s_x_i8m11111// CHECK-RV64-SAME: (i8 noundef signext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1112// CHECK-RV64-NEXT: entry:1113// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmv.s.x.nxv8i8.i64(<vscale x 8 x i8> poison, i8 [[SRC]], i64 [[VL]])1114// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]1115//1116vint8m1_t test_vmv_s_x_i8m1(int8_t src, size_t vl) {1117 return __riscv_vmv_s_x_i8m1(src, vl);1118}1119 1120// CHECK-RV64-LABEL: define dso_local signext i8 @test_vmv_x_s_i8m2_i81121// CHECK-RV64-SAME: (<vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {1122// CHECK-RV64-NEXT: entry:1123// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv16i8(<vscale x 16 x i8> [[SRC]])1124// CHECK-RV64-NEXT: ret i8 [[TMP0]]1125//1126int8_t test_vmv_x_s_i8m2_i8(vint8m2_t src) {1127 return __riscv_vmv_x_s_i8m2_i8(src);1128}1129 1130// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vmv_s_x_i8m21131// CHECK-RV64-SAME: (i8 noundef signext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1132// CHECK-RV64-NEXT: entry:1133// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmv.s.x.nxv16i8.i64(<vscale x 16 x i8> poison, i8 [[SRC]], i64 [[VL]])1134// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]1135//1136vint8m2_t test_vmv_s_x_i8m2(int8_t src, size_t vl) {1137 return __riscv_vmv_s_x_i8m2(src, vl);1138}1139 1140// CHECK-RV64-LABEL: define dso_local signext i8 @test_vmv_x_s_i8m4_i81141// CHECK-RV64-SAME: (<vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {1142// CHECK-RV64-NEXT: entry:1143// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv32i8(<vscale x 32 x i8> [[SRC]])1144// CHECK-RV64-NEXT: ret i8 [[TMP0]]1145//1146int8_t test_vmv_x_s_i8m4_i8(vint8m4_t src) {1147 return __riscv_vmv_x_s_i8m4_i8(src);1148}1149 1150// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vmv_s_x_i8m41151// CHECK-RV64-SAME: (i8 noundef signext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1152// CHECK-RV64-NEXT: entry:1153// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmv.s.x.nxv32i8.i64(<vscale x 32 x i8> poison, i8 [[SRC]], i64 [[VL]])1154// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]1155//1156vint8m4_t test_vmv_s_x_i8m4(int8_t src, size_t vl) {1157 return __riscv_vmv_s_x_i8m4(src, vl);1158}1159 1160// CHECK-RV64-LABEL: define dso_local signext i8 @test_vmv_x_s_i8m8_i81161// CHECK-RV64-SAME: (<vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {1162// CHECK-RV64-NEXT: entry:1163// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv64i8(<vscale x 64 x i8> [[SRC]])1164// CHECK-RV64-NEXT: ret i8 [[TMP0]]1165//1166int8_t test_vmv_x_s_i8m8_i8(vint8m8_t src) {1167 return __riscv_vmv_x_s_i8m8_i8(src);1168}1169 1170// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vmv_s_x_i8m81171// CHECK-RV64-SAME: (i8 noundef signext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1172// CHECK-RV64-NEXT: entry:1173// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmv.s.x.nxv64i8.i64(<vscale x 64 x i8> poison, i8 [[SRC]], i64 [[VL]])1174// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]1175//1176vint8m8_t test_vmv_s_x_i8m8(int8_t src, size_t vl) {1177 return __riscv_vmv_s_x_i8m8(src, vl);1178}1179 1180// CHECK-RV64-LABEL: define dso_local signext i16 @test_vmv_x_s_i16mf4_i161181// CHECK-RV64-SAME: (<vscale x 1 x i16> [[SRC:%.*]]) #[[ATTR0]] {1182// CHECK-RV64-NEXT: entry:1183// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv1i16(<vscale x 1 x i16> [[SRC]])1184// CHECK-RV64-NEXT: ret i16 [[TMP0]]1185//1186int16_t test_vmv_x_s_i16mf4_i16(vint16mf4_t src) {1187 return __riscv_vmv_x_s_i16mf4_i16(src);1188}1189 1190// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vmv_s_x_i16mf41191// CHECK-RV64-SAME: (i16 noundef signext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1192// CHECK-RV64-NEXT: entry:1193// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmv.s.x.nxv1i16.i64(<vscale x 1 x i16> poison, i16 [[SRC]], i64 [[VL]])1194// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]1195//1196vint16mf4_t test_vmv_s_x_i16mf4(int16_t src, size_t vl) {1197 return __riscv_vmv_s_x_i16mf4(src, vl);1198}1199 1200// CHECK-RV64-LABEL: define dso_local signext i16 @test_vmv_x_s_i16mf2_i161201// CHECK-RV64-SAME: (<vscale x 2 x i16> [[SRC:%.*]]) #[[ATTR0]] {1202// CHECK-RV64-NEXT: entry:1203// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv2i16(<vscale x 2 x i16> [[SRC]])1204// CHECK-RV64-NEXT: ret i16 [[TMP0]]1205//1206int16_t test_vmv_x_s_i16mf2_i16(vint16mf2_t src) {1207 return __riscv_vmv_x_s_i16mf2_i16(src);1208}1209 1210// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vmv_s_x_i16mf21211// CHECK-RV64-SAME: (i16 noundef signext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1212// CHECK-RV64-NEXT: entry:1213// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmv.s.x.nxv2i16.i64(<vscale x 2 x i16> poison, i16 [[SRC]], i64 [[VL]])1214// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]1215//1216vint16mf2_t test_vmv_s_x_i16mf2(int16_t src, size_t vl) {1217 return __riscv_vmv_s_x_i16mf2(src, vl);1218}1219 1220// CHECK-RV64-LABEL: define dso_local signext i16 @test_vmv_x_s_i16m1_i161221// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {1222// CHECK-RV64-NEXT: entry:1223// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv4i16(<vscale x 4 x i16> [[SRC]])1224// CHECK-RV64-NEXT: ret i16 [[TMP0]]1225//1226int16_t test_vmv_x_s_i16m1_i16(vint16m1_t src) {1227 return __riscv_vmv_x_s_i16m1_i16(src);1228}1229 1230// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vmv_s_x_i16m11231// CHECK-RV64-SAME: (i16 noundef signext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1232// CHECK-RV64-NEXT: entry:1233// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmv.s.x.nxv4i16.i64(<vscale x 4 x i16> poison, i16 [[SRC]], i64 [[VL]])1234// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]1235//1236vint16m1_t test_vmv_s_x_i16m1(int16_t src, size_t vl) {1237 return __riscv_vmv_s_x_i16m1(src, vl);1238}1239 1240// CHECK-RV64-LABEL: define dso_local signext i16 @test_vmv_x_s_i16m2_i161241// CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {1242// CHECK-RV64-NEXT: entry:1243// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv8i16(<vscale x 8 x i16> [[SRC]])1244// CHECK-RV64-NEXT: ret i16 [[TMP0]]1245//1246int16_t test_vmv_x_s_i16m2_i16(vint16m2_t src) {1247 return __riscv_vmv_x_s_i16m2_i16(src);1248}1249 1250// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vmv_s_x_i16m21251// CHECK-RV64-SAME: (i16 noundef signext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1252// CHECK-RV64-NEXT: entry:1253// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmv.s.x.nxv8i16.i64(<vscale x 8 x i16> poison, i16 [[SRC]], i64 [[VL]])1254// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]1255//1256vint16m2_t test_vmv_s_x_i16m2(int16_t src, size_t vl) {1257 return __riscv_vmv_s_x_i16m2(src, vl);1258}1259 1260// CHECK-RV64-LABEL: define dso_local signext i16 @test_vmv_x_s_i16m4_i161261// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {1262// CHECK-RV64-NEXT: entry:1263// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv16i16(<vscale x 16 x i16> [[SRC]])1264// CHECK-RV64-NEXT: ret i16 [[TMP0]]1265//1266int16_t test_vmv_x_s_i16m4_i16(vint16m4_t src) {1267 return __riscv_vmv_x_s_i16m4_i16(src);1268}1269 1270// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vmv_s_x_i16m41271// CHECK-RV64-SAME: (i16 noundef signext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1272// CHECK-RV64-NEXT: entry:1273// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmv.s.x.nxv16i16.i64(<vscale x 16 x i16> poison, i16 [[SRC]], i64 [[VL]])1274// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]1275//1276vint16m4_t test_vmv_s_x_i16m4(int16_t src, size_t vl) {1277 return __riscv_vmv_s_x_i16m4(src, vl);1278}1279 1280// CHECK-RV64-LABEL: define dso_local signext i16 @test_vmv_x_s_i16m8_i161281// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {1282// CHECK-RV64-NEXT: entry:1283// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv32i16(<vscale x 32 x i16> [[SRC]])1284// CHECK-RV64-NEXT: ret i16 [[TMP0]]1285//1286int16_t test_vmv_x_s_i16m8_i16(vint16m8_t src) {1287 return __riscv_vmv_x_s_i16m8_i16(src);1288}1289 1290// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vmv_s_x_i16m81291// CHECK-RV64-SAME: (i16 noundef signext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1292// CHECK-RV64-NEXT: entry:1293// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmv.s.x.nxv32i16.i64(<vscale x 32 x i16> poison, i16 [[SRC]], i64 [[VL]])1294// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]1295//1296vint16m8_t test_vmv_s_x_i16m8(int16_t src, size_t vl) {1297 return __riscv_vmv_s_x_i16m8(src, vl);1298}1299 1300// CHECK-RV64-LABEL: define dso_local signext i32 @test_vmv_x_s_i32mf2_i321301// CHECK-RV64-SAME: (<vscale x 1 x i32> [[SRC:%.*]]) #[[ATTR0]] {1302// CHECK-RV64-NEXT: entry:1303// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv1i32(<vscale x 1 x i32> [[SRC]])1304// CHECK-RV64-NEXT: ret i32 [[TMP0]]1305//1306int32_t test_vmv_x_s_i32mf2_i32(vint32mf2_t src) {1307 return __riscv_vmv_x_s_i32mf2_i32(src);1308}1309 1310// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vmv_s_x_i32mf21311// CHECK-RV64-SAME: (i32 noundef signext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1312// CHECK-RV64-NEXT: entry:1313// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmv.s.x.nxv1i32.i64(<vscale x 1 x i32> poison, i32 [[SRC]], i64 [[VL]])1314// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]1315//1316vint32mf2_t test_vmv_s_x_i32mf2(int32_t src, size_t vl) {1317 return __riscv_vmv_s_x_i32mf2(src, vl);1318}1319 1320// CHECK-RV64-LABEL: define dso_local signext i32 @test_vmv_x_s_i32m1_i321321// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {1322// CHECK-RV64-NEXT: entry:1323// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv2i32(<vscale x 2 x i32> [[SRC]])1324// CHECK-RV64-NEXT: ret i32 [[TMP0]]1325//1326int32_t test_vmv_x_s_i32m1_i32(vint32m1_t src) {1327 return __riscv_vmv_x_s_i32m1_i32(src);1328}1329 1330// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vmv_s_x_i32m11331// CHECK-RV64-SAME: (i32 noundef signext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1332// CHECK-RV64-NEXT: entry:1333// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmv.s.x.nxv2i32.i64(<vscale x 2 x i32> poison, i32 [[SRC]], i64 [[VL]])1334// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]1335//1336vint32m1_t test_vmv_s_x_i32m1(int32_t src, size_t vl) {1337 return __riscv_vmv_s_x_i32m1(src, vl);1338}1339 1340// CHECK-RV64-LABEL: define dso_local signext i32 @test_vmv_x_s_i32m2_i321341// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {1342// CHECK-RV64-NEXT: entry:1343// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv4i32(<vscale x 4 x i32> [[SRC]])1344// CHECK-RV64-NEXT: ret i32 [[TMP0]]1345//1346int32_t test_vmv_x_s_i32m2_i32(vint32m2_t src) {1347 return __riscv_vmv_x_s_i32m2_i32(src);1348}1349 1350// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vmv_s_x_i32m21351// CHECK-RV64-SAME: (i32 noundef signext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1352// CHECK-RV64-NEXT: entry:1353// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmv.s.x.nxv4i32.i64(<vscale x 4 x i32> poison, i32 [[SRC]], i64 [[VL]])1354// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]1355//1356vint32m2_t test_vmv_s_x_i32m2(int32_t src, size_t vl) {1357 return __riscv_vmv_s_x_i32m2(src, vl);1358}1359 1360// CHECK-RV64-LABEL: define dso_local signext i32 @test_vmv_x_s_i32m4_i321361// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {1362// CHECK-RV64-NEXT: entry:1363// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv8i32(<vscale x 8 x i32> [[SRC]])1364// CHECK-RV64-NEXT: ret i32 [[TMP0]]1365//1366int32_t test_vmv_x_s_i32m4_i32(vint32m4_t src) {1367 return __riscv_vmv_x_s_i32m4_i32(src);1368}1369 1370// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vmv_s_x_i32m41371// CHECK-RV64-SAME: (i32 noundef signext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1372// CHECK-RV64-NEXT: entry:1373// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmv.s.x.nxv8i32.i64(<vscale x 8 x i32> poison, i32 [[SRC]], i64 [[VL]])1374// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]1375//1376vint32m4_t test_vmv_s_x_i32m4(int32_t src, size_t vl) {1377 return __riscv_vmv_s_x_i32m4(src, vl);1378}1379 1380// CHECK-RV64-LABEL: define dso_local signext i32 @test_vmv_x_s_i32m8_i321381// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {1382// CHECK-RV64-NEXT: entry:1383// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv16i32(<vscale x 16 x i32> [[SRC]])1384// CHECK-RV64-NEXT: ret i32 [[TMP0]]1385//1386int32_t test_vmv_x_s_i32m8_i32(vint32m8_t src) {1387 return __riscv_vmv_x_s_i32m8_i32(src);1388}1389 1390// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vmv_s_x_i32m81391// CHECK-RV64-SAME: (i32 noundef signext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1392// CHECK-RV64-NEXT: entry:1393// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmv.s.x.nxv16i32.i64(<vscale x 16 x i32> poison, i32 [[SRC]], i64 [[VL]])1394// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]1395//1396vint32m8_t test_vmv_s_x_i32m8(int32_t src, size_t vl) {1397 return __riscv_vmv_s_x_i32m8(src, vl);1398}1399 1400// CHECK-RV64-LABEL: define dso_local i64 @test_vmv_x_s_i64m1_i641401// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {1402// CHECK-RV64-NEXT: entry:1403// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vmv.x.s.nxv1i64(<vscale x 1 x i64> [[SRC]])1404// CHECK-RV64-NEXT: ret i64 [[TMP0]]1405//1406int64_t test_vmv_x_s_i64m1_i64(vint64m1_t src) {1407 return __riscv_vmv_x_s_i64m1_i64(src);1408}1409 1410// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vmv_s_x_i64m11411// CHECK-RV64-SAME: (i64 noundef [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1412// CHECK-RV64-NEXT: entry:1413// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmv.s.x.nxv1i64.i64(<vscale x 1 x i64> poison, i64 [[SRC]], i64 [[VL]])1414// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]1415//1416vint64m1_t test_vmv_s_x_i64m1(int64_t src, size_t vl) {1417 return __riscv_vmv_s_x_i64m1(src, vl);1418}1419 1420// CHECK-RV64-LABEL: define dso_local i64 @test_vmv_x_s_i64m2_i641421// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {1422// CHECK-RV64-NEXT: entry:1423// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vmv.x.s.nxv2i64(<vscale x 2 x i64> [[SRC]])1424// CHECK-RV64-NEXT: ret i64 [[TMP0]]1425//1426int64_t test_vmv_x_s_i64m2_i64(vint64m2_t src) {1427 return __riscv_vmv_x_s_i64m2_i64(src);1428}1429 1430// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vmv_s_x_i64m21431// CHECK-RV64-SAME: (i64 noundef [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1432// CHECK-RV64-NEXT: entry:1433// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmv.s.x.nxv2i64.i64(<vscale x 2 x i64> poison, i64 [[SRC]], i64 [[VL]])1434// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]1435//1436vint64m2_t test_vmv_s_x_i64m2(int64_t src, size_t vl) {1437 return __riscv_vmv_s_x_i64m2(src, vl);1438}1439 1440// CHECK-RV64-LABEL: define dso_local i64 @test_vmv_x_s_i64m4_i641441// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {1442// CHECK-RV64-NEXT: entry:1443// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vmv.x.s.nxv4i64(<vscale x 4 x i64> [[SRC]])1444// CHECK-RV64-NEXT: ret i64 [[TMP0]]1445//1446int64_t test_vmv_x_s_i64m4_i64(vint64m4_t src) {1447 return __riscv_vmv_x_s_i64m4_i64(src);1448}1449 1450// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vmv_s_x_i64m41451// CHECK-RV64-SAME: (i64 noundef [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1452// CHECK-RV64-NEXT: entry:1453// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmv.s.x.nxv4i64.i64(<vscale x 4 x i64> poison, i64 [[SRC]], i64 [[VL]])1454// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]1455//1456vint64m4_t test_vmv_s_x_i64m4(int64_t src, size_t vl) {1457 return __riscv_vmv_s_x_i64m4(src, vl);1458}1459 1460// CHECK-RV64-LABEL: define dso_local i64 @test_vmv_x_s_i64m8_i641461// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {1462// CHECK-RV64-NEXT: entry:1463// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vmv.x.s.nxv8i64(<vscale x 8 x i64> [[SRC]])1464// CHECK-RV64-NEXT: ret i64 [[TMP0]]1465//1466int64_t test_vmv_x_s_i64m8_i64(vint64m8_t src) {1467 return __riscv_vmv_x_s_i64m8_i64(src);1468}1469 1470// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vmv_s_x_i64m81471// CHECK-RV64-SAME: (i64 noundef [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1472// CHECK-RV64-NEXT: entry:1473// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmv.s.x.nxv8i64.i64(<vscale x 8 x i64> poison, i64 [[SRC]], i64 [[VL]])1474// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]1475//1476vint64m8_t test_vmv_s_x_i64m8(int64_t src, size_t vl) {1477 return __riscv_vmv_s_x_i64m8(src, vl);1478}1479 1480// CHECK-RV64-LABEL: define dso_local zeroext i8 @test_vmv_x_s_u8mf8_u81481// CHECK-RV64-SAME: (<vscale x 1 x i8> [[SRC:%.*]]) #[[ATTR0]] {1482// CHECK-RV64-NEXT: entry:1483// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv1i8(<vscale x 1 x i8> [[SRC]])1484// CHECK-RV64-NEXT: ret i8 [[TMP0]]1485//1486uint8_t test_vmv_x_s_u8mf8_u8(vuint8mf8_t src) {1487 return __riscv_vmv_x_s_u8mf8_u8(src);1488}1489 1490// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vmv_s_x_u8mf81491// CHECK-RV64-SAME: (i8 noundef zeroext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1492// CHECK-RV64-NEXT: entry:1493// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmv.s.x.nxv1i8.i64(<vscale x 1 x i8> poison, i8 [[SRC]], i64 [[VL]])1494// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]1495//1496vuint8mf8_t test_vmv_s_x_u8mf8(uint8_t src, size_t vl) {1497 return __riscv_vmv_s_x_u8mf8(src, vl);1498}1499 1500// CHECK-RV64-LABEL: define dso_local zeroext i8 @test_vmv_x_s_u8mf4_u81501// CHECK-RV64-SAME: (<vscale x 2 x i8> [[SRC:%.*]]) #[[ATTR0]] {1502// CHECK-RV64-NEXT: entry:1503// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv2i8(<vscale x 2 x i8> [[SRC]])1504// CHECK-RV64-NEXT: ret i8 [[TMP0]]1505//1506uint8_t test_vmv_x_s_u8mf4_u8(vuint8mf4_t src) {1507 return __riscv_vmv_x_s_u8mf4_u8(src);1508}1509 1510// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vmv_s_x_u8mf41511// CHECK-RV64-SAME: (i8 noundef zeroext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1512// CHECK-RV64-NEXT: entry:1513// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmv.s.x.nxv2i8.i64(<vscale x 2 x i8> poison, i8 [[SRC]], i64 [[VL]])1514// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]1515//1516vuint8mf4_t test_vmv_s_x_u8mf4(uint8_t src, size_t vl) {1517 return __riscv_vmv_s_x_u8mf4(src, vl);1518}1519 1520// CHECK-RV64-LABEL: define dso_local zeroext i8 @test_vmv_x_s_u8mf2_u81521// CHECK-RV64-SAME: (<vscale x 4 x i8> [[SRC:%.*]]) #[[ATTR0]] {1522// CHECK-RV64-NEXT: entry:1523// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv4i8(<vscale x 4 x i8> [[SRC]])1524// CHECK-RV64-NEXT: ret i8 [[TMP0]]1525//1526uint8_t test_vmv_x_s_u8mf2_u8(vuint8mf2_t src) {1527 return __riscv_vmv_x_s_u8mf2_u8(src);1528}1529 1530// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vmv_s_x_u8mf21531// CHECK-RV64-SAME: (i8 noundef zeroext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1532// CHECK-RV64-NEXT: entry:1533// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmv.s.x.nxv4i8.i64(<vscale x 4 x i8> poison, i8 [[SRC]], i64 [[VL]])1534// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]1535//1536vuint8mf2_t test_vmv_s_x_u8mf2(uint8_t src, size_t vl) {1537 return __riscv_vmv_s_x_u8mf2(src, vl);1538}1539 1540// CHECK-RV64-LABEL: define dso_local zeroext i8 @test_vmv_x_s_u8m1_u81541// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {1542// CHECK-RV64-NEXT: entry:1543// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv8i8(<vscale x 8 x i8> [[SRC]])1544// CHECK-RV64-NEXT: ret i8 [[TMP0]]1545//1546uint8_t test_vmv_x_s_u8m1_u8(vuint8m1_t src) {1547 return __riscv_vmv_x_s_u8m1_u8(src);1548}1549 1550// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vmv_s_x_u8m11551// CHECK-RV64-SAME: (i8 noundef zeroext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1552// CHECK-RV64-NEXT: entry:1553// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmv.s.x.nxv8i8.i64(<vscale x 8 x i8> poison, i8 [[SRC]], i64 [[VL]])1554// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]1555//1556vuint8m1_t test_vmv_s_x_u8m1(uint8_t src, size_t vl) {1557 return __riscv_vmv_s_x_u8m1(src, vl);1558}1559 1560// CHECK-RV64-LABEL: define dso_local zeroext i8 @test_vmv_x_s_u8m2_u81561// CHECK-RV64-SAME: (<vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {1562// CHECK-RV64-NEXT: entry:1563// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv16i8(<vscale x 16 x i8> [[SRC]])1564// CHECK-RV64-NEXT: ret i8 [[TMP0]]1565//1566uint8_t test_vmv_x_s_u8m2_u8(vuint8m2_t src) {1567 return __riscv_vmv_x_s_u8m2_u8(src);1568}1569 1570// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vmv_s_x_u8m21571// CHECK-RV64-SAME: (i8 noundef zeroext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1572// CHECK-RV64-NEXT: entry:1573// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmv.s.x.nxv16i8.i64(<vscale x 16 x i8> poison, i8 [[SRC]], i64 [[VL]])1574// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]1575//1576vuint8m2_t test_vmv_s_x_u8m2(uint8_t src, size_t vl) {1577 return __riscv_vmv_s_x_u8m2(src, vl);1578}1579 1580// CHECK-RV64-LABEL: define dso_local zeroext i8 @test_vmv_x_s_u8m4_u81581// CHECK-RV64-SAME: (<vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {1582// CHECK-RV64-NEXT: entry:1583// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv32i8(<vscale x 32 x i8> [[SRC]])1584// CHECK-RV64-NEXT: ret i8 [[TMP0]]1585//1586uint8_t test_vmv_x_s_u8m4_u8(vuint8m4_t src) {1587 return __riscv_vmv_x_s_u8m4_u8(src);1588}1589 1590// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vmv_s_x_u8m41591// CHECK-RV64-SAME: (i8 noundef zeroext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1592// CHECK-RV64-NEXT: entry:1593// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmv.s.x.nxv32i8.i64(<vscale x 32 x i8> poison, i8 [[SRC]], i64 [[VL]])1594// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]1595//1596vuint8m4_t test_vmv_s_x_u8m4(uint8_t src, size_t vl) {1597 return __riscv_vmv_s_x_u8m4(src, vl);1598}1599 1600// CHECK-RV64-LABEL: define dso_local zeroext i8 @test_vmv_x_s_u8m8_u81601// CHECK-RV64-SAME: (<vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {1602// CHECK-RV64-NEXT: entry:1603// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv64i8(<vscale x 64 x i8> [[SRC]])1604// CHECK-RV64-NEXT: ret i8 [[TMP0]]1605//1606uint8_t test_vmv_x_s_u8m8_u8(vuint8m8_t src) {1607 return __riscv_vmv_x_s_u8m8_u8(src);1608}1609 1610// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vmv_s_x_u8m81611// CHECK-RV64-SAME: (i8 noundef zeroext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1612// CHECK-RV64-NEXT: entry:1613// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmv.s.x.nxv64i8.i64(<vscale x 64 x i8> poison, i8 [[SRC]], i64 [[VL]])1614// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]1615//1616vuint8m8_t test_vmv_s_x_u8m8(uint8_t src, size_t vl) {1617 return __riscv_vmv_s_x_u8m8(src, vl);1618}1619 1620// CHECK-RV64-LABEL: define dso_local zeroext i16 @test_vmv_x_s_u16mf4_u161621// CHECK-RV64-SAME: (<vscale x 1 x i16> [[SRC:%.*]]) #[[ATTR0]] {1622// CHECK-RV64-NEXT: entry:1623// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv1i16(<vscale x 1 x i16> [[SRC]])1624// CHECK-RV64-NEXT: ret i16 [[TMP0]]1625//1626uint16_t test_vmv_x_s_u16mf4_u16(vuint16mf4_t src) {1627 return __riscv_vmv_x_s_u16mf4_u16(src);1628}1629 1630// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vmv_s_x_u16mf41631// CHECK-RV64-SAME: (i16 noundef zeroext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1632// CHECK-RV64-NEXT: entry:1633// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmv.s.x.nxv1i16.i64(<vscale x 1 x i16> poison, i16 [[SRC]], i64 [[VL]])1634// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]1635//1636vuint16mf4_t test_vmv_s_x_u16mf4(uint16_t src, size_t vl) {1637 return __riscv_vmv_s_x_u16mf4(src, vl);1638}1639 1640// CHECK-RV64-LABEL: define dso_local zeroext i16 @test_vmv_x_s_u16mf2_u161641// CHECK-RV64-SAME: (<vscale x 2 x i16> [[SRC:%.*]]) #[[ATTR0]] {1642// CHECK-RV64-NEXT: entry:1643// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv2i16(<vscale x 2 x i16> [[SRC]])1644// CHECK-RV64-NEXT: ret i16 [[TMP0]]1645//1646uint16_t test_vmv_x_s_u16mf2_u16(vuint16mf2_t src) {1647 return __riscv_vmv_x_s_u16mf2_u16(src);1648}1649 1650// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vmv_s_x_u16mf21651// CHECK-RV64-SAME: (i16 noundef zeroext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1652// CHECK-RV64-NEXT: entry:1653// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmv.s.x.nxv2i16.i64(<vscale x 2 x i16> poison, i16 [[SRC]], i64 [[VL]])1654// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]1655//1656vuint16mf2_t test_vmv_s_x_u16mf2(uint16_t src, size_t vl) {1657 return __riscv_vmv_s_x_u16mf2(src, vl);1658}1659 1660// CHECK-RV64-LABEL: define dso_local zeroext i16 @test_vmv_x_s_u16m1_u161661// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {1662// CHECK-RV64-NEXT: entry:1663// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv4i16(<vscale x 4 x i16> [[SRC]])1664// CHECK-RV64-NEXT: ret i16 [[TMP0]]1665//1666uint16_t test_vmv_x_s_u16m1_u16(vuint16m1_t src) {1667 return __riscv_vmv_x_s_u16m1_u16(src);1668}1669 1670// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vmv_s_x_u16m11671// CHECK-RV64-SAME: (i16 noundef zeroext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1672// CHECK-RV64-NEXT: entry:1673// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmv.s.x.nxv4i16.i64(<vscale x 4 x i16> poison, i16 [[SRC]], i64 [[VL]])1674// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]1675//1676vuint16m1_t test_vmv_s_x_u16m1(uint16_t src, size_t vl) {1677 return __riscv_vmv_s_x_u16m1(src, vl);1678}1679 1680// CHECK-RV64-LABEL: define dso_local zeroext i16 @test_vmv_x_s_u16m2_u161681// CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {1682// CHECK-RV64-NEXT: entry:1683// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv8i16(<vscale x 8 x i16> [[SRC]])1684// CHECK-RV64-NEXT: ret i16 [[TMP0]]1685//1686uint16_t test_vmv_x_s_u16m2_u16(vuint16m2_t src) {1687 return __riscv_vmv_x_s_u16m2_u16(src);1688}1689 1690// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vmv_s_x_u16m21691// CHECK-RV64-SAME: (i16 noundef zeroext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1692// CHECK-RV64-NEXT: entry:1693// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmv.s.x.nxv8i16.i64(<vscale x 8 x i16> poison, i16 [[SRC]], i64 [[VL]])1694// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]1695//1696vuint16m2_t test_vmv_s_x_u16m2(uint16_t src, size_t vl) {1697 return __riscv_vmv_s_x_u16m2(src, vl);1698}1699 1700// CHECK-RV64-LABEL: define dso_local zeroext i16 @test_vmv_x_s_u16m4_u161701// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {1702// CHECK-RV64-NEXT: entry:1703// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv16i16(<vscale x 16 x i16> [[SRC]])1704// CHECK-RV64-NEXT: ret i16 [[TMP0]]1705//1706uint16_t test_vmv_x_s_u16m4_u16(vuint16m4_t src) {1707 return __riscv_vmv_x_s_u16m4_u16(src);1708}1709 1710// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vmv_s_x_u16m41711// CHECK-RV64-SAME: (i16 noundef zeroext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1712// CHECK-RV64-NEXT: entry:1713// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmv.s.x.nxv16i16.i64(<vscale x 16 x i16> poison, i16 [[SRC]], i64 [[VL]])1714// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]1715//1716vuint16m4_t test_vmv_s_x_u16m4(uint16_t src, size_t vl) {1717 return __riscv_vmv_s_x_u16m4(src, vl);1718}1719 1720// CHECK-RV64-LABEL: define dso_local zeroext i16 @test_vmv_x_s_u16m8_u161721// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {1722// CHECK-RV64-NEXT: entry:1723// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv32i16(<vscale x 32 x i16> [[SRC]])1724// CHECK-RV64-NEXT: ret i16 [[TMP0]]1725//1726uint16_t test_vmv_x_s_u16m8_u16(vuint16m8_t src) {1727 return __riscv_vmv_x_s_u16m8_u16(src);1728}1729 1730// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vmv_s_x_u16m81731// CHECK-RV64-SAME: (i16 noundef zeroext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1732// CHECK-RV64-NEXT: entry:1733// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmv.s.x.nxv32i16.i64(<vscale x 32 x i16> poison, i16 [[SRC]], i64 [[VL]])1734// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]1735//1736vuint16m8_t test_vmv_s_x_u16m8(uint16_t src, size_t vl) {1737 return __riscv_vmv_s_x_u16m8(src, vl);1738}1739 1740// CHECK-RV64-LABEL: define dso_local signext i32 @test_vmv_x_s_u32mf2_u321741// CHECK-RV64-SAME: (<vscale x 1 x i32> [[SRC:%.*]]) #[[ATTR0]] {1742// CHECK-RV64-NEXT: entry:1743// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv1i32(<vscale x 1 x i32> [[SRC]])1744// CHECK-RV64-NEXT: ret i32 [[TMP0]]1745//1746uint32_t test_vmv_x_s_u32mf2_u32(vuint32mf2_t src) {1747 return __riscv_vmv_x_s_u32mf2_u32(src);1748}1749 1750// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vmv_s_x_u32mf21751// CHECK-RV64-SAME: (i32 noundef signext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1752// CHECK-RV64-NEXT: entry:1753// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmv.s.x.nxv1i32.i64(<vscale x 1 x i32> poison, i32 [[SRC]], i64 [[VL]])1754// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]1755//1756vuint32mf2_t test_vmv_s_x_u32mf2(uint32_t src, size_t vl) {1757 return __riscv_vmv_s_x_u32mf2(src, vl);1758}1759 1760// CHECK-RV64-LABEL: define dso_local signext i32 @test_vmv_x_s_u32m1_u321761// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {1762// CHECK-RV64-NEXT: entry:1763// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv2i32(<vscale x 2 x i32> [[SRC]])1764// CHECK-RV64-NEXT: ret i32 [[TMP0]]1765//1766uint32_t test_vmv_x_s_u32m1_u32(vuint32m1_t src) {1767 return __riscv_vmv_x_s_u32m1_u32(src);1768}1769 1770// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vmv_s_x_u32m11771// CHECK-RV64-SAME: (i32 noundef signext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1772// CHECK-RV64-NEXT: entry:1773// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmv.s.x.nxv2i32.i64(<vscale x 2 x i32> poison, i32 [[SRC]], i64 [[VL]])1774// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]1775//1776vuint32m1_t test_vmv_s_x_u32m1(uint32_t src, size_t vl) {1777 return __riscv_vmv_s_x_u32m1(src, vl);1778}1779 1780// CHECK-RV64-LABEL: define dso_local signext i32 @test_vmv_x_s_u32m2_u321781// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {1782// CHECK-RV64-NEXT: entry:1783// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv4i32(<vscale x 4 x i32> [[SRC]])1784// CHECK-RV64-NEXT: ret i32 [[TMP0]]1785//1786uint32_t test_vmv_x_s_u32m2_u32(vuint32m2_t src) {1787 return __riscv_vmv_x_s_u32m2_u32(src);1788}1789 1790// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vmv_s_x_u32m21791// CHECK-RV64-SAME: (i32 noundef signext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1792// CHECK-RV64-NEXT: entry:1793// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmv.s.x.nxv4i32.i64(<vscale x 4 x i32> poison, i32 [[SRC]], i64 [[VL]])1794// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]1795//1796vuint32m2_t test_vmv_s_x_u32m2(uint32_t src, size_t vl) {1797 return __riscv_vmv_s_x_u32m2(src, vl);1798}1799 1800// CHECK-RV64-LABEL: define dso_local signext i32 @test_vmv_x_s_u32m4_u321801// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {1802// CHECK-RV64-NEXT: entry:1803// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv8i32(<vscale x 8 x i32> [[SRC]])1804// CHECK-RV64-NEXT: ret i32 [[TMP0]]1805//1806uint32_t test_vmv_x_s_u32m4_u32(vuint32m4_t src) {1807 return __riscv_vmv_x_s_u32m4_u32(src);1808}1809 1810// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vmv_s_x_u32m41811// CHECK-RV64-SAME: (i32 noundef signext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1812// CHECK-RV64-NEXT: entry:1813// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmv.s.x.nxv8i32.i64(<vscale x 8 x i32> poison, i32 [[SRC]], i64 [[VL]])1814// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]1815//1816vuint32m4_t test_vmv_s_x_u32m4(uint32_t src, size_t vl) {1817 return __riscv_vmv_s_x_u32m4(src, vl);1818}1819 1820// CHECK-RV64-LABEL: define dso_local signext i32 @test_vmv_x_s_u32m8_u321821// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {1822// CHECK-RV64-NEXT: entry:1823// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv16i32(<vscale x 16 x i32> [[SRC]])1824// CHECK-RV64-NEXT: ret i32 [[TMP0]]1825//1826uint32_t test_vmv_x_s_u32m8_u32(vuint32m8_t src) {1827 return __riscv_vmv_x_s_u32m8_u32(src);1828}1829 1830// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vmv_s_x_u32m81831// CHECK-RV64-SAME: (i32 noundef signext [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1832// CHECK-RV64-NEXT: entry:1833// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmv.s.x.nxv16i32.i64(<vscale x 16 x i32> poison, i32 [[SRC]], i64 [[VL]])1834// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]1835//1836vuint32m8_t test_vmv_s_x_u32m8(uint32_t src, size_t vl) {1837 return __riscv_vmv_s_x_u32m8(src, vl);1838}1839 1840// CHECK-RV64-LABEL: define dso_local i64 @test_vmv_x_s_u64m1_u641841// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {1842// CHECK-RV64-NEXT: entry:1843// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vmv.x.s.nxv1i64(<vscale x 1 x i64> [[SRC]])1844// CHECK-RV64-NEXT: ret i64 [[TMP0]]1845//1846uint64_t test_vmv_x_s_u64m1_u64(vuint64m1_t src) {1847 return __riscv_vmv_x_s_u64m1_u64(src);1848}1849 1850// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vmv_s_x_u64m11851// CHECK-RV64-SAME: (i64 noundef [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1852// CHECK-RV64-NEXT: entry:1853// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmv.s.x.nxv1i64.i64(<vscale x 1 x i64> poison, i64 [[SRC]], i64 [[VL]])1854// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]1855//1856vuint64m1_t test_vmv_s_x_u64m1(uint64_t src, size_t vl) {1857 return __riscv_vmv_s_x_u64m1(src, vl);1858}1859 1860// CHECK-RV64-LABEL: define dso_local i64 @test_vmv_x_s_u64m2_u641861// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {1862// CHECK-RV64-NEXT: entry:1863// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vmv.x.s.nxv2i64(<vscale x 2 x i64> [[SRC]])1864// CHECK-RV64-NEXT: ret i64 [[TMP0]]1865//1866uint64_t test_vmv_x_s_u64m2_u64(vuint64m2_t src) {1867 return __riscv_vmv_x_s_u64m2_u64(src);1868}1869 1870// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vmv_s_x_u64m21871// CHECK-RV64-SAME: (i64 noundef [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1872// CHECK-RV64-NEXT: entry:1873// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmv.s.x.nxv2i64.i64(<vscale x 2 x i64> poison, i64 [[SRC]], i64 [[VL]])1874// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]1875//1876vuint64m2_t test_vmv_s_x_u64m2(uint64_t src, size_t vl) {1877 return __riscv_vmv_s_x_u64m2(src, vl);1878}1879 1880// CHECK-RV64-LABEL: define dso_local i64 @test_vmv_x_s_u64m4_u641881// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {1882// CHECK-RV64-NEXT: entry:1883// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vmv.x.s.nxv4i64(<vscale x 4 x i64> [[SRC]])1884// CHECK-RV64-NEXT: ret i64 [[TMP0]]1885//1886uint64_t test_vmv_x_s_u64m4_u64(vuint64m4_t src) {1887 return __riscv_vmv_x_s_u64m4_u64(src);1888}1889 1890// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vmv_s_x_u64m41891// CHECK-RV64-SAME: (i64 noundef [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1892// CHECK-RV64-NEXT: entry:1893// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmv.s.x.nxv4i64.i64(<vscale x 4 x i64> poison, i64 [[SRC]], i64 [[VL]])1894// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]1895//1896vuint64m4_t test_vmv_s_x_u64m4(uint64_t src, size_t vl) {1897 return __riscv_vmv_s_x_u64m4(src, vl);1898}1899 1900// CHECK-RV64-LABEL: define dso_local i64 @test_vmv_x_s_u64m8_u641901// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {1902// CHECK-RV64-NEXT: entry:1903// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vmv.x.s.nxv8i64(<vscale x 8 x i64> [[SRC]])1904// CHECK-RV64-NEXT: ret i64 [[TMP0]]1905//1906uint64_t test_vmv_x_s_u64m8_u64(vuint64m8_t src) {1907 return __riscv_vmv_x_s_u64m8_u64(src);1908}1909 1910// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vmv_s_x_u64m81911// CHECK-RV64-SAME: (i64 noundef [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1912// CHECK-RV64-NEXT: entry:1913// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmv.s.x.nxv8i64.i64(<vscale x 8 x i64> poison, i64 [[SRC]], i64 [[VL]])1914// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]1915//1916vuint64m8_t test_vmv_s_x_u64m8(uint64_t src, size_t vl) {1917 return __riscv_vmv_s_x_u64m8(src, vl);1918}1919 1920// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vmv_v_v_bf16mf41921// CHECK-RV64-SAME: (<vscale x 1 x bfloat> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1922// CHECK-RV64-NEXT: entry:1923// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vmv.v.v.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> [[SRC]], i64 [[VL]])1924// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]1925//1926vbfloat16mf4_t test_vmv_v_v_bf16mf4(vbfloat16mf4_t src, size_t vl) {1927 return __riscv_vmv_v_v_bf16mf4(src, vl);1928}1929 1930// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vmv_v_v_bf16mf21931// CHECK-RV64-SAME: (<vscale x 2 x bfloat> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1932// CHECK-RV64-NEXT: entry:1933// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vmv.v.v.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> [[SRC]], i64 [[VL]])1934// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]1935//1936vbfloat16mf2_t test_vmv_v_v_bf16mf2(vbfloat16mf2_t src, size_t vl) {1937 return __riscv_vmv_v_v_bf16mf2(src, vl);1938}1939 1940// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vmv_v_v_bf16m11941// CHECK-RV64-SAME: (<vscale x 4 x bfloat> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1942// CHECK-RV64-NEXT: entry:1943// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vmv.v.v.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> [[SRC]], i64 [[VL]])1944// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]1945//1946vbfloat16m1_t test_vmv_v_v_bf16m1(vbfloat16m1_t src, size_t vl) {1947 return __riscv_vmv_v_v_bf16m1(src, vl);1948}1949 1950// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vmv_v_v_bf16m21951// CHECK-RV64-SAME: (<vscale x 8 x bfloat> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1952// CHECK-RV64-NEXT: entry:1953// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vmv.v.v.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> [[SRC]], i64 [[VL]])1954// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]1955//1956vbfloat16m2_t test_vmv_v_v_bf16m2(vbfloat16m2_t src, size_t vl) {1957 return __riscv_vmv_v_v_bf16m2(src, vl);1958}1959 1960// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vmv_v_v_bf16m41961// CHECK-RV64-SAME: (<vscale x 16 x bfloat> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1962// CHECK-RV64-NEXT: entry:1963// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vmv.v.v.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> [[SRC]], i64 [[VL]])1964// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]1965//1966vbfloat16m4_t test_vmv_v_v_bf16m4(vbfloat16m4_t src, size_t vl) {1967 return __riscv_vmv_v_v_bf16m4(src, vl);1968}1969 1970// CHECK-RV64-LABEL: define dso_local <vscale x 32 x bfloat> @test_vmv_v_v_bf16m81971// CHECK-RV64-SAME: (<vscale x 32 x bfloat> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1972// CHECK-RV64-NEXT: entry:1973// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x bfloat> @llvm.riscv.vmv.v.v.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> [[SRC]], i64 [[VL]])1974// CHECK-RV64-NEXT: ret <vscale x 32 x bfloat> [[TMP0]]1975//1976vbfloat16m8_t test_vmv_v_v_bf16m8(vbfloat16m8_t src, size_t vl) {1977 return __riscv_vmv_v_v_bf16m8(src, vl);1978}1979 1980