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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 22// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone \4// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \5// RUN: FileCheck --check-prefix=CHECK-RV64 %s6 7#include <riscv_vector.h>8 9// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vnclip_wv_i8mf810// CHECK-RV64-SAME: (<vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {11// CHECK-RV64-NEXT: entry:12// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> [[OP1]], <vscale x 1 x i8> [[SHIFT]], i64 0, i64 [[VL]])13// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]14//15vint8mf8_t test_vnclip_wv_i8mf8(vint16mf4_t op1, vuint8mf8_t shift, size_t vl) {16 return __riscv_vnclip_wv_i8mf8(op1, shift, __RISCV_VXRM_RNU, vl);17}18 19// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vnclip_wx_i8mf820// CHECK-RV64-SAME: (<vscale x 1 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {21// CHECK-RV64-NEXT: entry:22// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> [[OP1]], i64 [[SHIFT]], i64 0, i64 [[VL]])23// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]24//25vint8mf8_t test_vnclip_wx_i8mf8(vint16mf4_t op1, size_t shift, size_t vl) {26 return __riscv_vnclip_wx_i8mf8(op1, shift, __RISCV_VXRM_RNU, vl);27}28 29// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vnclip_wv_i8mf430// CHECK-RV64-SAME: (<vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {31// CHECK-RV64-NEXT: entry:32// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> [[OP1]], <vscale x 2 x i8> [[SHIFT]], i64 0, i64 [[VL]])33// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]34//35vint8mf4_t test_vnclip_wv_i8mf4(vint16mf2_t op1, vuint8mf4_t shift, size_t vl) {36 return __riscv_vnclip_wv_i8mf4(op1, shift, __RISCV_VXRM_RNU, vl);37}38 39// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vnclip_wx_i8mf440// CHECK-RV64-SAME: (<vscale x 2 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {41// CHECK-RV64-NEXT: entry:42// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> [[OP1]], i64 [[SHIFT]], i64 0, i64 [[VL]])43// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]44//45vint8mf4_t test_vnclip_wx_i8mf4(vint16mf2_t op1, size_t shift, size_t vl) {46 return __riscv_vnclip_wx_i8mf4(op1, shift, __RISCV_VXRM_RNU, vl);47}48 49// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vnclip_wv_i8mf250// CHECK-RV64-SAME: (<vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {51// CHECK-RV64-NEXT: entry:52// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> [[OP1]], <vscale x 4 x i8> [[SHIFT]], i64 0, i64 [[VL]])53// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]54//55vint8mf2_t test_vnclip_wv_i8mf2(vint16m1_t op1, vuint8mf2_t shift, size_t vl) {56 return __riscv_vnclip_wv_i8mf2(op1, shift, __RISCV_VXRM_RNU, vl);57}58 59// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vnclip_wx_i8mf260// CHECK-RV64-SAME: (<vscale x 4 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {61// CHECK-RV64-NEXT: entry:62// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> [[OP1]], i64 [[SHIFT]], i64 0, i64 [[VL]])63// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]64//65vint8mf2_t test_vnclip_wx_i8mf2(vint16m1_t op1, size_t shift, size_t vl) {66 return __riscv_vnclip_wx_i8mf2(op1, shift, __RISCV_VXRM_RNU, vl);67}68 69// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vnclip_wv_i8m170// CHECK-RV64-SAME: (<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {71// CHECK-RV64-NEXT: entry:72// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> [[OP1]], <vscale x 8 x i8> [[SHIFT]], i64 0, i64 [[VL]])73// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]74//75vint8m1_t test_vnclip_wv_i8m1(vint16m2_t op1, vuint8m1_t shift, size_t vl) {76 return __riscv_vnclip_wv_i8m1(op1, shift, __RISCV_VXRM_RNU, vl);77}78 79// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vnclip_wx_i8m180// CHECK-RV64-SAME: (<vscale x 8 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {81// CHECK-RV64-NEXT: entry:82// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> [[OP1]], i64 [[SHIFT]], i64 0, i64 [[VL]])83// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]84//85vint8m1_t test_vnclip_wx_i8m1(vint16m2_t op1, size_t shift, size_t vl) {86 return __riscv_vnclip_wx_i8m1(op1, shift, __RISCV_VXRM_RNU, vl);87}88 89// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vnclip_wv_i8m290// CHECK-RV64-SAME: (<vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {91// CHECK-RV64-NEXT: entry:92// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> [[OP1]], <vscale x 16 x i8> [[SHIFT]], i64 0, i64 [[VL]])93// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]94//95vint8m2_t test_vnclip_wv_i8m2(vint16m4_t op1, vuint8m2_t shift, size_t vl) {96 return __riscv_vnclip_wv_i8m2(op1, shift, __RISCV_VXRM_RNU, vl);97}98 99// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vnclip_wx_i8m2100// CHECK-RV64-SAME: (<vscale x 16 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {101// CHECK-RV64-NEXT: entry:102// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> [[OP1]], i64 [[SHIFT]], i64 0, i64 [[VL]])103// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]104//105vint8m2_t test_vnclip_wx_i8m2(vint16m4_t op1, size_t shift, size_t vl) {106 return __riscv_vnclip_wx_i8m2(op1, shift, __RISCV_VXRM_RNU, vl);107}108 109// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vnclip_wv_i8m4110// CHECK-RV64-SAME: (<vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {111// CHECK-RV64-NEXT: entry:112// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vnclip.nxv32i8.nxv32i16.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i16> [[OP1]], <vscale x 32 x i8> [[SHIFT]], i64 0, i64 [[VL]])113// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]114//115vint8m4_t test_vnclip_wv_i8m4(vint16m8_t op1, vuint8m4_t shift, size_t vl) {116 return __riscv_vnclip_wv_i8m4(op1, shift, __RISCV_VXRM_RNU, vl);117}118 119// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vnclip_wx_i8m4120// CHECK-RV64-SAME: (<vscale x 32 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {121// CHECK-RV64-NEXT: entry:122// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vnclip.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8> poison, <vscale x 32 x i16> [[OP1]], i64 [[SHIFT]], i64 0, i64 [[VL]])123// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]124//125vint8m4_t test_vnclip_wx_i8m4(vint16m8_t op1, size_t shift, size_t vl) {126 return __riscv_vnclip_wx_i8m4(op1, shift, __RISCV_VXRM_RNU, vl);127}128 129// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vnclip_wv_i16mf4130// CHECK-RV64-SAME: (<vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {131// CHECK-RV64-NEXT: entry:132// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vnclip.nxv1i16.nxv1i32.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i32> [[OP1]], <vscale x 1 x i16> [[SHIFT]], i64 0, i64 [[VL]])133// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]134//135vint16mf4_t test_vnclip_wv_i16mf4(vint32mf2_t op1, vuint16mf4_t shift, size_t vl) {136 return __riscv_vnclip_wv_i16mf4(op1, shift, __RISCV_VXRM_RNU, vl);137}138 139// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vnclip_wx_i16mf4140// CHECK-RV64-SAME: (<vscale x 1 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {141// CHECK-RV64-NEXT: entry:142// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vnclip.nxv1i16.nxv1i32.i64.i64(<vscale x 1 x i16> poison, <vscale x 1 x i32> [[OP1]], i64 [[SHIFT]], i64 0, i64 [[VL]])143// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]144//145vint16mf4_t test_vnclip_wx_i16mf4(vint32mf2_t op1, size_t shift, size_t vl) {146 return __riscv_vnclip_wx_i16mf4(op1, shift, __RISCV_VXRM_RNU, vl);147}148 149// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vnclip_wv_i16mf2150// CHECK-RV64-SAME: (<vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {151// CHECK-RV64-NEXT: entry:152// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vnclip.nxv2i16.nxv2i32.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i32> [[OP1]], <vscale x 2 x i16> [[SHIFT]], i64 0, i64 [[VL]])153// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]154//155vint16mf2_t test_vnclip_wv_i16mf2(vint32m1_t op1, vuint16mf2_t shift, size_t vl) {156 return __riscv_vnclip_wv_i16mf2(op1, shift, __RISCV_VXRM_RNU, vl);157}158 159// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vnclip_wx_i16mf2160// CHECK-RV64-SAME: (<vscale x 2 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {161// CHECK-RV64-NEXT: entry:162// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vnclip.nxv2i16.nxv2i32.i64.i64(<vscale x 2 x i16> poison, <vscale x 2 x i32> [[OP1]], i64 [[SHIFT]], i64 0, i64 [[VL]])163// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]164//165vint16mf2_t test_vnclip_wx_i16mf2(vint32m1_t op1, size_t shift, size_t vl) {166 return __riscv_vnclip_wx_i16mf2(op1, shift, __RISCV_VXRM_RNU, vl);167}168 169// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vnclip_wv_i16m1170// CHECK-RV64-SAME: (<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {171// CHECK-RV64-NEXT: entry:172// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vnclip.nxv4i16.nxv4i32.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i32> [[OP1]], <vscale x 4 x i16> [[SHIFT]], i64 0, i64 [[VL]])173// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]174//175vint16m1_t test_vnclip_wv_i16m1(vint32m2_t op1, vuint16m1_t shift, size_t vl) {176 return __riscv_vnclip_wv_i16m1(op1, shift, __RISCV_VXRM_RNU, vl);177}178 179// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vnclip_wx_i16m1180// CHECK-RV64-SAME: (<vscale x 4 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {181// CHECK-RV64-NEXT: entry:182// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vnclip.nxv4i16.nxv4i32.i64.i64(<vscale x 4 x i16> poison, <vscale x 4 x i32> [[OP1]], i64 [[SHIFT]], i64 0, i64 [[VL]])183// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]184//185vint16m1_t test_vnclip_wx_i16m1(vint32m2_t op1, size_t shift, size_t vl) {186 return __riscv_vnclip_wx_i16m1(op1, shift, __RISCV_VXRM_RNU, vl);187}188 189// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vnclip_wv_i16m2190// CHECK-RV64-SAME: (<vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {191// CHECK-RV64-NEXT: entry:192// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vnclip.nxv8i16.nxv8i32.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i32> [[OP1]], <vscale x 8 x i16> [[SHIFT]], i64 0, i64 [[VL]])193// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]194//195vint16m2_t test_vnclip_wv_i16m2(vint32m4_t op1, vuint16m2_t shift, size_t vl) {196 return __riscv_vnclip_wv_i16m2(op1, shift, __RISCV_VXRM_RNU, vl);197}198 199// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vnclip_wx_i16m2200// CHECK-RV64-SAME: (<vscale x 8 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {201// CHECK-RV64-NEXT: entry:202// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vnclip.nxv8i16.nxv8i32.i64.i64(<vscale x 8 x i16> poison, <vscale x 8 x i32> [[OP1]], i64 [[SHIFT]], i64 0, i64 [[VL]])203// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]204//205vint16m2_t test_vnclip_wx_i16m2(vint32m4_t op1, size_t shift, size_t vl) {206 return __riscv_vnclip_wx_i16m2(op1, shift, __RISCV_VXRM_RNU, vl);207}208 209// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vnclip_wv_i16m4210// CHECK-RV64-SAME: (<vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {211// CHECK-RV64-NEXT: entry:212// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vnclip.nxv16i16.nxv16i32.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i32> [[OP1]], <vscale x 16 x i16> [[SHIFT]], i64 0, i64 [[VL]])213// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]214//215vint16m4_t test_vnclip_wv_i16m4(vint32m8_t op1, vuint16m4_t shift, size_t vl) {216 return __riscv_vnclip_wv_i16m4(op1, shift, __RISCV_VXRM_RNU, vl);217}218 219// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vnclip_wx_i16m4220// CHECK-RV64-SAME: (<vscale x 16 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {221// CHECK-RV64-NEXT: entry:222// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vnclip.nxv16i16.nxv16i32.i64.i64(<vscale x 16 x i16> poison, <vscale x 16 x i32> [[OP1]], i64 [[SHIFT]], i64 0, i64 [[VL]])223// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]224//225vint16m4_t test_vnclip_wx_i16m4(vint32m8_t op1, size_t shift, size_t vl) {226 return __riscv_vnclip_wx_i16m4(op1, shift, __RISCV_VXRM_RNU, vl);227}228 229// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vnclip_wv_i32mf2230// CHECK-RV64-SAME: (<vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {231// CHECK-RV64-NEXT: entry:232// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vnclip.nxv1i32.nxv1i64.nxv1i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i64> [[OP1]], <vscale x 1 x i32> [[SHIFT]], i64 0, i64 [[VL]])233// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]234//235vint32mf2_t test_vnclip_wv_i32mf2(vint64m1_t op1, vuint32mf2_t shift, size_t vl) {236 return __riscv_vnclip_wv_i32mf2(op1, shift, __RISCV_VXRM_RNU, vl);237}238 239// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vnclip_wx_i32mf2240// CHECK-RV64-SAME: (<vscale x 1 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {241// CHECK-RV64-NEXT: entry:242// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vnclip.nxv1i32.nxv1i64.i64.i64(<vscale x 1 x i32> poison, <vscale x 1 x i64> [[OP1]], i64 [[SHIFT]], i64 0, i64 [[VL]])243// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]244//245vint32mf2_t test_vnclip_wx_i32mf2(vint64m1_t op1, size_t shift, size_t vl) {246 return __riscv_vnclip_wx_i32mf2(op1, shift, __RISCV_VXRM_RNU, vl);247}248 249// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vnclip_wv_i32m1250// CHECK-RV64-SAME: (<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {251// CHECK-RV64-NEXT: entry:252// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vnclip.nxv2i32.nxv2i64.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i64> [[OP1]], <vscale x 2 x i32> [[SHIFT]], i64 0, i64 [[VL]])253// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]254//255vint32m1_t test_vnclip_wv_i32m1(vint64m2_t op1, vuint32m1_t shift, size_t vl) {256 return __riscv_vnclip_wv_i32m1(op1, shift, __RISCV_VXRM_RNU, vl);257}258 259// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vnclip_wx_i32m1260// CHECK-RV64-SAME: (<vscale x 2 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {261// CHECK-RV64-NEXT: entry:262// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vnclip.nxv2i32.nxv2i64.i64.i64(<vscale x 2 x i32> poison, <vscale x 2 x i64> [[OP1]], i64 [[SHIFT]], i64 0, i64 [[VL]])263// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]264//265vint32m1_t test_vnclip_wx_i32m1(vint64m2_t op1, size_t shift, size_t vl) {266 return __riscv_vnclip_wx_i32m1(op1, shift, __RISCV_VXRM_RNU, vl);267}268 269// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vnclip_wv_i32m2270// CHECK-RV64-SAME: (<vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {271// CHECK-RV64-NEXT: entry:272// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vnclip.nxv4i32.nxv4i64.nxv4i32.i64(<vscale x 4 x i32> poison, <vscale x 4 x i64> [[OP1]], <vscale x 4 x i32> [[SHIFT]], i64 0, i64 [[VL]])273// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]274//275vint32m2_t test_vnclip_wv_i32m2(vint64m4_t op1, vuint32m2_t shift, size_t vl) {276 return __riscv_vnclip_wv_i32m2(op1, shift, __RISCV_VXRM_RNU, vl);277}278 279// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vnclip_wx_i32m2280// CHECK-RV64-SAME: (<vscale x 4 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {281// CHECK-RV64-NEXT: entry:282// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vnclip.nxv4i32.nxv4i64.i64.i64(<vscale x 4 x i32> poison, <vscale x 4 x i64> [[OP1]], i64 [[SHIFT]], i64 0, i64 [[VL]])283// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]284//285vint32m2_t test_vnclip_wx_i32m2(vint64m4_t op1, size_t shift, size_t vl) {286 return __riscv_vnclip_wx_i32m2(op1, shift, __RISCV_VXRM_RNU, vl);287}288 289// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vnclip_wv_i32m4290// CHECK-RV64-SAME: (<vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {291// CHECK-RV64-NEXT: entry:292// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vnclip.nxv8i32.nxv8i64.nxv8i32.i64(<vscale x 8 x i32> poison, <vscale x 8 x i64> [[OP1]], <vscale x 8 x i32> [[SHIFT]], i64 0, i64 [[VL]])293// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]294//295vint32m4_t test_vnclip_wv_i32m4(vint64m8_t op1, vuint32m4_t shift, size_t vl) {296 return __riscv_vnclip_wv_i32m4(op1, shift, __RISCV_VXRM_RNU, vl);297}298 299// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vnclip_wx_i32m4300// CHECK-RV64-SAME: (<vscale x 8 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {301// CHECK-RV64-NEXT: entry:302// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vnclip.nxv8i32.nxv8i64.i64.i64(<vscale x 8 x i32> poison, <vscale x 8 x i64> [[OP1]], i64 [[SHIFT]], i64 0, i64 [[VL]])303// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]304//305vint32m4_t test_vnclip_wx_i32m4(vint64m8_t op1, size_t shift, size_t vl) {306 return __riscv_vnclip_wx_i32m4(op1, shift, __RISCV_VXRM_RNU, vl);307}308 309// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vnclip_wv_i8mf8_m310// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {311// CHECK-RV64-NEXT: entry:312// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vnclip.mask.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> [[OP1]], <vscale x 1 x i8> [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)313// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]314//315vint8mf8_t test_vnclip_wv_i8mf8_m(vbool64_t mask, vint16mf4_t op1, vuint8mf8_t shift, size_t vl) {316 return __riscv_vnclip_wv_i8mf8_m(mask, op1, shift, __RISCV_VXRM_RNU, vl);317}318 319// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vnclip_wx_i8mf8_m320// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {321// CHECK-RV64-NEXT: entry:322// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vnclip.mask.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)323// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]324//325vint8mf8_t test_vnclip_wx_i8mf8_m(vbool64_t mask, vint16mf4_t op1, size_t shift, size_t vl) {326 return __riscv_vnclip_wx_i8mf8_m(mask, op1, shift, __RISCV_VXRM_RNU, vl);327}328 329// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vnclip_wv_i8mf4_m330// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {331// CHECK-RV64-NEXT: entry:332// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vnclip.mask.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> [[OP1]], <vscale x 2 x i8> [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)333// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]334//335vint8mf4_t test_vnclip_wv_i8mf4_m(vbool32_t mask, vint16mf2_t op1, vuint8mf4_t shift, size_t vl) {336 return __riscv_vnclip_wv_i8mf4_m(mask, op1, shift, __RISCV_VXRM_RNU, vl);337}338 339// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vnclip_wx_i8mf4_m340// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {341// CHECK-RV64-NEXT: entry:342// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vnclip.mask.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)343// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]344//345vint8mf4_t test_vnclip_wx_i8mf4_m(vbool32_t mask, vint16mf2_t op1, size_t shift, size_t vl) {346 return __riscv_vnclip_wx_i8mf4_m(mask, op1, shift, __RISCV_VXRM_RNU, vl);347}348 349// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vnclip_wv_i8mf2_m350// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {351// CHECK-RV64-NEXT: entry:352// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vnclip.mask.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> [[OP1]], <vscale x 4 x i8> [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)353// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]354//355vint8mf2_t test_vnclip_wv_i8mf2_m(vbool16_t mask, vint16m1_t op1, vuint8mf2_t shift, size_t vl) {356 return __riscv_vnclip_wv_i8mf2_m(mask, op1, shift, __RISCV_VXRM_RNU, vl);357}358 359// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vnclip_wx_i8mf2_m360// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {361// CHECK-RV64-NEXT: entry:362// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vnclip.mask.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)363// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]364//365vint8mf2_t test_vnclip_wx_i8mf2_m(vbool16_t mask, vint16m1_t op1, size_t shift, size_t vl) {366 return __riscv_vnclip_wx_i8mf2_m(mask, op1, shift, __RISCV_VXRM_RNU, vl);367}368 369// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vnclip_wv_i8m1_m370// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {371// CHECK-RV64-NEXT: entry:372// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vnclip.mask.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> [[OP1]], <vscale x 8 x i8> [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)373// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]374//375vint8m1_t test_vnclip_wv_i8m1_m(vbool8_t mask, vint16m2_t op1, vuint8m1_t shift, size_t vl) {376 return __riscv_vnclip_wv_i8m1_m(mask, op1, shift, __RISCV_VXRM_RNU, vl);377}378 379// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vnclip_wx_i8m1_m380// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {381// CHECK-RV64-NEXT: entry:382// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vnclip.mask.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)383// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]384//385vint8m1_t test_vnclip_wx_i8m1_m(vbool8_t mask, vint16m2_t op1, size_t shift, size_t vl) {386 return __riscv_vnclip_wx_i8m1_m(mask, op1, shift, __RISCV_VXRM_RNU, vl);387}388 389// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vnclip_wv_i8m2_m390// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {391// CHECK-RV64-NEXT: entry:392// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vnclip.mask.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> [[OP1]], <vscale x 16 x i8> [[SHIFT]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)393// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]394//395vint8m2_t test_vnclip_wv_i8m2_m(vbool4_t mask, vint16m4_t op1, vuint8m2_t shift, size_t vl) {396 return __riscv_vnclip_wv_i8m2_m(mask, op1, shift, __RISCV_VXRM_RNU, vl);397}398 399// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vnclip_wx_i8m2_m400// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {401// CHECK-RV64-NEXT: entry:402// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vnclip.mask.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)403// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]404//405vint8m2_t test_vnclip_wx_i8m2_m(vbool4_t mask, vint16m4_t op1, size_t shift, size_t vl) {406 return __riscv_vnclip_wx_i8m2_m(mask, op1, shift, __RISCV_VXRM_RNU, vl);407}408 409// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vnclip_wv_i8m4_m410// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {411// CHECK-RV64-NEXT: entry:412// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vnclip.mask.nxv32i8.nxv32i16.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i16> [[OP1]], <vscale x 32 x i8> [[SHIFT]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)413// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]414//415vint8m4_t test_vnclip_wv_i8m4_m(vbool2_t mask, vint16m8_t op1, vuint8m4_t shift, size_t vl) {416 return __riscv_vnclip_wv_i8m4_m(mask, op1, shift, __RISCV_VXRM_RNU, vl);417}418 419// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vnclip_wx_i8m4_m420// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {421// CHECK-RV64-NEXT: entry:422// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vnclip.mask.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8> poison, <vscale x 32 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)423// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]424//425vint8m4_t test_vnclip_wx_i8m4_m(vbool2_t mask, vint16m8_t op1, size_t shift, size_t vl) {426 return __riscv_vnclip_wx_i8m4_m(mask, op1, shift, __RISCV_VXRM_RNU, vl);427}428 429// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vnclip_wv_i16mf4_m430// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {431// CHECK-RV64-NEXT: entry:432// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vnclip.mask.nxv1i16.nxv1i32.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i32> [[OP1]], <vscale x 1 x i16> [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)433// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]434//435vint16mf4_t test_vnclip_wv_i16mf4_m(vbool64_t mask, vint32mf2_t op1, vuint16mf4_t shift, size_t vl) {436 return __riscv_vnclip_wv_i16mf4_m(mask, op1, shift, __RISCV_VXRM_RNU, vl);437}438 439// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vnclip_wx_i16mf4_m440// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {441// CHECK-RV64-NEXT: entry:442// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vnclip.mask.nxv1i16.nxv1i32.i64.i64(<vscale x 1 x i16> poison, <vscale x 1 x i32> [[OP1]], i64 [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)443// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]444//445vint16mf4_t test_vnclip_wx_i16mf4_m(vbool64_t mask, vint32mf2_t op1, size_t shift, size_t vl) {446 return __riscv_vnclip_wx_i16mf4_m(mask, op1, shift, __RISCV_VXRM_RNU, vl);447}448 449// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vnclip_wv_i16mf2_m450// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {451// CHECK-RV64-NEXT: entry:452// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vnclip.mask.nxv2i16.nxv2i32.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i32> [[OP1]], <vscale x 2 x i16> [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)453// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]454//455vint16mf2_t test_vnclip_wv_i16mf2_m(vbool32_t mask, vint32m1_t op1, vuint16mf2_t shift, size_t vl) {456 return __riscv_vnclip_wv_i16mf2_m(mask, op1, shift, __RISCV_VXRM_RNU, vl);457}458 459// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vnclip_wx_i16mf2_m460// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {461// CHECK-RV64-NEXT: entry:462// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vnclip.mask.nxv2i16.nxv2i32.i64.i64(<vscale x 2 x i16> poison, <vscale x 2 x i32> [[OP1]], i64 [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)463// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]464//465vint16mf2_t test_vnclip_wx_i16mf2_m(vbool32_t mask, vint32m1_t op1, size_t shift, size_t vl) {466 return __riscv_vnclip_wx_i16mf2_m(mask, op1, shift, __RISCV_VXRM_RNU, vl);467}468 469// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vnclip_wv_i16m1_m470// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {471// CHECK-RV64-NEXT: entry:472// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vnclip.mask.nxv4i16.nxv4i32.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i32> [[OP1]], <vscale x 4 x i16> [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)473// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]474//475vint16m1_t test_vnclip_wv_i16m1_m(vbool16_t mask, vint32m2_t op1, vuint16m1_t shift, size_t vl) {476 return __riscv_vnclip_wv_i16m1_m(mask, op1, shift, __RISCV_VXRM_RNU, vl);477}478 479// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vnclip_wx_i16m1_m480// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {481// CHECK-RV64-NEXT: entry:482// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vnclip.mask.nxv4i16.nxv4i32.i64.i64(<vscale x 4 x i16> poison, <vscale x 4 x i32> [[OP1]], i64 [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)483// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]484//485vint16m1_t test_vnclip_wx_i16m1_m(vbool16_t mask, vint32m2_t op1, size_t shift, size_t vl) {486 return __riscv_vnclip_wx_i16m1_m(mask, op1, shift, __RISCV_VXRM_RNU, vl);487}488 489// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vnclip_wv_i16m2_m490// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {491// CHECK-RV64-NEXT: entry:492// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vnclip.mask.nxv8i16.nxv8i32.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i32> [[OP1]], <vscale x 8 x i16> [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)493// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]494//495vint16m2_t test_vnclip_wv_i16m2_m(vbool8_t mask, vint32m4_t op1, vuint16m2_t shift, size_t vl) {496 return __riscv_vnclip_wv_i16m2_m(mask, op1, shift, __RISCV_VXRM_RNU, vl);497}498 499// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vnclip_wx_i16m2_m500// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {501// CHECK-RV64-NEXT: entry:502// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vnclip.mask.nxv8i16.nxv8i32.i64.i64(<vscale x 8 x i16> poison, <vscale x 8 x i32> [[OP1]], i64 [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)503// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]504//505vint16m2_t test_vnclip_wx_i16m2_m(vbool8_t mask, vint32m4_t op1, size_t shift, size_t vl) {506 return __riscv_vnclip_wx_i16m2_m(mask, op1, shift, __RISCV_VXRM_RNU, vl);507}508 509// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vnclip_wv_i16m4_m510// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {511// CHECK-RV64-NEXT: entry:512// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vnclip.mask.nxv16i16.nxv16i32.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i32> [[OP1]], <vscale x 16 x i16> [[SHIFT]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)513// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]514//515vint16m4_t test_vnclip_wv_i16m4_m(vbool4_t mask, vint32m8_t op1, vuint16m4_t shift, size_t vl) {516 return __riscv_vnclip_wv_i16m4_m(mask, op1, shift, __RISCV_VXRM_RNU, vl);517}518 519// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vnclip_wx_i16m4_m520// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {521// CHECK-RV64-NEXT: entry:522// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vnclip.mask.nxv16i16.nxv16i32.i64.i64(<vscale x 16 x i16> poison, <vscale x 16 x i32> [[OP1]], i64 [[SHIFT]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)523// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]524//525vint16m4_t test_vnclip_wx_i16m4_m(vbool4_t mask, vint32m8_t op1, size_t shift, size_t vl) {526 return __riscv_vnclip_wx_i16m4_m(mask, op1, shift, __RISCV_VXRM_RNU, vl);527}528 529// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vnclip_wv_i32mf2_m530// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {531// CHECK-RV64-NEXT: entry:532// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vnclip.mask.nxv1i32.nxv1i64.nxv1i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i64> [[OP1]], <vscale x 1 x i32> [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)533// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]534//535vint32mf2_t test_vnclip_wv_i32mf2_m(vbool64_t mask, vint64m1_t op1, vuint32mf2_t shift, size_t vl) {536 return __riscv_vnclip_wv_i32mf2_m(mask, op1, shift, __RISCV_VXRM_RNU, vl);537}538 539// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vnclip_wx_i32mf2_m540// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {541// CHECK-RV64-NEXT: entry:542// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vnclip.mask.nxv1i32.nxv1i64.i64.i64(<vscale x 1 x i32> poison, <vscale x 1 x i64> [[OP1]], i64 [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)543// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]544//545vint32mf2_t test_vnclip_wx_i32mf2_m(vbool64_t mask, vint64m1_t op1, size_t shift, size_t vl) {546 return __riscv_vnclip_wx_i32mf2_m(mask, op1, shift, __RISCV_VXRM_RNU, vl);547}548 549// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vnclip_wv_i32m1_m550// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {551// CHECK-RV64-NEXT: entry:552// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vnclip.mask.nxv2i32.nxv2i64.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i64> [[OP1]], <vscale x 2 x i32> [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)553// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]554//555vint32m1_t test_vnclip_wv_i32m1_m(vbool32_t mask, vint64m2_t op1, vuint32m1_t shift, size_t vl) {556 return __riscv_vnclip_wv_i32m1_m(mask, op1, shift, __RISCV_VXRM_RNU, vl);557}558 559// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vnclip_wx_i32m1_m560// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {561// CHECK-RV64-NEXT: entry:562// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vnclip.mask.nxv2i32.nxv2i64.i64.i64(<vscale x 2 x i32> poison, <vscale x 2 x i64> [[OP1]], i64 [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)563// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]564//565vint32m1_t test_vnclip_wx_i32m1_m(vbool32_t mask, vint64m2_t op1, size_t shift, size_t vl) {566 return __riscv_vnclip_wx_i32m1_m(mask, op1, shift, __RISCV_VXRM_RNU, vl);567}568 569// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vnclip_wv_i32m2_m570// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {571// CHECK-RV64-NEXT: entry:572// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vnclip.mask.nxv4i32.nxv4i64.nxv4i32.i64(<vscale x 4 x i32> poison, <vscale x 4 x i64> [[OP1]], <vscale x 4 x i32> [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)573// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]574//575vint32m2_t test_vnclip_wv_i32m2_m(vbool16_t mask, vint64m4_t op1, vuint32m2_t shift, size_t vl) {576 return __riscv_vnclip_wv_i32m2_m(mask, op1, shift, __RISCV_VXRM_RNU, vl);577}578 579// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vnclip_wx_i32m2_m580// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {581// CHECK-RV64-NEXT: entry:582// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vnclip.mask.nxv4i32.nxv4i64.i64.i64(<vscale x 4 x i32> poison, <vscale x 4 x i64> [[OP1]], i64 [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)583// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]584//585vint32m2_t test_vnclip_wx_i32m2_m(vbool16_t mask, vint64m4_t op1, size_t shift, size_t vl) {586 return __riscv_vnclip_wx_i32m2_m(mask, op1, shift, __RISCV_VXRM_RNU, vl);587}588 589// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vnclip_wv_i32m4_m590// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {591// CHECK-RV64-NEXT: entry:592// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vnclip.mask.nxv8i32.nxv8i64.nxv8i32.i64(<vscale x 8 x i32> poison, <vscale x 8 x i64> [[OP1]], <vscale x 8 x i32> [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)593// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]594//595vint32m4_t test_vnclip_wv_i32m4_m(vbool8_t mask, vint64m8_t op1, vuint32m4_t shift, size_t vl) {596 return __riscv_vnclip_wv_i32m4_m(mask, op1, shift, __RISCV_VXRM_RNU, vl);597}598 599// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vnclip_wx_i32m4_m600// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {601// CHECK-RV64-NEXT: entry:602// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vnclip.mask.nxv8i32.nxv8i64.i64.i64(<vscale x 8 x i32> poison, <vscale x 8 x i64> [[OP1]], i64 [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)603// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]604//605vint32m4_t test_vnclip_wx_i32m4_m(vbool8_t mask, vint64m8_t op1, size_t shift, size_t vl) {606 return __riscv_vnclip_wx_i32m4_m(mask, op1, shift, __RISCV_VXRM_RNU, vl);607}608 609