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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 22// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \4// RUN: -target-feature +zvfh -disable-O0-optnone \5// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \6// RUN: FileCheck --check-prefix=CHECK-RV64 %s7 8#include <riscv_vector.h>9 10// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vneg_v_i8mf811// CHECK-RV64-SAME: (<vscale x 1 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {12// CHECK-RV64-NEXT: entry:13// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> [[OP1]], i8 0, i64 [[VL]])14// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]15//16vint8mf8_t test_vneg_v_i8mf8(vint8mf8_t op1, size_t vl) {17 return __riscv_vneg_v_i8mf8(op1, vl);18}19 20// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vneg_v_i8mf421// CHECK-RV64-SAME: (<vscale x 2 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {22// CHECK-RV64-NEXT: entry:23// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> [[OP1]], i8 0, i64 [[VL]])24// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]25//26vint8mf4_t test_vneg_v_i8mf4(vint8mf4_t op1, size_t vl) {27 return __riscv_vneg_v_i8mf4(op1, vl);28}29 30// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vneg_v_i8mf231// CHECK-RV64-SAME: (<vscale x 4 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {32// CHECK-RV64-NEXT: entry:33// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> [[OP1]], i8 0, i64 [[VL]])34// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]35//36vint8mf2_t test_vneg_v_i8mf2(vint8mf2_t op1, size_t vl) {37 return __riscv_vneg_v_i8mf2(op1, vl);38}39 40// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vneg_v_i8m141// CHECK-RV64-SAME: (<vscale x 8 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {42// CHECK-RV64-NEXT: entry:43// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> [[OP1]], i8 0, i64 [[VL]])44// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]45//46vint8m1_t test_vneg_v_i8m1(vint8m1_t op1, size_t vl) {47 return __riscv_vneg_v_i8m1(op1, vl);48}49 50// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vneg_v_i8m251// CHECK-RV64-SAME: (<vscale x 16 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {52// CHECK-RV64-NEXT: entry:53// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> [[OP1]], i8 0, i64 [[VL]])54// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]55//56vint8m2_t test_vneg_v_i8m2(vint8m2_t op1, size_t vl) {57 return __riscv_vneg_v_i8m2(op1, vl);58}59 60// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vneg_v_i8m461// CHECK-RV64-SAME: (<vscale x 32 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {62// CHECK-RV64-NEXT: entry:63// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> [[OP1]], i8 0, i64 [[VL]])64// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]65//66vint8m4_t test_vneg_v_i8m4(vint8m4_t op1, size_t vl) {67 return __riscv_vneg_v_i8m4(op1, vl);68}69 70// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vneg_v_i8m871// CHECK-RV64-SAME: (<vscale x 64 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {72// CHECK-RV64-NEXT: entry:73// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> [[OP1]], i8 0, i64 [[VL]])74// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]75//76vint8m8_t test_vneg_v_i8m8(vint8m8_t op1, size_t vl) {77 return __riscv_vneg_v_i8m8(op1, vl);78}79 80// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vneg_v_i16mf481// CHECK-RV64-SAME: (<vscale x 1 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {82// CHECK-RV64-NEXT: entry:83// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[OP1]], i16 0, i64 [[VL]])84// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]85//86vint16mf4_t test_vneg_v_i16mf4(vint16mf4_t op1, size_t vl) {87 return __riscv_vneg_v_i16mf4(op1, vl);88}89 90// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vneg_v_i16mf291// CHECK-RV64-SAME: (<vscale x 2 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {92// CHECK-RV64-NEXT: entry:93// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> [[OP1]], i16 0, i64 [[VL]])94// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]95//96vint16mf2_t test_vneg_v_i16mf2(vint16mf2_t op1, size_t vl) {97 return __riscv_vneg_v_i16mf2(op1, vl);98}99 100// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vneg_v_i16m1101// CHECK-RV64-SAME: (<vscale x 4 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {102// CHECK-RV64-NEXT: entry:103// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> [[OP1]], i16 0, i64 [[VL]])104// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]105//106vint16m1_t test_vneg_v_i16m1(vint16m1_t op1, size_t vl) {107 return __riscv_vneg_v_i16m1(op1, vl);108}109 110// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vneg_v_i16m2111// CHECK-RV64-SAME: (<vscale x 8 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {112// CHECK-RV64-NEXT: entry:113// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vrsub.nxv8i16.i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> [[OP1]], i16 0, i64 [[VL]])114// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]115//116vint16m2_t test_vneg_v_i16m2(vint16m2_t op1, size_t vl) {117 return __riscv_vneg_v_i16m2(op1, vl);118}119 120// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vneg_v_i16m4121// CHECK-RV64-SAME: (<vscale x 16 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {122// CHECK-RV64-NEXT: entry:123// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vrsub.nxv16i16.i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> [[OP1]], i16 0, i64 [[VL]])124// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]125//126vint16m4_t test_vneg_v_i16m4(vint16m4_t op1, size_t vl) {127 return __riscv_vneg_v_i16m4(op1, vl);128}129 130// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vneg_v_i16m8131// CHECK-RV64-SAME: (<vscale x 32 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {132// CHECK-RV64-NEXT: entry:133// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vrsub.nxv32i16.i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> [[OP1]], i16 0, i64 [[VL]])134// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]135//136vint16m8_t test_vneg_v_i16m8(vint16m8_t op1, size_t vl) {137 return __riscv_vneg_v_i16m8(op1, vl);138}139 140// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vneg_v_i32mf2141// CHECK-RV64-SAME: (<vscale x 1 x i32> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {142// CHECK-RV64-NEXT: entry:143// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vrsub.nxv1i32.i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[OP1]], i32 0, i64 [[VL]])144// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]145//146vint32mf2_t test_vneg_v_i32mf2(vint32mf2_t op1, size_t vl) {147 return __riscv_vneg_v_i32mf2(op1, vl);148}149 150// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vneg_v_i32m1151// CHECK-RV64-SAME: (<vscale x 2 x i32> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {152// CHECK-RV64-NEXT: entry:153// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vrsub.nxv2i32.i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[OP1]], i32 0, i64 [[VL]])154// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]155//156vint32m1_t test_vneg_v_i32m1(vint32m1_t op1, size_t vl) {157 return __riscv_vneg_v_i32m1(op1, vl);158}159 160// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vneg_v_i32m2161// CHECK-RV64-SAME: (<vscale x 4 x i32> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {162// CHECK-RV64-NEXT: entry:163// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vrsub.nxv4i32.i32.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> [[OP1]], i32 0, i64 [[VL]])164// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]165//166vint32m2_t test_vneg_v_i32m2(vint32m2_t op1, size_t vl) {167 return __riscv_vneg_v_i32m2(op1, vl);168}169 170// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vneg_v_i32m4171// CHECK-RV64-SAME: (<vscale x 8 x i32> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {172// CHECK-RV64-NEXT: entry:173// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vrsub.nxv8i32.i32.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> [[OP1]], i32 0, i64 [[VL]])174// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]175//176vint32m4_t test_vneg_v_i32m4(vint32m4_t op1, size_t vl) {177 return __riscv_vneg_v_i32m4(op1, vl);178}179 180// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vneg_v_i32m8181// CHECK-RV64-SAME: (<vscale x 16 x i32> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {182// CHECK-RV64-NEXT: entry:183// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vrsub.nxv16i32.i32.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> [[OP1]], i32 0, i64 [[VL]])184// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]185//186vint32m8_t test_vneg_v_i32m8(vint32m8_t op1, size_t vl) {187 return __riscv_vneg_v_i32m8(op1, vl);188}189 190// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vneg_v_i64m1191// CHECK-RV64-SAME: (<vscale x 1 x i64> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {192// CHECK-RV64-NEXT: entry:193// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vrsub.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> [[OP1]], i64 0, i64 [[VL]])194// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]195//196vint64m1_t test_vneg_v_i64m1(vint64m1_t op1, size_t vl) {197 return __riscv_vneg_v_i64m1(op1, vl);198}199 200// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vneg_v_i64m2201// CHECK-RV64-SAME: (<vscale x 2 x i64> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {202// CHECK-RV64-NEXT: entry:203// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vrsub.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> [[OP1]], i64 0, i64 [[VL]])204// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]205//206vint64m2_t test_vneg_v_i64m2(vint64m2_t op1, size_t vl) {207 return __riscv_vneg_v_i64m2(op1, vl);208}209 210// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vneg_v_i64m4211// CHECK-RV64-SAME: (<vscale x 4 x i64> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {212// CHECK-RV64-NEXT: entry:213// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vrsub.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> [[OP1]], i64 0, i64 [[VL]])214// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]215//216vint64m4_t test_vneg_v_i64m4(vint64m4_t op1, size_t vl) {217 return __riscv_vneg_v_i64m4(op1, vl);218}219 220// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vneg_v_i64m8221// CHECK-RV64-SAME: (<vscale x 8 x i64> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {222// CHECK-RV64-NEXT: entry:223// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vrsub.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> [[OP1]], i64 0, i64 [[VL]])224// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]225//226vint64m8_t test_vneg_v_i64m8(vint64m8_t op1, size_t vl) {227 return __riscv_vneg_v_i64m8(op1, vl);228}229 230// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vneg_v_i8mf8_m231// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {232// CHECK-RV64-NEXT: entry:233// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vrsub.mask.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> [[OP1]], i8 0, <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)234// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]235//236vint8mf8_t test_vneg_v_i8mf8_m(vbool64_t mask, vint8mf8_t op1, size_t vl) {237 return __riscv_vneg_v_i8mf8_m(mask, op1, vl);238}239 240// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vneg_v_i8mf4_m241// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {242// CHECK-RV64-NEXT: entry:243// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vrsub.mask.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> [[OP1]], i8 0, <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)244// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]245//246vint8mf4_t test_vneg_v_i8mf4_m(vbool32_t mask, vint8mf4_t op1, size_t vl) {247 return __riscv_vneg_v_i8mf4_m(mask, op1, vl);248}249 250// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vneg_v_i8mf2_m251// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {252// CHECK-RV64-NEXT: entry:253// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vrsub.mask.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> [[OP1]], i8 0, <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)254// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]255//256vint8mf2_t test_vneg_v_i8mf2_m(vbool16_t mask, vint8mf2_t op1, size_t vl) {257 return __riscv_vneg_v_i8mf2_m(mask, op1, vl);258}259 260// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vneg_v_i8m1_m261// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {262// CHECK-RV64-NEXT: entry:263// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vrsub.mask.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> [[OP1]], i8 0, <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)264// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]265//266vint8m1_t test_vneg_v_i8m1_m(vbool8_t mask, vint8m1_t op1, size_t vl) {267 return __riscv_vneg_v_i8m1_m(mask, op1, vl);268}269 270// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vneg_v_i8m2_m271// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {272// CHECK-RV64-NEXT: entry:273// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vrsub.mask.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> [[OP1]], i8 0, <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3)274// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]275//276vint8m2_t test_vneg_v_i8m2_m(vbool4_t mask, vint8m2_t op1, size_t vl) {277 return __riscv_vneg_v_i8m2_m(mask, op1, vl);278}279 280// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vneg_v_i8m4_m281// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {282// CHECK-RV64-NEXT: entry:283// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vrsub.mask.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> [[OP1]], i8 0, <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3)284// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]285//286vint8m4_t test_vneg_v_i8m4_m(vbool2_t mask, vint8m4_t op1, size_t vl) {287 return __riscv_vneg_v_i8m4_m(mask, op1, vl);288}289 290// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vneg_v_i8m8_m291// CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {292// CHECK-RV64-NEXT: entry:293// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vrsub.mask.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> [[OP1]], i8 0, <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 3)294// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]295//296vint8m8_t test_vneg_v_i8m8_m(vbool1_t mask, vint8m8_t op1, size_t vl) {297 return __riscv_vneg_v_i8m8_m(mask, op1, vl);298}299 300// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vneg_v_i16mf4_m301// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {302// CHECK-RV64-NEXT: entry:303// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vrsub.mask.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[OP1]], i16 0, <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)304// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]305//306vint16mf4_t test_vneg_v_i16mf4_m(vbool64_t mask, vint16mf4_t op1, size_t vl) {307 return __riscv_vneg_v_i16mf4_m(mask, op1, vl);308}309 310// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vneg_v_i16mf2_m311// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {312// CHECK-RV64-NEXT: entry:313// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vrsub.mask.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> [[OP1]], i16 0, <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)314// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]315//316vint16mf2_t test_vneg_v_i16mf2_m(vbool32_t mask, vint16mf2_t op1, size_t vl) {317 return __riscv_vneg_v_i16mf2_m(mask, op1, vl);318}319 320// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vneg_v_i16m1_m321// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {322// CHECK-RV64-NEXT: entry:323// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vrsub.mask.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> [[OP1]], i16 0, <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)324// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]325//326vint16m1_t test_vneg_v_i16m1_m(vbool16_t mask, vint16m1_t op1, size_t vl) {327 return __riscv_vneg_v_i16m1_m(mask, op1, vl);328}329 330// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vneg_v_i16m2_m331// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {332// CHECK-RV64-NEXT: entry:333// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vrsub.mask.nxv8i16.i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> [[OP1]], i16 0, <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)334// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]335//336vint16m2_t test_vneg_v_i16m2_m(vbool8_t mask, vint16m2_t op1, size_t vl) {337 return __riscv_vneg_v_i16m2_m(mask, op1, vl);338}339 340// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vneg_v_i16m4_m341// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {342// CHECK-RV64-NEXT: entry:343// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vrsub.mask.nxv16i16.i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> [[OP1]], i16 0, <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3)344// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]345//346vint16m4_t test_vneg_v_i16m4_m(vbool4_t mask, vint16m4_t op1, size_t vl) {347 return __riscv_vneg_v_i16m4_m(mask, op1, vl);348}349 350// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vneg_v_i16m8_m351// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {352// CHECK-RV64-NEXT: entry:353// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vrsub.mask.nxv32i16.i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> [[OP1]], i16 0, <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3)354// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]355//356vint16m8_t test_vneg_v_i16m8_m(vbool2_t mask, vint16m8_t op1, size_t vl) {357 return __riscv_vneg_v_i16m8_m(mask, op1, vl);358}359 360// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vneg_v_i32mf2_m361// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {362// CHECK-RV64-NEXT: entry:363// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vrsub.mask.nxv1i32.i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[OP1]], i32 0, <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)364// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]365//366vint32mf2_t test_vneg_v_i32mf2_m(vbool64_t mask, vint32mf2_t op1, size_t vl) {367 return __riscv_vneg_v_i32mf2_m(mask, op1, vl);368}369 370// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vneg_v_i32m1_m371// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {372// CHECK-RV64-NEXT: entry:373// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vrsub.mask.nxv2i32.i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[OP1]], i32 0, <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)374// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]375//376vint32m1_t test_vneg_v_i32m1_m(vbool32_t mask, vint32m1_t op1, size_t vl) {377 return __riscv_vneg_v_i32m1_m(mask, op1, vl);378}379 380// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vneg_v_i32m2_m381// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {382// CHECK-RV64-NEXT: entry:383// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vrsub.mask.nxv4i32.i32.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> [[OP1]], i32 0, <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)384// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]385//386vint32m2_t test_vneg_v_i32m2_m(vbool16_t mask, vint32m2_t op1, size_t vl) {387 return __riscv_vneg_v_i32m2_m(mask, op1, vl);388}389 390// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vneg_v_i32m4_m391// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {392// CHECK-RV64-NEXT: entry:393// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vrsub.mask.nxv8i32.i32.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> [[OP1]], i32 0, <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)394// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]395//396vint32m4_t test_vneg_v_i32m4_m(vbool8_t mask, vint32m4_t op1, size_t vl) {397 return __riscv_vneg_v_i32m4_m(mask, op1, vl);398}399 400// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vneg_v_i32m8_m401// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {402// CHECK-RV64-NEXT: entry:403// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vrsub.mask.nxv16i32.i32.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> [[OP1]], i32 0, <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3)404// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]405//406vint32m8_t test_vneg_v_i32m8_m(vbool4_t mask, vint32m8_t op1, size_t vl) {407 return __riscv_vneg_v_i32m8_m(mask, op1, vl);408}409 410// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vneg_v_i64m1_m411// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {412// CHECK-RV64-NEXT: entry:413// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vrsub.mask.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> [[OP1]], i64 0, <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)414// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]415//416vint64m1_t test_vneg_v_i64m1_m(vbool64_t mask, vint64m1_t op1, size_t vl) {417 return __riscv_vneg_v_i64m1_m(mask, op1, vl);418}419 420// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vneg_v_i64m2_m421// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {422// CHECK-RV64-NEXT: entry:423// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vrsub.mask.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> [[OP1]], i64 0, <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)424// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]425//426vint64m2_t test_vneg_v_i64m2_m(vbool32_t mask, vint64m2_t op1, size_t vl) {427 return __riscv_vneg_v_i64m2_m(mask, op1, vl);428}429 430// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vneg_v_i64m4_m431// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {432// CHECK-RV64-NEXT: entry:433// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vrsub.mask.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> [[OP1]], i64 0, <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)434// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]435//436vint64m4_t test_vneg_v_i64m4_m(vbool16_t mask, vint64m4_t op1, size_t vl) {437 return __riscv_vneg_v_i64m4_m(mask, op1, vl);438}439 440// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vneg_v_i64m8_m441// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {442// CHECK-RV64-NEXT: entry:443// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vrsub.mask.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> [[OP1]], i64 0, <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)444// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]445//446vint64m8_t test_vneg_v_i64m8_m(vbool8_t mask, vint64m8_t op1, size_t vl) {447 return __riscv_vneg_v_i64m8_m(mask, op1, vl);448}449 450