3094 lines · c
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 22// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \4// RUN: -target-feature +zvfhmin -disable-O0-optnone \5// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \6// RUN: FileCheck --check-prefix=CHECK-RV64 %s7 8#include <riscv_vector.h>9 10// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vreinterpret_v_i8mf8_u8mf811// CHECK-RV64-SAME: (<vscale x 1 x i8> [[SRC:%.*]]) #[[ATTR0:[0-9]+]] {12// CHECK-RV64-NEXT: entry:13// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[SRC]]14//15vuint8mf8_t test_vreinterpret_v_i8mf8_u8mf8(vint8mf8_t src) {16 return __riscv_vreinterpret_v_i8mf8_u8mf8(src);17}18 19// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vreinterpret_v_i8mf4_u8mf420// CHECK-RV64-SAME: (<vscale x 2 x i8> [[SRC:%.*]]) #[[ATTR0]] {21// CHECK-RV64-NEXT: entry:22// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[SRC]]23//24vuint8mf4_t test_vreinterpret_v_i8mf4_u8mf4(vint8mf4_t src) {25 return __riscv_vreinterpret_v_i8mf4_u8mf4(src);26}27 28// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vreinterpret_v_i8mf2_u8mf229// CHECK-RV64-SAME: (<vscale x 4 x i8> [[SRC:%.*]]) #[[ATTR0]] {30// CHECK-RV64-NEXT: entry:31// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[SRC]]32//33vuint8mf2_t test_vreinterpret_v_i8mf2_u8mf2(vint8mf2_t src) {34 return __riscv_vreinterpret_v_i8mf2_u8mf2(src);35}36 37// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_i8m1_u8m138// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {39// CHECK-RV64-NEXT: entry:40// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[SRC]]41//42vuint8m1_t test_vreinterpret_v_i8m1_u8m1(vint8m1_t src) {43 return __riscv_vreinterpret_v_i8m1_u8m1(src);44}45 46// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vreinterpret_v_i8m2_u8m247// CHECK-RV64-SAME: (<vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {48// CHECK-RV64-NEXT: entry:49// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[SRC]]50//51vuint8m2_t test_vreinterpret_v_i8m2_u8m2(vint8m2_t src) {52 return __riscv_vreinterpret_v_i8m2_u8m2(src);53}54 55// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vreinterpret_v_i8m4_u8m456// CHECK-RV64-SAME: (<vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {57// CHECK-RV64-NEXT: entry:58// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[SRC]]59//60vuint8m4_t test_vreinterpret_v_i8m4_u8m4(vint8m4_t src) {61 return __riscv_vreinterpret_v_i8m4_u8m4(src);62}63 64// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vreinterpret_v_i8m8_u8m865// CHECK-RV64-SAME: (<vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {66// CHECK-RV64-NEXT: entry:67// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[SRC]]68//69vuint8m8_t test_vreinterpret_v_i8m8_u8m8(vint8m8_t src) {70 return __riscv_vreinterpret_v_i8m8_u8m8(src);71}72 73// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vreinterpret_v_u8mf8_i8mf874// CHECK-RV64-SAME: (<vscale x 1 x i8> [[SRC:%.*]]) #[[ATTR0]] {75// CHECK-RV64-NEXT: entry:76// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[SRC]]77//78vint8mf8_t test_vreinterpret_v_u8mf8_i8mf8(vuint8mf8_t src) {79 return __riscv_vreinterpret_v_u8mf8_i8mf8(src);80}81 82// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vreinterpret_v_u8mf4_i8mf483// CHECK-RV64-SAME: (<vscale x 2 x i8> [[SRC:%.*]]) #[[ATTR0]] {84// CHECK-RV64-NEXT: entry:85// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[SRC]]86//87vint8mf4_t test_vreinterpret_v_u8mf4_i8mf4(vuint8mf4_t src) {88 return __riscv_vreinterpret_v_u8mf4_i8mf4(src);89}90 91// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vreinterpret_v_u8mf2_i8mf292// CHECK-RV64-SAME: (<vscale x 4 x i8> [[SRC:%.*]]) #[[ATTR0]] {93// CHECK-RV64-NEXT: entry:94// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[SRC]]95//96vint8mf2_t test_vreinterpret_v_u8mf2_i8mf2(vuint8mf2_t src) {97 return __riscv_vreinterpret_v_u8mf2_i8mf2(src);98}99 100// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u8m1_i8m1101// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {102// CHECK-RV64-NEXT: entry:103// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[SRC]]104//105vint8m1_t test_vreinterpret_v_u8m1_i8m1(vuint8m1_t src) {106 return __riscv_vreinterpret_v_u8m1_i8m1(src);107}108 109// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u8m2_i8m2110// CHECK-RV64-SAME: (<vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {111// CHECK-RV64-NEXT: entry:112// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[SRC]]113//114vint8m2_t test_vreinterpret_v_u8m2_i8m2(vuint8m2_t src) {115 return __riscv_vreinterpret_v_u8m2_i8m2(src);116}117 118// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u8m4_i8m4119// CHECK-RV64-SAME: (<vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {120// CHECK-RV64-NEXT: entry:121// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[SRC]]122//123vint8m4_t test_vreinterpret_v_u8m4_i8m4(vuint8m4_t src) {124 return __riscv_vreinterpret_v_u8m4_i8m4(src);125}126 127// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u8m8_i8m8128// CHECK-RV64-SAME: (<vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {129// CHECK-RV64-NEXT: entry:130// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[SRC]]131//132vint8m8_t test_vreinterpret_v_u8m8_i8m8(vuint8m8_t src) {133 return __riscv_vreinterpret_v_u8m8_i8m8(src);134}135 136// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vreinterpret_v_i16mf4_f16mf4137// CHECK-RV64-SAME: (<vscale x 1 x i16> [[SRC:%.*]]) #[[ATTR0]] {138// CHECK-RV64-NEXT: entry:139// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 1 x i16> [[SRC]] to <vscale x 1 x half>140// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]141//142vfloat16mf4_t test_vreinterpret_v_i16mf4_f16mf4(vint16mf4_t src) {143 return __riscv_vreinterpret_v_i16mf4_f16mf4(src);144}145 146// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vreinterpret_v_i16mf2_f16mf2147// CHECK-RV64-SAME: (<vscale x 2 x i16> [[SRC:%.*]]) #[[ATTR0]] {148// CHECK-RV64-NEXT: entry:149// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 2 x i16> [[SRC]] to <vscale x 2 x half>150// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]151//152vfloat16mf2_t test_vreinterpret_v_i16mf2_f16mf2(vint16mf2_t src) {153 return __riscv_vreinterpret_v_i16mf2_f16mf2(src);154}155 156// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vreinterpret_v_i16m1_f16m1157// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {158// CHECK-RV64-NEXT: entry:159// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 4 x half>160// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]161//162vfloat16m1_t test_vreinterpret_v_i16m1_f16m1(vint16m1_t src) {163 return __riscv_vreinterpret_v_i16m1_f16m1(src);164}165 166// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vreinterpret_v_i16m2_f16m2167// CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {168// CHECK-RV64-NEXT: entry:169// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC]] to <vscale x 8 x half>170// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]171//172vfloat16m2_t test_vreinterpret_v_i16m2_f16m2(vint16m2_t src) {173 return __riscv_vreinterpret_v_i16m2_f16m2(src);174}175 176// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vreinterpret_v_i16m4_f16m4177// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {178// CHECK-RV64-NEXT: entry:179// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC]] to <vscale x 16 x half>180// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]181//182vfloat16m4_t test_vreinterpret_v_i16m4_f16m4(vint16m4_t src) {183 return __riscv_vreinterpret_v_i16m4_f16m4(src);184}185 186// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vreinterpret_v_i16m8_f16m8187// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {188// CHECK-RV64-NEXT: entry:189// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC]] to <vscale x 32 x half>190// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]191//192vfloat16m8_t test_vreinterpret_v_i16m8_f16m8(vint16m8_t src) {193 return __riscv_vreinterpret_v_i16m8_f16m8(src);194}195 196// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vreinterpret_v_u16mf4_f16mf4197// CHECK-RV64-SAME: (<vscale x 1 x i16> [[SRC:%.*]]) #[[ATTR0]] {198// CHECK-RV64-NEXT: entry:199// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 1 x i16> [[SRC]] to <vscale x 1 x half>200// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]201//202vfloat16mf4_t test_vreinterpret_v_u16mf4_f16mf4(vuint16mf4_t src) {203 return __riscv_vreinterpret_v_u16mf4_f16mf4(src);204}205 206// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vreinterpret_v_u16mf2_f16mf2207// CHECK-RV64-SAME: (<vscale x 2 x i16> [[SRC:%.*]]) #[[ATTR0]] {208// CHECK-RV64-NEXT: entry:209// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 2 x i16> [[SRC]] to <vscale x 2 x half>210// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]211//212vfloat16mf2_t test_vreinterpret_v_u16mf2_f16mf2(vuint16mf2_t src) {213 return __riscv_vreinterpret_v_u16mf2_f16mf2(src);214}215 216// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vreinterpret_v_u16m1_f16m1217// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {218// CHECK-RV64-NEXT: entry:219// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 4 x half>220// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]221//222vfloat16m1_t test_vreinterpret_v_u16m1_f16m1(vuint16m1_t src) {223 return __riscv_vreinterpret_v_u16m1_f16m1(src);224}225 226// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vreinterpret_v_u16m2_f16m2227// CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {228// CHECK-RV64-NEXT: entry:229// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC]] to <vscale x 8 x half>230// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]231//232vfloat16m2_t test_vreinterpret_v_u16m2_f16m2(vuint16m2_t src) {233 return __riscv_vreinterpret_v_u16m2_f16m2(src);234}235 236// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vreinterpret_v_u16m4_f16m4237// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {238// CHECK-RV64-NEXT: entry:239// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC]] to <vscale x 16 x half>240// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]241//242vfloat16m4_t test_vreinterpret_v_u16m4_f16m4(vuint16m4_t src) {243 return __riscv_vreinterpret_v_u16m4_f16m4(src);244}245 246// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vreinterpret_v_u16m8_f16m8247// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {248// CHECK-RV64-NEXT: entry:249// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC]] to <vscale x 32 x half>250// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]251//252vfloat16m8_t test_vreinterpret_v_u16m8_f16m8(vuint16m8_t src) {253 return __riscv_vreinterpret_v_u16m8_f16m8(src);254}255 256// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vreinterpret_v_i16mf4_u16mf4257// CHECK-RV64-SAME: (<vscale x 1 x i16> [[SRC:%.*]]) #[[ATTR0]] {258// CHECK-RV64-NEXT: entry:259// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[SRC]]260//261vuint16mf4_t test_vreinterpret_v_i16mf4_u16mf4(vint16mf4_t src) {262 return __riscv_vreinterpret_v_i16mf4_u16mf4(src);263}264 265// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vreinterpret_v_i16mf2_u16mf2266// CHECK-RV64-SAME: (<vscale x 2 x i16> [[SRC:%.*]]) #[[ATTR0]] {267// CHECK-RV64-NEXT: entry:268// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[SRC]]269//270vuint16mf2_t test_vreinterpret_v_i16mf2_u16mf2(vint16mf2_t src) {271 return __riscv_vreinterpret_v_i16mf2_u16mf2(src);272}273 274// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_i16m1_u16m1275// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {276// CHECK-RV64-NEXT: entry:277// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[SRC]]278//279vuint16m1_t test_vreinterpret_v_i16m1_u16m1(vint16m1_t src) {280 return __riscv_vreinterpret_v_i16m1_u16m1(src);281}282 283// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_i16m2_u16m2284// CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {285// CHECK-RV64-NEXT: entry:286// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[SRC]]287//288vuint16m2_t test_vreinterpret_v_i16m2_u16m2(vint16m2_t src) {289 return __riscv_vreinterpret_v_i16m2_u16m2(src);290}291 292// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_i16m4_u16m4293// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {294// CHECK-RV64-NEXT: entry:295// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[SRC]]296//297vuint16m4_t test_vreinterpret_v_i16m4_u16m4(vint16m4_t src) {298 return __riscv_vreinterpret_v_i16m4_u16m4(src);299}300 301// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_i16m8_u16m8302// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {303// CHECK-RV64-NEXT: entry:304// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[SRC]]305//306vuint16m8_t test_vreinterpret_v_i16m8_u16m8(vint16m8_t src) {307 return __riscv_vreinterpret_v_i16m8_u16m8(src);308}309 310// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vreinterpret_v_u16mf4_i16mf4311// CHECK-RV64-SAME: (<vscale x 1 x i16> [[SRC:%.*]]) #[[ATTR0]] {312// CHECK-RV64-NEXT: entry:313// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[SRC]]314//315vint16mf4_t test_vreinterpret_v_u16mf4_i16mf4(vuint16mf4_t src) {316 return __riscv_vreinterpret_v_u16mf4_i16mf4(src);317}318 319// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vreinterpret_v_u16mf2_i16mf2320// CHECK-RV64-SAME: (<vscale x 2 x i16> [[SRC:%.*]]) #[[ATTR0]] {321// CHECK-RV64-NEXT: entry:322// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[SRC]]323//324vint16mf2_t test_vreinterpret_v_u16mf2_i16mf2(vuint16mf2_t src) {325 return __riscv_vreinterpret_v_u16mf2_i16mf2(src);326}327 328// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_u16m1_i16m1329// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {330// CHECK-RV64-NEXT: entry:331// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[SRC]]332//333vint16m1_t test_vreinterpret_v_u16m1_i16m1(vuint16m1_t src) {334 return __riscv_vreinterpret_v_u16m1_i16m1(src);335}336 337// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_u16m2_i16m2338// CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {339// CHECK-RV64-NEXT: entry:340// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[SRC]]341//342vint16m2_t test_vreinterpret_v_u16m2_i16m2(vuint16m2_t src) {343 return __riscv_vreinterpret_v_u16m2_i16m2(src);344}345 346// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_u16m4_i16m4347// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {348// CHECK-RV64-NEXT: entry:349// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[SRC]]350//351vint16m4_t test_vreinterpret_v_u16m4_i16m4(vuint16m4_t src) {352 return __riscv_vreinterpret_v_u16m4_i16m4(src);353}354 355// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_u16m8_i16m8356// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {357// CHECK-RV64-NEXT: entry:358// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[SRC]]359//360vint16m8_t test_vreinterpret_v_u16m8_i16m8(vuint16m8_t src) {361 return __riscv_vreinterpret_v_u16m8_i16m8(src);362}363 364// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vreinterpret_v_f16mf4_i16mf4365// CHECK-RV64-SAME: (<vscale x 1 x half> [[SRC:%.*]]) #[[ATTR0]] {366// CHECK-RV64-NEXT: entry:367// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 1 x half> [[SRC]] to <vscale x 1 x i16>368// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]369//370vint16mf4_t test_vreinterpret_v_f16mf4_i16mf4(vfloat16mf4_t src) {371 return __riscv_vreinterpret_v_f16mf4_i16mf4(src);372}373 374// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vreinterpret_v_f16mf2_i16mf2375// CHECK-RV64-SAME: (<vscale x 2 x half> [[SRC:%.*]]) #[[ATTR0]] {376// CHECK-RV64-NEXT: entry:377// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 2 x half> [[SRC]] to <vscale x 2 x i16>378// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]379//380vint16mf2_t test_vreinterpret_v_f16mf2_i16mf2(vfloat16mf2_t src) {381 return __riscv_vreinterpret_v_f16mf2_i16mf2(src);382}383 384// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_f16m1_i16m1385// CHECK-RV64-SAME: (<vscale x 4 x half> [[SRC:%.*]]) #[[ATTR0]] {386// CHECK-RV64-NEXT: entry:387// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 4 x half> [[SRC]] to <vscale x 4 x i16>388// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]389//390vint16m1_t test_vreinterpret_v_f16m1_i16m1(vfloat16m1_t src) {391 return __riscv_vreinterpret_v_f16m1_i16m1(src);392}393 394// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_f16m2_i16m2395// CHECK-RV64-SAME: (<vscale x 8 x half> [[SRC:%.*]]) #[[ATTR0]] {396// CHECK-RV64-NEXT: entry:397// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x half> [[SRC]] to <vscale x 8 x i16>398// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]399//400vint16m2_t test_vreinterpret_v_f16m2_i16m2(vfloat16m2_t src) {401 return __riscv_vreinterpret_v_f16m2_i16m2(src);402}403 404// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_f16m4_i16m4405// CHECK-RV64-SAME: (<vscale x 16 x half> [[SRC:%.*]]) #[[ATTR0]] {406// CHECK-RV64-NEXT: entry:407// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 16 x half> [[SRC]] to <vscale x 16 x i16>408// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]409//410vint16m4_t test_vreinterpret_v_f16m4_i16m4(vfloat16m4_t src) {411 return __riscv_vreinterpret_v_f16m4_i16m4(src);412}413 414// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_f16m8_i16m8415// CHECK-RV64-SAME: (<vscale x 32 x half> [[SRC:%.*]]) #[[ATTR0]] {416// CHECK-RV64-NEXT: entry:417// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 32 x half> [[SRC]] to <vscale x 32 x i16>418// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]419//420vint16m8_t test_vreinterpret_v_f16m8_i16m8(vfloat16m8_t src) {421 return __riscv_vreinterpret_v_f16m8_i16m8(src);422}423 424// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vreinterpret_v_f16mf4_u16mf4425// CHECK-RV64-SAME: (<vscale x 1 x half> [[SRC:%.*]]) #[[ATTR0]] {426// CHECK-RV64-NEXT: entry:427// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 1 x half> [[SRC]] to <vscale x 1 x i16>428// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]429//430vuint16mf4_t test_vreinterpret_v_f16mf4_u16mf4(vfloat16mf4_t src) {431 return __riscv_vreinterpret_v_f16mf4_u16mf4(src);432}433 434// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vreinterpret_v_f16mf2_u16mf2435// CHECK-RV64-SAME: (<vscale x 2 x half> [[SRC:%.*]]) #[[ATTR0]] {436// CHECK-RV64-NEXT: entry:437// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 2 x half> [[SRC]] to <vscale x 2 x i16>438// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]439//440vuint16mf2_t test_vreinterpret_v_f16mf2_u16mf2(vfloat16mf2_t src) {441 return __riscv_vreinterpret_v_f16mf2_u16mf2(src);442}443 444// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_f16m1_u16m1445// CHECK-RV64-SAME: (<vscale x 4 x half> [[SRC:%.*]]) #[[ATTR0]] {446// CHECK-RV64-NEXT: entry:447// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 4 x half> [[SRC]] to <vscale x 4 x i16>448// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]449//450vuint16m1_t test_vreinterpret_v_f16m1_u16m1(vfloat16m1_t src) {451 return __riscv_vreinterpret_v_f16m1_u16m1(src);452}453 454// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_f16m2_u16m2455// CHECK-RV64-SAME: (<vscale x 8 x half> [[SRC:%.*]]) #[[ATTR0]] {456// CHECK-RV64-NEXT: entry:457// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x half> [[SRC]] to <vscale x 8 x i16>458// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]459//460vuint16m2_t test_vreinterpret_v_f16m2_u16m2(vfloat16m2_t src) {461 return __riscv_vreinterpret_v_f16m2_u16m2(src);462}463 464// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_f16m4_u16m4465// CHECK-RV64-SAME: (<vscale x 16 x half> [[SRC:%.*]]) #[[ATTR0]] {466// CHECK-RV64-NEXT: entry:467// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 16 x half> [[SRC]] to <vscale x 16 x i16>468// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]469//470vuint16m4_t test_vreinterpret_v_f16m4_u16m4(vfloat16m4_t src) {471 return __riscv_vreinterpret_v_f16m4_u16m4(src);472}473 474// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_f16m8_u16m8475// CHECK-RV64-SAME: (<vscale x 32 x half> [[SRC:%.*]]) #[[ATTR0]] {476// CHECK-RV64-NEXT: entry:477// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 32 x half> [[SRC]] to <vscale x 32 x i16>478// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]479//480vuint16m8_t test_vreinterpret_v_f16m8_u16m8(vfloat16m8_t src) {481 return __riscv_vreinterpret_v_f16m8_u16m8(src);482}483 484// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vreinterpret_v_i32mf2_f32mf2485// CHECK-RV64-SAME: (<vscale x 1 x i32> [[SRC:%.*]]) #[[ATTR0]] {486// CHECK-RV64-NEXT: entry:487// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 1 x i32> [[SRC]] to <vscale x 1 x float>488// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]489//490vfloat32mf2_t test_vreinterpret_v_i32mf2_f32mf2(vint32mf2_t src) {491 return __riscv_vreinterpret_v_i32mf2_f32mf2(src);492}493 494// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vreinterpret_v_i32m1_f32m1495// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {496// CHECK-RV64-NEXT: entry:497// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 2 x float>498// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]499//500vfloat32m1_t test_vreinterpret_v_i32m1_f32m1(vint32m1_t src) {501 return __riscv_vreinterpret_v_i32m1_f32m1(src);502}503 504// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vreinterpret_v_i32m2_f32m2505// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {506// CHECK-RV64-NEXT: entry:507// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC]] to <vscale x 4 x float>508// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]509//510vfloat32m2_t test_vreinterpret_v_i32m2_f32m2(vint32m2_t src) {511 return __riscv_vreinterpret_v_i32m2_f32m2(src);512}513 514// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vreinterpret_v_i32m4_f32m4515// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {516// CHECK-RV64-NEXT: entry:517// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC]] to <vscale x 8 x float>518// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]519//520vfloat32m4_t test_vreinterpret_v_i32m4_f32m4(vint32m4_t src) {521 return __riscv_vreinterpret_v_i32m4_f32m4(src);522}523 524// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vreinterpret_v_i32m8_f32m8525// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {526// CHECK-RV64-NEXT: entry:527// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC]] to <vscale x 16 x float>528// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]529//530vfloat32m8_t test_vreinterpret_v_i32m8_f32m8(vint32m8_t src) {531 return __riscv_vreinterpret_v_i32m8_f32m8(src);532}533 534// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vreinterpret_v_u32mf2_f32mf2535// CHECK-RV64-SAME: (<vscale x 1 x i32> [[SRC:%.*]]) #[[ATTR0]] {536// CHECK-RV64-NEXT: entry:537// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 1 x i32> [[SRC]] to <vscale x 1 x float>538// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]539//540vfloat32mf2_t test_vreinterpret_v_u32mf2_f32mf2(vuint32mf2_t src) {541 return __riscv_vreinterpret_v_u32mf2_f32mf2(src);542}543 544// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vreinterpret_v_u32m1_f32m1545// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {546// CHECK-RV64-NEXT: entry:547// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 2 x float>548// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]549//550vfloat32m1_t test_vreinterpret_v_u32m1_f32m1(vuint32m1_t src) {551 return __riscv_vreinterpret_v_u32m1_f32m1(src);552}553 554// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vreinterpret_v_u32m2_f32m2555// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {556// CHECK-RV64-NEXT: entry:557// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC]] to <vscale x 4 x float>558// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]559//560vfloat32m2_t test_vreinterpret_v_u32m2_f32m2(vuint32m2_t src) {561 return __riscv_vreinterpret_v_u32m2_f32m2(src);562}563 564// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vreinterpret_v_u32m4_f32m4565// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {566// CHECK-RV64-NEXT: entry:567// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC]] to <vscale x 8 x float>568// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]569//570vfloat32m4_t test_vreinterpret_v_u32m4_f32m4(vuint32m4_t src) {571 return __riscv_vreinterpret_v_u32m4_f32m4(src);572}573 574// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vreinterpret_v_u32m8_f32m8575// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {576// CHECK-RV64-NEXT: entry:577// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC]] to <vscale x 16 x float>578// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]579//580vfloat32m8_t test_vreinterpret_v_u32m8_f32m8(vuint32m8_t src) {581 return __riscv_vreinterpret_v_u32m8_f32m8(src);582}583 584// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vreinterpret_v_i32mf2_u32mf2585// CHECK-RV64-SAME: (<vscale x 1 x i32> [[SRC:%.*]]) #[[ATTR0]] {586// CHECK-RV64-NEXT: entry:587// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[SRC]]588//589vuint32mf2_t test_vreinterpret_v_i32mf2_u32mf2(vint32mf2_t src) {590 return __riscv_vreinterpret_v_i32mf2_u32mf2(src);591}592 593// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_i32m1_u32m1594// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {595// CHECK-RV64-NEXT: entry:596// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[SRC]]597//598vuint32m1_t test_vreinterpret_v_i32m1_u32m1(vint32m1_t src) {599 return __riscv_vreinterpret_v_i32m1_u32m1(src);600}601 602// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_i32m2_u32m2603// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {604// CHECK-RV64-NEXT: entry:605// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[SRC]]606//607vuint32m2_t test_vreinterpret_v_i32m2_u32m2(vint32m2_t src) {608 return __riscv_vreinterpret_v_i32m2_u32m2(src);609}610 611// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_i32m4_u32m4612// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {613// CHECK-RV64-NEXT: entry:614// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[SRC]]615//616vuint32m4_t test_vreinterpret_v_i32m4_u32m4(vint32m4_t src) {617 return __riscv_vreinterpret_v_i32m4_u32m4(src);618}619 620// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_i32m8_u32m8621// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {622// CHECK-RV64-NEXT: entry:623// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[SRC]]624//625vuint32m8_t test_vreinterpret_v_i32m8_u32m8(vint32m8_t src) {626 return __riscv_vreinterpret_v_i32m8_u32m8(src);627}628 629// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vreinterpret_v_u32mf2_i32mf2630// CHECK-RV64-SAME: (<vscale x 1 x i32> [[SRC:%.*]]) #[[ATTR0]] {631// CHECK-RV64-NEXT: entry:632// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[SRC]]633//634vint32mf2_t test_vreinterpret_v_u32mf2_i32mf2(vuint32mf2_t src) {635 return __riscv_vreinterpret_v_u32mf2_i32mf2(src);636}637 638// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_u32m1_i32m1639// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {640// CHECK-RV64-NEXT: entry:641// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[SRC]]642//643vint32m1_t test_vreinterpret_v_u32m1_i32m1(vuint32m1_t src) {644 return __riscv_vreinterpret_v_u32m1_i32m1(src);645}646 647// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_u32m2_i32m2648// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {649// CHECK-RV64-NEXT: entry:650// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[SRC]]651//652vint32m2_t test_vreinterpret_v_u32m2_i32m2(vuint32m2_t src) {653 return __riscv_vreinterpret_v_u32m2_i32m2(src);654}655 656// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_u32m4_i32m4657// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {658// CHECK-RV64-NEXT: entry:659// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[SRC]]660//661vint32m4_t test_vreinterpret_v_u32m4_i32m4(vuint32m4_t src) {662 return __riscv_vreinterpret_v_u32m4_i32m4(src);663}664 665// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_u32m8_i32m8666// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {667// CHECK-RV64-NEXT: entry:668// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[SRC]]669//670vint32m8_t test_vreinterpret_v_u32m8_i32m8(vuint32m8_t src) {671 return __riscv_vreinterpret_v_u32m8_i32m8(src);672}673 674// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vreinterpret_v_f32mf2_i32mf2675// CHECK-RV64-SAME: (<vscale x 1 x float> [[SRC:%.*]]) #[[ATTR0]] {676// CHECK-RV64-NEXT: entry:677// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 1 x float> [[SRC]] to <vscale x 1 x i32>678// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]679//680vint32mf2_t test_vreinterpret_v_f32mf2_i32mf2(vfloat32mf2_t src) {681 return __riscv_vreinterpret_v_f32mf2_i32mf2(src);682}683 684// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_f32m1_i32m1685// CHECK-RV64-SAME: (<vscale x 2 x float> [[SRC:%.*]]) #[[ATTR0]] {686// CHECK-RV64-NEXT: entry:687// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 2 x float> [[SRC]] to <vscale x 2 x i32>688// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]689//690vint32m1_t test_vreinterpret_v_f32m1_i32m1(vfloat32m1_t src) {691 return __riscv_vreinterpret_v_f32m1_i32m1(src);692}693 694// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_f32m2_i32m2695// CHECK-RV64-SAME: (<vscale x 4 x float> [[SRC:%.*]]) #[[ATTR0]] {696// CHECK-RV64-NEXT: entry:697// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 4 x float> [[SRC]] to <vscale x 4 x i32>698// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]699//700vint32m2_t test_vreinterpret_v_f32m2_i32m2(vfloat32m2_t src) {701 return __riscv_vreinterpret_v_f32m2_i32m2(src);702}703 704// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_f32m4_i32m4705// CHECK-RV64-SAME: (<vscale x 8 x float> [[SRC:%.*]]) #[[ATTR0]] {706// CHECK-RV64-NEXT: entry:707// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x float> [[SRC]] to <vscale x 8 x i32>708// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]709//710vint32m4_t test_vreinterpret_v_f32m4_i32m4(vfloat32m4_t src) {711 return __riscv_vreinterpret_v_f32m4_i32m4(src);712}713 714// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_f32m8_i32m8715// CHECK-RV64-SAME: (<vscale x 16 x float> [[SRC:%.*]]) #[[ATTR0]] {716// CHECK-RV64-NEXT: entry:717// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 16 x float> [[SRC]] to <vscale x 16 x i32>718// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]719//720vint32m8_t test_vreinterpret_v_f32m8_i32m8(vfloat32m8_t src) {721 return __riscv_vreinterpret_v_f32m8_i32m8(src);722}723 724// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vreinterpret_v_f32mf2_u32mf2725// CHECK-RV64-SAME: (<vscale x 1 x float> [[SRC:%.*]]) #[[ATTR0]] {726// CHECK-RV64-NEXT: entry:727// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 1 x float> [[SRC]] to <vscale x 1 x i32>728// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]729//730vuint32mf2_t test_vreinterpret_v_f32mf2_u32mf2(vfloat32mf2_t src) {731 return __riscv_vreinterpret_v_f32mf2_u32mf2(src);732}733 734// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_f32m1_u32m1735// CHECK-RV64-SAME: (<vscale x 2 x float> [[SRC:%.*]]) #[[ATTR0]] {736// CHECK-RV64-NEXT: entry:737// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 2 x float> [[SRC]] to <vscale x 2 x i32>738// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]739//740vuint32m1_t test_vreinterpret_v_f32m1_u32m1(vfloat32m1_t src) {741 return __riscv_vreinterpret_v_f32m1_u32m1(src);742}743 744// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_f32m2_u32m2745// CHECK-RV64-SAME: (<vscale x 4 x float> [[SRC:%.*]]) #[[ATTR0]] {746// CHECK-RV64-NEXT: entry:747// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 4 x float> [[SRC]] to <vscale x 4 x i32>748// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]749//750vuint32m2_t test_vreinterpret_v_f32m2_u32m2(vfloat32m2_t src) {751 return __riscv_vreinterpret_v_f32m2_u32m2(src);752}753 754// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_f32m4_u32m4755// CHECK-RV64-SAME: (<vscale x 8 x float> [[SRC:%.*]]) #[[ATTR0]] {756// CHECK-RV64-NEXT: entry:757// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x float> [[SRC]] to <vscale x 8 x i32>758// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]759//760vuint32m4_t test_vreinterpret_v_f32m4_u32m4(vfloat32m4_t src) {761 return __riscv_vreinterpret_v_f32m4_u32m4(src);762}763 764// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_f32m8_u32m8765// CHECK-RV64-SAME: (<vscale x 16 x float> [[SRC:%.*]]) #[[ATTR0]] {766// CHECK-RV64-NEXT: entry:767// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 16 x float> [[SRC]] to <vscale x 16 x i32>768// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]769//770vuint32m8_t test_vreinterpret_v_f32m8_u32m8(vfloat32m8_t src) {771 return __riscv_vreinterpret_v_f32m8_u32m8(src);772}773 774// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vreinterpret_v_i64m1_f64m1775// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {776// CHECK-RV64-NEXT: entry:777// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 1 x double>778// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]779//780vfloat64m1_t test_vreinterpret_v_i64m1_f64m1(vint64m1_t src) {781 return __riscv_vreinterpret_v_i64m1_f64m1(src);782}783 784// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vreinterpret_v_i64m2_f64m2785// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {786// CHECK-RV64-NEXT: entry:787// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC]] to <vscale x 2 x double>788// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]789//790vfloat64m2_t test_vreinterpret_v_i64m2_f64m2(vint64m2_t src) {791 return __riscv_vreinterpret_v_i64m2_f64m2(src);792}793 794// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vreinterpret_v_i64m4_f64m4795// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {796// CHECK-RV64-NEXT: entry:797// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC]] to <vscale x 4 x double>798// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]799//800vfloat64m4_t test_vreinterpret_v_i64m4_f64m4(vint64m4_t src) {801 return __riscv_vreinterpret_v_i64m4_f64m4(src);802}803 804// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vreinterpret_v_i64m8_f64m8805// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {806// CHECK-RV64-NEXT: entry:807// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC]] to <vscale x 8 x double>808// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]809//810vfloat64m8_t test_vreinterpret_v_i64m8_f64m8(vint64m8_t src) {811 return __riscv_vreinterpret_v_i64m8_f64m8(src);812}813 814// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vreinterpret_v_u64m1_f64m1815// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {816// CHECK-RV64-NEXT: entry:817// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 1 x double>818// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]819//820vfloat64m1_t test_vreinterpret_v_u64m1_f64m1(vuint64m1_t src) {821 return __riscv_vreinterpret_v_u64m1_f64m1(src);822}823 824// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vreinterpret_v_u64m2_f64m2825// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {826// CHECK-RV64-NEXT: entry:827// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC]] to <vscale x 2 x double>828// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]829//830vfloat64m2_t test_vreinterpret_v_u64m2_f64m2(vuint64m2_t src) {831 return __riscv_vreinterpret_v_u64m2_f64m2(src);832}833 834// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vreinterpret_v_u64m4_f64m4835// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {836// CHECK-RV64-NEXT: entry:837// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC]] to <vscale x 4 x double>838// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]839//840vfloat64m4_t test_vreinterpret_v_u64m4_f64m4(vuint64m4_t src) {841 return __riscv_vreinterpret_v_u64m4_f64m4(src);842}843 844// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vreinterpret_v_u64m8_f64m8845// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {846// CHECK-RV64-NEXT: entry:847// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC]] to <vscale x 8 x double>848// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]849//850vfloat64m8_t test_vreinterpret_v_u64m8_f64m8(vuint64m8_t src) {851 return __riscv_vreinterpret_v_u64m8_f64m8(src);852}853 854// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_i64m1_u64m1855// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {856// CHECK-RV64-NEXT: entry:857// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[SRC]]858//859vuint64m1_t test_vreinterpret_v_i64m1_u64m1(vint64m1_t src) {860 return __riscv_vreinterpret_v_i64m1_u64m1(src);861}862 863// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_i64m2_u64m2864// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {865// CHECK-RV64-NEXT: entry:866// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[SRC]]867//868vuint64m2_t test_vreinterpret_v_i64m2_u64m2(vint64m2_t src) {869 return __riscv_vreinterpret_v_i64m2_u64m2(src);870}871 872// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_i64m4_u64m4873// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {874// CHECK-RV64-NEXT: entry:875// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[SRC]]876//877vuint64m4_t test_vreinterpret_v_i64m4_u64m4(vint64m4_t src) {878 return __riscv_vreinterpret_v_i64m4_u64m4(src);879}880 881// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_i64m8_u64m8882// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {883// CHECK-RV64-NEXT: entry:884// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[SRC]]885//886vuint64m8_t test_vreinterpret_v_i64m8_u64m8(vint64m8_t src) {887 return __riscv_vreinterpret_v_i64m8_u64m8(src);888}889 890// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_u64m1_i64m1891// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {892// CHECK-RV64-NEXT: entry:893// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[SRC]]894//895vint64m1_t test_vreinterpret_v_u64m1_i64m1(vuint64m1_t src) {896 return __riscv_vreinterpret_v_u64m1_i64m1(src);897}898 899// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_u64m2_i64m2900// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {901// CHECK-RV64-NEXT: entry:902// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[SRC]]903//904vint64m2_t test_vreinterpret_v_u64m2_i64m2(vuint64m2_t src) {905 return __riscv_vreinterpret_v_u64m2_i64m2(src);906}907 908// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_u64m4_i64m4909// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {910// CHECK-RV64-NEXT: entry:911// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[SRC]]912//913vint64m4_t test_vreinterpret_v_u64m4_i64m4(vuint64m4_t src) {914 return __riscv_vreinterpret_v_u64m4_i64m4(src);915}916 917// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_u64m8_i64m8918// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {919// CHECK-RV64-NEXT: entry:920// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[SRC]]921//922vint64m8_t test_vreinterpret_v_u64m8_i64m8(vuint64m8_t src) {923 return __riscv_vreinterpret_v_u64m8_i64m8(src);924}925 926// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_f64m1_i64m1927// CHECK-RV64-SAME: (<vscale x 1 x double> [[SRC:%.*]]) #[[ATTR0]] {928// CHECK-RV64-NEXT: entry:929// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 1 x double> [[SRC]] to <vscale x 1 x i64>930// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]931//932vint64m1_t test_vreinterpret_v_f64m1_i64m1(vfloat64m1_t src) {933 return __riscv_vreinterpret_v_f64m1_i64m1(src);934}935 936// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_f64m2_i64m2937// CHECK-RV64-SAME: (<vscale x 2 x double> [[SRC:%.*]]) #[[ATTR0]] {938// CHECK-RV64-NEXT: entry:939// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 2 x double> [[SRC]] to <vscale x 2 x i64>940// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]941//942vint64m2_t test_vreinterpret_v_f64m2_i64m2(vfloat64m2_t src) {943 return __riscv_vreinterpret_v_f64m2_i64m2(src);944}945 946// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_f64m4_i64m4947// CHECK-RV64-SAME: (<vscale x 4 x double> [[SRC:%.*]]) #[[ATTR0]] {948// CHECK-RV64-NEXT: entry:949// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 4 x double> [[SRC]] to <vscale x 4 x i64>950// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]951//952vint64m4_t test_vreinterpret_v_f64m4_i64m4(vfloat64m4_t src) {953 return __riscv_vreinterpret_v_f64m4_i64m4(src);954}955 956// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_f64m8_i64m8957// CHECK-RV64-SAME: (<vscale x 8 x double> [[SRC:%.*]]) #[[ATTR0]] {958// CHECK-RV64-NEXT: entry:959// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x double> [[SRC]] to <vscale x 8 x i64>960// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]961//962vint64m8_t test_vreinterpret_v_f64m8_i64m8(vfloat64m8_t src) {963 return __riscv_vreinterpret_v_f64m8_i64m8(src);964}965 966// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_f64m1_u64m1967// CHECK-RV64-SAME: (<vscale x 1 x double> [[SRC:%.*]]) #[[ATTR0]] {968// CHECK-RV64-NEXT: entry:969// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 1 x double> [[SRC]] to <vscale x 1 x i64>970// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]971//972vuint64m1_t test_vreinterpret_v_f64m1_u64m1(vfloat64m1_t src) {973 return __riscv_vreinterpret_v_f64m1_u64m1(src);974}975 976// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_f64m2_u64m2977// CHECK-RV64-SAME: (<vscale x 2 x double> [[SRC:%.*]]) #[[ATTR0]] {978// CHECK-RV64-NEXT: entry:979// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 2 x double> [[SRC]] to <vscale x 2 x i64>980// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]981//982vuint64m2_t test_vreinterpret_v_f64m2_u64m2(vfloat64m2_t src) {983 return __riscv_vreinterpret_v_f64m2_u64m2(src);984}985 986// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_f64m4_u64m4987// CHECK-RV64-SAME: (<vscale x 4 x double> [[SRC:%.*]]) #[[ATTR0]] {988// CHECK-RV64-NEXT: entry:989// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 4 x double> [[SRC]] to <vscale x 4 x i64>990// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]991//992vuint64m4_t test_vreinterpret_v_f64m4_u64m4(vfloat64m4_t src) {993 return __riscv_vreinterpret_v_f64m4_u64m4(src);994}995 996// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_f64m8_u64m8997// CHECK-RV64-SAME: (<vscale x 8 x double> [[SRC:%.*]]) #[[ATTR0]] {998// CHECK-RV64-NEXT: entry:999// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x double> [[SRC]] to <vscale x 8 x i64>1000// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]1001//1002vuint64m8_t test_vreinterpret_v_f64m8_u64m8(vfloat64m8_t src) {1003 return __riscv_vreinterpret_v_f64m8_u64m8(src);1004}1005 1006// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vreinterpret_v_i8mf4_i16mf41007// CHECK-RV64-SAME: (<vscale x 2 x i8> [[SRC:%.*]]) #[[ATTR0]] {1008// CHECK-RV64-NEXT: entry:1009// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 2 x i8> [[SRC]] to <vscale x 1 x i16>1010// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]1011//1012vint16mf4_t test_vreinterpret_v_i8mf4_i16mf4(vint8mf4_t src) {1013 return __riscv_vreinterpret_v_i8mf4_i16mf4(src);1014}1015 1016// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vreinterpret_v_i8mf2_i16mf21017// CHECK-RV64-SAME: (<vscale x 4 x i8> [[SRC:%.*]]) #[[ATTR0]] {1018// CHECK-RV64-NEXT: entry:1019// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 4 x i8> [[SRC]] to <vscale x 2 x i16>1020// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]1021//1022vint16mf2_t test_vreinterpret_v_i8mf2_i16mf2(vint8mf2_t src) {1023 return __riscv_vreinterpret_v_i8mf2_i16mf2(src);1024}1025 1026// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_i8m1_i16m11027// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {1028// CHECK-RV64-NEXT: entry:1029// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 4 x i16>1030// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]1031//1032vint16m1_t test_vreinterpret_v_i8m1_i16m1(vint8m1_t src) {1033 return __riscv_vreinterpret_v_i8m1_i16m1(src);1034}1035 1036// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_i8m2_i16m21037// CHECK-RV64-SAME: (<vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {1038// CHECK-RV64-NEXT: entry:1039// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 16 x i8> [[SRC]] to <vscale x 8 x i16>1040// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]1041//1042vint16m2_t test_vreinterpret_v_i8m2_i16m2(vint8m2_t src) {1043 return __riscv_vreinterpret_v_i8m2_i16m2(src);1044}1045 1046// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_i8m4_i16m41047// CHECK-RV64-SAME: (<vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {1048// CHECK-RV64-NEXT: entry:1049// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 32 x i8> [[SRC]] to <vscale x 16 x i16>1050// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]1051//1052vint16m4_t test_vreinterpret_v_i8m4_i16m4(vint8m4_t src) {1053 return __riscv_vreinterpret_v_i8m4_i16m4(src);1054}1055 1056// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_i8m8_i16m81057// CHECK-RV64-SAME: (<vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {1058// CHECK-RV64-NEXT: entry:1059// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 64 x i8> [[SRC]] to <vscale x 32 x i16>1060// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]1061//1062vint16m8_t test_vreinterpret_v_i8m8_i16m8(vint8m8_t src) {1063 return __riscv_vreinterpret_v_i8m8_i16m8(src);1064}1065 1066// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vreinterpret_v_u8mf4_u16mf41067// CHECK-RV64-SAME: (<vscale x 2 x i8> [[SRC:%.*]]) #[[ATTR0]] {1068// CHECK-RV64-NEXT: entry:1069// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 2 x i8> [[SRC]] to <vscale x 1 x i16>1070// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]1071//1072vuint16mf4_t test_vreinterpret_v_u8mf4_u16mf4(vuint8mf4_t src) {1073 return __riscv_vreinterpret_v_u8mf4_u16mf4(src);1074}1075 1076// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vreinterpret_v_u8mf2_u16mf21077// CHECK-RV64-SAME: (<vscale x 4 x i8> [[SRC:%.*]]) #[[ATTR0]] {1078// CHECK-RV64-NEXT: entry:1079// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 4 x i8> [[SRC]] to <vscale x 2 x i16>1080// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]1081//1082vuint16mf2_t test_vreinterpret_v_u8mf2_u16mf2(vuint8mf2_t src) {1083 return __riscv_vreinterpret_v_u8mf2_u16mf2(src);1084}1085 1086// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_u8m1_u16m11087// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {1088// CHECK-RV64-NEXT: entry:1089// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 4 x i16>1090// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]1091//1092vuint16m1_t test_vreinterpret_v_u8m1_u16m1(vuint8m1_t src) {1093 return __riscv_vreinterpret_v_u8m1_u16m1(src);1094}1095 1096// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_u8m2_u16m21097// CHECK-RV64-SAME: (<vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {1098// CHECK-RV64-NEXT: entry:1099// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 16 x i8> [[SRC]] to <vscale x 8 x i16>1100// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]1101//1102vuint16m2_t test_vreinterpret_v_u8m2_u16m2(vuint8m2_t src) {1103 return __riscv_vreinterpret_v_u8m2_u16m2(src);1104}1105 1106// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_u8m4_u16m41107// CHECK-RV64-SAME: (<vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {1108// CHECK-RV64-NEXT: entry:1109// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 32 x i8> [[SRC]] to <vscale x 16 x i16>1110// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]1111//1112vuint16m4_t test_vreinterpret_v_u8m4_u16m4(vuint8m4_t src) {1113 return __riscv_vreinterpret_v_u8m4_u16m4(src);1114}1115 1116// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_u8m8_u16m81117// CHECK-RV64-SAME: (<vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {1118// CHECK-RV64-NEXT: entry:1119// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 64 x i8> [[SRC]] to <vscale x 32 x i16>1120// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]1121//1122vuint16m8_t test_vreinterpret_v_u8m8_u16m8(vuint8m8_t src) {1123 return __riscv_vreinterpret_v_u8m8_u16m8(src);1124}1125 1126// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vreinterpret_v_i8mf2_i32mf21127// CHECK-RV64-SAME: (<vscale x 4 x i8> [[SRC:%.*]]) #[[ATTR0]] {1128// CHECK-RV64-NEXT: entry:1129// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 4 x i8> [[SRC]] to <vscale x 1 x i32>1130// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]1131//1132vint32mf2_t test_vreinterpret_v_i8mf2_i32mf2(vint8mf2_t src) {1133 return __riscv_vreinterpret_v_i8mf2_i32mf2(src);1134}1135 1136// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_i8m1_i32m11137// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {1138// CHECK-RV64-NEXT: entry:1139// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 2 x i32>1140// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]1141//1142vint32m1_t test_vreinterpret_v_i8m1_i32m1(vint8m1_t src) {1143 return __riscv_vreinterpret_v_i8m1_i32m1(src);1144}1145 1146// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_i8m2_i32m21147// CHECK-RV64-SAME: (<vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {1148// CHECK-RV64-NEXT: entry:1149// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 16 x i8> [[SRC]] to <vscale x 4 x i32>1150// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]1151//1152vint32m2_t test_vreinterpret_v_i8m2_i32m2(vint8m2_t src) {1153 return __riscv_vreinterpret_v_i8m2_i32m2(src);1154}1155 1156// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_i8m4_i32m41157// CHECK-RV64-SAME: (<vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {1158// CHECK-RV64-NEXT: entry:1159// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 32 x i8> [[SRC]] to <vscale x 8 x i32>1160// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]1161//1162vint32m4_t test_vreinterpret_v_i8m4_i32m4(vint8m4_t src) {1163 return __riscv_vreinterpret_v_i8m4_i32m4(src);1164}1165 1166// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_i8m8_i32m81167// CHECK-RV64-SAME: (<vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {1168// CHECK-RV64-NEXT: entry:1169// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 64 x i8> [[SRC]] to <vscale x 16 x i32>1170// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]1171//1172vint32m8_t test_vreinterpret_v_i8m8_i32m8(vint8m8_t src) {1173 return __riscv_vreinterpret_v_i8m8_i32m8(src);1174}1175 1176// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vreinterpret_v_u8mf2_u32mf21177// CHECK-RV64-SAME: (<vscale x 4 x i8> [[SRC:%.*]]) #[[ATTR0]] {1178// CHECK-RV64-NEXT: entry:1179// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 4 x i8> [[SRC]] to <vscale x 1 x i32>1180// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]1181//1182vuint32mf2_t test_vreinterpret_v_u8mf2_u32mf2(vuint8mf2_t src) {1183 return __riscv_vreinterpret_v_u8mf2_u32mf2(src);1184}1185 1186// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_u8m1_u32m11187// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {1188// CHECK-RV64-NEXT: entry:1189// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 2 x i32>1190// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]1191//1192vuint32m1_t test_vreinterpret_v_u8m1_u32m1(vuint8m1_t src) {1193 return __riscv_vreinterpret_v_u8m1_u32m1(src);1194}1195 1196// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_u8m2_u32m21197// CHECK-RV64-SAME: (<vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {1198// CHECK-RV64-NEXT: entry:1199// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 16 x i8> [[SRC]] to <vscale x 4 x i32>1200// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]1201//1202vuint32m2_t test_vreinterpret_v_u8m2_u32m2(vuint8m2_t src) {1203 return __riscv_vreinterpret_v_u8m2_u32m2(src);1204}1205 1206// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_u8m4_u32m41207// CHECK-RV64-SAME: (<vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {1208// CHECK-RV64-NEXT: entry:1209// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 32 x i8> [[SRC]] to <vscale x 8 x i32>1210// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]1211//1212vuint32m4_t test_vreinterpret_v_u8m4_u32m4(vuint8m4_t src) {1213 return __riscv_vreinterpret_v_u8m4_u32m4(src);1214}1215 1216// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_u8m8_u32m81217// CHECK-RV64-SAME: (<vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {1218// CHECK-RV64-NEXT: entry:1219// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 64 x i8> [[SRC]] to <vscale x 16 x i32>1220// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]1221//1222vuint32m8_t test_vreinterpret_v_u8m8_u32m8(vuint8m8_t src) {1223 return __riscv_vreinterpret_v_u8m8_u32m8(src);1224}1225 1226// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_i8m1_i64m11227// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {1228// CHECK-RV64-NEXT: entry:1229// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 1 x i64>1230// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]1231//1232vint64m1_t test_vreinterpret_v_i8m1_i64m1(vint8m1_t src) {1233 return __riscv_vreinterpret_v_i8m1_i64m1(src);1234}1235 1236// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_i8m2_i64m21237// CHECK-RV64-SAME: (<vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {1238// CHECK-RV64-NEXT: entry:1239// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 16 x i8> [[SRC]] to <vscale x 2 x i64>1240// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]1241//1242vint64m2_t test_vreinterpret_v_i8m2_i64m2(vint8m2_t src) {1243 return __riscv_vreinterpret_v_i8m2_i64m2(src);1244}1245 1246// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_i8m4_i64m41247// CHECK-RV64-SAME: (<vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {1248// CHECK-RV64-NEXT: entry:1249// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 32 x i8> [[SRC]] to <vscale x 4 x i64>1250// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]1251//1252vint64m4_t test_vreinterpret_v_i8m4_i64m4(vint8m4_t src) {1253 return __riscv_vreinterpret_v_i8m4_i64m4(src);1254}1255 1256// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_i8m8_i64m81257// CHECK-RV64-SAME: (<vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {1258// CHECK-RV64-NEXT: entry:1259// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 64 x i8> [[SRC]] to <vscale x 8 x i64>1260// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]1261//1262vint64m8_t test_vreinterpret_v_i8m8_i64m8(vint8m8_t src) {1263 return __riscv_vreinterpret_v_i8m8_i64m8(src);1264}1265 1266// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_u8m1_u64m11267// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {1268// CHECK-RV64-NEXT: entry:1269// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 1 x i64>1270// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]1271//1272vuint64m1_t test_vreinterpret_v_u8m1_u64m1(vuint8m1_t src) {1273 return __riscv_vreinterpret_v_u8m1_u64m1(src);1274}1275 1276// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_u8m2_u64m21277// CHECK-RV64-SAME: (<vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {1278// CHECK-RV64-NEXT: entry:1279// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 16 x i8> [[SRC]] to <vscale x 2 x i64>1280// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]1281//1282vuint64m2_t test_vreinterpret_v_u8m2_u64m2(vuint8m2_t src) {1283 return __riscv_vreinterpret_v_u8m2_u64m2(src);1284}1285 1286// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_u8m4_u64m41287// CHECK-RV64-SAME: (<vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {1288// CHECK-RV64-NEXT: entry:1289// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 32 x i8> [[SRC]] to <vscale x 4 x i64>1290// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]1291//1292vuint64m4_t test_vreinterpret_v_u8m4_u64m4(vuint8m4_t src) {1293 return __riscv_vreinterpret_v_u8m4_u64m4(src);1294}1295 1296// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_u8m8_u64m81297// CHECK-RV64-SAME: (<vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {1298// CHECK-RV64-NEXT: entry:1299// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 64 x i8> [[SRC]] to <vscale x 8 x i64>1300// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]1301//1302vuint64m8_t test_vreinterpret_v_u8m8_u64m8(vuint8m8_t src) {1303 return __riscv_vreinterpret_v_u8m8_u64m8(src);1304}1305 1306// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vreinterpret_v_i16mf4_i8mf41307// CHECK-RV64-SAME: (<vscale x 1 x i16> [[SRC:%.*]]) #[[ATTR0]] {1308// CHECK-RV64-NEXT: entry:1309// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 1 x i16> [[SRC]] to <vscale x 2 x i8>1310// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]1311//1312vint8mf4_t test_vreinterpret_v_i16mf4_i8mf4(vint16mf4_t src) {1313 return __riscv_vreinterpret_v_i16mf4_i8mf4(src);1314}1315 1316// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vreinterpret_v_i16mf2_i8mf21317// CHECK-RV64-SAME: (<vscale x 2 x i16> [[SRC:%.*]]) #[[ATTR0]] {1318// CHECK-RV64-NEXT: entry:1319// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 2 x i16> [[SRC]] to <vscale x 4 x i8>1320// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]1321//1322vint8mf2_t test_vreinterpret_v_i16mf2_i8mf2(vint16mf2_t src) {1323 return __riscv_vreinterpret_v_i16mf2_i8mf2(src);1324}1325 1326// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_i16m1_i8m11327// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {1328// CHECK-RV64-NEXT: entry:1329// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 8 x i8>1330// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]1331//1332vint8m1_t test_vreinterpret_v_i16m1_i8m1(vint16m1_t src) {1333 return __riscv_vreinterpret_v_i16m1_i8m1(src);1334}1335 1336// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vreinterpret_v_i16m2_i8m21337// CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {1338// CHECK-RV64-NEXT: entry:1339// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC]] to <vscale x 16 x i8>1340// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]1341//1342vint8m2_t test_vreinterpret_v_i16m2_i8m2(vint16m2_t src) {1343 return __riscv_vreinterpret_v_i16m2_i8m2(src);1344}1345 1346// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vreinterpret_v_i16m4_i8m41347// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {1348// CHECK-RV64-NEXT: entry:1349// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC]] to <vscale x 32 x i8>1350// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]1351//1352vint8m4_t test_vreinterpret_v_i16m4_i8m4(vint16m4_t src) {1353 return __riscv_vreinterpret_v_i16m4_i8m4(src);1354}1355 1356// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vreinterpret_v_i16m8_i8m81357// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {1358// CHECK-RV64-NEXT: entry:1359// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC]] to <vscale x 64 x i8>1360// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]1361//1362vint8m8_t test_vreinterpret_v_i16m8_i8m8(vint16m8_t src) {1363 return __riscv_vreinterpret_v_i16m8_i8m8(src);1364}1365 1366// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vreinterpret_v_u16mf4_u8mf41367// CHECK-RV64-SAME: (<vscale x 1 x i16> [[SRC:%.*]]) #[[ATTR0]] {1368// CHECK-RV64-NEXT: entry:1369// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 1 x i16> [[SRC]] to <vscale x 2 x i8>1370// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]1371//1372vuint8mf4_t test_vreinterpret_v_u16mf4_u8mf4(vuint16mf4_t src) {1373 return __riscv_vreinterpret_v_u16mf4_u8mf4(src);1374}1375 1376// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vreinterpret_v_u16mf2_u8mf21377// CHECK-RV64-SAME: (<vscale x 2 x i16> [[SRC:%.*]]) #[[ATTR0]] {1378// CHECK-RV64-NEXT: entry:1379// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 2 x i16> [[SRC]] to <vscale x 4 x i8>1380// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]1381//1382vuint8mf2_t test_vreinterpret_v_u16mf2_u8mf2(vuint16mf2_t src) {1383 return __riscv_vreinterpret_v_u16mf2_u8mf2(src);1384}1385 1386// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u16m1_u8m11387// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {1388// CHECK-RV64-NEXT: entry:1389// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 8 x i8>1390// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]1391//1392vuint8m1_t test_vreinterpret_v_u16m1_u8m1(vuint16m1_t src) {1393 return __riscv_vreinterpret_v_u16m1_u8m1(src);1394}1395 1396// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u16m2_u8m21397// CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {1398// CHECK-RV64-NEXT: entry:1399// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC]] to <vscale x 16 x i8>1400// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]1401//1402vuint8m2_t test_vreinterpret_v_u16m2_u8m2(vuint16m2_t src) {1403 return __riscv_vreinterpret_v_u16m2_u8m2(src);1404}1405 1406// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u16m4_u8m41407// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {1408// CHECK-RV64-NEXT: entry:1409// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC]] to <vscale x 32 x i8>1410// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]1411//1412vuint8m4_t test_vreinterpret_v_u16m4_u8m4(vuint16m4_t src) {1413 return __riscv_vreinterpret_v_u16m4_u8m4(src);1414}1415 1416// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u16m8_u8m81417// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {1418// CHECK-RV64-NEXT: entry:1419// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC]] to <vscale x 64 x i8>1420// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]1421//1422vuint8m8_t test_vreinterpret_v_u16m8_u8m8(vuint16m8_t src) {1423 return __riscv_vreinterpret_v_u16m8_u8m8(src);1424}1425 1426// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vreinterpret_v_i16mf2_i32mf21427// CHECK-RV64-SAME: (<vscale x 2 x i16> [[SRC:%.*]]) #[[ATTR0]] {1428// CHECK-RV64-NEXT: entry:1429// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 2 x i16> [[SRC]] to <vscale x 1 x i32>1430// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]1431//1432vint32mf2_t test_vreinterpret_v_i16mf2_i32mf2(vint16mf2_t src) {1433 return __riscv_vreinterpret_v_i16mf2_i32mf2(src);1434}1435 1436// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_i16m1_i32m11437// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {1438// CHECK-RV64-NEXT: entry:1439// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 2 x i32>1440// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]1441//1442vint32m1_t test_vreinterpret_v_i16m1_i32m1(vint16m1_t src) {1443 return __riscv_vreinterpret_v_i16m1_i32m1(src);1444}1445 1446// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_i16m2_i32m21447// CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {1448// CHECK-RV64-NEXT: entry:1449// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC]] to <vscale x 4 x i32>1450// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]1451//1452vint32m2_t test_vreinterpret_v_i16m2_i32m2(vint16m2_t src) {1453 return __riscv_vreinterpret_v_i16m2_i32m2(src);1454}1455 1456// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_i16m4_i32m41457// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {1458// CHECK-RV64-NEXT: entry:1459// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC]] to <vscale x 8 x i32>1460// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]1461//1462vint32m4_t test_vreinterpret_v_i16m4_i32m4(vint16m4_t src) {1463 return __riscv_vreinterpret_v_i16m4_i32m4(src);1464}1465 1466// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_i16m8_i32m81467// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {1468// CHECK-RV64-NEXT: entry:1469// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC]] to <vscale x 16 x i32>1470// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]1471//1472vint32m8_t test_vreinterpret_v_i16m8_i32m8(vint16m8_t src) {1473 return __riscv_vreinterpret_v_i16m8_i32m8(src);1474}1475 1476// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vreinterpret_v_u16mf2_u32mf21477// CHECK-RV64-SAME: (<vscale x 2 x i16> [[SRC:%.*]]) #[[ATTR0]] {1478// CHECK-RV64-NEXT: entry:1479// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 2 x i16> [[SRC]] to <vscale x 1 x i32>1480// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]1481//1482vuint32mf2_t test_vreinterpret_v_u16mf2_u32mf2(vuint16mf2_t src) {1483 return __riscv_vreinterpret_v_u16mf2_u32mf2(src);1484}1485 1486// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_u16m1_u32m11487// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {1488// CHECK-RV64-NEXT: entry:1489// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 2 x i32>1490// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]1491//1492vuint32m1_t test_vreinterpret_v_u16m1_u32m1(vuint16m1_t src) {1493 return __riscv_vreinterpret_v_u16m1_u32m1(src);1494}1495 1496// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_u16m2_u32m21497// CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {1498// CHECK-RV64-NEXT: entry:1499// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC]] to <vscale x 4 x i32>1500// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]1501//1502vuint32m2_t test_vreinterpret_v_u16m2_u32m2(vuint16m2_t src) {1503 return __riscv_vreinterpret_v_u16m2_u32m2(src);1504}1505 1506// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_u16m4_u32m41507// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {1508// CHECK-RV64-NEXT: entry:1509// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC]] to <vscale x 8 x i32>1510// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]1511//1512vuint32m4_t test_vreinterpret_v_u16m4_u32m4(vuint16m4_t src) {1513 return __riscv_vreinterpret_v_u16m4_u32m4(src);1514}1515 1516// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_u16m8_u32m81517// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {1518// CHECK-RV64-NEXT: entry:1519// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC]] to <vscale x 16 x i32>1520// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]1521//1522vuint32m8_t test_vreinterpret_v_u16m8_u32m8(vuint16m8_t src) {1523 return __riscv_vreinterpret_v_u16m8_u32m8(src);1524}1525 1526// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_i16m1_i64m11527// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {1528// CHECK-RV64-NEXT: entry:1529// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 1 x i64>1530// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]1531//1532vint64m1_t test_vreinterpret_v_i16m1_i64m1(vint16m1_t src) {1533 return __riscv_vreinterpret_v_i16m1_i64m1(src);1534}1535 1536// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_i16m2_i64m21537// CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {1538// CHECK-RV64-NEXT: entry:1539// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC]] to <vscale x 2 x i64>1540// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]1541//1542vint64m2_t test_vreinterpret_v_i16m2_i64m2(vint16m2_t src) {1543 return __riscv_vreinterpret_v_i16m2_i64m2(src);1544}1545 1546// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_i16m4_i64m41547// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {1548// CHECK-RV64-NEXT: entry:1549// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC]] to <vscale x 4 x i64>1550// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]1551//1552vint64m4_t test_vreinterpret_v_i16m4_i64m4(vint16m4_t src) {1553 return __riscv_vreinterpret_v_i16m4_i64m4(src);1554}1555 1556// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_i16m8_i64m81557// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {1558// CHECK-RV64-NEXT: entry:1559// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC]] to <vscale x 8 x i64>1560// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]1561//1562vint64m8_t test_vreinterpret_v_i16m8_i64m8(vint16m8_t src) {1563 return __riscv_vreinterpret_v_i16m8_i64m8(src);1564}1565 1566// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_u16m1_u64m11567// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {1568// CHECK-RV64-NEXT: entry:1569// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 1 x i64>1570// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]1571//1572vuint64m1_t test_vreinterpret_v_u16m1_u64m1(vuint16m1_t src) {1573 return __riscv_vreinterpret_v_u16m1_u64m1(src);1574}1575 1576// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_u16m2_u64m21577// CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {1578// CHECK-RV64-NEXT: entry:1579// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC]] to <vscale x 2 x i64>1580// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]1581//1582vuint64m2_t test_vreinterpret_v_u16m2_u64m2(vuint16m2_t src) {1583 return __riscv_vreinterpret_v_u16m2_u64m2(src);1584}1585 1586// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_u16m4_u64m41587// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {1588// CHECK-RV64-NEXT: entry:1589// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC]] to <vscale x 4 x i64>1590// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]1591//1592vuint64m4_t test_vreinterpret_v_u16m4_u64m4(vuint16m4_t src) {1593 return __riscv_vreinterpret_v_u16m4_u64m4(src);1594}1595 1596// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_u16m8_u64m81597// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {1598// CHECK-RV64-NEXT: entry:1599// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC]] to <vscale x 8 x i64>1600// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]1601//1602vuint64m8_t test_vreinterpret_v_u16m8_u64m8(vuint16m8_t src) {1603 return __riscv_vreinterpret_v_u16m8_u64m8(src);1604}1605 1606// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vreinterpret_v_i32mf2_i8mf21607// CHECK-RV64-SAME: (<vscale x 1 x i32> [[SRC:%.*]]) #[[ATTR0]] {1608// CHECK-RV64-NEXT: entry:1609// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 1 x i32> [[SRC]] to <vscale x 4 x i8>1610// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]1611//1612vint8mf2_t test_vreinterpret_v_i32mf2_i8mf2(vint32mf2_t src) {1613 return __riscv_vreinterpret_v_i32mf2_i8mf2(src);1614}1615 1616// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_i32m1_i8m11617// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {1618// CHECK-RV64-NEXT: entry:1619// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 8 x i8>1620// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]1621//1622vint8m1_t test_vreinterpret_v_i32m1_i8m1(vint32m1_t src) {1623 return __riscv_vreinterpret_v_i32m1_i8m1(src);1624}1625 1626// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vreinterpret_v_i32m2_i8m21627// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {1628// CHECK-RV64-NEXT: entry:1629// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC]] to <vscale x 16 x i8>1630// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]1631//1632vint8m2_t test_vreinterpret_v_i32m2_i8m2(vint32m2_t src) {1633 return __riscv_vreinterpret_v_i32m2_i8m2(src);1634}1635 1636// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vreinterpret_v_i32m4_i8m41637// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {1638// CHECK-RV64-NEXT: entry:1639// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC]] to <vscale x 32 x i8>1640// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]1641//1642vint8m4_t test_vreinterpret_v_i32m4_i8m4(vint32m4_t src) {1643 return __riscv_vreinterpret_v_i32m4_i8m4(src);1644}1645 1646// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vreinterpret_v_i32m8_i8m81647// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {1648// CHECK-RV64-NEXT: entry:1649// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC]] to <vscale x 64 x i8>1650// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]1651//1652vint8m8_t test_vreinterpret_v_i32m8_i8m8(vint32m8_t src) {1653 return __riscv_vreinterpret_v_i32m8_i8m8(src);1654}1655 1656// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vreinterpret_v_u32mf2_u8mf21657// CHECK-RV64-SAME: (<vscale x 1 x i32> [[SRC:%.*]]) #[[ATTR0]] {1658// CHECK-RV64-NEXT: entry:1659// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 1 x i32> [[SRC]] to <vscale x 4 x i8>1660// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]1661//1662vuint8mf2_t test_vreinterpret_v_u32mf2_u8mf2(vuint32mf2_t src) {1663 return __riscv_vreinterpret_v_u32mf2_u8mf2(src);1664}1665 1666// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u32m1_u8m11667// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {1668// CHECK-RV64-NEXT: entry:1669// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 8 x i8>1670// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]1671//1672vuint8m1_t test_vreinterpret_v_u32m1_u8m1(vuint32m1_t src) {1673 return __riscv_vreinterpret_v_u32m1_u8m1(src);1674}1675 1676// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u32m2_u8m21677// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {1678// CHECK-RV64-NEXT: entry:1679// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC]] to <vscale x 16 x i8>1680// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]1681//1682vuint8m2_t test_vreinterpret_v_u32m2_u8m2(vuint32m2_t src) {1683 return __riscv_vreinterpret_v_u32m2_u8m2(src);1684}1685 1686// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u32m4_u8m41687// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {1688// CHECK-RV64-NEXT: entry:1689// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC]] to <vscale x 32 x i8>1690// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]1691//1692vuint8m4_t test_vreinterpret_v_u32m4_u8m4(vuint32m4_t src) {1693 return __riscv_vreinterpret_v_u32m4_u8m4(src);1694}1695 1696// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u32m8_u8m81697// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {1698// CHECK-RV64-NEXT: entry:1699// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC]] to <vscale x 64 x i8>1700// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]1701//1702vuint8m8_t test_vreinterpret_v_u32m8_u8m8(vuint32m8_t src) {1703 return __riscv_vreinterpret_v_u32m8_u8m8(src);1704}1705 1706// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vreinterpret_v_i32mf2_i16mf21707// CHECK-RV64-SAME: (<vscale x 1 x i32> [[SRC:%.*]]) #[[ATTR0]] {1708// CHECK-RV64-NEXT: entry:1709// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 1 x i32> [[SRC]] to <vscale x 2 x i16>1710// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]1711//1712vint16mf2_t test_vreinterpret_v_i32mf2_i16mf2(vint32mf2_t src) {1713 return __riscv_vreinterpret_v_i32mf2_i16mf2(src);1714}1715 1716// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_i32m1_i16m11717// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {1718// CHECK-RV64-NEXT: entry:1719// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 4 x i16>1720// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]1721//1722vint16m1_t test_vreinterpret_v_i32m1_i16m1(vint32m1_t src) {1723 return __riscv_vreinterpret_v_i32m1_i16m1(src);1724}1725 1726// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_i32m2_i16m21727// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {1728// CHECK-RV64-NEXT: entry:1729// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC]] to <vscale x 8 x i16>1730// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]1731//1732vint16m2_t test_vreinterpret_v_i32m2_i16m2(vint32m2_t src) {1733 return __riscv_vreinterpret_v_i32m2_i16m2(src);1734}1735 1736// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_i32m4_i16m41737// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {1738// CHECK-RV64-NEXT: entry:1739// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC]] to <vscale x 16 x i16>1740// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]1741//1742vint16m4_t test_vreinterpret_v_i32m4_i16m4(vint32m4_t src) {1743 return __riscv_vreinterpret_v_i32m4_i16m4(src);1744}1745 1746// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_i32m8_i16m81747// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {1748// CHECK-RV64-NEXT: entry:1749// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC]] to <vscale x 32 x i16>1750// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]1751//1752vint16m8_t test_vreinterpret_v_i32m8_i16m8(vint32m8_t src) {1753 return __riscv_vreinterpret_v_i32m8_i16m8(src);1754}1755 1756// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vreinterpret_v_u32mf2_u16mf21757// CHECK-RV64-SAME: (<vscale x 1 x i32> [[SRC:%.*]]) #[[ATTR0]] {1758// CHECK-RV64-NEXT: entry:1759// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 1 x i32> [[SRC]] to <vscale x 2 x i16>1760// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]1761//1762vuint16mf2_t test_vreinterpret_v_u32mf2_u16mf2(vuint32mf2_t src) {1763 return __riscv_vreinterpret_v_u32mf2_u16mf2(src);1764}1765 1766// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_u32m1_u16m11767// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {1768// CHECK-RV64-NEXT: entry:1769// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 4 x i16>1770// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]1771//1772vuint16m1_t test_vreinterpret_v_u32m1_u16m1(vuint32m1_t src) {1773 return __riscv_vreinterpret_v_u32m1_u16m1(src);1774}1775 1776// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_u32m2_u16m21777// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {1778// CHECK-RV64-NEXT: entry:1779// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC]] to <vscale x 8 x i16>1780// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]1781//1782vuint16m2_t test_vreinterpret_v_u32m2_u16m2(vuint32m2_t src) {1783 return __riscv_vreinterpret_v_u32m2_u16m2(src);1784}1785 1786// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_u32m4_u16m41787// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {1788// CHECK-RV64-NEXT: entry:1789// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC]] to <vscale x 16 x i16>1790// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]1791//1792vuint16m4_t test_vreinterpret_v_u32m4_u16m4(vuint32m4_t src) {1793 return __riscv_vreinterpret_v_u32m4_u16m4(src);1794}1795 1796// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_u32m8_u16m81797// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {1798// CHECK-RV64-NEXT: entry:1799// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC]] to <vscale x 32 x i16>1800// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]1801//1802vuint16m8_t test_vreinterpret_v_u32m8_u16m8(vuint32m8_t src) {1803 return __riscv_vreinterpret_v_u32m8_u16m8(src);1804}1805 1806// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_i32m1_i64m11807// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {1808// CHECK-RV64-NEXT: entry:1809// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 1 x i64>1810// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]1811//1812vint64m1_t test_vreinterpret_v_i32m1_i64m1(vint32m1_t src) {1813 return __riscv_vreinterpret_v_i32m1_i64m1(src);1814}1815 1816// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_i32m2_i64m21817// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {1818// CHECK-RV64-NEXT: entry:1819// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC]] to <vscale x 2 x i64>1820// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]1821//1822vint64m2_t test_vreinterpret_v_i32m2_i64m2(vint32m2_t src) {1823 return __riscv_vreinterpret_v_i32m2_i64m2(src);1824}1825 1826// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_i32m4_i64m41827// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {1828// CHECK-RV64-NEXT: entry:1829// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC]] to <vscale x 4 x i64>1830// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]1831//1832vint64m4_t test_vreinterpret_v_i32m4_i64m4(vint32m4_t src) {1833 return __riscv_vreinterpret_v_i32m4_i64m4(src);1834}1835 1836// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_i32m8_i64m81837// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {1838// CHECK-RV64-NEXT: entry:1839// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC]] to <vscale x 8 x i64>1840// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]1841//1842vint64m8_t test_vreinterpret_v_i32m8_i64m8(vint32m8_t src) {1843 return __riscv_vreinterpret_v_i32m8_i64m8(src);1844}1845 1846// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_u32m1_u64m11847// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {1848// CHECK-RV64-NEXT: entry:1849// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 1 x i64>1850// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]1851//1852vuint64m1_t test_vreinterpret_v_u32m1_u64m1(vuint32m1_t src) {1853 return __riscv_vreinterpret_v_u32m1_u64m1(src);1854}1855 1856// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_u32m2_u64m21857// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {1858// CHECK-RV64-NEXT: entry:1859// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC]] to <vscale x 2 x i64>1860// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]1861//1862vuint64m2_t test_vreinterpret_v_u32m2_u64m2(vuint32m2_t src) {1863 return __riscv_vreinterpret_v_u32m2_u64m2(src);1864}1865 1866// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_u32m4_u64m41867// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {1868// CHECK-RV64-NEXT: entry:1869// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC]] to <vscale x 4 x i64>1870// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]1871//1872vuint64m4_t test_vreinterpret_v_u32m4_u64m4(vuint32m4_t src) {1873 return __riscv_vreinterpret_v_u32m4_u64m4(src);1874}1875 1876// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_u32m8_u64m81877// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {1878// CHECK-RV64-NEXT: entry:1879// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC]] to <vscale x 8 x i64>1880// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]1881//1882vuint64m8_t test_vreinterpret_v_u32m8_u64m8(vuint32m8_t src) {1883 return __riscv_vreinterpret_v_u32m8_u64m8(src);1884}1885 1886// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_i64m1_i8m11887// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {1888// CHECK-RV64-NEXT: entry:1889// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 8 x i8>1890// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]1891//1892vint8m1_t test_vreinterpret_v_i64m1_i8m1(vint64m1_t src) {1893 return __riscv_vreinterpret_v_i64m1_i8m1(src);1894}1895 1896// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vreinterpret_v_i64m2_i8m21897// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {1898// CHECK-RV64-NEXT: entry:1899// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC]] to <vscale x 16 x i8>1900// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]1901//1902vint8m2_t test_vreinterpret_v_i64m2_i8m2(vint64m2_t src) {1903 return __riscv_vreinterpret_v_i64m2_i8m2(src);1904}1905 1906// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vreinterpret_v_i64m4_i8m41907// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {1908// CHECK-RV64-NEXT: entry:1909// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC]] to <vscale x 32 x i8>1910// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]1911//1912vint8m4_t test_vreinterpret_v_i64m4_i8m4(vint64m4_t src) {1913 return __riscv_vreinterpret_v_i64m4_i8m4(src);1914}1915 1916// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vreinterpret_v_i64m8_i8m81917// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {1918// CHECK-RV64-NEXT: entry:1919// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC]] to <vscale x 64 x i8>1920// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]1921//1922vint8m8_t test_vreinterpret_v_i64m8_i8m8(vint64m8_t src) {1923 return __riscv_vreinterpret_v_i64m8_i8m8(src);1924}1925 1926// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u64m1_u8m11927// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {1928// CHECK-RV64-NEXT: entry:1929// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 8 x i8>1930// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]1931//1932vuint8m1_t test_vreinterpret_v_u64m1_u8m1(vuint64m1_t src) {1933 return __riscv_vreinterpret_v_u64m1_u8m1(src);1934}1935 1936// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u64m2_u8m21937// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {1938// CHECK-RV64-NEXT: entry:1939// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC]] to <vscale x 16 x i8>1940// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]1941//1942vuint8m2_t test_vreinterpret_v_u64m2_u8m2(vuint64m2_t src) {1943 return __riscv_vreinterpret_v_u64m2_u8m2(src);1944}1945 1946// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u64m4_u8m41947// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {1948// CHECK-RV64-NEXT: entry:1949// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC]] to <vscale x 32 x i8>1950// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]1951//1952vuint8m4_t test_vreinterpret_v_u64m4_u8m4(vuint64m4_t src) {1953 return __riscv_vreinterpret_v_u64m4_u8m4(src);1954}1955 1956// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u64m8_u8m81957// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {1958// CHECK-RV64-NEXT: entry:1959// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC]] to <vscale x 64 x i8>1960// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]1961//1962vuint8m8_t test_vreinterpret_v_u64m8_u8m8(vuint64m8_t src) {1963 return __riscv_vreinterpret_v_u64m8_u8m8(src);1964}1965 1966// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_i64m1_i16m11967// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {1968// CHECK-RV64-NEXT: entry:1969// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 4 x i16>1970// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]1971//1972vint16m1_t test_vreinterpret_v_i64m1_i16m1(vint64m1_t src) {1973 return __riscv_vreinterpret_v_i64m1_i16m1(src);1974}1975 1976// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_i64m2_i16m21977// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {1978// CHECK-RV64-NEXT: entry:1979// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC]] to <vscale x 8 x i16>1980// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]1981//1982vint16m2_t test_vreinterpret_v_i64m2_i16m2(vint64m2_t src) {1983 return __riscv_vreinterpret_v_i64m2_i16m2(src);1984}1985 1986// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_i64m4_i16m41987// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {1988// CHECK-RV64-NEXT: entry:1989// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC]] to <vscale x 16 x i16>1990// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]1991//1992vint16m4_t test_vreinterpret_v_i64m4_i16m4(vint64m4_t src) {1993 return __riscv_vreinterpret_v_i64m4_i16m4(src);1994}1995 1996// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_i64m8_i16m81997// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {1998// CHECK-RV64-NEXT: entry:1999// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC]] to <vscale x 32 x i16>2000// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]2001//2002vint16m8_t test_vreinterpret_v_i64m8_i16m8(vint64m8_t src) {2003 return __riscv_vreinterpret_v_i64m8_i16m8(src);2004}2005 2006// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_u64m1_u16m12007// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {2008// CHECK-RV64-NEXT: entry:2009// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 4 x i16>2010// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]2011//2012vuint16m1_t test_vreinterpret_v_u64m1_u16m1(vuint64m1_t src) {2013 return __riscv_vreinterpret_v_u64m1_u16m1(src);2014}2015 2016// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_u64m2_u16m22017// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {2018// CHECK-RV64-NEXT: entry:2019// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC]] to <vscale x 8 x i16>2020// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]2021//2022vuint16m2_t test_vreinterpret_v_u64m2_u16m2(vuint64m2_t src) {2023 return __riscv_vreinterpret_v_u64m2_u16m2(src);2024}2025 2026// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_u64m4_u16m42027// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {2028// CHECK-RV64-NEXT: entry:2029// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC]] to <vscale x 16 x i16>2030// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]2031//2032vuint16m4_t test_vreinterpret_v_u64m4_u16m4(vuint64m4_t src) {2033 return __riscv_vreinterpret_v_u64m4_u16m4(src);2034}2035 2036// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_u64m8_u16m82037// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {2038// CHECK-RV64-NEXT: entry:2039// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC]] to <vscale x 32 x i16>2040// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]2041//2042vuint16m8_t test_vreinterpret_v_u64m8_u16m8(vuint64m8_t src) {2043 return __riscv_vreinterpret_v_u64m8_u16m8(src);2044}2045 2046// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_i64m1_i32m12047// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {2048// CHECK-RV64-NEXT: entry:2049// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 2 x i32>2050// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]2051//2052vint32m1_t test_vreinterpret_v_i64m1_i32m1(vint64m1_t src) {2053 return __riscv_vreinterpret_v_i64m1_i32m1(src);2054}2055 2056// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_i64m2_i32m22057// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {2058// CHECK-RV64-NEXT: entry:2059// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC]] to <vscale x 4 x i32>2060// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]2061//2062vint32m2_t test_vreinterpret_v_i64m2_i32m2(vint64m2_t src) {2063 return __riscv_vreinterpret_v_i64m2_i32m2(src);2064}2065 2066// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_i64m4_i32m42067// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {2068// CHECK-RV64-NEXT: entry:2069// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC]] to <vscale x 8 x i32>2070// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]2071//2072vint32m4_t test_vreinterpret_v_i64m4_i32m4(vint64m4_t src) {2073 return __riscv_vreinterpret_v_i64m4_i32m4(src);2074}2075 2076// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_i64m8_i32m82077// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {2078// CHECK-RV64-NEXT: entry:2079// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC]] to <vscale x 16 x i32>2080// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]2081//2082vint32m8_t test_vreinterpret_v_i64m8_i32m8(vint64m8_t src) {2083 return __riscv_vreinterpret_v_i64m8_i32m8(src);2084}2085 2086// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_u64m1_u32m12087// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {2088// CHECK-RV64-NEXT: entry:2089// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 2 x i32>2090// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]2091//2092vuint32m1_t test_vreinterpret_v_u64m1_u32m1(vuint64m1_t src) {2093 return __riscv_vreinterpret_v_u64m1_u32m1(src);2094}2095 2096// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_u64m2_u32m22097// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {2098// CHECK-RV64-NEXT: entry:2099// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC]] to <vscale x 4 x i32>2100// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]2101//2102vuint32m2_t test_vreinterpret_v_u64m2_u32m2(vuint64m2_t src) {2103 return __riscv_vreinterpret_v_u64m2_u32m2(src);2104}2105 2106// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_u64m4_u32m42107// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {2108// CHECK-RV64-NEXT: entry:2109// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC]] to <vscale x 8 x i32>2110// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]2111//2112vuint32m4_t test_vreinterpret_v_u64m4_u32m4(vuint64m4_t src) {2113 return __riscv_vreinterpret_v_u64m4_u32m4(src);2114}2115 2116// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_u64m8_u32m82117// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {2118// CHECK-RV64-NEXT: entry:2119// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC]] to <vscale x 16 x i32>2120// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]2121//2122vuint32m8_t test_vreinterpret_v_u64m8_u32m8(vuint64m8_t src) {2123 return __riscv_vreinterpret_v_u64m8_u32m8(src);2124}2125 2126// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vreinterpret_v_i8m1_b642127// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {2128// CHECK-RV64-NEXT: entry:2129// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 64 x i1>2130// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)2131// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP1]]2132//2133vbool64_t test_vreinterpret_v_i8m1_b64(vint8m1_t src) {2134 return __riscv_vreinterpret_v_i8m1_b64(src);2135}2136 2137// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b64_i8m12138// CHECK-RV64-SAME: (<vscale x 1 x i1> [[SRC:%.*]]) #[[ATTR0]] {2139// CHECK-RV64-NEXT: entry:2140// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv1i1(<vscale x 64 x i1> poison, <vscale x 1 x i1> [[SRC]], i64 0)2141// CHECK-RV64-NEXT: [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 8 x i8>2142// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]2143//2144vint8m1_t test_vreinterpret_v_b64_i8m1(vbool64_t src) {2145 return __riscv_vreinterpret_v_b64_i8m1(src);2146}2147 2148// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vreinterpret_v_i8m1_b322149// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {2150// CHECK-RV64-NEXT: entry:2151// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 64 x i1>2152// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)2153// CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP1]]2154//2155vbool32_t test_vreinterpret_v_i8m1_b32(vint8m1_t src) {2156 return __riscv_vreinterpret_v_i8m1_b32(src);2157}2158 2159// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b32_i8m12160// CHECK-RV64-SAME: (<vscale x 2 x i1> [[SRC:%.*]]) #[[ATTR0]] {2161// CHECK-RV64-NEXT: entry:2162// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv2i1(<vscale x 64 x i1> poison, <vscale x 2 x i1> [[SRC]], i64 0)2163// CHECK-RV64-NEXT: [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 8 x i8>2164// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]2165//2166vint8m1_t test_vreinterpret_v_b32_i8m1(vbool32_t src) {2167 return __riscv_vreinterpret_v_b32_i8m1(src);2168}2169 2170// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vreinterpret_v_i8m1_b162171// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {2172// CHECK-RV64-NEXT: entry:2173// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 64 x i1>2174// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)2175// CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP1]]2176//2177vbool16_t test_vreinterpret_v_i8m1_b16(vint8m1_t src) {2178 return __riscv_vreinterpret_v_i8m1_b16(src);2179}2180 2181// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b16_i8m12182// CHECK-RV64-SAME: (<vscale x 4 x i1> [[SRC:%.*]]) #[[ATTR0]] {2183// CHECK-RV64-NEXT: entry:2184// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv4i1(<vscale x 64 x i1> poison, <vscale x 4 x i1> [[SRC]], i64 0)2185// CHECK-RV64-NEXT: [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 8 x i8>2186// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]2187//2188vint8m1_t test_vreinterpret_v_b16_i8m1(vbool16_t src) {2189 return __riscv_vreinterpret_v_b16_i8m1(src);2190}2191 2192// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vreinterpret_v_i8m1_b82193// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {2194// CHECK-RV64-NEXT: entry:2195// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 64 x i1>2196// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)2197// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP1]]2198//2199vbool8_t test_vreinterpret_v_i8m1_b8(vint8m1_t src) {2200 return __riscv_vreinterpret_v_i8m1_b8(src);2201}2202 2203// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b8_i8m12204// CHECK-RV64-SAME: (<vscale x 8 x i1> [[SRC:%.*]]) #[[ATTR0]] {2205// CHECK-RV64-NEXT: entry:2206// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv8i1(<vscale x 64 x i1> poison, <vscale x 8 x i1> [[SRC]], i64 0)2207// CHECK-RV64-NEXT: [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 8 x i8>2208// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]2209//2210vint8m1_t test_vreinterpret_v_b8_i8m1(vbool8_t src) {2211 return __riscv_vreinterpret_v_b8_i8m1(src);2212}2213 2214// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vreinterpret_v_i8m1_b42215// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {2216// CHECK-RV64-NEXT: entry:2217// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 64 x i1>2218// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i1> @llvm.vector.extract.nxv16i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)2219// CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP1]]2220//2221vbool4_t test_vreinterpret_v_i8m1_b4(vint8m1_t src) {2222 return __riscv_vreinterpret_v_i8m1_b4(src);2223}2224 2225// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b4_i8m12226// CHECK-RV64-SAME: (<vscale x 16 x i1> [[SRC:%.*]]) #[[ATTR0]] {2227// CHECK-RV64-NEXT: entry:2228// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv16i1(<vscale x 64 x i1> poison, <vscale x 16 x i1> [[SRC]], i64 0)2229// CHECK-RV64-NEXT: [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 8 x i8>2230// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]2231//2232vint8m1_t test_vreinterpret_v_b4_i8m1(vbool4_t src) {2233 return __riscv_vreinterpret_v_b4_i8m1(src);2234}2235 2236// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vreinterpret_v_i8m1_b22237// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {2238// CHECK-RV64-NEXT: entry:2239// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 64 x i1>2240// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i1> @llvm.vector.extract.nxv32i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)2241// CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP1]]2242//2243vbool2_t test_vreinterpret_v_i8m1_b2(vint8m1_t src) {2244 return __riscv_vreinterpret_v_i8m1_b2(src);2245}2246 2247// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b2_i8m12248// CHECK-RV64-SAME: (<vscale x 32 x i1> [[SRC:%.*]]) #[[ATTR0]] {2249// CHECK-RV64-NEXT: entry:2250// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv32i1(<vscale x 64 x i1> poison, <vscale x 32 x i1> [[SRC]], i64 0)2251// CHECK-RV64-NEXT: [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 8 x i8>2252// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]2253//2254vint8m1_t test_vreinterpret_v_b2_i8m1(vbool2_t src) {2255 return __riscv_vreinterpret_v_b2_i8m1(src);2256}2257 2258// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i1> @test_vreinterpret_v_i8m1_b12259// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {2260// CHECK-RV64-NEXT: entry:2261// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 64 x i1>2262// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 64 x i1> @llvm.vector.extract.nxv64i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)2263// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP1]]2264//2265vbool1_t test_vreinterpret_v_i8m1_b1(vint8m1_t src) {2266 return __riscv_vreinterpret_v_i8m1_b1(src);2267}2268 2269// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b1_i8m12270// CHECK-RV64-SAME: (<vscale x 64 x i1> [[SRC:%.*]]) #[[ATTR0]] {2271// CHECK-RV64-NEXT: entry:2272// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv64i1(<vscale x 64 x i1> poison, <vscale x 64 x i1> [[SRC]], i64 0)2273// CHECK-RV64-NEXT: [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 8 x i8>2274// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]2275//2276vint8m1_t test_vreinterpret_v_b1_i8m1(vbool1_t src) {2277 return __riscv_vreinterpret_v_b1_i8m1(src);2278}2279 2280// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vreinterpret_v_u8m1_b642281// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {2282// CHECK-RV64-NEXT: entry:2283// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 64 x i1>2284// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)2285// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP1]]2286//2287vbool64_t test_vreinterpret_v_u8m1_b64(vuint8m1_t src) {2288 return __riscv_vreinterpret_v_u8m1_b64(src);2289}2290 2291// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b64_u8m12292// CHECK-RV64-SAME: (<vscale x 1 x i1> [[SRC:%.*]]) #[[ATTR0]] {2293// CHECK-RV64-NEXT: entry:2294// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv1i1(<vscale x 64 x i1> poison, <vscale x 1 x i1> [[SRC]], i64 0)2295// CHECK-RV64-NEXT: [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 8 x i8>2296// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]2297//2298vuint8m1_t test_vreinterpret_v_b64_u8m1(vbool64_t src) {2299 return __riscv_vreinterpret_v_b64_u8m1(src);2300}2301 2302// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vreinterpret_v_u8m1_b322303// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {2304// CHECK-RV64-NEXT: entry:2305// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 64 x i1>2306// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)2307// CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP1]]2308//2309vbool32_t test_vreinterpret_v_u8m1_b32(vuint8m1_t src) {2310 return __riscv_vreinterpret_v_u8m1_b32(src);2311}2312 2313// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b32_u8m12314// CHECK-RV64-SAME: (<vscale x 2 x i1> [[SRC:%.*]]) #[[ATTR0]] {2315// CHECK-RV64-NEXT: entry:2316// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv2i1(<vscale x 64 x i1> poison, <vscale x 2 x i1> [[SRC]], i64 0)2317// CHECK-RV64-NEXT: [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 8 x i8>2318// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]2319//2320vuint8m1_t test_vreinterpret_v_b32_u8m1(vbool32_t src) {2321 return __riscv_vreinterpret_v_b32_u8m1(src);2322}2323 2324// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vreinterpret_v_u8m1_b162325// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {2326// CHECK-RV64-NEXT: entry:2327// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 64 x i1>2328// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)2329// CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP1]]2330//2331vbool16_t test_vreinterpret_v_u8m1_b16(vuint8m1_t src) {2332 return __riscv_vreinterpret_v_u8m1_b16(src);2333}2334 2335// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b16_u8m12336// CHECK-RV64-SAME: (<vscale x 4 x i1> [[SRC:%.*]]) #[[ATTR0]] {2337// CHECK-RV64-NEXT: entry:2338// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv4i1(<vscale x 64 x i1> poison, <vscale x 4 x i1> [[SRC]], i64 0)2339// CHECK-RV64-NEXT: [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 8 x i8>2340// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]2341//2342vuint8m1_t test_vreinterpret_v_b16_u8m1(vbool16_t src) {2343 return __riscv_vreinterpret_v_b16_u8m1(src);2344}2345 2346// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vreinterpret_v_u8m1_b82347// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {2348// CHECK-RV64-NEXT: entry:2349// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 64 x i1>2350// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)2351// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP1]]2352//2353vbool8_t test_vreinterpret_v_u8m1_b8(vuint8m1_t src) {2354 return __riscv_vreinterpret_v_u8m1_b8(src);2355}2356 2357// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b8_u8m12358// CHECK-RV64-SAME: (<vscale x 8 x i1> [[SRC:%.*]]) #[[ATTR0]] {2359// CHECK-RV64-NEXT: entry:2360// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv8i1(<vscale x 64 x i1> poison, <vscale x 8 x i1> [[SRC]], i64 0)2361// CHECK-RV64-NEXT: [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 8 x i8>2362// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]2363//2364vuint8m1_t test_vreinterpret_v_b8_u8m1(vbool8_t src) {2365 return __riscv_vreinterpret_v_b8_u8m1(src);2366}2367 2368// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vreinterpret_v_u8m1_b42369// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {2370// CHECK-RV64-NEXT: entry:2371// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 64 x i1>2372// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i1> @llvm.vector.extract.nxv16i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)2373// CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP1]]2374//2375vbool4_t test_vreinterpret_v_u8m1_b4(vuint8m1_t src) {2376 return __riscv_vreinterpret_v_u8m1_b4(src);2377}2378 2379// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b4_u8m12380// CHECK-RV64-SAME: (<vscale x 16 x i1> [[SRC:%.*]]) #[[ATTR0]] {2381// CHECK-RV64-NEXT: entry:2382// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv16i1(<vscale x 64 x i1> poison, <vscale x 16 x i1> [[SRC]], i64 0)2383// CHECK-RV64-NEXT: [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 8 x i8>2384// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]2385//2386vuint8m1_t test_vreinterpret_v_b4_u8m1(vbool4_t src) {2387 return __riscv_vreinterpret_v_b4_u8m1(src);2388}2389 2390// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vreinterpret_v_u8m1_b22391// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {2392// CHECK-RV64-NEXT: entry:2393// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 64 x i1>2394// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i1> @llvm.vector.extract.nxv32i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)2395// CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP1]]2396//2397vbool2_t test_vreinterpret_v_u8m1_b2(vuint8m1_t src) {2398 return __riscv_vreinterpret_v_u8m1_b2(src);2399}2400 2401// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b2_u8m12402// CHECK-RV64-SAME: (<vscale x 32 x i1> [[SRC:%.*]]) #[[ATTR0]] {2403// CHECK-RV64-NEXT: entry:2404// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv32i1(<vscale x 64 x i1> poison, <vscale x 32 x i1> [[SRC]], i64 0)2405// CHECK-RV64-NEXT: [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 8 x i8>2406// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]2407//2408vuint8m1_t test_vreinterpret_v_b2_u8m1(vbool2_t src) {2409 return __riscv_vreinterpret_v_b2_u8m1(src);2410}2411 2412// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i1> @test_vreinterpret_v_u8m1_b12413// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {2414// CHECK-RV64-NEXT: entry:2415// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 64 x i1>2416// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 64 x i1> @llvm.vector.extract.nxv64i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)2417// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP1]]2418//2419vbool1_t test_vreinterpret_v_u8m1_b1(vuint8m1_t src) {2420 return __riscv_vreinterpret_v_u8m1_b1(src);2421}2422 2423// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b1_u8m12424// CHECK-RV64-SAME: (<vscale x 64 x i1> [[SRC:%.*]]) #[[ATTR0]] {2425// CHECK-RV64-NEXT: entry:2426// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv64i1(<vscale x 64 x i1> poison, <vscale x 64 x i1> [[SRC]], i64 0)2427// CHECK-RV64-NEXT: [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 8 x i8>2428// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]2429//2430vuint8m1_t test_vreinterpret_v_b1_u8m1(vbool1_t src) {2431 return __riscv_vreinterpret_v_b1_u8m1(src);2432}2433 2434// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vreinterpret_v_i16m1_b642435// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {2436// CHECK-RV64-NEXT: entry:2437// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 64 x i1>2438// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)2439// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP1]]2440//2441vbool64_t test_vreinterpret_v_i16m1_b64(vint16m1_t src) {2442 return __riscv_vreinterpret_v_i16m1_b64(src);2443}2444 2445// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b64_i16m12446// CHECK-RV64-SAME: (<vscale x 1 x i1> [[SRC:%.*]]) #[[ATTR0]] {2447// CHECK-RV64-NEXT: entry:2448// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv1i1(<vscale x 64 x i1> poison, <vscale x 1 x i1> [[SRC]], i64 0)2449// CHECK-RV64-NEXT: [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 4 x i16>2450// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]2451//2452vint16m1_t test_vreinterpret_v_b64_i16m1(vbool64_t src) {2453 return __riscv_vreinterpret_v_b64_i16m1(src);2454}2455 2456// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vreinterpret_v_i16m1_b322457// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {2458// CHECK-RV64-NEXT: entry:2459// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 64 x i1>2460// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)2461// CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP1]]2462//2463vbool32_t test_vreinterpret_v_i16m1_b32(vint16m1_t src) {2464 return __riscv_vreinterpret_v_i16m1_b32(src);2465}2466 2467// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b32_i16m12468// CHECK-RV64-SAME: (<vscale x 2 x i1> [[SRC:%.*]]) #[[ATTR0]] {2469// CHECK-RV64-NEXT: entry:2470// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv2i1(<vscale x 64 x i1> poison, <vscale x 2 x i1> [[SRC]], i64 0)2471// CHECK-RV64-NEXT: [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 4 x i16>2472// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]2473//2474vint16m1_t test_vreinterpret_v_b32_i16m1(vbool32_t src) {2475 return __riscv_vreinterpret_v_b32_i16m1(src);2476}2477 2478// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vreinterpret_v_i16m1_b162479// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {2480// CHECK-RV64-NEXT: entry:2481// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 64 x i1>2482// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)2483// CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP1]]2484//2485vbool16_t test_vreinterpret_v_i16m1_b16(vint16m1_t src) {2486 return __riscv_vreinterpret_v_i16m1_b16(src);2487}2488 2489// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b16_i16m12490// CHECK-RV64-SAME: (<vscale x 4 x i1> [[SRC:%.*]]) #[[ATTR0]] {2491// CHECK-RV64-NEXT: entry:2492// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv4i1(<vscale x 64 x i1> poison, <vscale x 4 x i1> [[SRC]], i64 0)2493// CHECK-RV64-NEXT: [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 4 x i16>2494// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]2495//2496vint16m1_t test_vreinterpret_v_b16_i16m1(vbool16_t src) {2497 return __riscv_vreinterpret_v_b16_i16m1(src);2498}2499 2500// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vreinterpret_v_i16m1_b82501// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {2502// CHECK-RV64-NEXT: entry:2503// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 64 x i1>2504// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)2505// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP1]]2506//2507vbool8_t test_vreinterpret_v_i16m1_b8(vint16m1_t src) {2508 return __riscv_vreinterpret_v_i16m1_b8(src);2509}2510 2511// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b8_i16m12512// CHECK-RV64-SAME: (<vscale x 8 x i1> [[SRC:%.*]]) #[[ATTR0]] {2513// CHECK-RV64-NEXT: entry:2514// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv8i1(<vscale x 64 x i1> poison, <vscale x 8 x i1> [[SRC]], i64 0)2515// CHECK-RV64-NEXT: [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 4 x i16>2516// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]2517//2518vint16m1_t test_vreinterpret_v_b8_i16m1(vbool8_t src) {2519 return __riscv_vreinterpret_v_b8_i16m1(src);2520}2521 2522// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vreinterpret_v_i16m1_b42523// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {2524// CHECK-RV64-NEXT: entry:2525// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 64 x i1>2526// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i1> @llvm.vector.extract.nxv16i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)2527// CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP1]]2528//2529vbool4_t test_vreinterpret_v_i16m1_b4(vint16m1_t src) {2530 return __riscv_vreinterpret_v_i16m1_b4(src);2531}2532 2533// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b4_i16m12534// CHECK-RV64-SAME: (<vscale x 16 x i1> [[SRC:%.*]]) #[[ATTR0]] {2535// CHECK-RV64-NEXT: entry:2536// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv16i1(<vscale x 64 x i1> poison, <vscale x 16 x i1> [[SRC]], i64 0)2537// CHECK-RV64-NEXT: [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 4 x i16>2538// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]2539//2540vint16m1_t test_vreinterpret_v_b4_i16m1(vbool4_t src) {2541 return __riscv_vreinterpret_v_b4_i16m1(src);2542}2543 2544// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vreinterpret_v_i16m1_b22545// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {2546// CHECK-RV64-NEXT: entry:2547// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 64 x i1>2548// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i1> @llvm.vector.extract.nxv32i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)2549// CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP1]]2550//2551vbool2_t test_vreinterpret_v_i16m1_b2(vint16m1_t src) {2552 return __riscv_vreinterpret_v_i16m1_b2(src);2553}2554 2555// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b2_i16m12556// CHECK-RV64-SAME: (<vscale x 32 x i1> [[SRC:%.*]]) #[[ATTR0]] {2557// CHECK-RV64-NEXT: entry:2558// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv32i1(<vscale x 64 x i1> poison, <vscale x 32 x i1> [[SRC]], i64 0)2559// CHECK-RV64-NEXT: [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 4 x i16>2560// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]2561//2562vint16m1_t test_vreinterpret_v_b2_i16m1(vbool2_t src) {2563 return __riscv_vreinterpret_v_b2_i16m1(src);2564}2565 2566// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vreinterpret_v_u16m1_b642567// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {2568// CHECK-RV64-NEXT: entry:2569// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 64 x i1>2570// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)2571// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP1]]2572//2573vbool64_t test_vreinterpret_v_u16m1_b64(vuint16m1_t src) {2574 return __riscv_vreinterpret_v_u16m1_b64(src);2575}2576 2577// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b64_u16m12578// CHECK-RV64-SAME: (<vscale x 1 x i1> [[SRC:%.*]]) #[[ATTR0]] {2579// CHECK-RV64-NEXT: entry:2580// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv1i1(<vscale x 64 x i1> poison, <vscale x 1 x i1> [[SRC]], i64 0)2581// CHECK-RV64-NEXT: [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 4 x i16>2582// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]2583//2584vuint16m1_t test_vreinterpret_v_b64_u16m1(vbool64_t src) {2585 return __riscv_vreinterpret_v_b64_u16m1(src);2586}2587 2588// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vreinterpret_v_u16m1_b322589// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {2590// CHECK-RV64-NEXT: entry:2591// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 64 x i1>2592// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)2593// CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP1]]2594//2595vbool32_t test_vreinterpret_v_u16m1_b32(vuint16m1_t src) {2596 return __riscv_vreinterpret_v_u16m1_b32(src);2597}2598 2599// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b32_u16m12600// CHECK-RV64-SAME: (<vscale x 2 x i1> [[SRC:%.*]]) #[[ATTR0]] {2601// CHECK-RV64-NEXT: entry:2602// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv2i1(<vscale x 64 x i1> poison, <vscale x 2 x i1> [[SRC]], i64 0)2603// CHECK-RV64-NEXT: [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 4 x i16>2604// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]2605//2606vuint16m1_t test_vreinterpret_v_b32_u16m1(vbool32_t src) {2607 return __riscv_vreinterpret_v_b32_u16m1(src);2608}2609 2610// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vreinterpret_v_u16m1_b162611// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {2612// CHECK-RV64-NEXT: entry:2613// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 64 x i1>2614// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)2615// CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP1]]2616//2617vbool16_t test_vreinterpret_v_u16m1_b16(vuint16m1_t src) {2618 return __riscv_vreinterpret_v_u16m1_b16(src);2619}2620 2621// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b16_u16m12622// CHECK-RV64-SAME: (<vscale x 4 x i1> [[SRC:%.*]]) #[[ATTR0]] {2623// CHECK-RV64-NEXT: entry:2624// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv4i1(<vscale x 64 x i1> poison, <vscale x 4 x i1> [[SRC]], i64 0)2625// CHECK-RV64-NEXT: [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 4 x i16>2626// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]2627//2628vuint16m1_t test_vreinterpret_v_b16_u16m1(vbool16_t src) {2629 return __riscv_vreinterpret_v_b16_u16m1(src);2630}2631 2632// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vreinterpret_v_u16m1_b82633// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {2634// CHECK-RV64-NEXT: entry:2635// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 64 x i1>2636// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)2637// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP1]]2638//2639vbool8_t test_vreinterpret_v_u16m1_b8(vuint16m1_t src) {2640 return __riscv_vreinterpret_v_u16m1_b8(src);2641}2642 2643// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b8_u16m12644// CHECK-RV64-SAME: (<vscale x 8 x i1> [[SRC:%.*]]) #[[ATTR0]] {2645// CHECK-RV64-NEXT: entry:2646// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv8i1(<vscale x 64 x i1> poison, <vscale x 8 x i1> [[SRC]], i64 0)2647// CHECK-RV64-NEXT: [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 4 x i16>2648// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]2649//2650vuint16m1_t test_vreinterpret_v_b8_u16m1(vbool8_t src) {2651 return __riscv_vreinterpret_v_b8_u16m1(src);2652}2653 2654// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vreinterpret_v_u16m1_b42655// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {2656// CHECK-RV64-NEXT: entry:2657// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 64 x i1>2658// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i1> @llvm.vector.extract.nxv16i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)2659// CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP1]]2660//2661vbool4_t test_vreinterpret_v_u16m1_b4(vuint16m1_t src) {2662 return __riscv_vreinterpret_v_u16m1_b4(src);2663}2664 2665// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b4_u16m12666// CHECK-RV64-SAME: (<vscale x 16 x i1> [[SRC:%.*]]) #[[ATTR0]] {2667// CHECK-RV64-NEXT: entry:2668// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv16i1(<vscale x 64 x i1> poison, <vscale x 16 x i1> [[SRC]], i64 0)2669// CHECK-RV64-NEXT: [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 4 x i16>2670// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]2671//2672vuint16m1_t test_vreinterpret_v_b4_u16m1(vbool4_t src) {2673 return __riscv_vreinterpret_v_b4_u16m1(src);2674}2675 2676// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vreinterpret_v_u16m1_b22677// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {2678// CHECK-RV64-NEXT: entry:2679// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 64 x i1>2680// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i1> @llvm.vector.extract.nxv32i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)2681// CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP1]]2682//2683vbool2_t test_vreinterpret_v_u16m1_b2(vuint16m1_t src) {2684 return __riscv_vreinterpret_v_u16m1_b2(src);2685}2686 2687// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b2_u16m12688// CHECK-RV64-SAME: (<vscale x 32 x i1> [[SRC:%.*]]) #[[ATTR0]] {2689// CHECK-RV64-NEXT: entry:2690// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv32i1(<vscale x 64 x i1> poison, <vscale x 32 x i1> [[SRC]], i64 0)2691// CHECK-RV64-NEXT: [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 4 x i16>2692// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]2693//2694vuint16m1_t test_vreinterpret_v_b2_u16m1(vbool2_t src) {2695 return __riscv_vreinterpret_v_b2_u16m1(src);2696}2697 2698// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vreinterpret_v_i32m1_b642699// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {2700// CHECK-RV64-NEXT: entry:2701// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 64 x i1>2702// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)2703// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP1]]2704//2705vbool64_t test_vreinterpret_v_i32m1_b64(vint32m1_t src) {2706 return __riscv_vreinterpret_v_i32m1_b64(src);2707}2708 2709// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_b64_i32m12710// CHECK-RV64-SAME: (<vscale x 1 x i1> [[SRC:%.*]]) #[[ATTR0]] {2711// CHECK-RV64-NEXT: entry:2712// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv1i1(<vscale x 64 x i1> poison, <vscale x 1 x i1> [[SRC]], i64 0)2713// CHECK-RV64-NEXT: [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 2 x i32>2714// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]2715//2716vint32m1_t test_vreinterpret_v_b64_i32m1(vbool64_t src) {2717 return __riscv_vreinterpret_v_b64_i32m1(src);2718}2719 2720// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vreinterpret_v_i32m1_b322721// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {2722// CHECK-RV64-NEXT: entry:2723// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 64 x i1>2724// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)2725// CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP1]]2726//2727vbool32_t test_vreinterpret_v_i32m1_b32(vint32m1_t src) {2728 return __riscv_vreinterpret_v_i32m1_b32(src);2729}2730 2731// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_b32_i32m12732// CHECK-RV64-SAME: (<vscale x 2 x i1> [[SRC:%.*]]) #[[ATTR0]] {2733// CHECK-RV64-NEXT: entry:2734// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv2i1(<vscale x 64 x i1> poison, <vscale x 2 x i1> [[SRC]], i64 0)2735// CHECK-RV64-NEXT: [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 2 x i32>2736// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]2737//2738vint32m1_t test_vreinterpret_v_b32_i32m1(vbool32_t src) {2739 return __riscv_vreinterpret_v_b32_i32m1(src);2740}2741 2742// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vreinterpret_v_i32m1_b162743// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {2744// CHECK-RV64-NEXT: entry:2745// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 64 x i1>2746// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)2747// CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP1]]2748//2749vbool16_t test_vreinterpret_v_i32m1_b16(vint32m1_t src) {2750 return __riscv_vreinterpret_v_i32m1_b16(src);2751}2752 2753// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_b16_i32m12754// CHECK-RV64-SAME: (<vscale x 4 x i1> [[SRC:%.*]]) #[[ATTR0]] {2755// CHECK-RV64-NEXT: entry:2756// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv4i1(<vscale x 64 x i1> poison, <vscale x 4 x i1> [[SRC]], i64 0)2757// CHECK-RV64-NEXT: [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 2 x i32>2758// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]2759//2760vint32m1_t test_vreinterpret_v_b16_i32m1(vbool16_t src) {2761 return __riscv_vreinterpret_v_b16_i32m1(src);2762}2763 2764// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vreinterpret_v_i32m1_b82765// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {2766// CHECK-RV64-NEXT: entry:2767// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 64 x i1>2768// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)2769// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP1]]2770//2771vbool8_t test_vreinterpret_v_i32m1_b8(vint32m1_t src) {2772 return __riscv_vreinterpret_v_i32m1_b8(src);2773}2774 2775// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_b8_i32m12776// CHECK-RV64-SAME: (<vscale x 8 x i1> [[SRC:%.*]]) #[[ATTR0]] {2777// CHECK-RV64-NEXT: entry:2778// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv8i1(<vscale x 64 x i1> poison, <vscale x 8 x i1> [[SRC]], i64 0)2779// CHECK-RV64-NEXT: [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 2 x i32>2780// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]2781//2782vint32m1_t test_vreinterpret_v_b8_i32m1(vbool8_t src) {2783 return __riscv_vreinterpret_v_b8_i32m1(src);2784}2785 2786// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vreinterpret_v_i32m1_b42787// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {2788// CHECK-RV64-NEXT: entry:2789// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 64 x i1>2790// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i1> @llvm.vector.extract.nxv16i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)2791// CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP1]]2792//2793vbool4_t test_vreinterpret_v_i32m1_b4(vint32m1_t src) {2794 return __riscv_vreinterpret_v_i32m1_b4(src);2795}2796 2797// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_b4_i32m12798// CHECK-RV64-SAME: (<vscale x 16 x i1> [[SRC:%.*]]) #[[ATTR0]] {2799// CHECK-RV64-NEXT: entry:2800// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv16i1(<vscale x 64 x i1> poison, <vscale x 16 x i1> [[SRC]], i64 0)2801// CHECK-RV64-NEXT: [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 2 x i32>2802// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]2803//2804vint32m1_t test_vreinterpret_v_b4_i32m1(vbool4_t src) {2805 return __riscv_vreinterpret_v_b4_i32m1(src);2806}2807 2808// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vreinterpret_v_u32m1_b642809// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {2810// CHECK-RV64-NEXT: entry:2811// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 64 x i1>2812// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)2813// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP1]]2814//2815vbool64_t test_vreinterpret_v_u32m1_b64(vuint32m1_t src) {2816 return __riscv_vreinterpret_v_u32m1_b64(src);2817}2818 2819// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_b64_u32m12820// CHECK-RV64-SAME: (<vscale x 1 x i1> [[SRC:%.*]]) #[[ATTR0]] {2821// CHECK-RV64-NEXT: entry:2822// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv1i1(<vscale x 64 x i1> poison, <vscale x 1 x i1> [[SRC]], i64 0)2823// CHECK-RV64-NEXT: [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 2 x i32>2824// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]2825//2826vuint32m1_t test_vreinterpret_v_b64_u32m1(vbool64_t src) {2827 return __riscv_vreinterpret_v_b64_u32m1(src);2828}2829 2830// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vreinterpret_v_u32m1_b322831// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {2832// CHECK-RV64-NEXT: entry:2833// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 64 x i1>2834// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)2835// CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP1]]2836//2837vbool32_t test_vreinterpret_v_u32m1_b32(vuint32m1_t src) {2838 return __riscv_vreinterpret_v_u32m1_b32(src);2839}2840 2841// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_b32_u32m12842// CHECK-RV64-SAME: (<vscale x 2 x i1> [[SRC:%.*]]) #[[ATTR0]] {2843// CHECK-RV64-NEXT: entry:2844// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv2i1(<vscale x 64 x i1> poison, <vscale x 2 x i1> [[SRC]], i64 0)2845// CHECK-RV64-NEXT: [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 2 x i32>2846// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]2847//2848vuint32m1_t test_vreinterpret_v_b32_u32m1(vbool32_t src) {2849 return __riscv_vreinterpret_v_b32_u32m1(src);2850}2851 2852// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vreinterpret_v_u32m1_b162853// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {2854// CHECK-RV64-NEXT: entry:2855// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 64 x i1>2856// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)2857// CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP1]]2858//2859vbool16_t test_vreinterpret_v_u32m1_b16(vuint32m1_t src) {2860 return __riscv_vreinterpret_v_u32m1_b16(src);2861}2862 2863// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_b16_u32m12864// CHECK-RV64-SAME: (<vscale x 4 x i1> [[SRC:%.*]]) #[[ATTR0]] {2865// CHECK-RV64-NEXT: entry:2866// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv4i1(<vscale x 64 x i1> poison, <vscale x 4 x i1> [[SRC]], i64 0)2867// CHECK-RV64-NEXT: [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 2 x i32>2868// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]2869//2870vuint32m1_t test_vreinterpret_v_b16_u32m1(vbool16_t src) {2871 return __riscv_vreinterpret_v_b16_u32m1(src);2872}2873 2874// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vreinterpret_v_u32m1_b82875// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {2876// CHECK-RV64-NEXT: entry:2877// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 64 x i1>2878// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)2879// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP1]]2880//2881vbool8_t test_vreinterpret_v_u32m1_b8(vuint32m1_t src) {2882 return __riscv_vreinterpret_v_u32m1_b8(src);2883}2884 2885// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_b8_u32m12886// CHECK-RV64-SAME: (<vscale x 8 x i1> [[SRC:%.*]]) #[[ATTR0]] {2887// CHECK-RV64-NEXT: entry:2888// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv8i1(<vscale x 64 x i1> poison, <vscale x 8 x i1> [[SRC]], i64 0)2889// CHECK-RV64-NEXT: [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 2 x i32>2890// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]2891//2892vuint32m1_t test_vreinterpret_v_b8_u32m1(vbool8_t src) {2893 return __riscv_vreinterpret_v_b8_u32m1(src);2894}2895 2896// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vreinterpret_v_u32m1_b42897// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {2898// CHECK-RV64-NEXT: entry:2899// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 64 x i1>2900// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i1> @llvm.vector.extract.nxv16i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)2901// CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP1]]2902//2903vbool4_t test_vreinterpret_v_u32m1_b4(vuint32m1_t src) {2904 return __riscv_vreinterpret_v_u32m1_b4(src);2905}2906 2907// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_b4_u32m12908// CHECK-RV64-SAME: (<vscale x 16 x i1> [[SRC:%.*]]) #[[ATTR0]] {2909// CHECK-RV64-NEXT: entry:2910// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv16i1(<vscale x 64 x i1> poison, <vscale x 16 x i1> [[SRC]], i64 0)2911// CHECK-RV64-NEXT: [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 2 x i32>2912// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]2913//2914vuint32m1_t test_vreinterpret_v_b4_u32m1(vbool4_t src) {2915 return __riscv_vreinterpret_v_b4_u32m1(src);2916}2917 2918// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vreinterpret_v_i64m1_b642919// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {2920// CHECK-RV64-NEXT: entry:2921// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 64 x i1>2922// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)2923// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP1]]2924//2925vbool64_t test_vreinterpret_v_i64m1_b64(vint64m1_t src) {2926 return __riscv_vreinterpret_v_i64m1_b64(src);2927}2928 2929// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_b64_i64m12930// CHECK-RV64-SAME: (<vscale x 1 x i1> [[SRC:%.*]]) #[[ATTR0]] {2931// CHECK-RV64-NEXT: entry:2932// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv1i1(<vscale x 64 x i1> poison, <vscale x 1 x i1> [[SRC]], i64 0)2933// CHECK-RV64-NEXT: [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 1 x i64>2934// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]2935//2936vint64m1_t test_vreinterpret_v_b64_i64m1(vbool64_t src) {2937 return __riscv_vreinterpret_v_b64_i64m1(src);2938}2939 2940// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vreinterpret_v_i64m1_b322941// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {2942// CHECK-RV64-NEXT: entry:2943// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 64 x i1>2944// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)2945// CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP1]]2946//2947vbool32_t test_vreinterpret_v_i64m1_b32(vint64m1_t src) {2948 return __riscv_vreinterpret_v_i64m1_b32(src);2949}2950 2951// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_b32_i64m12952// CHECK-RV64-SAME: (<vscale x 2 x i1> [[SRC:%.*]]) #[[ATTR0]] {2953// CHECK-RV64-NEXT: entry:2954// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv2i1(<vscale x 64 x i1> poison, <vscale x 2 x i1> [[SRC]], i64 0)2955// CHECK-RV64-NEXT: [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 1 x i64>2956// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]2957//2958vint64m1_t test_vreinterpret_v_b32_i64m1(vbool32_t src) {2959 return __riscv_vreinterpret_v_b32_i64m1(src);2960}2961 2962// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vreinterpret_v_i64m1_b162963// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {2964// CHECK-RV64-NEXT: entry:2965// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 64 x i1>2966// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)2967// CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP1]]2968//2969vbool16_t test_vreinterpret_v_i64m1_b16(vint64m1_t src) {2970 return __riscv_vreinterpret_v_i64m1_b16(src);2971}2972 2973// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_b16_i64m12974// CHECK-RV64-SAME: (<vscale x 4 x i1> [[SRC:%.*]]) #[[ATTR0]] {2975// CHECK-RV64-NEXT: entry:2976// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv4i1(<vscale x 64 x i1> poison, <vscale x 4 x i1> [[SRC]], i64 0)2977// CHECK-RV64-NEXT: [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 1 x i64>2978// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]2979//2980vint64m1_t test_vreinterpret_v_b16_i64m1(vbool16_t src) {2981 return __riscv_vreinterpret_v_b16_i64m1(src);2982}2983 2984// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vreinterpret_v_i64m1_b82985// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {2986// CHECK-RV64-NEXT: entry:2987// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 64 x i1>2988// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)2989// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP1]]2990//2991vbool8_t test_vreinterpret_v_i64m1_b8(vint64m1_t src) {2992 return __riscv_vreinterpret_v_i64m1_b8(src);2993}2994 2995// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_b8_i64m12996// CHECK-RV64-SAME: (<vscale x 8 x i1> [[SRC:%.*]]) #[[ATTR0]] {2997// CHECK-RV64-NEXT: entry:2998// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv8i1(<vscale x 64 x i1> poison, <vscale x 8 x i1> [[SRC]], i64 0)2999// CHECK-RV64-NEXT: [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 1 x i64>3000// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]3001//3002vint64m1_t test_vreinterpret_v_b8_i64m1(vbool8_t src) {3003 return __riscv_vreinterpret_v_b8_i64m1(src);3004}3005 3006// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vreinterpret_v_u64m1_b643007// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {3008// CHECK-RV64-NEXT: entry:3009// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 64 x i1>3010// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)3011// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP1]]3012//3013vbool64_t test_vreinterpret_v_u64m1_b64(vuint64m1_t src) {3014 return __riscv_vreinterpret_v_u64m1_b64(src);3015}3016 3017// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_b64_u64m13018// CHECK-RV64-SAME: (<vscale x 1 x i1> [[SRC:%.*]]) #[[ATTR0]] {3019// CHECK-RV64-NEXT: entry:3020// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv1i1(<vscale x 64 x i1> poison, <vscale x 1 x i1> [[SRC]], i64 0)3021// CHECK-RV64-NEXT: [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 1 x i64>3022// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]3023//3024vuint64m1_t test_vreinterpret_v_b64_u64m1(vbool64_t src) {3025 return __riscv_vreinterpret_v_b64_u64m1(src);3026}3027 3028// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vreinterpret_v_u64m1_b323029// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {3030// CHECK-RV64-NEXT: entry:3031// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 64 x i1>3032// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)3033// CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP1]]3034//3035vbool32_t test_vreinterpret_v_u64m1_b32(vuint64m1_t src) {3036 return __riscv_vreinterpret_v_u64m1_b32(src);3037}3038 3039// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_b32_u64m13040// CHECK-RV64-SAME: (<vscale x 2 x i1> [[SRC:%.*]]) #[[ATTR0]] {3041// CHECK-RV64-NEXT: entry:3042// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv2i1(<vscale x 64 x i1> poison, <vscale x 2 x i1> [[SRC]], i64 0)3043// CHECK-RV64-NEXT: [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 1 x i64>3044// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]3045//3046vuint64m1_t test_vreinterpret_v_b32_u64m1(vbool32_t src) {3047 return __riscv_vreinterpret_v_b32_u64m1(src);3048}3049 3050// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vreinterpret_v_u64m1_b163051// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {3052// CHECK-RV64-NEXT: entry:3053// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 64 x i1>3054// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)3055// CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP1]]3056//3057vbool16_t test_vreinterpret_v_u64m1_b16(vuint64m1_t src) {3058 return __riscv_vreinterpret_v_u64m1_b16(src);3059}3060 3061// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_b16_u64m13062// CHECK-RV64-SAME: (<vscale x 4 x i1> [[SRC:%.*]]) #[[ATTR0]] {3063// CHECK-RV64-NEXT: entry:3064// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv4i1(<vscale x 64 x i1> poison, <vscale x 4 x i1> [[SRC]], i64 0)3065// CHECK-RV64-NEXT: [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 1 x i64>3066// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]3067//3068vuint64m1_t test_vreinterpret_v_b16_u64m1(vbool16_t src) {3069 return __riscv_vreinterpret_v_b16_u64m1(src);3070}3071 3072// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vreinterpret_v_u64m1_b83073// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {3074// CHECK-RV64-NEXT: entry:3075// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 64 x i1>3076// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)3077// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP1]]3078//3079vbool8_t test_vreinterpret_v_u64m1_b8(vuint64m1_t src) {3080 return __riscv_vreinterpret_v_u64m1_b8(src);3081}3082 3083// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_b8_u64m13084// CHECK-RV64-SAME: (<vscale x 8 x i1> [[SRC:%.*]]) #[[ATTR0]] {3085// CHECK-RV64-NEXT: entry:3086// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv8i1(<vscale x 64 x i1> poison, <vscale x 8 x i1> [[SRC]], i64 0)3087// CHECK-RV64-NEXT: [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 1 x i64>3088// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]3089//3090vuint64m1_t test_vreinterpret_v_b8_u64m1(vbool8_t src) {3091 return __riscv_vreinterpret_v_b8_u64m1(src);3092}3093 3094