310 lines · c
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 22// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \4// RUN: -target-feature +zvfh -disable-O0-optnone \5// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \6// RUN: FileCheck --check-prefix=CHECK-RV64 %s7 8#include <riscv_vector.h>9 10// CHECK-RV64-LABEL: define dso_local void @test_vse32_v_f32mf211// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], <vscale x 1 x float> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {12// CHECK-RV64-NEXT: entry:13// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv1f32.p0.i64(<vscale x 1 x float> [[VALUE]], ptr [[BASE]], i64 [[VL]])14// CHECK-RV64-NEXT: ret void15//16void test_vse32_v_f32mf2(float *base, vfloat32mf2_t value, size_t vl) {17 return __riscv_vse32_v_f32mf2(base, value, vl);18}19 20// CHECK-RV64-LABEL: define dso_local void @test_vse32_v_f32m121// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], <vscale x 2 x float> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {22// CHECK-RV64-NEXT: entry:23// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv2f32.p0.i64(<vscale x 2 x float> [[VALUE]], ptr [[BASE]], i64 [[VL]])24// CHECK-RV64-NEXT: ret void25//26void test_vse32_v_f32m1(float *base, vfloat32m1_t value, size_t vl) {27 return __riscv_vse32_v_f32m1(base, value, vl);28}29 30// CHECK-RV64-LABEL: define dso_local void @test_vse32_v_f32m231// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], <vscale x 4 x float> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {32// CHECK-RV64-NEXT: entry:33// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv4f32.p0.i64(<vscale x 4 x float> [[VALUE]], ptr [[BASE]], i64 [[VL]])34// CHECK-RV64-NEXT: ret void35//36void test_vse32_v_f32m2(float *base, vfloat32m2_t value, size_t vl) {37 return __riscv_vse32_v_f32m2(base, value, vl);38}39 40// CHECK-RV64-LABEL: define dso_local void @test_vse32_v_f32m441// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], <vscale x 8 x float> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {42// CHECK-RV64-NEXT: entry:43// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv8f32.p0.i64(<vscale x 8 x float> [[VALUE]], ptr [[BASE]], i64 [[VL]])44// CHECK-RV64-NEXT: ret void45//46void test_vse32_v_f32m4(float *base, vfloat32m4_t value, size_t vl) {47 return __riscv_vse32_v_f32m4(base, value, vl);48}49 50// CHECK-RV64-LABEL: define dso_local void @test_vse32_v_f32m851// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], <vscale x 16 x float> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {52// CHECK-RV64-NEXT: entry:53// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv16f32.p0.i64(<vscale x 16 x float> [[VALUE]], ptr [[BASE]], i64 [[VL]])54// CHECK-RV64-NEXT: ret void55//56void test_vse32_v_f32m8(float *base, vfloat32m8_t value, size_t vl) {57 return __riscv_vse32_v_f32m8(base, value, vl);58}59 60// CHECK-RV64-LABEL: define dso_local void @test_vse32_v_i32mf261// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], <vscale x 1 x i32> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {62// CHECK-RV64-NEXT: entry:63// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv1i32.p0.i64(<vscale x 1 x i32> [[VALUE]], ptr [[BASE]], i64 [[VL]])64// CHECK-RV64-NEXT: ret void65//66void test_vse32_v_i32mf2(int32_t *base, vint32mf2_t value, size_t vl) {67 return __riscv_vse32_v_i32mf2(base, value, vl);68}69 70// CHECK-RV64-LABEL: define dso_local void @test_vse32_v_i32m171// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], <vscale x 2 x i32> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {72// CHECK-RV64-NEXT: entry:73// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv2i32.p0.i64(<vscale x 2 x i32> [[VALUE]], ptr [[BASE]], i64 [[VL]])74// CHECK-RV64-NEXT: ret void75//76void test_vse32_v_i32m1(int32_t *base, vint32m1_t value, size_t vl) {77 return __riscv_vse32_v_i32m1(base, value, vl);78}79 80// CHECK-RV64-LABEL: define dso_local void @test_vse32_v_i32m281// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], <vscale x 4 x i32> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {82// CHECK-RV64-NEXT: entry:83// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv4i32.p0.i64(<vscale x 4 x i32> [[VALUE]], ptr [[BASE]], i64 [[VL]])84// CHECK-RV64-NEXT: ret void85//86void test_vse32_v_i32m2(int32_t *base, vint32m2_t value, size_t vl) {87 return __riscv_vse32_v_i32m2(base, value, vl);88}89 90// CHECK-RV64-LABEL: define dso_local void @test_vse32_v_i32m491// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], <vscale x 8 x i32> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {92// CHECK-RV64-NEXT: entry:93// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv8i32.p0.i64(<vscale x 8 x i32> [[VALUE]], ptr [[BASE]], i64 [[VL]])94// CHECK-RV64-NEXT: ret void95//96void test_vse32_v_i32m4(int32_t *base, vint32m4_t value, size_t vl) {97 return __riscv_vse32_v_i32m4(base, value, vl);98}99 100// CHECK-RV64-LABEL: define dso_local void @test_vse32_v_i32m8101// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], <vscale x 16 x i32> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {102// CHECK-RV64-NEXT: entry:103// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv16i32.p0.i64(<vscale x 16 x i32> [[VALUE]], ptr [[BASE]], i64 [[VL]])104// CHECK-RV64-NEXT: ret void105//106void test_vse32_v_i32m8(int32_t *base, vint32m8_t value, size_t vl) {107 return __riscv_vse32_v_i32m8(base, value, vl);108}109 110// CHECK-RV64-LABEL: define dso_local void @test_vse32_v_u32mf2111// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], <vscale x 1 x i32> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {112// CHECK-RV64-NEXT: entry:113// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv1i32.p0.i64(<vscale x 1 x i32> [[VALUE]], ptr [[BASE]], i64 [[VL]])114// CHECK-RV64-NEXT: ret void115//116void test_vse32_v_u32mf2(uint32_t *base, vuint32mf2_t value, size_t vl) {117 return __riscv_vse32_v_u32mf2(base, value, vl);118}119 120// CHECK-RV64-LABEL: define dso_local void @test_vse32_v_u32m1121// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], <vscale x 2 x i32> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {122// CHECK-RV64-NEXT: entry:123// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv2i32.p0.i64(<vscale x 2 x i32> [[VALUE]], ptr [[BASE]], i64 [[VL]])124// CHECK-RV64-NEXT: ret void125//126void test_vse32_v_u32m1(uint32_t *base, vuint32m1_t value, size_t vl) {127 return __riscv_vse32_v_u32m1(base, value, vl);128}129 130// CHECK-RV64-LABEL: define dso_local void @test_vse32_v_u32m2131// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], <vscale x 4 x i32> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {132// CHECK-RV64-NEXT: entry:133// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv4i32.p0.i64(<vscale x 4 x i32> [[VALUE]], ptr [[BASE]], i64 [[VL]])134// CHECK-RV64-NEXT: ret void135//136void test_vse32_v_u32m2(uint32_t *base, vuint32m2_t value, size_t vl) {137 return __riscv_vse32_v_u32m2(base, value, vl);138}139 140// CHECK-RV64-LABEL: define dso_local void @test_vse32_v_u32m4141// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], <vscale x 8 x i32> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {142// CHECK-RV64-NEXT: entry:143// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv8i32.p0.i64(<vscale x 8 x i32> [[VALUE]], ptr [[BASE]], i64 [[VL]])144// CHECK-RV64-NEXT: ret void145//146void test_vse32_v_u32m4(uint32_t *base, vuint32m4_t value, size_t vl) {147 return __riscv_vse32_v_u32m4(base, value, vl);148}149 150// CHECK-RV64-LABEL: define dso_local void @test_vse32_v_u32m8151// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], <vscale x 16 x i32> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {152// CHECK-RV64-NEXT: entry:153// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv16i32.p0.i64(<vscale x 16 x i32> [[VALUE]], ptr [[BASE]], i64 [[VL]])154// CHECK-RV64-NEXT: ret void155//156void test_vse32_v_u32m8(uint32_t *base, vuint32m8_t value, size_t vl) {157 return __riscv_vse32_v_u32m8(base, value, vl);158}159 160// CHECK-RV64-LABEL: define dso_local void @test_vse32_v_f32mf2_m161// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], <vscale x 1 x float> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {162// CHECK-RV64-NEXT: entry:163// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv1f32.p0.i64(<vscale x 1 x float> [[VALUE]], ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])164// CHECK-RV64-NEXT: ret void165//166void test_vse32_v_f32mf2_m(vbool64_t mask, float *base, vfloat32mf2_t value, size_t vl) {167 return __riscv_vse32_v_f32mf2_m(mask, base, value, vl);168}169 170// CHECK-RV64-LABEL: define dso_local void @test_vse32_v_f32m1_m171// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], <vscale x 2 x float> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {172// CHECK-RV64-NEXT: entry:173// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv2f32.p0.i64(<vscale x 2 x float> [[VALUE]], ptr [[BASE]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])174// CHECK-RV64-NEXT: ret void175//176void test_vse32_v_f32m1_m(vbool32_t mask, float *base, vfloat32m1_t value, size_t vl) {177 return __riscv_vse32_v_f32m1_m(mask, base, value, vl);178}179 180// CHECK-RV64-LABEL: define dso_local void @test_vse32_v_f32m2_m181// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], <vscale x 4 x float> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {182// CHECK-RV64-NEXT: entry:183// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv4f32.p0.i64(<vscale x 4 x float> [[VALUE]], ptr [[BASE]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])184// CHECK-RV64-NEXT: ret void185//186void test_vse32_v_f32m2_m(vbool16_t mask, float *base, vfloat32m2_t value, size_t vl) {187 return __riscv_vse32_v_f32m2_m(mask, base, value, vl);188}189 190// CHECK-RV64-LABEL: define dso_local void @test_vse32_v_f32m4_m191// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], <vscale x 8 x float> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {192// CHECK-RV64-NEXT: entry:193// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv8f32.p0.i64(<vscale x 8 x float> [[VALUE]], ptr [[BASE]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])194// CHECK-RV64-NEXT: ret void195//196void test_vse32_v_f32m4_m(vbool8_t mask, float *base, vfloat32m4_t value, size_t vl) {197 return __riscv_vse32_v_f32m4_m(mask, base, value, vl);198}199 200// CHECK-RV64-LABEL: define dso_local void @test_vse32_v_f32m8_m201// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], <vscale x 16 x float> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {202// CHECK-RV64-NEXT: entry:203// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv16f32.p0.i64(<vscale x 16 x float> [[VALUE]], ptr [[BASE]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])204// CHECK-RV64-NEXT: ret void205//206void test_vse32_v_f32m8_m(vbool4_t mask, float *base, vfloat32m8_t value, size_t vl) {207 return __riscv_vse32_v_f32m8_m(mask, base, value, vl);208}209 210// CHECK-RV64-LABEL: define dso_local void @test_vse32_v_i32mf2_m211// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], <vscale x 1 x i32> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {212// CHECK-RV64-NEXT: entry:213// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv1i32.p0.i64(<vscale x 1 x i32> [[VALUE]], ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])214// CHECK-RV64-NEXT: ret void215//216void test_vse32_v_i32mf2_m(vbool64_t mask, int32_t *base, vint32mf2_t value, size_t vl) {217 return __riscv_vse32_v_i32mf2_m(mask, base, value, vl);218}219 220// CHECK-RV64-LABEL: define dso_local void @test_vse32_v_i32m1_m221// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], <vscale x 2 x i32> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {222// CHECK-RV64-NEXT: entry:223// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv2i32.p0.i64(<vscale x 2 x i32> [[VALUE]], ptr [[BASE]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])224// CHECK-RV64-NEXT: ret void225//226void test_vse32_v_i32m1_m(vbool32_t mask, int32_t *base, vint32m1_t value, size_t vl) {227 return __riscv_vse32_v_i32m1_m(mask, base, value, vl);228}229 230// CHECK-RV64-LABEL: define dso_local void @test_vse32_v_i32m2_m231// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], <vscale x 4 x i32> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {232// CHECK-RV64-NEXT: entry:233// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv4i32.p0.i64(<vscale x 4 x i32> [[VALUE]], ptr [[BASE]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])234// CHECK-RV64-NEXT: ret void235//236void test_vse32_v_i32m2_m(vbool16_t mask, int32_t *base, vint32m2_t value, size_t vl) {237 return __riscv_vse32_v_i32m2_m(mask, base, value, vl);238}239 240// CHECK-RV64-LABEL: define dso_local void @test_vse32_v_i32m4_m241// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], <vscale x 8 x i32> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {242// CHECK-RV64-NEXT: entry:243// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv8i32.p0.i64(<vscale x 8 x i32> [[VALUE]], ptr [[BASE]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])244// CHECK-RV64-NEXT: ret void245//246void test_vse32_v_i32m4_m(vbool8_t mask, int32_t *base, vint32m4_t value, size_t vl) {247 return __riscv_vse32_v_i32m4_m(mask, base, value, vl);248}249 250// CHECK-RV64-LABEL: define dso_local void @test_vse32_v_i32m8_m251// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], <vscale x 16 x i32> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {252// CHECK-RV64-NEXT: entry:253// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv16i32.p0.i64(<vscale x 16 x i32> [[VALUE]], ptr [[BASE]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])254// CHECK-RV64-NEXT: ret void255//256void test_vse32_v_i32m8_m(vbool4_t mask, int32_t *base, vint32m8_t value, size_t vl) {257 return __riscv_vse32_v_i32m8_m(mask, base, value, vl);258}259 260// CHECK-RV64-LABEL: define dso_local void @test_vse32_v_u32mf2_m261// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], <vscale x 1 x i32> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {262// CHECK-RV64-NEXT: entry:263// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv1i32.p0.i64(<vscale x 1 x i32> [[VALUE]], ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])264// CHECK-RV64-NEXT: ret void265//266void test_vse32_v_u32mf2_m(vbool64_t mask, uint32_t *base, vuint32mf2_t value, size_t vl) {267 return __riscv_vse32_v_u32mf2_m(mask, base, value, vl);268}269 270// CHECK-RV64-LABEL: define dso_local void @test_vse32_v_u32m1_m271// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], <vscale x 2 x i32> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {272// CHECK-RV64-NEXT: entry:273// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv2i32.p0.i64(<vscale x 2 x i32> [[VALUE]], ptr [[BASE]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])274// CHECK-RV64-NEXT: ret void275//276void test_vse32_v_u32m1_m(vbool32_t mask, uint32_t *base, vuint32m1_t value, size_t vl) {277 return __riscv_vse32_v_u32m1_m(mask, base, value, vl);278}279 280// CHECK-RV64-LABEL: define dso_local void @test_vse32_v_u32m2_m281// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], <vscale x 4 x i32> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {282// CHECK-RV64-NEXT: entry:283// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv4i32.p0.i64(<vscale x 4 x i32> [[VALUE]], ptr [[BASE]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])284// CHECK-RV64-NEXT: ret void285//286void test_vse32_v_u32m2_m(vbool16_t mask, uint32_t *base, vuint32m2_t value, size_t vl) {287 return __riscv_vse32_v_u32m2_m(mask, base, value, vl);288}289 290// CHECK-RV64-LABEL: define dso_local void @test_vse32_v_u32m4_m291// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], <vscale x 8 x i32> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {292// CHECK-RV64-NEXT: entry:293// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv8i32.p0.i64(<vscale x 8 x i32> [[VALUE]], ptr [[BASE]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])294// CHECK-RV64-NEXT: ret void295//296void test_vse32_v_u32m4_m(vbool8_t mask, uint32_t *base, vuint32m4_t value, size_t vl) {297 return __riscv_vse32_v_u32m4_m(mask, base, value, vl);298}299 300// CHECK-RV64-LABEL: define dso_local void @test_vse32_v_u32m8_m301// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], <vscale x 16 x i32> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {302// CHECK-RV64-NEXT: entry:303// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv16i32.p0.i64(<vscale x 16 x i32> [[VALUE]], ptr [[BASE]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])304// CHECK-RV64-NEXT: ret void305//306void test_vse32_v_u32m8_m(vbool4_t mask, uint32_t *base, vuint32m8_t value, size_t vl) {307 return __riscv_vse32_v_u32m8_m(mask, base, value, vl);308}309 310