1769 lines · c
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 22// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone \4// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \5// RUN: FileCheck --check-prefix=CHECK-RV64 %s6 7#include <riscv_vector.h>8 9// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vsll_vv_i8mf810// CHECK-RV64-SAME: (<vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {11// CHECK-RV64-NEXT: entry:12// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> [[OP1]], <vscale x 1 x i8> [[SHIFT]], i64 [[VL]])13// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]14//15vint8mf8_t test_vsll_vv_i8mf8(vint8mf8_t op1, vuint8mf8_t shift, size_t vl) {16 return __riscv_vsll_vv_i8mf8(op1, shift, vl);17}18 19// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vsll_vx_i8mf820// CHECK-RV64-SAME: (<vscale x 1 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {21// CHECK-RV64-NEXT: entry:22// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> [[OP1]], i64 [[SHIFT]], i64 [[VL]])23// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]24//25vint8mf8_t test_vsll_vx_i8mf8(vint8mf8_t op1, size_t shift, size_t vl) {26 return __riscv_vsll_vx_i8mf8(op1, shift, vl);27}28 29// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vsll_vv_i8mf430// CHECK-RV64-SAME: (<vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {31// CHECK-RV64-NEXT: entry:32// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> [[OP1]], <vscale x 2 x i8> [[SHIFT]], i64 [[VL]])33// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]34//35vint8mf4_t test_vsll_vv_i8mf4(vint8mf4_t op1, vuint8mf4_t shift, size_t vl) {36 return __riscv_vsll_vv_i8mf4(op1, shift, vl);37}38 39// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vsll_vx_i8mf440// CHECK-RV64-SAME: (<vscale x 2 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {41// CHECK-RV64-NEXT: entry:42// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> [[OP1]], i64 [[SHIFT]], i64 [[VL]])43// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]44//45vint8mf4_t test_vsll_vx_i8mf4(vint8mf4_t op1, size_t shift, size_t vl) {46 return __riscv_vsll_vx_i8mf4(op1, shift, vl);47}48 49// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vsll_vv_i8mf250// CHECK-RV64-SAME: (<vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {51// CHECK-RV64-NEXT: entry:52// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> [[OP1]], <vscale x 4 x i8> [[SHIFT]], i64 [[VL]])53// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]54//55vint8mf2_t test_vsll_vv_i8mf2(vint8mf2_t op1, vuint8mf2_t shift, size_t vl) {56 return __riscv_vsll_vv_i8mf2(op1, shift, vl);57}58 59// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vsll_vx_i8mf260// CHECK-RV64-SAME: (<vscale x 4 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {61// CHECK-RV64-NEXT: entry:62// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> [[OP1]], i64 [[SHIFT]], i64 [[VL]])63// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]64//65vint8mf2_t test_vsll_vx_i8mf2(vint8mf2_t op1, size_t shift, size_t vl) {66 return __riscv_vsll_vx_i8mf2(op1, shift, vl);67}68 69// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vsll_vv_i8m170// CHECK-RV64-SAME: (<vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {71// CHECK-RV64-NEXT: entry:72// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> [[OP1]], <vscale x 8 x i8> [[SHIFT]], i64 [[VL]])73// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]74//75vint8m1_t test_vsll_vv_i8m1(vint8m1_t op1, vuint8m1_t shift, size_t vl) {76 return __riscv_vsll_vv_i8m1(op1, shift, vl);77}78 79// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vsll_vx_i8m180// CHECK-RV64-SAME: (<vscale x 8 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {81// CHECK-RV64-NEXT: entry:82// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> [[OP1]], i64 [[SHIFT]], i64 [[VL]])83// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]84//85vint8m1_t test_vsll_vx_i8m1(vint8m1_t op1, size_t shift, size_t vl) {86 return __riscv_vsll_vx_i8m1(op1, shift, vl);87}88 89// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vsll_vv_i8m290// CHECK-RV64-SAME: (<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {91// CHECK-RV64-NEXT: entry:92// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> [[OP1]], <vscale x 16 x i8> [[SHIFT]], i64 [[VL]])93// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]94//95vint8m2_t test_vsll_vv_i8m2(vint8m2_t op1, vuint8m2_t shift, size_t vl) {96 return __riscv_vsll_vv_i8m2(op1, shift, vl);97}98 99// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vsll_vx_i8m2100// CHECK-RV64-SAME: (<vscale x 16 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {101// CHECK-RV64-NEXT: entry:102// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> [[OP1]], i64 [[SHIFT]], i64 [[VL]])103// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]104//105vint8m2_t test_vsll_vx_i8m2(vint8m2_t op1, size_t shift, size_t vl) {106 return __riscv_vsll_vx_i8m2(op1, shift, vl);107}108 109// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vsll_vv_i8m4110// CHECK-RV64-SAME: (<vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {111// CHECK-RV64-NEXT: entry:112// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vsll.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> [[OP1]], <vscale x 32 x i8> [[SHIFT]], i64 [[VL]])113// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]114//115vint8m4_t test_vsll_vv_i8m4(vint8m4_t op1, vuint8m4_t shift, size_t vl) {116 return __riscv_vsll_vv_i8m4(op1, shift, vl);117}118 119// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vsll_vx_i8m4120// CHECK-RV64-SAME: (<vscale x 32 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {121// CHECK-RV64-NEXT: entry:122// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vsll.nxv32i8.i64.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> [[OP1]], i64 [[SHIFT]], i64 [[VL]])123// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]124//125vint8m4_t test_vsll_vx_i8m4(vint8m4_t op1, size_t shift, size_t vl) {126 return __riscv_vsll_vx_i8m4(op1, shift, vl);127}128 129// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vsll_vv_i8m8130// CHECK-RV64-SAME: (<vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {131// CHECK-RV64-NEXT: entry:132// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vsll.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> [[OP1]], <vscale x 64 x i8> [[SHIFT]], i64 [[VL]])133// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]134//135vint8m8_t test_vsll_vv_i8m8(vint8m8_t op1, vuint8m8_t shift, size_t vl) {136 return __riscv_vsll_vv_i8m8(op1, shift, vl);137}138 139// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vsll_vx_i8m8140// CHECK-RV64-SAME: (<vscale x 64 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {141// CHECK-RV64-NEXT: entry:142// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vsll.nxv64i8.i64.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> [[OP1]], i64 [[SHIFT]], i64 [[VL]])143// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]144//145vint8m8_t test_vsll_vx_i8m8(vint8m8_t op1, size_t shift, size_t vl) {146 return __riscv_vsll_vx_i8m8(op1, shift, vl);147}148 149// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vsll_vv_i16mf4150// CHECK-RV64-SAME: (<vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {151// CHECK-RV64-NEXT: entry:152// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vsll.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[OP1]], <vscale x 1 x i16> [[SHIFT]], i64 [[VL]])153// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]154//155vint16mf4_t test_vsll_vv_i16mf4(vint16mf4_t op1, vuint16mf4_t shift, size_t vl) {156 return __riscv_vsll_vv_i16mf4(op1, shift, vl);157}158 159// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vsll_vx_i16mf4160// CHECK-RV64-SAME: (<vscale x 1 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {161// CHECK-RV64-NEXT: entry:162// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vsll.nxv1i16.i64.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[OP1]], i64 [[SHIFT]], i64 [[VL]])163// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]164//165vint16mf4_t test_vsll_vx_i16mf4(vint16mf4_t op1, size_t shift, size_t vl) {166 return __riscv_vsll_vx_i16mf4(op1, shift, vl);167}168 169// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vsll_vv_i16mf2170// CHECK-RV64-SAME: (<vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {171// CHECK-RV64-NEXT: entry:172// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vsll.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> [[OP1]], <vscale x 2 x i16> [[SHIFT]], i64 [[VL]])173// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]174//175vint16mf2_t test_vsll_vv_i16mf2(vint16mf2_t op1, vuint16mf2_t shift, size_t vl) {176 return __riscv_vsll_vv_i16mf2(op1, shift, vl);177}178 179// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vsll_vx_i16mf2180// CHECK-RV64-SAME: (<vscale x 2 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {181// CHECK-RV64-NEXT: entry:182// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vsll.nxv2i16.i64.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> [[OP1]], i64 [[SHIFT]], i64 [[VL]])183// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]184//185vint16mf2_t test_vsll_vx_i16mf2(vint16mf2_t op1, size_t shift, size_t vl) {186 return __riscv_vsll_vx_i16mf2(op1, shift, vl);187}188 189// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vsll_vv_i16m1190// CHECK-RV64-SAME: (<vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {191// CHECK-RV64-NEXT: entry:192// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vsll.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> [[OP1]], <vscale x 4 x i16> [[SHIFT]], i64 [[VL]])193// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]194//195vint16m1_t test_vsll_vv_i16m1(vint16m1_t op1, vuint16m1_t shift, size_t vl) {196 return __riscv_vsll_vv_i16m1(op1, shift, vl);197}198 199// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vsll_vx_i16m1200// CHECK-RV64-SAME: (<vscale x 4 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {201// CHECK-RV64-NEXT: entry:202// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vsll.nxv4i16.i64.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> [[OP1]], i64 [[SHIFT]], i64 [[VL]])203// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]204//205vint16m1_t test_vsll_vx_i16m1(vint16m1_t op1, size_t shift, size_t vl) {206 return __riscv_vsll_vx_i16m1(op1, shift, vl);207}208 209// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vsll_vv_i16m2210// CHECK-RV64-SAME: (<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {211// CHECK-RV64-NEXT: entry:212// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vsll.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> [[OP1]], <vscale x 8 x i16> [[SHIFT]], i64 [[VL]])213// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]214//215vint16m2_t test_vsll_vv_i16m2(vint16m2_t op1, vuint16m2_t shift, size_t vl) {216 return __riscv_vsll_vv_i16m2(op1, shift, vl);217}218 219// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vsll_vx_i16m2220// CHECK-RV64-SAME: (<vscale x 8 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {221// CHECK-RV64-NEXT: entry:222// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vsll.nxv8i16.i64.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> [[OP1]], i64 [[SHIFT]], i64 [[VL]])223// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]224//225vint16m2_t test_vsll_vx_i16m2(vint16m2_t op1, size_t shift, size_t vl) {226 return __riscv_vsll_vx_i16m2(op1, shift, vl);227}228 229// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vsll_vv_i16m4230// CHECK-RV64-SAME: (<vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {231// CHECK-RV64-NEXT: entry:232// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vsll.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> [[OP1]], <vscale x 16 x i16> [[SHIFT]], i64 [[VL]])233// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]234//235vint16m4_t test_vsll_vv_i16m4(vint16m4_t op1, vuint16m4_t shift, size_t vl) {236 return __riscv_vsll_vv_i16m4(op1, shift, vl);237}238 239// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vsll_vx_i16m4240// CHECK-RV64-SAME: (<vscale x 16 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {241// CHECK-RV64-NEXT: entry:242// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vsll.nxv16i16.i64.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> [[OP1]], i64 [[SHIFT]], i64 [[VL]])243// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]244//245vint16m4_t test_vsll_vx_i16m4(vint16m4_t op1, size_t shift, size_t vl) {246 return __riscv_vsll_vx_i16m4(op1, shift, vl);247}248 249// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vsll_vv_i16m8250// CHECK-RV64-SAME: (<vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {251// CHECK-RV64-NEXT: entry:252// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vsll.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> [[OP1]], <vscale x 32 x i16> [[SHIFT]], i64 [[VL]])253// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]254//255vint16m8_t test_vsll_vv_i16m8(vint16m8_t op1, vuint16m8_t shift, size_t vl) {256 return __riscv_vsll_vv_i16m8(op1, shift, vl);257}258 259// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vsll_vx_i16m8260// CHECK-RV64-SAME: (<vscale x 32 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {261// CHECK-RV64-NEXT: entry:262// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vsll.nxv32i16.i64.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> [[OP1]], i64 [[SHIFT]], i64 [[VL]])263// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]264//265vint16m8_t test_vsll_vx_i16m8(vint16m8_t op1, size_t shift, size_t vl) {266 return __riscv_vsll_vx_i16m8(op1, shift, vl);267}268 269// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vsll_vv_i32mf2270// CHECK-RV64-SAME: (<vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {271// CHECK-RV64-NEXT: entry:272// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vsll.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[OP1]], <vscale x 1 x i32> [[SHIFT]], i64 [[VL]])273// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]274//275vint32mf2_t test_vsll_vv_i32mf2(vint32mf2_t op1, vuint32mf2_t shift, size_t vl) {276 return __riscv_vsll_vv_i32mf2(op1, shift, vl);277}278 279// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vsll_vx_i32mf2280// CHECK-RV64-SAME: (<vscale x 1 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {281// CHECK-RV64-NEXT: entry:282// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vsll.nxv1i32.i64.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[OP1]], i64 [[SHIFT]], i64 [[VL]])283// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]284//285vint32mf2_t test_vsll_vx_i32mf2(vint32mf2_t op1, size_t shift, size_t vl) {286 return __riscv_vsll_vx_i32mf2(op1, shift, vl);287}288 289// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vsll_vv_i32m1290// CHECK-RV64-SAME: (<vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {291// CHECK-RV64-NEXT: entry:292// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vsll.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[OP1]], <vscale x 2 x i32> [[SHIFT]], i64 [[VL]])293// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]294//295vint32m1_t test_vsll_vv_i32m1(vint32m1_t op1, vuint32m1_t shift, size_t vl) {296 return __riscv_vsll_vv_i32m1(op1, shift, vl);297}298 299// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vsll_vx_i32m1300// CHECK-RV64-SAME: (<vscale x 2 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {301// CHECK-RV64-NEXT: entry:302// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vsll.nxv2i32.i64.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[OP1]], i64 [[SHIFT]], i64 [[VL]])303// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]304//305vint32m1_t test_vsll_vx_i32m1(vint32m1_t op1, size_t shift, size_t vl) {306 return __riscv_vsll_vx_i32m1(op1, shift, vl);307}308 309// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vsll_vv_i32m2310// CHECK-RV64-SAME: (<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {311// CHECK-RV64-NEXT: entry:312// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vsll.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> [[OP1]], <vscale x 4 x i32> [[SHIFT]], i64 [[VL]])313// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]314//315vint32m2_t test_vsll_vv_i32m2(vint32m2_t op1, vuint32m2_t shift, size_t vl) {316 return __riscv_vsll_vv_i32m2(op1, shift, vl);317}318 319// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vsll_vx_i32m2320// CHECK-RV64-SAME: (<vscale x 4 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {321// CHECK-RV64-NEXT: entry:322// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vsll.nxv4i32.i64.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> [[OP1]], i64 [[SHIFT]], i64 [[VL]])323// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]324//325vint32m2_t test_vsll_vx_i32m2(vint32m2_t op1, size_t shift, size_t vl) {326 return __riscv_vsll_vx_i32m2(op1, shift, vl);327}328 329// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vsll_vv_i32m4330// CHECK-RV64-SAME: (<vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {331// CHECK-RV64-NEXT: entry:332// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vsll.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> [[OP1]], <vscale x 8 x i32> [[SHIFT]], i64 [[VL]])333// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]334//335vint32m4_t test_vsll_vv_i32m4(vint32m4_t op1, vuint32m4_t shift, size_t vl) {336 return __riscv_vsll_vv_i32m4(op1, shift, vl);337}338 339// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vsll_vx_i32m4340// CHECK-RV64-SAME: (<vscale x 8 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {341// CHECK-RV64-NEXT: entry:342// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vsll.nxv8i32.i64.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> [[OP1]], i64 [[SHIFT]], i64 [[VL]])343// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]344//345vint32m4_t test_vsll_vx_i32m4(vint32m4_t op1, size_t shift, size_t vl) {346 return __riscv_vsll_vx_i32m4(op1, shift, vl);347}348 349// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vsll_vv_i32m8350// CHECK-RV64-SAME: (<vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {351// CHECK-RV64-NEXT: entry:352// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vsll.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> [[OP1]], <vscale x 16 x i32> [[SHIFT]], i64 [[VL]])353// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]354//355vint32m8_t test_vsll_vv_i32m8(vint32m8_t op1, vuint32m8_t shift, size_t vl) {356 return __riscv_vsll_vv_i32m8(op1, shift, vl);357}358 359// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vsll_vx_i32m8360// CHECK-RV64-SAME: (<vscale x 16 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {361// CHECK-RV64-NEXT: entry:362// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vsll.nxv16i32.i64.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> [[OP1]], i64 [[SHIFT]], i64 [[VL]])363// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]364//365vint32m8_t test_vsll_vx_i32m8(vint32m8_t op1, size_t shift, size_t vl) {366 return __riscv_vsll_vx_i32m8(op1, shift, vl);367}368 369// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vsll_vv_i64m1370// CHECK-RV64-SAME: (<vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {371// CHECK-RV64-NEXT: entry:372// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vsll.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> [[OP1]], <vscale x 1 x i64> [[SHIFT]], i64 [[VL]])373// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]374//375vint64m1_t test_vsll_vv_i64m1(vint64m1_t op1, vuint64m1_t shift, size_t vl) {376 return __riscv_vsll_vv_i64m1(op1, shift, vl);377}378 379// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vsll_vx_i64m1380// CHECK-RV64-SAME: (<vscale x 1 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {381// CHECK-RV64-NEXT: entry:382// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vsll.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> [[OP1]], i64 [[SHIFT]], i64 [[VL]])383// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]384//385vint64m1_t test_vsll_vx_i64m1(vint64m1_t op1, size_t shift, size_t vl) {386 return __riscv_vsll_vx_i64m1(op1, shift, vl);387}388 389// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vsll_vv_i64m2390// CHECK-RV64-SAME: (<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {391// CHECK-RV64-NEXT: entry:392// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vsll.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> [[OP1]], <vscale x 2 x i64> [[SHIFT]], i64 [[VL]])393// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]394//395vint64m2_t test_vsll_vv_i64m2(vint64m2_t op1, vuint64m2_t shift, size_t vl) {396 return __riscv_vsll_vv_i64m2(op1, shift, vl);397}398 399// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vsll_vx_i64m2400// CHECK-RV64-SAME: (<vscale x 2 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {401// CHECK-RV64-NEXT: entry:402// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vsll.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> [[OP1]], i64 [[SHIFT]], i64 [[VL]])403// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]404//405vint64m2_t test_vsll_vx_i64m2(vint64m2_t op1, size_t shift, size_t vl) {406 return __riscv_vsll_vx_i64m2(op1, shift, vl);407}408 409// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vsll_vv_i64m4410// CHECK-RV64-SAME: (<vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {411// CHECK-RV64-NEXT: entry:412// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vsll.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> [[OP1]], <vscale x 4 x i64> [[SHIFT]], i64 [[VL]])413// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]414//415vint64m4_t test_vsll_vv_i64m4(vint64m4_t op1, vuint64m4_t shift, size_t vl) {416 return __riscv_vsll_vv_i64m4(op1, shift, vl);417}418 419// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vsll_vx_i64m4420// CHECK-RV64-SAME: (<vscale x 4 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {421// CHECK-RV64-NEXT: entry:422// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vsll.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> [[OP1]], i64 [[SHIFT]], i64 [[VL]])423// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]424//425vint64m4_t test_vsll_vx_i64m4(vint64m4_t op1, size_t shift, size_t vl) {426 return __riscv_vsll_vx_i64m4(op1, shift, vl);427}428 429// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vsll_vv_i64m8430// CHECK-RV64-SAME: (<vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {431// CHECK-RV64-NEXT: entry:432// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vsll.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> [[OP1]], <vscale x 8 x i64> [[SHIFT]], i64 [[VL]])433// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]434//435vint64m8_t test_vsll_vv_i64m8(vint64m8_t op1, vuint64m8_t shift, size_t vl) {436 return __riscv_vsll_vv_i64m8(op1, shift, vl);437}438 439// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vsll_vx_i64m8440// CHECK-RV64-SAME: (<vscale x 8 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {441// CHECK-RV64-NEXT: entry:442// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vsll.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> [[OP1]], i64 [[SHIFT]], i64 [[VL]])443// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]444//445vint64m8_t test_vsll_vx_i64m8(vint64m8_t op1, size_t shift, size_t vl) {446 return __riscv_vsll_vx_i64m8(op1, shift, vl);447}448 449// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vsll_vv_u8mf8450// CHECK-RV64-SAME: (<vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {451// CHECK-RV64-NEXT: entry:452// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> [[OP1]], <vscale x 1 x i8> [[SHIFT]], i64 [[VL]])453// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]454//455vuint8mf8_t test_vsll_vv_u8mf8(vuint8mf8_t op1, vuint8mf8_t shift, size_t vl) {456 return __riscv_vsll_vv_u8mf8(op1, shift, vl);457}458 459// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vsll_vx_u8mf8460// CHECK-RV64-SAME: (<vscale x 1 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {461// CHECK-RV64-NEXT: entry:462// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> [[OP1]], i64 [[SHIFT]], i64 [[VL]])463// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]464//465vuint8mf8_t test_vsll_vx_u8mf8(vuint8mf8_t op1, size_t shift, size_t vl) {466 return __riscv_vsll_vx_u8mf8(op1, shift, vl);467}468 469// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vsll_vv_u8mf4470// CHECK-RV64-SAME: (<vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {471// CHECK-RV64-NEXT: entry:472// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> [[OP1]], <vscale x 2 x i8> [[SHIFT]], i64 [[VL]])473// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]474//475vuint8mf4_t test_vsll_vv_u8mf4(vuint8mf4_t op1, vuint8mf4_t shift, size_t vl) {476 return __riscv_vsll_vv_u8mf4(op1, shift, vl);477}478 479// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vsll_vx_u8mf4480// CHECK-RV64-SAME: (<vscale x 2 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {481// CHECK-RV64-NEXT: entry:482// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> [[OP1]], i64 [[SHIFT]], i64 [[VL]])483// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]484//485vuint8mf4_t test_vsll_vx_u8mf4(vuint8mf4_t op1, size_t shift, size_t vl) {486 return __riscv_vsll_vx_u8mf4(op1, shift, vl);487}488 489// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vsll_vv_u8mf2490// CHECK-RV64-SAME: (<vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {491// CHECK-RV64-NEXT: entry:492// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> [[OP1]], <vscale x 4 x i8> [[SHIFT]], i64 [[VL]])493// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]494//495vuint8mf2_t test_vsll_vv_u8mf2(vuint8mf2_t op1, vuint8mf2_t shift, size_t vl) {496 return __riscv_vsll_vv_u8mf2(op1, shift, vl);497}498 499// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vsll_vx_u8mf2500// CHECK-RV64-SAME: (<vscale x 4 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {501// CHECK-RV64-NEXT: entry:502// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> [[OP1]], i64 [[SHIFT]], i64 [[VL]])503// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]504//505vuint8mf2_t test_vsll_vx_u8mf2(vuint8mf2_t op1, size_t shift, size_t vl) {506 return __riscv_vsll_vx_u8mf2(op1, shift, vl);507}508 509// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vsll_vv_u8m1510// CHECK-RV64-SAME: (<vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {511// CHECK-RV64-NEXT: entry:512// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> [[OP1]], <vscale x 8 x i8> [[SHIFT]], i64 [[VL]])513// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]514//515vuint8m1_t test_vsll_vv_u8m1(vuint8m1_t op1, vuint8m1_t shift, size_t vl) {516 return __riscv_vsll_vv_u8m1(op1, shift, vl);517}518 519// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vsll_vx_u8m1520// CHECK-RV64-SAME: (<vscale x 8 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {521// CHECK-RV64-NEXT: entry:522// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> [[OP1]], i64 [[SHIFT]], i64 [[VL]])523// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]524//525vuint8m1_t test_vsll_vx_u8m1(vuint8m1_t op1, size_t shift, size_t vl) {526 return __riscv_vsll_vx_u8m1(op1, shift, vl);527}528 529// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vsll_vv_u8m2530// CHECK-RV64-SAME: (<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {531// CHECK-RV64-NEXT: entry:532// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> [[OP1]], <vscale x 16 x i8> [[SHIFT]], i64 [[VL]])533// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]534//535vuint8m2_t test_vsll_vv_u8m2(vuint8m2_t op1, vuint8m2_t shift, size_t vl) {536 return __riscv_vsll_vv_u8m2(op1, shift, vl);537}538 539// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vsll_vx_u8m2540// CHECK-RV64-SAME: (<vscale x 16 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {541// CHECK-RV64-NEXT: entry:542// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> [[OP1]], i64 [[SHIFT]], i64 [[VL]])543// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]544//545vuint8m2_t test_vsll_vx_u8m2(vuint8m2_t op1, size_t shift, size_t vl) {546 return __riscv_vsll_vx_u8m2(op1, shift, vl);547}548 549// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vsll_vv_u8m4550// CHECK-RV64-SAME: (<vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {551// CHECK-RV64-NEXT: entry:552// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vsll.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> [[OP1]], <vscale x 32 x i8> [[SHIFT]], i64 [[VL]])553// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]554//555vuint8m4_t test_vsll_vv_u8m4(vuint8m4_t op1, vuint8m4_t shift, size_t vl) {556 return __riscv_vsll_vv_u8m4(op1, shift, vl);557}558 559// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vsll_vx_u8m4560// CHECK-RV64-SAME: (<vscale x 32 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {561// CHECK-RV64-NEXT: entry:562// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vsll.nxv32i8.i64.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> [[OP1]], i64 [[SHIFT]], i64 [[VL]])563// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]564//565vuint8m4_t test_vsll_vx_u8m4(vuint8m4_t op1, size_t shift, size_t vl) {566 return __riscv_vsll_vx_u8m4(op1, shift, vl);567}568 569// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vsll_vv_u8m8570// CHECK-RV64-SAME: (<vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {571// CHECK-RV64-NEXT: entry:572// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vsll.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> [[OP1]], <vscale x 64 x i8> [[SHIFT]], i64 [[VL]])573// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]574//575vuint8m8_t test_vsll_vv_u8m8(vuint8m8_t op1, vuint8m8_t shift, size_t vl) {576 return __riscv_vsll_vv_u8m8(op1, shift, vl);577}578 579// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vsll_vx_u8m8580// CHECK-RV64-SAME: (<vscale x 64 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {581// CHECK-RV64-NEXT: entry:582// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vsll.nxv64i8.i64.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> [[OP1]], i64 [[SHIFT]], i64 [[VL]])583// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]584//585vuint8m8_t test_vsll_vx_u8m8(vuint8m8_t op1, size_t shift, size_t vl) {586 return __riscv_vsll_vx_u8m8(op1, shift, vl);587}588 589// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vsll_vv_u16mf4590// CHECK-RV64-SAME: (<vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {591// CHECK-RV64-NEXT: entry:592// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vsll.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[OP1]], <vscale x 1 x i16> [[SHIFT]], i64 [[VL]])593// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]594//595vuint16mf4_t test_vsll_vv_u16mf4(vuint16mf4_t op1, vuint16mf4_t shift, size_t vl) {596 return __riscv_vsll_vv_u16mf4(op1, shift, vl);597}598 599// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vsll_vx_u16mf4600// CHECK-RV64-SAME: (<vscale x 1 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {601// CHECK-RV64-NEXT: entry:602// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vsll.nxv1i16.i64.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[OP1]], i64 [[SHIFT]], i64 [[VL]])603// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]604//605vuint16mf4_t test_vsll_vx_u16mf4(vuint16mf4_t op1, size_t shift, size_t vl) {606 return __riscv_vsll_vx_u16mf4(op1, shift, vl);607}608 609// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vsll_vv_u16mf2610// CHECK-RV64-SAME: (<vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {611// CHECK-RV64-NEXT: entry:612// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vsll.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> [[OP1]], <vscale x 2 x i16> [[SHIFT]], i64 [[VL]])613// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]614//615vuint16mf2_t test_vsll_vv_u16mf2(vuint16mf2_t op1, vuint16mf2_t shift, size_t vl) {616 return __riscv_vsll_vv_u16mf2(op1, shift, vl);617}618 619// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vsll_vx_u16mf2620// CHECK-RV64-SAME: (<vscale x 2 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {621// CHECK-RV64-NEXT: entry:622// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vsll.nxv2i16.i64.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> [[OP1]], i64 [[SHIFT]], i64 [[VL]])623// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]624//625vuint16mf2_t test_vsll_vx_u16mf2(vuint16mf2_t op1, size_t shift, size_t vl) {626 return __riscv_vsll_vx_u16mf2(op1, shift, vl);627}628 629// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vsll_vv_u16m1630// CHECK-RV64-SAME: (<vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {631// CHECK-RV64-NEXT: entry:632// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vsll.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> [[OP1]], <vscale x 4 x i16> [[SHIFT]], i64 [[VL]])633// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]634//635vuint16m1_t test_vsll_vv_u16m1(vuint16m1_t op1, vuint16m1_t shift, size_t vl) {636 return __riscv_vsll_vv_u16m1(op1, shift, vl);637}638 639// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vsll_vx_u16m1640// CHECK-RV64-SAME: (<vscale x 4 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {641// CHECK-RV64-NEXT: entry:642// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vsll.nxv4i16.i64.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> [[OP1]], i64 [[SHIFT]], i64 [[VL]])643// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]644//645vuint16m1_t test_vsll_vx_u16m1(vuint16m1_t op1, size_t shift, size_t vl) {646 return __riscv_vsll_vx_u16m1(op1, shift, vl);647}648 649// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vsll_vv_u16m2650// CHECK-RV64-SAME: (<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {651// CHECK-RV64-NEXT: entry:652// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vsll.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> [[OP1]], <vscale x 8 x i16> [[SHIFT]], i64 [[VL]])653// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]654//655vuint16m2_t test_vsll_vv_u16m2(vuint16m2_t op1, vuint16m2_t shift, size_t vl) {656 return __riscv_vsll_vv_u16m2(op1, shift, vl);657}658 659// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vsll_vx_u16m2660// CHECK-RV64-SAME: (<vscale x 8 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {661// CHECK-RV64-NEXT: entry:662// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vsll.nxv8i16.i64.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> [[OP1]], i64 [[SHIFT]], i64 [[VL]])663// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]664//665vuint16m2_t test_vsll_vx_u16m2(vuint16m2_t op1, size_t shift, size_t vl) {666 return __riscv_vsll_vx_u16m2(op1, shift, vl);667}668 669// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vsll_vv_u16m4670// CHECK-RV64-SAME: (<vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {671// CHECK-RV64-NEXT: entry:672// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vsll.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> [[OP1]], <vscale x 16 x i16> [[SHIFT]], i64 [[VL]])673// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]674//675vuint16m4_t test_vsll_vv_u16m4(vuint16m4_t op1, vuint16m4_t shift, size_t vl) {676 return __riscv_vsll_vv_u16m4(op1, shift, vl);677}678 679// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vsll_vx_u16m4680// CHECK-RV64-SAME: (<vscale x 16 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {681// CHECK-RV64-NEXT: entry:682// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vsll.nxv16i16.i64.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> [[OP1]], i64 [[SHIFT]], i64 [[VL]])683// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]684//685vuint16m4_t test_vsll_vx_u16m4(vuint16m4_t op1, size_t shift, size_t vl) {686 return __riscv_vsll_vx_u16m4(op1, shift, vl);687}688 689// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vsll_vv_u16m8690// CHECK-RV64-SAME: (<vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {691// CHECK-RV64-NEXT: entry:692// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vsll.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> [[OP1]], <vscale x 32 x i16> [[SHIFT]], i64 [[VL]])693// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]694//695vuint16m8_t test_vsll_vv_u16m8(vuint16m8_t op1, vuint16m8_t shift, size_t vl) {696 return __riscv_vsll_vv_u16m8(op1, shift, vl);697}698 699// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vsll_vx_u16m8700// CHECK-RV64-SAME: (<vscale x 32 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {701// CHECK-RV64-NEXT: entry:702// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vsll.nxv32i16.i64.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> [[OP1]], i64 [[SHIFT]], i64 [[VL]])703// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]704//705vuint16m8_t test_vsll_vx_u16m8(vuint16m8_t op1, size_t shift, size_t vl) {706 return __riscv_vsll_vx_u16m8(op1, shift, vl);707}708 709// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vsll_vv_u32mf2710// CHECK-RV64-SAME: (<vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {711// CHECK-RV64-NEXT: entry:712// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vsll.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[OP1]], <vscale x 1 x i32> [[SHIFT]], i64 [[VL]])713// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]714//715vuint32mf2_t test_vsll_vv_u32mf2(vuint32mf2_t op1, vuint32mf2_t shift, size_t vl) {716 return __riscv_vsll_vv_u32mf2(op1, shift, vl);717}718 719// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vsll_vx_u32mf2720// CHECK-RV64-SAME: (<vscale x 1 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {721// CHECK-RV64-NEXT: entry:722// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vsll.nxv1i32.i64.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[OP1]], i64 [[SHIFT]], i64 [[VL]])723// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]724//725vuint32mf2_t test_vsll_vx_u32mf2(vuint32mf2_t op1, size_t shift, size_t vl) {726 return __riscv_vsll_vx_u32mf2(op1, shift, vl);727}728 729// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vsll_vv_u32m1730// CHECK-RV64-SAME: (<vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {731// CHECK-RV64-NEXT: entry:732// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vsll.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[OP1]], <vscale x 2 x i32> [[SHIFT]], i64 [[VL]])733// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]734//735vuint32m1_t test_vsll_vv_u32m1(vuint32m1_t op1, vuint32m1_t shift, size_t vl) {736 return __riscv_vsll_vv_u32m1(op1, shift, vl);737}738 739// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vsll_vx_u32m1740// CHECK-RV64-SAME: (<vscale x 2 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {741// CHECK-RV64-NEXT: entry:742// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vsll.nxv2i32.i64.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[OP1]], i64 [[SHIFT]], i64 [[VL]])743// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]744//745vuint32m1_t test_vsll_vx_u32m1(vuint32m1_t op1, size_t shift, size_t vl) {746 return __riscv_vsll_vx_u32m1(op1, shift, vl);747}748 749// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vsll_vv_u32m2750// CHECK-RV64-SAME: (<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {751// CHECK-RV64-NEXT: entry:752// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vsll.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> [[OP1]], <vscale x 4 x i32> [[SHIFT]], i64 [[VL]])753// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]754//755vuint32m2_t test_vsll_vv_u32m2(vuint32m2_t op1, vuint32m2_t shift, size_t vl) {756 return __riscv_vsll_vv_u32m2(op1, shift, vl);757}758 759// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vsll_vx_u32m2760// CHECK-RV64-SAME: (<vscale x 4 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {761// CHECK-RV64-NEXT: entry:762// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vsll.nxv4i32.i64.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> [[OP1]], i64 [[SHIFT]], i64 [[VL]])763// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]764//765vuint32m2_t test_vsll_vx_u32m2(vuint32m2_t op1, size_t shift, size_t vl) {766 return __riscv_vsll_vx_u32m2(op1, shift, vl);767}768 769// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vsll_vv_u32m4770// CHECK-RV64-SAME: (<vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {771// CHECK-RV64-NEXT: entry:772// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vsll.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> [[OP1]], <vscale x 8 x i32> [[SHIFT]], i64 [[VL]])773// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]774//775vuint32m4_t test_vsll_vv_u32m4(vuint32m4_t op1, vuint32m4_t shift, size_t vl) {776 return __riscv_vsll_vv_u32m4(op1, shift, vl);777}778 779// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vsll_vx_u32m4780// CHECK-RV64-SAME: (<vscale x 8 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {781// CHECK-RV64-NEXT: entry:782// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vsll.nxv8i32.i64.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> [[OP1]], i64 [[SHIFT]], i64 [[VL]])783// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]784//785vuint32m4_t test_vsll_vx_u32m4(vuint32m4_t op1, size_t shift, size_t vl) {786 return __riscv_vsll_vx_u32m4(op1, shift, vl);787}788 789// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vsll_vv_u32m8790// CHECK-RV64-SAME: (<vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {791// CHECK-RV64-NEXT: entry:792// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vsll.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> [[OP1]], <vscale x 16 x i32> [[SHIFT]], i64 [[VL]])793// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]794//795vuint32m8_t test_vsll_vv_u32m8(vuint32m8_t op1, vuint32m8_t shift, size_t vl) {796 return __riscv_vsll_vv_u32m8(op1, shift, vl);797}798 799// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vsll_vx_u32m8800// CHECK-RV64-SAME: (<vscale x 16 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {801// CHECK-RV64-NEXT: entry:802// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vsll.nxv16i32.i64.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> [[OP1]], i64 [[SHIFT]], i64 [[VL]])803// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]804//805vuint32m8_t test_vsll_vx_u32m8(vuint32m8_t op1, size_t shift, size_t vl) {806 return __riscv_vsll_vx_u32m8(op1, shift, vl);807}808 809// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vsll_vv_u64m1810// CHECK-RV64-SAME: (<vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {811// CHECK-RV64-NEXT: entry:812// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vsll.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> [[OP1]], <vscale x 1 x i64> [[SHIFT]], i64 [[VL]])813// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]814//815vuint64m1_t test_vsll_vv_u64m1(vuint64m1_t op1, vuint64m1_t shift, size_t vl) {816 return __riscv_vsll_vv_u64m1(op1, shift, vl);817}818 819// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vsll_vx_u64m1820// CHECK-RV64-SAME: (<vscale x 1 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {821// CHECK-RV64-NEXT: entry:822// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vsll.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> [[OP1]], i64 [[SHIFT]], i64 [[VL]])823// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]824//825vuint64m1_t test_vsll_vx_u64m1(vuint64m1_t op1, size_t shift, size_t vl) {826 return __riscv_vsll_vx_u64m1(op1, shift, vl);827}828 829// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vsll_vv_u64m2830// CHECK-RV64-SAME: (<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {831// CHECK-RV64-NEXT: entry:832// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vsll.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> [[OP1]], <vscale x 2 x i64> [[SHIFT]], i64 [[VL]])833// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]834//835vuint64m2_t test_vsll_vv_u64m2(vuint64m2_t op1, vuint64m2_t shift, size_t vl) {836 return __riscv_vsll_vv_u64m2(op1, shift, vl);837}838 839// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vsll_vx_u64m2840// CHECK-RV64-SAME: (<vscale x 2 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {841// CHECK-RV64-NEXT: entry:842// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vsll.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> [[OP1]], i64 [[SHIFT]], i64 [[VL]])843// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]844//845vuint64m2_t test_vsll_vx_u64m2(vuint64m2_t op1, size_t shift, size_t vl) {846 return __riscv_vsll_vx_u64m2(op1, shift, vl);847}848 849// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vsll_vv_u64m4850// CHECK-RV64-SAME: (<vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {851// CHECK-RV64-NEXT: entry:852// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vsll.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> [[OP1]], <vscale x 4 x i64> [[SHIFT]], i64 [[VL]])853// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]854//855vuint64m4_t test_vsll_vv_u64m4(vuint64m4_t op1, vuint64m4_t shift, size_t vl) {856 return __riscv_vsll_vv_u64m4(op1, shift, vl);857}858 859// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vsll_vx_u64m4860// CHECK-RV64-SAME: (<vscale x 4 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {861// CHECK-RV64-NEXT: entry:862// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vsll.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> [[OP1]], i64 [[SHIFT]], i64 [[VL]])863// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]864//865vuint64m4_t test_vsll_vx_u64m4(vuint64m4_t op1, size_t shift, size_t vl) {866 return __riscv_vsll_vx_u64m4(op1, shift, vl);867}868 869// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vsll_vv_u64m8870// CHECK-RV64-SAME: (<vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {871// CHECK-RV64-NEXT: entry:872// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vsll.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> [[OP1]], <vscale x 8 x i64> [[SHIFT]], i64 [[VL]])873// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]874//875vuint64m8_t test_vsll_vv_u64m8(vuint64m8_t op1, vuint64m8_t shift, size_t vl) {876 return __riscv_vsll_vv_u64m8(op1, shift, vl);877}878 879// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vsll_vx_u64m8880// CHECK-RV64-SAME: (<vscale x 8 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {881// CHECK-RV64-NEXT: entry:882// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vsll.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> [[OP1]], i64 [[SHIFT]], i64 [[VL]])883// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]884//885vuint64m8_t test_vsll_vx_u64m8(vuint64m8_t op1, size_t shift, size_t vl) {886 return __riscv_vsll_vx_u64m8(op1, shift, vl);887}888 889// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vsll_vv_i8mf8_m890// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {891// CHECK-RV64-NEXT: entry:892// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vsll.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> [[OP1]], <vscale x 1 x i8> [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)893// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]894//895vint8mf8_t test_vsll_vv_i8mf8_m(vbool64_t mask, vint8mf8_t op1, vuint8mf8_t shift, size_t vl) {896 return __riscv_vsll_vv_i8mf8_m(mask, op1, shift, vl);897}898 899// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vsll_vx_i8mf8_m900// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {901// CHECK-RV64-NEXT: entry:902// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vsll.mask.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)903// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]904//905vint8mf8_t test_vsll_vx_i8mf8_m(vbool64_t mask, vint8mf8_t op1, size_t shift, size_t vl) {906 return __riscv_vsll_vx_i8mf8_m(mask, op1, shift, vl);907}908 909// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vsll_vv_i8mf4_m910// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {911// CHECK-RV64-NEXT: entry:912// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vsll.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> [[OP1]], <vscale x 2 x i8> [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)913// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]914//915vint8mf4_t test_vsll_vv_i8mf4_m(vbool32_t mask, vint8mf4_t op1, vuint8mf4_t shift, size_t vl) {916 return __riscv_vsll_vv_i8mf4_m(mask, op1, shift, vl);917}918 919// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vsll_vx_i8mf4_m920// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {921// CHECK-RV64-NEXT: entry:922// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vsll.mask.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)923// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]924//925vint8mf4_t test_vsll_vx_i8mf4_m(vbool32_t mask, vint8mf4_t op1, size_t shift, size_t vl) {926 return __riscv_vsll_vx_i8mf4_m(mask, op1, shift, vl);927}928 929// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vsll_vv_i8mf2_m930// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {931// CHECK-RV64-NEXT: entry:932// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vsll.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> [[OP1]], <vscale x 4 x i8> [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)933// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]934//935vint8mf2_t test_vsll_vv_i8mf2_m(vbool16_t mask, vint8mf2_t op1, vuint8mf2_t shift, size_t vl) {936 return __riscv_vsll_vv_i8mf2_m(mask, op1, shift, vl);937}938 939// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vsll_vx_i8mf2_m940// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {941// CHECK-RV64-NEXT: entry:942// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vsll.mask.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)943// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]944//945vint8mf2_t test_vsll_vx_i8mf2_m(vbool16_t mask, vint8mf2_t op1, size_t shift, size_t vl) {946 return __riscv_vsll_vx_i8mf2_m(mask, op1, shift, vl);947}948 949// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vsll_vv_i8m1_m950// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {951// CHECK-RV64-NEXT: entry:952// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vsll.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> [[OP1]], <vscale x 8 x i8> [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)953// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]954//955vint8m1_t test_vsll_vv_i8m1_m(vbool8_t mask, vint8m1_t op1, vuint8m1_t shift, size_t vl) {956 return __riscv_vsll_vv_i8m1_m(mask, op1, shift, vl);957}958 959// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vsll_vx_i8m1_m960// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {961// CHECK-RV64-NEXT: entry:962// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vsll.mask.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)963// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]964//965vint8m1_t test_vsll_vx_i8m1_m(vbool8_t mask, vint8m1_t op1, size_t shift, size_t vl) {966 return __riscv_vsll_vx_i8m1_m(mask, op1, shift, vl);967}968 969// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vsll_vv_i8m2_m970// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {971// CHECK-RV64-NEXT: entry:972// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vsll.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> [[OP1]], <vscale x 16 x i8> [[SHIFT]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3)973// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]974//975vint8m2_t test_vsll_vv_i8m2_m(vbool4_t mask, vint8m2_t op1, vuint8m2_t shift, size_t vl) {976 return __riscv_vsll_vv_i8m2_m(mask, op1, shift, vl);977}978 979// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vsll_vx_i8m2_m980// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {981// CHECK-RV64-NEXT: entry:982// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vsll.mask.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3)983// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]984//985vint8m2_t test_vsll_vx_i8m2_m(vbool4_t mask, vint8m2_t op1, size_t shift, size_t vl) {986 return __riscv_vsll_vx_i8m2_m(mask, op1, shift, vl);987}988 989// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vsll_vv_i8m4_m990// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {991// CHECK-RV64-NEXT: entry:992// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vsll.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> [[OP1]], <vscale x 32 x i8> [[SHIFT]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3)993// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]994//995vint8m4_t test_vsll_vv_i8m4_m(vbool2_t mask, vint8m4_t op1, vuint8m4_t shift, size_t vl) {996 return __riscv_vsll_vv_i8m4_m(mask, op1, shift, vl);997}998 999// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vsll_vx_i8m4_m1000// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1001// CHECK-RV64-NEXT: entry:1002// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vsll.mask.nxv32i8.i64.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3)1003// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]1004//1005vint8m4_t test_vsll_vx_i8m4_m(vbool2_t mask, vint8m4_t op1, size_t shift, size_t vl) {1006 return __riscv_vsll_vx_i8m4_m(mask, op1, shift, vl);1007}1008 1009// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vsll_vv_i8m8_m1010// CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1011// CHECK-RV64-NEXT: entry:1012// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vsll.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> [[OP1]], <vscale x 64 x i8> [[SHIFT]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 3)1013// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]1014//1015vint8m8_t test_vsll_vv_i8m8_m(vbool1_t mask, vint8m8_t op1, vuint8m8_t shift, size_t vl) {1016 return __riscv_vsll_vv_i8m8_m(mask, op1, shift, vl);1017}1018 1019// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vsll_vx_i8m8_m1020// CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1021// CHECK-RV64-NEXT: entry:1022// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vsll.mask.nxv64i8.i64.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 3)1023// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]1024//1025vint8m8_t test_vsll_vx_i8m8_m(vbool1_t mask, vint8m8_t op1, size_t shift, size_t vl) {1026 return __riscv_vsll_vx_i8m8_m(mask, op1, shift, vl);1027}1028 1029// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vsll_vv_i16mf4_m1030// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1031// CHECK-RV64-NEXT: entry:1032// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vsll.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[OP1]], <vscale x 1 x i16> [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)1033// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]1034//1035vint16mf4_t test_vsll_vv_i16mf4_m(vbool64_t mask, vint16mf4_t op1, vuint16mf4_t shift, size_t vl) {1036 return __riscv_vsll_vv_i16mf4_m(mask, op1, shift, vl);1037}1038 1039// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vsll_vx_i16mf4_m1040// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1041// CHECK-RV64-NEXT: entry:1042// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vsll.mask.nxv1i16.i64.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)1043// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]1044//1045vint16mf4_t test_vsll_vx_i16mf4_m(vbool64_t mask, vint16mf4_t op1, size_t shift, size_t vl) {1046 return __riscv_vsll_vx_i16mf4_m(mask, op1, shift, vl);1047}1048 1049// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vsll_vv_i16mf2_m1050// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1051// CHECK-RV64-NEXT: entry:1052// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vsll.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> [[OP1]], <vscale x 2 x i16> [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)1053// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]1054//1055vint16mf2_t test_vsll_vv_i16mf2_m(vbool32_t mask, vint16mf2_t op1, vuint16mf2_t shift, size_t vl) {1056 return __riscv_vsll_vv_i16mf2_m(mask, op1, shift, vl);1057}1058 1059// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vsll_vx_i16mf2_m1060// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1061// CHECK-RV64-NEXT: entry:1062// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vsll.mask.nxv2i16.i64.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)1063// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]1064//1065vint16mf2_t test_vsll_vx_i16mf2_m(vbool32_t mask, vint16mf2_t op1, size_t shift, size_t vl) {1066 return __riscv_vsll_vx_i16mf2_m(mask, op1, shift, vl);1067}1068 1069// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vsll_vv_i16m1_m1070// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1071// CHECK-RV64-NEXT: entry:1072// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vsll.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> [[OP1]], <vscale x 4 x i16> [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)1073// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]1074//1075vint16m1_t test_vsll_vv_i16m1_m(vbool16_t mask, vint16m1_t op1, vuint16m1_t shift, size_t vl) {1076 return __riscv_vsll_vv_i16m1_m(mask, op1, shift, vl);1077}1078 1079// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vsll_vx_i16m1_m1080// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1081// CHECK-RV64-NEXT: entry:1082// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vsll.mask.nxv4i16.i64.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)1083// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]1084//1085vint16m1_t test_vsll_vx_i16m1_m(vbool16_t mask, vint16m1_t op1, size_t shift, size_t vl) {1086 return __riscv_vsll_vx_i16m1_m(mask, op1, shift, vl);1087}1088 1089// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vsll_vv_i16m2_m1090// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1091// CHECK-RV64-NEXT: entry:1092// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vsll.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> [[OP1]], <vscale x 8 x i16> [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)1093// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]1094//1095vint16m2_t test_vsll_vv_i16m2_m(vbool8_t mask, vint16m2_t op1, vuint16m2_t shift, size_t vl) {1096 return __riscv_vsll_vv_i16m2_m(mask, op1, shift, vl);1097}1098 1099// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vsll_vx_i16m2_m1100// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1101// CHECK-RV64-NEXT: entry:1102// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vsll.mask.nxv8i16.i64.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)1103// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]1104//1105vint16m2_t test_vsll_vx_i16m2_m(vbool8_t mask, vint16m2_t op1, size_t shift, size_t vl) {1106 return __riscv_vsll_vx_i16m2_m(mask, op1, shift, vl);1107}1108 1109// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vsll_vv_i16m4_m1110// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1111// CHECK-RV64-NEXT: entry:1112// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vsll.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> [[OP1]], <vscale x 16 x i16> [[SHIFT]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3)1113// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]1114//1115vint16m4_t test_vsll_vv_i16m4_m(vbool4_t mask, vint16m4_t op1, vuint16m4_t shift, size_t vl) {1116 return __riscv_vsll_vv_i16m4_m(mask, op1, shift, vl);1117}1118 1119// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vsll_vx_i16m4_m1120// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1121// CHECK-RV64-NEXT: entry:1122// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vsll.mask.nxv16i16.i64.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3)1123// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]1124//1125vint16m4_t test_vsll_vx_i16m4_m(vbool4_t mask, vint16m4_t op1, size_t shift, size_t vl) {1126 return __riscv_vsll_vx_i16m4_m(mask, op1, shift, vl);1127}1128 1129// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vsll_vv_i16m8_m1130// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1131// CHECK-RV64-NEXT: entry:1132// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vsll.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> [[OP1]], <vscale x 32 x i16> [[SHIFT]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3)1133// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]1134//1135vint16m8_t test_vsll_vv_i16m8_m(vbool2_t mask, vint16m8_t op1, vuint16m8_t shift, size_t vl) {1136 return __riscv_vsll_vv_i16m8_m(mask, op1, shift, vl);1137}1138 1139// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vsll_vx_i16m8_m1140// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1141// CHECK-RV64-NEXT: entry:1142// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vsll.mask.nxv32i16.i64.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3)1143// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]1144//1145vint16m8_t test_vsll_vx_i16m8_m(vbool2_t mask, vint16m8_t op1, size_t shift, size_t vl) {1146 return __riscv_vsll_vx_i16m8_m(mask, op1, shift, vl);1147}1148 1149// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vsll_vv_i32mf2_m1150// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1151// CHECK-RV64-NEXT: entry:1152// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vsll.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[OP1]], <vscale x 1 x i32> [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)1153// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]1154//1155vint32mf2_t test_vsll_vv_i32mf2_m(vbool64_t mask, vint32mf2_t op1, vuint32mf2_t shift, size_t vl) {1156 return __riscv_vsll_vv_i32mf2_m(mask, op1, shift, vl);1157}1158 1159// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vsll_vx_i32mf2_m1160// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1161// CHECK-RV64-NEXT: entry:1162// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vsll.mask.nxv1i32.i64.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[OP1]], i64 [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)1163// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]1164//1165vint32mf2_t test_vsll_vx_i32mf2_m(vbool64_t mask, vint32mf2_t op1, size_t shift, size_t vl) {1166 return __riscv_vsll_vx_i32mf2_m(mask, op1, shift, vl);1167}1168 1169// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vsll_vv_i32m1_m1170// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1171// CHECK-RV64-NEXT: entry:1172// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vsll.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[OP1]], <vscale x 2 x i32> [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)1173// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]1174//1175vint32m1_t test_vsll_vv_i32m1_m(vbool32_t mask, vint32m1_t op1, vuint32m1_t shift, size_t vl) {1176 return __riscv_vsll_vv_i32m1_m(mask, op1, shift, vl);1177}1178 1179// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vsll_vx_i32m1_m1180// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1181// CHECK-RV64-NEXT: entry:1182// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vsll.mask.nxv2i32.i64.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[OP1]], i64 [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)1183// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]1184//1185vint32m1_t test_vsll_vx_i32m1_m(vbool32_t mask, vint32m1_t op1, size_t shift, size_t vl) {1186 return __riscv_vsll_vx_i32m1_m(mask, op1, shift, vl);1187}1188 1189// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vsll_vv_i32m2_m1190// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1191// CHECK-RV64-NEXT: entry:1192// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vsll.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> [[OP1]], <vscale x 4 x i32> [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)1193// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]1194//1195vint32m2_t test_vsll_vv_i32m2_m(vbool16_t mask, vint32m2_t op1, vuint32m2_t shift, size_t vl) {1196 return __riscv_vsll_vv_i32m2_m(mask, op1, shift, vl);1197}1198 1199// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vsll_vx_i32m2_m1200// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1201// CHECK-RV64-NEXT: entry:1202// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vsll.mask.nxv4i32.i64.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> [[OP1]], i64 [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)1203// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]1204//1205vint32m2_t test_vsll_vx_i32m2_m(vbool16_t mask, vint32m2_t op1, size_t shift, size_t vl) {1206 return __riscv_vsll_vx_i32m2_m(mask, op1, shift, vl);1207}1208 1209// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vsll_vv_i32m4_m1210// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1211// CHECK-RV64-NEXT: entry:1212// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vsll.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> [[OP1]], <vscale x 8 x i32> [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)1213// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]1214//1215vint32m4_t test_vsll_vv_i32m4_m(vbool8_t mask, vint32m4_t op1, vuint32m4_t shift, size_t vl) {1216 return __riscv_vsll_vv_i32m4_m(mask, op1, shift, vl);1217}1218 1219// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vsll_vx_i32m4_m1220// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1221// CHECK-RV64-NEXT: entry:1222// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vsll.mask.nxv8i32.i64.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> [[OP1]], i64 [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)1223// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]1224//1225vint32m4_t test_vsll_vx_i32m4_m(vbool8_t mask, vint32m4_t op1, size_t shift, size_t vl) {1226 return __riscv_vsll_vx_i32m4_m(mask, op1, shift, vl);1227}1228 1229// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vsll_vv_i32m8_m1230// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1231// CHECK-RV64-NEXT: entry:1232// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vsll.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> [[OP1]], <vscale x 16 x i32> [[SHIFT]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3)1233// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]1234//1235vint32m8_t test_vsll_vv_i32m8_m(vbool4_t mask, vint32m8_t op1, vuint32m8_t shift, size_t vl) {1236 return __riscv_vsll_vv_i32m8_m(mask, op1, shift, vl);1237}1238 1239// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vsll_vx_i32m8_m1240// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1241// CHECK-RV64-NEXT: entry:1242// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vsll.mask.nxv16i32.i64.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> [[OP1]], i64 [[SHIFT]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3)1243// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]1244//1245vint32m8_t test_vsll_vx_i32m8_m(vbool4_t mask, vint32m8_t op1, size_t shift, size_t vl) {1246 return __riscv_vsll_vx_i32m8_m(mask, op1, shift, vl);1247}1248 1249// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vsll_vv_i64m1_m1250// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1251// CHECK-RV64-NEXT: entry:1252// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vsll.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> [[OP1]], <vscale x 1 x i64> [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)1253// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]1254//1255vint64m1_t test_vsll_vv_i64m1_m(vbool64_t mask, vint64m1_t op1, vuint64m1_t shift, size_t vl) {1256 return __riscv_vsll_vv_i64m1_m(mask, op1, shift, vl);1257}1258 1259// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vsll_vx_i64m1_m1260// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1261// CHECK-RV64-NEXT: entry:1262// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vsll.mask.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> [[OP1]], i64 [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)1263// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]1264//1265vint64m1_t test_vsll_vx_i64m1_m(vbool64_t mask, vint64m1_t op1, size_t shift, size_t vl) {1266 return __riscv_vsll_vx_i64m1_m(mask, op1, shift, vl);1267}1268 1269// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vsll_vv_i64m2_m1270// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1271// CHECK-RV64-NEXT: entry:1272// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vsll.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> [[OP1]], <vscale x 2 x i64> [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)1273// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]1274//1275vint64m2_t test_vsll_vv_i64m2_m(vbool32_t mask, vint64m2_t op1, vuint64m2_t shift, size_t vl) {1276 return __riscv_vsll_vv_i64m2_m(mask, op1, shift, vl);1277}1278 1279// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vsll_vx_i64m2_m1280// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1281// CHECK-RV64-NEXT: entry:1282// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vsll.mask.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> [[OP1]], i64 [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)1283// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]1284//1285vint64m2_t test_vsll_vx_i64m2_m(vbool32_t mask, vint64m2_t op1, size_t shift, size_t vl) {1286 return __riscv_vsll_vx_i64m2_m(mask, op1, shift, vl);1287}1288 1289// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vsll_vv_i64m4_m1290// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1291// CHECK-RV64-NEXT: entry:1292// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vsll.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> [[OP1]], <vscale x 4 x i64> [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)1293// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]1294//1295vint64m4_t test_vsll_vv_i64m4_m(vbool16_t mask, vint64m4_t op1, vuint64m4_t shift, size_t vl) {1296 return __riscv_vsll_vv_i64m4_m(mask, op1, shift, vl);1297}1298 1299// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vsll_vx_i64m4_m1300// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1301// CHECK-RV64-NEXT: entry:1302// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vsll.mask.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> [[OP1]], i64 [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)1303// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]1304//1305vint64m4_t test_vsll_vx_i64m4_m(vbool16_t mask, vint64m4_t op1, size_t shift, size_t vl) {1306 return __riscv_vsll_vx_i64m4_m(mask, op1, shift, vl);1307}1308 1309// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vsll_vv_i64m8_m1310// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1311// CHECK-RV64-NEXT: entry:1312// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vsll.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> [[OP1]], <vscale x 8 x i64> [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)1313// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]1314//1315vint64m8_t test_vsll_vv_i64m8_m(vbool8_t mask, vint64m8_t op1, vuint64m8_t shift, size_t vl) {1316 return __riscv_vsll_vv_i64m8_m(mask, op1, shift, vl);1317}1318 1319// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vsll_vx_i64m8_m1320// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1321// CHECK-RV64-NEXT: entry:1322// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vsll.mask.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> [[OP1]], i64 [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)1323// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]1324//1325vint64m8_t test_vsll_vx_i64m8_m(vbool8_t mask, vint64m8_t op1, size_t shift, size_t vl) {1326 return __riscv_vsll_vx_i64m8_m(mask, op1, shift, vl);1327}1328 1329// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vsll_vv_u8mf8_m1330// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1331// CHECK-RV64-NEXT: entry:1332// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vsll.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> [[OP1]], <vscale x 1 x i8> [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)1333// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]1334//1335vuint8mf8_t test_vsll_vv_u8mf8_m(vbool64_t mask, vuint8mf8_t op1, vuint8mf8_t shift, size_t vl) {1336 return __riscv_vsll_vv_u8mf8_m(mask, op1, shift, vl);1337}1338 1339// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vsll_vx_u8mf8_m1340// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1341// CHECK-RV64-NEXT: entry:1342// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vsll.mask.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)1343// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]1344//1345vuint8mf8_t test_vsll_vx_u8mf8_m(vbool64_t mask, vuint8mf8_t op1, size_t shift, size_t vl) {1346 return __riscv_vsll_vx_u8mf8_m(mask, op1, shift, vl);1347}1348 1349// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vsll_vv_u8mf4_m1350// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1351// CHECK-RV64-NEXT: entry:1352// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vsll.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> [[OP1]], <vscale x 2 x i8> [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)1353// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]1354//1355vuint8mf4_t test_vsll_vv_u8mf4_m(vbool32_t mask, vuint8mf4_t op1, vuint8mf4_t shift, size_t vl) {1356 return __riscv_vsll_vv_u8mf4_m(mask, op1, shift, vl);1357}1358 1359// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vsll_vx_u8mf4_m1360// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1361// CHECK-RV64-NEXT: entry:1362// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vsll.mask.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)1363// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]1364//1365vuint8mf4_t test_vsll_vx_u8mf4_m(vbool32_t mask, vuint8mf4_t op1, size_t shift, size_t vl) {1366 return __riscv_vsll_vx_u8mf4_m(mask, op1, shift, vl);1367}1368 1369// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vsll_vv_u8mf2_m1370// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1371// CHECK-RV64-NEXT: entry:1372// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vsll.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> [[OP1]], <vscale x 4 x i8> [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)1373// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]1374//1375vuint8mf2_t test_vsll_vv_u8mf2_m(vbool16_t mask, vuint8mf2_t op1, vuint8mf2_t shift, size_t vl) {1376 return __riscv_vsll_vv_u8mf2_m(mask, op1, shift, vl);1377}1378 1379// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vsll_vx_u8mf2_m1380// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1381// CHECK-RV64-NEXT: entry:1382// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vsll.mask.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)1383// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]1384//1385vuint8mf2_t test_vsll_vx_u8mf2_m(vbool16_t mask, vuint8mf2_t op1, size_t shift, size_t vl) {1386 return __riscv_vsll_vx_u8mf2_m(mask, op1, shift, vl);1387}1388 1389// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vsll_vv_u8m1_m1390// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1391// CHECK-RV64-NEXT: entry:1392// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vsll.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> [[OP1]], <vscale x 8 x i8> [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)1393// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]1394//1395vuint8m1_t test_vsll_vv_u8m1_m(vbool8_t mask, vuint8m1_t op1, vuint8m1_t shift, size_t vl) {1396 return __riscv_vsll_vv_u8m1_m(mask, op1, shift, vl);1397}1398 1399// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vsll_vx_u8m1_m1400// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1401// CHECK-RV64-NEXT: entry:1402// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vsll.mask.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)1403// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]1404//1405vuint8m1_t test_vsll_vx_u8m1_m(vbool8_t mask, vuint8m1_t op1, size_t shift, size_t vl) {1406 return __riscv_vsll_vx_u8m1_m(mask, op1, shift, vl);1407}1408 1409// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vsll_vv_u8m2_m1410// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1411// CHECK-RV64-NEXT: entry:1412// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vsll.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> [[OP1]], <vscale x 16 x i8> [[SHIFT]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3)1413// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]1414//1415vuint8m2_t test_vsll_vv_u8m2_m(vbool4_t mask, vuint8m2_t op1, vuint8m2_t shift, size_t vl) {1416 return __riscv_vsll_vv_u8m2_m(mask, op1, shift, vl);1417}1418 1419// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vsll_vx_u8m2_m1420// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1421// CHECK-RV64-NEXT: entry:1422// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vsll.mask.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3)1423// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]1424//1425vuint8m2_t test_vsll_vx_u8m2_m(vbool4_t mask, vuint8m2_t op1, size_t shift, size_t vl) {1426 return __riscv_vsll_vx_u8m2_m(mask, op1, shift, vl);1427}1428 1429// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vsll_vv_u8m4_m1430// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1431// CHECK-RV64-NEXT: entry:1432// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vsll.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> [[OP1]], <vscale x 32 x i8> [[SHIFT]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3)1433// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]1434//1435vuint8m4_t test_vsll_vv_u8m4_m(vbool2_t mask, vuint8m4_t op1, vuint8m4_t shift, size_t vl) {1436 return __riscv_vsll_vv_u8m4_m(mask, op1, shift, vl);1437}1438 1439// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vsll_vx_u8m4_m1440// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1441// CHECK-RV64-NEXT: entry:1442// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vsll.mask.nxv32i8.i64.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3)1443// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]1444//1445vuint8m4_t test_vsll_vx_u8m4_m(vbool2_t mask, vuint8m4_t op1, size_t shift, size_t vl) {1446 return __riscv_vsll_vx_u8m4_m(mask, op1, shift, vl);1447}1448 1449// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vsll_vv_u8m8_m1450// CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1451// CHECK-RV64-NEXT: entry:1452// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vsll.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> [[OP1]], <vscale x 64 x i8> [[SHIFT]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 3)1453// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]1454//1455vuint8m8_t test_vsll_vv_u8m8_m(vbool1_t mask, vuint8m8_t op1, vuint8m8_t shift, size_t vl) {1456 return __riscv_vsll_vv_u8m8_m(mask, op1, shift, vl);1457}1458 1459// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vsll_vx_u8m8_m1460// CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1461// CHECK-RV64-NEXT: entry:1462// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vsll.mask.nxv64i8.i64.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 3)1463// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]1464//1465vuint8m8_t test_vsll_vx_u8m8_m(vbool1_t mask, vuint8m8_t op1, size_t shift, size_t vl) {1466 return __riscv_vsll_vx_u8m8_m(mask, op1, shift, vl);1467}1468 1469// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vsll_vv_u16mf4_m1470// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1471// CHECK-RV64-NEXT: entry:1472// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vsll.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[OP1]], <vscale x 1 x i16> [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)1473// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]1474//1475vuint16mf4_t test_vsll_vv_u16mf4_m(vbool64_t mask, vuint16mf4_t op1, vuint16mf4_t shift, size_t vl) {1476 return __riscv_vsll_vv_u16mf4_m(mask, op1, shift, vl);1477}1478 1479// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vsll_vx_u16mf4_m1480// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1481// CHECK-RV64-NEXT: entry:1482// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vsll.mask.nxv1i16.i64.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)1483// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]1484//1485vuint16mf4_t test_vsll_vx_u16mf4_m(vbool64_t mask, vuint16mf4_t op1, size_t shift, size_t vl) {1486 return __riscv_vsll_vx_u16mf4_m(mask, op1, shift, vl);1487}1488 1489// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vsll_vv_u16mf2_m1490// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1491// CHECK-RV64-NEXT: entry:1492// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vsll.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> [[OP1]], <vscale x 2 x i16> [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)1493// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]1494//1495vuint16mf2_t test_vsll_vv_u16mf2_m(vbool32_t mask, vuint16mf2_t op1, vuint16mf2_t shift, size_t vl) {1496 return __riscv_vsll_vv_u16mf2_m(mask, op1, shift, vl);1497}1498 1499// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vsll_vx_u16mf2_m1500// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1501// CHECK-RV64-NEXT: entry:1502// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vsll.mask.nxv2i16.i64.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)1503// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]1504//1505vuint16mf2_t test_vsll_vx_u16mf2_m(vbool32_t mask, vuint16mf2_t op1, size_t shift, size_t vl) {1506 return __riscv_vsll_vx_u16mf2_m(mask, op1, shift, vl);1507}1508 1509// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vsll_vv_u16m1_m1510// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1511// CHECK-RV64-NEXT: entry:1512// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vsll.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> [[OP1]], <vscale x 4 x i16> [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)1513// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]1514//1515vuint16m1_t test_vsll_vv_u16m1_m(vbool16_t mask, vuint16m1_t op1, vuint16m1_t shift, size_t vl) {1516 return __riscv_vsll_vv_u16m1_m(mask, op1, shift, vl);1517}1518 1519// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vsll_vx_u16m1_m1520// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1521// CHECK-RV64-NEXT: entry:1522// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vsll.mask.nxv4i16.i64.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)1523// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]1524//1525vuint16m1_t test_vsll_vx_u16m1_m(vbool16_t mask, vuint16m1_t op1, size_t shift, size_t vl) {1526 return __riscv_vsll_vx_u16m1_m(mask, op1, shift, vl);1527}1528 1529// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vsll_vv_u16m2_m1530// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1531// CHECK-RV64-NEXT: entry:1532// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vsll.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> [[OP1]], <vscale x 8 x i16> [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)1533// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]1534//1535vuint16m2_t test_vsll_vv_u16m2_m(vbool8_t mask, vuint16m2_t op1, vuint16m2_t shift, size_t vl) {1536 return __riscv_vsll_vv_u16m2_m(mask, op1, shift, vl);1537}1538 1539// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vsll_vx_u16m2_m1540// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1541// CHECK-RV64-NEXT: entry:1542// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vsll.mask.nxv8i16.i64.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)1543// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]1544//1545vuint16m2_t test_vsll_vx_u16m2_m(vbool8_t mask, vuint16m2_t op1, size_t shift, size_t vl) {1546 return __riscv_vsll_vx_u16m2_m(mask, op1, shift, vl);1547}1548 1549// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vsll_vv_u16m4_m1550// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1551// CHECK-RV64-NEXT: entry:1552// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vsll.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> [[OP1]], <vscale x 16 x i16> [[SHIFT]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3)1553// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]1554//1555vuint16m4_t test_vsll_vv_u16m4_m(vbool4_t mask, vuint16m4_t op1, vuint16m4_t shift, size_t vl) {1556 return __riscv_vsll_vv_u16m4_m(mask, op1, shift, vl);1557}1558 1559// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vsll_vx_u16m4_m1560// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1561// CHECK-RV64-NEXT: entry:1562// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vsll.mask.nxv16i16.i64.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3)1563// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]1564//1565vuint16m4_t test_vsll_vx_u16m4_m(vbool4_t mask, vuint16m4_t op1, size_t shift, size_t vl) {1566 return __riscv_vsll_vx_u16m4_m(mask, op1, shift, vl);1567}1568 1569// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vsll_vv_u16m8_m1570// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1571// CHECK-RV64-NEXT: entry:1572// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vsll.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> [[OP1]], <vscale x 32 x i16> [[SHIFT]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3)1573// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]1574//1575vuint16m8_t test_vsll_vv_u16m8_m(vbool2_t mask, vuint16m8_t op1, vuint16m8_t shift, size_t vl) {1576 return __riscv_vsll_vv_u16m8_m(mask, op1, shift, vl);1577}1578 1579// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vsll_vx_u16m8_m1580// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1581// CHECK-RV64-NEXT: entry:1582// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vsll.mask.nxv32i16.i64.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3)1583// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]1584//1585vuint16m8_t test_vsll_vx_u16m8_m(vbool2_t mask, vuint16m8_t op1, size_t shift, size_t vl) {1586 return __riscv_vsll_vx_u16m8_m(mask, op1, shift, vl);1587}1588 1589// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vsll_vv_u32mf2_m1590// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1591// CHECK-RV64-NEXT: entry:1592// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vsll.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[OP1]], <vscale x 1 x i32> [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)1593// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]1594//1595vuint32mf2_t test_vsll_vv_u32mf2_m(vbool64_t mask, vuint32mf2_t op1, vuint32mf2_t shift, size_t vl) {1596 return __riscv_vsll_vv_u32mf2_m(mask, op1, shift, vl);1597}1598 1599// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vsll_vx_u32mf2_m1600// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1601// CHECK-RV64-NEXT: entry:1602// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vsll.mask.nxv1i32.i64.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[OP1]], i64 [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)1603// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]1604//1605vuint32mf2_t test_vsll_vx_u32mf2_m(vbool64_t mask, vuint32mf2_t op1, size_t shift, size_t vl) {1606 return __riscv_vsll_vx_u32mf2_m(mask, op1, shift, vl);1607}1608 1609// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vsll_vv_u32m1_m1610// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1611// CHECK-RV64-NEXT: entry:1612// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vsll.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[OP1]], <vscale x 2 x i32> [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)1613// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]1614//1615vuint32m1_t test_vsll_vv_u32m1_m(vbool32_t mask, vuint32m1_t op1, vuint32m1_t shift, size_t vl) {1616 return __riscv_vsll_vv_u32m1_m(mask, op1, shift, vl);1617}1618 1619// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vsll_vx_u32m1_m1620// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1621// CHECK-RV64-NEXT: entry:1622// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vsll.mask.nxv2i32.i64.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[OP1]], i64 [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)1623// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]1624//1625vuint32m1_t test_vsll_vx_u32m1_m(vbool32_t mask, vuint32m1_t op1, size_t shift, size_t vl) {1626 return __riscv_vsll_vx_u32m1_m(mask, op1, shift, vl);1627}1628 1629// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vsll_vv_u32m2_m1630// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1631// CHECK-RV64-NEXT: entry:1632// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vsll.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> [[OP1]], <vscale x 4 x i32> [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)1633// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]1634//1635vuint32m2_t test_vsll_vv_u32m2_m(vbool16_t mask, vuint32m2_t op1, vuint32m2_t shift, size_t vl) {1636 return __riscv_vsll_vv_u32m2_m(mask, op1, shift, vl);1637}1638 1639// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vsll_vx_u32m2_m1640// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1641// CHECK-RV64-NEXT: entry:1642// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vsll.mask.nxv4i32.i64.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> [[OP1]], i64 [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)1643// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]1644//1645vuint32m2_t test_vsll_vx_u32m2_m(vbool16_t mask, vuint32m2_t op1, size_t shift, size_t vl) {1646 return __riscv_vsll_vx_u32m2_m(mask, op1, shift, vl);1647}1648 1649// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vsll_vv_u32m4_m1650// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1651// CHECK-RV64-NEXT: entry:1652// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vsll.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> [[OP1]], <vscale x 8 x i32> [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)1653// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]1654//1655vuint32m4_t test_vsll_vv_u32m4_m(vbool8_t mask, vuint32m4_t op1, vuint32m4_t shift, size_t vl) {1656 return __riscv_vsll_vv_u32m4_m(mask, op1, shift, vl);1657}1658 1659// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vsll_vx_u32m4_m1660// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1661// CHECK-RV64-NEXT: entry:1662// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vsll.mask.nxv8i32.i64.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> [[OP1]], i64 [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)1663// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]1664//1665vuint32m4_t test_vsll_vx_u32m4_m(vbool8_t mask, vuint32m4_t op1, size_t shift, size_t vl) {1666 return __riscv_vsll_vx_u32m4_m(mask, op1, shift, vl);1667}1668 1669// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vsll_vv_u32m8_m1670// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1671// CHECK-RV64-NEXT: entry:1672// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vsll.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> [[OP1]], <vscale x 16 x i32> [[SHIFT]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3)1673// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]1674//1675vuint32m8_t test_vsll_vv_u32m8_m(vbool4_t mask, vuint32m8_t op1, vuint32m8_t shift, size_t vl) {1676 return __riscv_vsll_vv_u32m8_m(mask, op1, shift, vl);1677}1678 1679// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vsll_vx_u32m8_m1680// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1681// CHECK-RV64-NEXT: entry:1682// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vsll.mask.nxv16i32.i64.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> [[OP1]], i64 [[SHIFT]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3)1683// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]1684//1685vuint32m8_t test_vsll_vx_u32m8_m(vbool4_t mask, vuint32m8_t op1, size_t shift, size_t vl) {1686 return __riscv_vsll_vx_u32m8_m(mask, op1, shift, vl);1687}1688 1689// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vsll_vv_u64m1_m1690// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1691// CHECK-RV64-NEXT: entry:1692// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vsll.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> [[OP1]], <vscale x 1 x i64> [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)1693// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]1694//1695vuint64m1_t test_vsll_vv_u64m1_m(vbool64_t mask, vuint64m1_t op1, vuint64m1_t shift, size_t vl) {1696 return __riscv_vsll_vv_u64m1_m(mask, op1, shift, vl);1697}1698 1699// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vsll_vx_u64m1_m1700// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1701// CHECK-RV64-NEXT: entry:1702// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vsll.mask.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> [[OP1]], i64 [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)1703// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]1704//1705vuint64m1_t test_vsll_vx_u64m1_m(vbool64_t mask, vuint64m1_t op1, size_t shift, size_t vl) {1706 return __riscv_vsll_vx_u64m1_m(mask, op1, shift, vl);1707}1708 1709// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vsll_vv_u64m2_m1710// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1711// CHECK-RV64-NEXT: entry:1712// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vsll.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> [[OP1]], <vscale x 2 x i64> [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)1713// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]1714//1715vuint64m2_t test_vsll_vv_u64m2_m(vbool32_t mask, vuint64m2_t op1, vuint64m2_t shift, size_t vl) {1716 return __riscv_vsll_vv_u64m2_m(mask, op1, shift, vl);1717}1718 1719// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vsll_vx_u64m2_m1720// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1721// CHECK-RV64-NEXT: entry:1722// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vsll.mask.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> [[OP1]], i64 [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)1723// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]1724//1725vuint64m2_t test_vsll_vx_u64m2_m(vbool32_t mask, vuint64m2_t op1, size_t shift, size_t vl) {1726 return __riscv_vsll_vx_u64m2_m(mask, op1, shift, vl);1727}1728 1729// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vsll_vv_u64m4_m1730// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1731// CHECK-RV64-NEXT: entry:1732// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vsll.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> [[OP1]], <vscale x 4 x i64> [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)1733// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]1734//1735vuint64m4_t test_vsll_vv_u64m4_m(vbool16_t mask, vuint64m4_t op1, vuint64m4_t shift, size_t vl) {1736 return __riscv_vsll_vv_u64m4_m(mask, op1, shift, vl);1737}1738 1739// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vsll_vx_u64m4_m1740// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1741// CHECK-RV64-NEXT: entry:1742// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vsll.mask.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> [[OP1]], i64 [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)1743// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]1744//1745vuint64m4_t test_vsll_vx_u64m4_m(vbool16_t mask, vuint64m4_t op1, size_t shift, size_t vl) {1746 return __riscv_vsll_vx_u64m4_m(mask, op1, shift, vl);1747}1748 1749// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vsll_vv_u64m8_m1750// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1751// CHECK-RV64-NEXT: entry:1752// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vsll.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> [[OP1]], <vscale x 8 x i64> [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)1753// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]1754//1755vuint64m8_t test_vsll_vv_u64m8_m(vbool8_t mask, vuint64m8_t op1, vuint64m8_t shift, size_t vl) {1756 return __riscv_vsll_vv_u64m8_m(mask, op1, shift, vl);1757}1758 1759// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vsll_vx_u64m8_m1760// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1761// CHECK-RV64-NEXT: entry:1762// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vsll.mask.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> [[OP1]], i64 [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)1763// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]1764//1765vuint64m8_t test_vsll_vx_u64m8_m(vbool8_t mask, vuint64m8_t op1, size_t shift, size_t vl) {1766 return __riscv_vsll_vx_u64m8_m(mask, op1, shift, vl);1767}1768 1769