1209 lines · c
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 22// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone \4// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \5// RUN: FileCheck --check-prefix=CHECK-RV64 %s6 7#include <riscv_vector.h>8 9// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vwaddu_vv_u16mf410// CHECK-RV64-SAME: (<vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {11// CHECK-RV64-NEXT: entry:12// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> [[OP1]], <vscale x 1 x i8> [[OP2]], i64 [[VL]])13// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]14//15vuint16mf4_t test_vwaddu_vv_u16mf4(vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) {16 return __riscv_vwaddu_vv_u16mf4(op1, op2, vl);17}18 19// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vwaddu_vx_u16mf420// CHECK-RV64-SAME: (<vscale x 1 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {21// CHECK-RV64-NEXT: entry:22// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])23// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]24//25vuint16mf4_t test_vwaddu_vx_u16mf4(vuint8mf8_t op1, uint8_t op2, size_t vl) {26 return __riscv_vwaddu_vx_u16mf4(op1, op2, vl);27}28 29// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vwaddu_wv_u16mf430// CHECK-RV64-SAME: (<vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {31// CHECK-RV64-NEXT: entry:32// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[OP1]], <vscale x 1 x i8> [[OP2]], i64 [[VL]])33// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]34//35vuint16mf4_t test_vwaddu_wv_u16mf4(vuint16mf4_t op1, vuint8mf8_t op2, size_t vl) {36 return __riscv_vwaddu_wv_u16mf4(op1, op2, vl);37}38 39// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vwaddu_wx_u16mf440// CHECK-RV64-SAME: (<vscale x 1 x i16> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {41// CHECK-RV64-NEXT: entry:42// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[OP1]], i8 [[OP2]], i64 [[VL]])43// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]44//45vuint16mf4_t test_vwaddu_wx_u16mf4(vuint16mf4_t op1, uint8_t op2, size_t vl) {46 return __riscv_vwaddu_wx_u16mf4(op1, op2, vl);47}48 49// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vwaddu_vv_u16mf250// CHECK-RV64-SAME: (<vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {51// CHECK-RV64-NEXT: entry:52// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> [[OP1]], <vscale x 2 x i8> [[OP2]], i64 [[VL]])53// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]54//55vuint16mf2_t test_vwaddu_vv_u16mf2(vuint8mf4_t op1, vuint8mf4_t op2, size_t vl) {56 return __riscv_vwaddu_vv_u16mf2(op1, op2, vl);57}58 59// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vwaddu_vx_u16mf260// CHECK-RV64-SAME: (<vscale x 2 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {61// CHECK-RV64-NEXT: entry:62// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])63// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]64//65vuint16mf2_t test_vwaddu_vx_u16mf2(vuint8mf4_t op1, uint8_t op2, size_t vl) {66 return __riscv_vwaddu_vx_u16mf2(op1, op2, vl);67}68 69// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vwaddu_wv_u16mf270// CHECK-RV64-SAME: (<vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {71// CHECK-RV64-NEXT: entry:72// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> [[OP1]], <vscale x 2 x i8> [[OP2]], i64 [[VL]])73// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]74//75vuint16mf2_t test_vwaddu_wv_u16mf2(vuint16mf2_t op1, vuint8mf4_t op2, size_t vl) {76 return __riscv_vwaddu_wv_u16mf2(op1, op2, vl);77}78 79// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vwaddu_wx_u16mf280// CHECK-RV64-SAME: (<vscale x 2 x i16> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {81// CHECK-RV64-NEXT: entry:82// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> [[OP1]], i8 [[OP2]], i64 [[VL]])83// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]84//85vuint16mf2_t test_vwaddu_wx_u16mf2(vuint16mf2_t op1, uint8_t op2, size_t vl) {86 return __riscv_vwaddu_wx_u16mf2(op1, op2, vl);87}88 89// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vwaddu_vv_u16m190// CHECK-RV64-SAME: (<vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {91// CHECK-RV64-NEXT: entry:92// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> [[OP1]], <vscale x 4 x i8> [[OP2]], i64 [[VL]])93// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]94//95vuint16m1_t test_vwaddu_vv_u16m1(vuint8mf2_t op1, vuint8mf2_t op2, size_t vl) {96 return __riscv_vwaddu_vv_u16m1(op1, op2, vl);97}98 99// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vwaddu_vx_u16m1100// CHECK-RV64-SAME: (<vscale x 4 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {101// CHECK-RV64-NEXT: entry:102// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])103// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]104//105vuint16m1_t test_vwaddu_vx_u16m1(vuint8mf2_t op1, uint8_t op2, size_t vl) {106 return __riscv_vwaddu_vx_u16m1(op1, op2, vl);107}108 109// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vwaddu_wv_u16m1110// CHECK-RV64-SAME: (<vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {111// CHECK-RV64-NEXT: entry:112// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwaddu.w.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> [[OP1]], <vscale x 4 x i8> [[OP2]], i64 [[VL]])113// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]114//115vuint16m1_t test_vwaddu_wv_u16m1(vuint16m1_t op1, vuint8mf2_t op2, size_t vl) {116 return __riscv_vwaddu_wv_u16m1(op1, op2, vl);117}118 119// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vwaddu_wx_u16m1120// CHECK-RV64-SAME: (<vscale x 4 x i16> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {121// CHECK-RV64-NEXT: entry:122// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwaddu.w.nxv4i16.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> [[OP1]], i8 [[OP2]], i64 [[VL]])123// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]124//125vuint16m1_t test_vwaddu_wx_u16m1(vuint16m1_t op1, uint8_t op2, size_t vl) {126 return __riscv_vwaddu_wx_u16m1(op1, op2, vl);127}128 129// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vwaddu_vv_u16m2130// CHECK-RV64-SAME: (<vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {131// CHECK-RV64-NEXT: entry:132// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwaddu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> [[OP1]], <vscale x 8 x i8> [[OP2]], i64 [[VL]])133// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]134//135vuint16m2_t test_vwaddu_vv_u16m2(vuint8m1_t op1, vuint8m1_t op2, size_t vl) {136 return __riscv_vwaddu_vv_u16m2(op1, op2, vl);137}138 139// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vwaddu_vx_u16m2140// CHECK-RV64-SAME: (<vscale x 8 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {141// CHECK-RV64-NEXT: entry:142// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])143// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]144//145vuint16m2_t test_vwaddu_vx_u16m2(vuint8m1_t op1, uint8_t op2, size_t vl) {146 return __riscv_vwaddu_vx_u16m2(op1, op2, vl);147}148 149// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vwaddu_wv_u16m2150// CHECK-RV64-SAME: (<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {151// CHECK-RV64-NEXT: entry:152// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwaddu.w.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> [[OP1]], <vscale x 8 x i8> [[OP2]], i64 [[VL]])153// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]154//155vuint16m2_t test_vwaddu_wv_u16m2(vuint16m2_t op1, vuint8m1_t op2, size_t vl) {156 return __riscv_vwaddu_wv_u16m2(op1, op2, vl);157}158 159// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vwaddu_wx_u16m2160// CHECK-RV64-SAME: (<vscale x 8 x i16> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {161// CHECK-RV64-NEXT: entry:162// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwaddu.w.nxv8i16.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> [[OP1]], i8 [[OP2]], i64 [[VL]])163// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]164//165vuint16m2_t test_vwaddu_wx_u16m2(vuint16m2_t op1, uint8_t op2, size_t vl) {166 return __riscv_vwaddu_wx_u16m2(op1, op2, vl);167}168 169// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vwaddu_vv_u16m4170// CHECK-RV64-SAME: (<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {171// CHECK-RV64-NEXT: entry:172// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwaddu.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> [[OP1]], <vscale x 16 x i8> [[OP2]], i64 [[VL]])173// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]174//175vuint16m4_t test_vwaddu_vv_u16m4(vuint8m2_t op1, vuint8m2_t op2, size_t vl) {176 return __riscv_vwaddu_vv_u16m4(op1, op2, vl);177}178 179// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vwaddu_vx_u16m4180// CHECK-RV64-SAME: (<vscale x 16 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {181// CHECK-RV64-NEXT: entry:182// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])183// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]184//185vuint16m4_t test_vwaddu_vx_u16m4(vuint8m2_t op1, uint8_t op2, size_t vl) {186 return __riscv_vwaddu_vx_u16m4(op1, op2, vl);187}188 189// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vwaddu_wv_u16m4190// CHECK-RV64-SAME: (<vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {191// CHECK-RV64-NEXT: entry:192// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwaddu.w.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> [[OP1]], <vscale x 16 x i8> [[OP2]], i64 [[VL]])193// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]194//195vuint16m4_t test_vwaddu_wv_u16m4(vuint16m4_t op1, vuint8m2_t op2, size_t vl) {196 return __riscv_vwaddu_wv_u16m4(op1, op2, vl);197}198 199// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vwaddu_wx_u16m4200// CHECK-RV64-SAME: (<vscale x 16 x i16> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {201// CHECK-RV64-NEXT: entry:202// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwaddu.w.nxv16i16.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> [[OP1]], i8 [[OP2]], i64 [[VL]])203// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]204//205vuint16m4_t test_vwaddu_wx_u16m4(vuint16m4_t op1, uint8_t op2, size_t vl) {206 return __riscv_vwaddu_wx_u16m4(op1, op2, vl);207}208 209// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vwaddu_vv_u16m8210// CHECK-RV64-SAME: (<vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {211// CHECK-RV64-NEXT: entry:212// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwaddu.nxv32i16.nxv32i8.nxv32i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> [[OP1]], <vscale x 32 x i8> [[OP2]], i64 [[VL]])213// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]214//215vuint16m8_t test_vwaddu_vv_u16m8(vuint8m4_t op1, vuint8m4_t op2, size_t vl) {216 return __riscv_vwaddu_vv_u16m8(op1, op2, vl);217}218 219// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vwaddu_vx_u16m8220// CHECK-RV64-SAME: (<vscale x 32 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {221// CHECK-RV64-NEXT: entry:222// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])223// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]224//225vuint16m8_t test_vwaddu_vx_u16m8(vuint8m4_t op1, uint8_t op2, size_t vl) {226 return __riscv_vwaddu_vx_u16m8(op1, op2, vl);227}228 229// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vwaddu_wv_u16m8230// CHECK-RV64-SAME: (<vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {231// CHECK-RV64-NEXT: entry:232// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwaddu.w.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> [[OP1]], <vscale x 32 x i8> [[OP2]], i64 [[VL]])233// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]234//235vuint16m8_t test_vwaddu_wv_u16m8(vuint16m8_t op1, vuint8m4_t op2, size_t vl) {236 return __riscv_vwaddu_wv_u16m8(op1, op2, vl);237}238 239// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vwaddu_wx_u16m8240// CHECK-RV64-SAME: (<vscale x 32 x i16> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {241// CHECK-RV64-NEXT: entry:242// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwaddu.w.nxv32i16.i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> [[OP1]], i8 [[OP2]], i64 [[VL]])243// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]244//245vuint16m8_t test_vwaddu_wx_u16m8(vuint16m8_t op1, uint8_t op2, size_t vl) {246 return __riscv_vwaddu_wx_u16m8(op1, op2, vl);247}248 249// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vwaddu_vv_u32mf2250// CHECK-RV64-SAME: (<vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {251// CHECK-RV64-NEXT: entry:252// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwaddu.nxv1i32.nxv1i16.nxv1i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> [[OP1]], <vscale x 1 x i16> [[OP2]], i64 [[VL]])253// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]254//255vuint32mf2_t test_vwaddu_vv_u32mf2(vuint16mf4_t op1, vuint16mf4_t op2, size_t vl) {256 return __riscv_vwaddu_vv_u32mf2(op1, op2, vl);257}258 259// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vwaddu_vx_u32mf2260// CHECK-RV64-SAME: (<vscale x 1 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {261// CHECK-RV64-NEXT: entry:262// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])263// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]264//265vuint32mf2_t test_vwaddu_vx_u32mf2(vuint16mf4_t op1, uint16_t op2, size_t vl) {266 return __riscv_vwaddu_vx_u32mf2(op1, op2, vl);267}268 269// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vwaddu_wv_u32mf2270// CHECK-RV64-SAME: (<vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {271// CHECK-RV64-NEXT: entry:272// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwaddu.w.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[OP1]], <vscale x 1 x i16> [[OP2]], i64 [[VL]])273// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]274//275vuint32mf2_t test_vwaddu_wv_u32mf2(vuint32mf2_t op1, vuint16mf4_t op2, size_t vl) {276 return __riscv_vwaddu_wv_u32mf2(op1, op2, vl);277}278 279// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vwaddu_wx_u32mf2280// CHECK-RV64-SAME: (<vscale x 1 x i32> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {281// CHECK-RV64-NEXT: entry:282// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwaddu.w.nxv1i32.i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[OP1]], i16 [[OP2]], i64 [[VL]])283// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]284//285vuint32mf2_t test_vwaddu_wx_u32mf2(vuint32mf2_t op1, uint16_t op2, size_t vl) {286 return __riscv_vwaddu_wx_u32mf2(op1, op2, vl);287}288 289// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vwaddu_vv_u32m1290// CHECK-RV64-SAME: (<vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {291// CHECK-RV64-NEXT: entry:292// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwaddu.nxv2i32.nxv2i16.nxv2i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> [[OP1]], <vscale x 2 x i16> [[OP2]], i64 [[VL]])293// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]294//295vuint32m1_t test_vwaddu_vv_u32m1(vuint16mf2_t op1, vuint16mf2_t op2, size_t vl) {296 return __riscv_vwaddu_vv_u32m1(op1, op2, vl);297}298 299// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vwaddu_vx_u32m1300// CHECK-RV64-SAME: (<vscale x 2 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {301// CHECK-RV64-NEXT: entry:302// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])303// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]304//305vuint32m1_t test_vwaddu_vx_u32m1(vuint16mf2_t op1, uint16_t op2, size_t vl) {306 return __riscv_vwaddu_vx_u32m1(op1, op2, vl);307}308 309// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vwaddu_wv_u32m1310// CHECK-RV64-SAME: (<vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {311// CHECK-RV64-NEXT: entry:312// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwaddu.w.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[OP1]], <vscale x 2 x i16> [[OP2]], i64 [[VL]])313// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]314//315vuint32m1_t test_vwaddu_wv_u32m1(vuint32m1_t op1, vuint16mf2_t op2, size_t vl) {316 return __riscv_vwaddu_wv_u32m1(op1, op2, vl);317}318 319// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vwaddu_wx_u32m1320// CHECK-RV64-SAME: (<vscale x 2 x i32> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {321// CHECK-RV64-NEXT: entry:322// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwaddu.w.nxv2i32.i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[OP1]], i16 [[OP2]], i64 [[VL]])323// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]324//325vuint32m1_t test_vwaddu_wx_u32m1(vuint32m1_t op1, uint16_t op2, size_t vl) {326 return __riscv_vwaddu_wx_u32m1(op1, op2, vl);327}328 329// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vwaddu_vv_u32m2330// CHECK-RV64-SAME: (<vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {331// CHECK-RV64-NEXT: entry:332// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwaddu.nxv4i32.nxv4i16.nxv4i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> [[OP1]], <vscale x 4 x i16> [[OP2]], i64 [[VL]])333// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]334//335vuint32m2_t test_vwaddu_vv_u32m2(vuint16m1_t op1, vuint16m1_t op2, size_t vl) {336 return __riscv_vwaddu_vv_u32m2(op1, op2, vl);337}338 339// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vwaddu_vx_u32m2340// CHECK-RV64-SAME: (<vscale x 4 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {341// CHECK-RV64-NEXT: entry:342// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])343// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]344//345vuint32m2_t test_vwaddu_vx_u32m2(vuint16m1_t op1, uint16_t op2, size_t vl) {346 return __riscv_vwaddu_vx_u32m2(op1, op2, vl);347}348 349// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vwaddu_wv_u32m2350// CHECK-RV64-SAME: (<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {351// CHECK-RV64-NEXT: entry:352// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwaddu.w.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> [[OP1]], <vscale x 4 x i16> [[OP2]], i64 [[VL]])353// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]354//355vuint32m2_t test_vwaddu_wv_u32m2(vuint32m2_t op1, vuint16m1_t op2, size_t vl) {356 return __riscv_vwaddu_wv_u32m2(op1, op2, vl);357}358 359// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vwaddu_wx_u32m2360// CHECK-RV64-SAME: (<vscale x 4 x i32> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {361// CHECK-RV64-NEXT: entry:362// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwaddu.w.nxv4i32.i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> [[OP1]], i16 [[OP2]], i64 [[VL]])363// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]364//365vuint32m2_t test_vwaddu_wx_u32m2(vuint32m2_t op1, uint16_t op2, size_t vl) {366 return __riscv_vwaddu_wx_u32m2(op1, op2, vl);367}368 369// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vwaddu_vv_u32m4370// CHECK-RV64-SAME: (<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {371// CHECK-RV64-NEXT: entry:372// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwaddu.nxv8i32.nxv8i16.nxv8i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> [[OP1]], <vscale x 8 x i16> [[OP2]], i64 [[VL]])373// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]374//375vuint32m4_t test_vwaddu_vv_u32m4(vuint16m2_t op1, vuint16m2_t op2, size_t vl) {376 return __riscv_vwaddu_vv_u32m4(op1, op2, vl);377}378 379// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vwaddu_vx_u32m4380// CHECK-RV64-SAME: (<vscale x 8 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {381// CHECK-RV64-NEXT: entry:382// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwaddu.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])383// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]384//385vuint32m4_t test_vwaddu_vx_u32m4(vuint16m2_t op1, uint16_t op2, size_t vl) {386 return __riscv_vwaddu_vx_u32m4(op1, op2, vl);387}388 389// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vwaddu_wv_u32m4390// CHECK-RV64-SAME: (<vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {391// CHECK-RV64-NEXT: entry:392// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwaddu.w.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> [[OP1]], <vscale x 8 x i16> [[OP2]], i64 [[VL]])393// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]394//395vuint32m4_t test_vwaddu_wv_u32m4(vuint32m4_t op1, vuint16m2_t op2, size_t vl) {396 return __riscv_vwaddu_wv_u32m4(op1, op2, vl);397}398 399// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vwaddu_wx_u32m4400// CHECK-RV64-SAME: (<vscale x 8 x i32> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {401// CHECK-RV64-NEXT: entry:402// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwaddu.w.nxv8i32.i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> [[OP1]], i16 [[OP2]], i64 [[VL]])403// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]404//405vuint32m4_t test_vwaddu_wx_u32m4(vuint32m4_t op1, uint16_t op2, size_t vl) {406 return __riscv_vwaddu_wx_u32m4(op1, op2, vl);407}408 409// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vwaddu_vv_u32m8410// CHECK-RV64-SAME: (<vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {411// CHECK-RV64-NEXT: entry:412// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwaddu.nxv16i32.nxv16i16.nxv16i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> [[OP1]], <vscale x 16 x i16> [[OP2]], i64 [[VL]])413// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]414//415vuint32m8_t test_vwaddu_vv_u32m8(vuint16m4_t op1, vuint16m4_t op2, size_t vl) {416 return __riscv_vwaddu_vv_u32m8(op1, op2, vl);417}418 419// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vwaddu_vx_u32m8420// CHECK-RV64-SAME: (<vscale x 16 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {421// CHECK-RV64-NEXT: entry:422// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwaddu.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])423// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]424//425vuint32m8_t test_vwaddu_vx_u32m8(vuint16m4_t op1, uint16_t op2, size_t vl) {426 return __riscv_vwaddu_vx_u32m8(op1, op2, vl);427}428 429// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vwaddu_wv_u32m8430// CHECK-RV64-SAME: (<vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {431// CHECK-RV64-NEXT: entry:432// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwaddu.w.nxv16i32.nxv16i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> [[OP1]], <vscale x 16 x i16> [[OP2]], i64 [[VL]])433// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]434//435vuint32m8_t test_vwaddu_wv_u32m8(vuint32m8_t op1, vuint16m4_t op2, size_t vl) {436 return __riscv_vwaddu_wv_u32m8(op1, op2, vl);437}438 439// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vwaddu_wx_u32m8440// CHECK-RV64-SAME: (<vscale x 16 x i32> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {441// CHECK-RV64-NEXT: entry:442// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwaddu.w.nxv16i32.i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> [[OP1]], i16 [[OP2]], i64 [[VL]])443// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]444//445vuint32m8_t test_vwaddu_wx_u32m8(vuint32m8_t op1, uint16_t op2, size_t vl) {446 return __riscv_vwaddu_wx_u32m8(op1, op2, vl);447}448 449// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vwaddu_vv_u64m1450// CHECK-RV64-SAME: (<vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {451// CHECK-RV64-NEXT: entry:452// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwaddu.nxv1i64.nxv1i32.nxv1i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> [[OP1]], <vscale x 1 x i32> [[OP2]], i64 [[VL]])453// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]454//455vuint64m1_t test_vwaddu_vv_u64m1(vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {456 return __riscv_vwaddu_vv_u64m1(op1, op2, vl);457}458 459// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vwaddu_vx_u64m1460// CHECK-RV64-SAME: (<vscale x 1 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {461// CHECK-RV64-NEXT: entry:462// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwaddu.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> [[OP1]], i32 [[OP2]], i64 [[VL]])463// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]464//465vuint64m1_t test_vwaddu_vx_u64m1(vuint32mf2_t op1, uint32_t op2, size_t vl) {466 return __riscv_vwaddu_vx_u64m1(op1, op2, vl);467}468 469// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vwaddu_wv_u64m1470// CHECK-RV64-SAME: (<vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {471// CHECK-RV64-NEXT: entry:472// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwaddu.w.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> [[OP1]], <vscale x 1 x i32> [[OP2]], i64 [[VL]])473// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]474//475vuint64m1_t test_vwaddu_wv_u64m1(vuint64m1_t op1, vuint32mf2_t op2, size_t vl) {476 return __riscv_vwaddu_wv_u64m1(op1, op2, vl);477}478 479// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vwaddu_wx_u64m1480// CHECK-RV64-SAME: (<vscale x 1 x i64> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {481// CHECK-RV64-NEXT: entry:482// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwaddu.w.nxv1i64.i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> [[OP1]], i32 [[OP2]], i64 [[VL]])483// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]484//485vuint64m1_t test_vwaddu_wx_u64m1(vuint64m1_t op1, uint32_t op2, size_t vl) {486 return __riscv_vwaddu_wx_u64m1(op1, op2, vl);487}488 489// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vwaddu_vv_u64m2490// CHECK-RV64-SAME: (<vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {491// CHECK-RV64-NEXT: entry:492// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwaddu.nxv2i64.nxv2i32.nxv2i32.i64(<vscale x 2 x i64> poison, <vscale x 2 x i32> [[OP1]], <vscale x 2 x i32> [[OP2]], i64 [[VL]])493// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]494//495vuint64m2_t test_vwaddu_vv_u64m2(vuint32m1_t op1, vuint32m1_t op2, size_t vl) {496 return __riscv_vwaddu_vv_u64m2(op1, op2, vl);497}498 499// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vwaddu_vx_u64m2500// CHECK-RV64-SAME: (<vscale x 2 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {501// CHECK-RV64-NEXT: entry:502// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwaddu.nxv2i64.nxv2i32.i32.i64(<vscale x 2 x i64> poison, <vscale x 2 x i32> [[OP1]], i32 [[OP2]], i64 [[VL]])503// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]504//505vuint64m2_t test_vwaddu_vx_u64m2(vuint32m1_t op1, uint32_t op2, size_t vl) {506 return __riscv_vwaddu_vx_u64m2(op1, op2, vl);507}508 509// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vwaddu_wv_u64m2510// CHECK-RV64-SAME: (<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {511// CHECK-RV64-NEXT: entry:512// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwaddu.w.nxv2i64.nxv2i32.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> [[OP1]], <vscale x 2 x i32> [[OP2]], i64 [[VL]])513// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]514//515vuint64m2_t test_vwaddu_wv_u64m2(vuint64m2_t op1, vuint32m1_t op2, size_t vl) {516 return __riscv_vwaddu_wv_u64m2(op1, op2, vl);517}518 519// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vwaddu_wx_u64m2520// CHECK-RV64-SAME: (<vscale x 2 x i64> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {521// CHECK-RV64-NEXT: entry:522// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwaddu.w.nxv2i64.i32.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> [[OP1]], i32 [[OP2]], i64 [[VL]])523// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]524//525vuint64m2_t test_vwaddu_wx_u64m2(vuint64m2_t op1, uint32_t op2, size_t vl) {526 return __riscv_vwaddu_wx_u64m2(op1, op2, vl);527}528 529// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vwaddu_vv_u64m4530// CHECK-RV64-SAME: (<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {531// CHECK-RV64-NEXT: entry:532// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwaddu.nxv4i64.nxv4i32.nxv4i32.i64(<vscale x 4 x i64> poison, <vscale x 4 x i32> [[OP1]], <vscale x 4 x i32> [[OP2]], i64 [[VL]])533// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]534//535vuint64m4_t test_vwaddu_vv_u64m4(vuint32m2_t op1, vuint32m2_t op2, size_t vl) {536 return __riscv_vwaddu_vv_u64m4(op1, op2, vl);537}538 539// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vwaddu_vx_u64m4540// CHECK-RV64-SAME: (<vscale x 4 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {541// CHECK-RV64-NEXT: entry:542// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwaddu.nxv4i64.nxv4i32.i32.i64(<vscale x 4 x i64> poison, <vscale x 4 x i32> [[OP1]], i32 [[OP2]], i64 [[VL]])543// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]544//545vuint64m4_t test_vwaddu_vx_u64m4(vuint32m2_t op1, uint32_t op2, size_t vl) {546 return __riscv_vwaddu_vx_u64m4(op1, op2, vl);547}548 549// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vwaddu_wv_u64m4550// CHECK-RV64-SAME: (<vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {551// CHECK-RV64-NEXT: entry:552// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwaddu.w.nxv4i64.nxv4i32.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> [[OP1]], <vscale x 4 x i32> [[OP2]], i64 [[VL]])553// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]554//555vuint64m4_t test_vwaddu_wv_u64m4(vuint64m4_t op1, vuint32m2_t op2, size_t vl) {556 return __riscv_vwaddu_wv_u64m4(op1, op2, vl);557}558 559// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vwaddu_wx_u64m4560// CHECK-RV64-SAME: (<vscale x 4 x i64> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {561// CHECK-RV64-NEXT: entry:562// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwaddu.w.nxv4i64.i32.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> [[OP1]], i32 [[OP2]], i64 [[VL]])563// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]564//565vuint64m4_t test_vwaddu_wx_u64m4(vuint64m4_t op1, uint32_t op2, size_t vl) {566 return __riscv_vwaddu_wx_u64m4(op1, op2, vl);567}568 569// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vwaddu_vv_u64m8570// CHECK-RV64-SAME: (<vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {571// CHECK-RV64-NEXT: entry:572// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwaddu.nxv8i64.nxv8i32.nxv8i32.i64(<vscale x 8 x i64> poison, <vscale x 8 x i32> [[OP1]], <vscale x 8 x i32> [[OP2]], i64 [[VL]])573// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]574//575vuint64m8_t test_vwaddu_vv_u64m8(vuint32m4_t op1, vuint32m4_t op2, size_t vl) {576 return __riscv_vwaddu_vv_u64m8(op1, op2, vl);577}578 579// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vwaddu_vx_u64m8580// CHECK-RV64-SAME: (<vscale x 8 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {581// CHECK-RV64-NEXT: entry:582// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwaddu.nxv8i64.nxv8i32.i32.i64(<vscale x 8 x i64> poison, <vscale x 8 x i32> [[OP1]], i32 [[OP2]], i64 [[VL]])583// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]584//585vuint64m8_t test_vwaddu_vx_u64m8(vuint32m4_t op1, uint32_t op2, size_t vl) {586 return __riscv_vwaddu_vx_u64m8(op1, op2, vl);587}588 589// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vwaddu_wv_u64m8590// CHECK-RV64-SAME: (<vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {591// CHECK-RV64-NEXT: entry:592// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwaddu.w.nxv8i64.nxv8i32.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> [[OP1]], <vscale x 8 x i32> [[OP2]], i64 [[VL]])593// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]594//595vuint64m8_t test_vwaddu_wv_u64m8(vuint64m8_t op1, vuint32m4_t op2, size_t vl) {596 return __riscv_vwaddu_wv_u64m8(op1, op2, vl);597}598 599// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vwaddu_wx_u64m8600// CHECK-RV64-SAME: (<vscale x 8 x i64> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {601// CHECK-RV64-NEXT: entry:602// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwaddu.w.nxv8i64.i32.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> [[OP1]], i32 [[OP2]], i64 [[VL]])603// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]604//605vuint64m8_t test_vwaddu_wx_u64m8(vuint64m8_t op1, uint32_t op2, size_t vl) {606 return __riscv_vwaddu_wx_u64m8(op1, op2, vl);607}608 609// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vwaddu_vv_u16mf4_m610// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {611// CHECK-RV64-NEXT: entry:612// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwaddu.mask.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> [[OP1]], <vscale x 1 x i8> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)613// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]614//615vuint16mf4_t test_vwaddu_vv_u16mf4_m(vbool64_t mask, vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) {616 return __riscv_vwaddu_vv_u16mf4_m(mask, op1, op2, vl);617}618 619// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vwaddu_vx_u16mf4_m620// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {621// CHECK-RV64-NEXT: entry:622// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwaddu.mask.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> [[OP1]], i8 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)623// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]624//625vuint16mf4_t test_vwaddu_vx_u16mf4_m(vbool64_t mask, vuint8mf8_t op1, uint8_t op2, size_t vl) {626 return __riscv_vwaddu_vx_u16mf4_m(mask, op1, op2, vl);627}628 629// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vwaddu_wv_u16mf4_m630// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {631// CHECK-RV64-NEXT: entry:632// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.mask.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[OP1]], <vscale x 1 x i8> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)633// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]634//635vuint16mf4_t test_vwaddu_wv_u16mf4_m(vbool64_t mask, vuint16mf4_t op1, vuint8mf8_t op2, size_t vl) {636 return __riscv_vwaddu_wv_u16mf4_m(mask, op1, op2, vl);637}638 639// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vwaddu_wx_u16mf4_m640// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {641// CHECK-RV64-NEXT: entry:642// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.mask.nxv1i16.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[OP1]], i8 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)643// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]644//645vuint16mf4_t test_vwaddu_wx_u16mf4_m(vbool64_t mask, vuint16mf4_t op1, uint8_t op2, size_t vl) {646 return __riscv_vwaddu_wx_u16mf4_m(mask, op1, op2, vl);647}648 649// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vwaddu_vv_u16mf2_m650// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {651// CHECK-RV64-NEXT: entry:652// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwaddu.mask.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> [[OP1]], <vscale x 2 x i8> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)653// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]654//655vuint16mf2_t test_vwaddu_vv_u16mf2_m(vbool32_t mask, vuint8mf4_t op1, vuint8mf4_t op2, size_t vl) {656 return __riscv_vwaddu_vv_u16mf2_m(mask, op1, op2, vl);657}658 659// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vwaddu_vx_u16mf2_m660// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {661// CHECK-RV64-NEXT: entry:662// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwaddu.mask.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> [[OP1]], i8 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)663// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]664//665vuint16mf2_t test_vwaddu_vx_u16mf2_m(vbool32_t mask, vuint8mf4_t op1, uint8_t op2, size_t vl) {666 return __riscv_vwaddu_vx_u16mf2_m(mask, op1, op2, vl);667}668 669// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vwaddu_wv_u16mf2_m670// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {671// CHECK-RV64-NEXT: entry:672// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.mask.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> [[OP1]], <vscale x 2 x i8> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)673// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]674//675vuint16mf2_t test_vwaddu_wv_u16mf2_m(vbool32_t mask, vuint16mf2_t op1, vuint8mf4_t op2, size_t vl) {676 return __riscv_vwaddu_wv_u16mf2_m(mask, op1, op2, vl);677}678 679// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vwaddu_wx_u16mf2_m680// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {681// CHECK-RV64-NEXT: entry:682// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.mask.nxv2i16.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> [[OP1]], i8 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)683// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]684//685vuint16mf2_t test_vwaddu_wx_u16mf2_m(vbool32_t mask, vuint16mf2_t op1, uint8_t op2, size_t vl) {686 return __riscv_vwaddu_wx_u16mf2_m(mask, op1, op2, vl);687}688 689// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vwaddu_vv_u16m1_m690// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {691// CHECK-RV64-NEXT: entry:692// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwaddu.mask.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> [[OP1]], <vscale x 4 x i8> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)693// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]694//695vuint16m1_t test_vwaddu_vv_u16m1_m(vbool16_t mask, vuint8mf2_t op1, vuint8mf2_t op2, size_t vl) {696 return __riscv_vwaddu_vv_u16m1_m(mask, op1, op2, vl);697}698 699// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vwaddu_vx_u16m1_m700// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {701// CHECK-RV64-NEXT: entry:702// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwaddu.mask.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> [[OP1]], i8 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)703// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]704//705vuint16m1_t test_vwaddu_vx_u16m1_m(vbool16_t mask, vuint8mf2_t op1, uint8_t op2, size_t vl) {706 return __riscv_vwaddu_vx_u16m1_m(mask, op1, op2, vl);707}708 709// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vwaddu_wv_u16m1_m710// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {711// CHECK-RV64-NEXT: entry:712// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwaddu.w.mask.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> [[OP1]], <vscale x 4 x i8> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)713// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]714//715vuint16m1_t test_vwaddu_wv_u16m1_m(vbool16_t mask, vuint16m1_t op1, vuint8mf2_t op2, size_t vl) {716 return __riscv_vwaddu_wv_u16m1_m(mask, op1, op2, vl);717}718 719// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vwaddu_wx_u16m1_m720// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {721// CHECK-RV64-NEXT: entry:722// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwaddu.w.mask.nxv4i16.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> [[OP1]], i8 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)723// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]724//725vuint16m1_t test_vwaddu_wx_u16m1_m(vbool16_t mask, vuint16m1_t op1, uint8_t op2, size_t vl) {726 return __riscv_vwaddu_wx_u16m1_m(mask, op1, op2, vl);727}728 729// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vwaddu_vv_u16m2_m730// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {731// CHECK-RV64-NEXT: entry:732// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwaddu.mask.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> [[OP1]], <vscale x 8 x i8> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)733// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]734//735vuint16m2_t test_vwaddu_vv_u16m2_m(vbool8_t mask, vuint8m1_t op1, vuint8m1_t op2, size_t vl) {736 return __riscv_vwaddu_vv_u16m2_m(mask, op1, op2, vl);737}738 739// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vwaddu_vx_u16m2_m740// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {741// CHECK-RV64-NEXT: entry:742// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwaddu.mask.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> [[OP1]], i8 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)743// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]744//745vuint16m2_t test_vwaddu_vx_u16m2_m(vbool8_t mask, vuint8m1_t op1, uint8_t op2, size_t vl) {746 return __riscv_vwaddu_vx_u16m2_m(mask, op1, op2, vl);747}748 749// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vwaddu_wv_u16m2_m750// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {751// CHECK-RV64-NEXT: entry:752// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwaddu.w.mask.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> [[OP1]], <vscale x 8 x i8> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)753// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]754//755vuint16m2_t test_vwaddu_wv_u16m2_m(vbool8_t mask, vuint16m2_t op1, vuint8m1_t op2, size_t vl) {756 return __riscv_vwaddu_wv_u16m2_m(mask, op1, op2, vl);757}758 759// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vwaddu_wx_u16m2_m760// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {761// CHECK-RV64-NEXT: entry:762// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwaddu.w.mask.nxv8i16.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> [[OP1]], i8 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)763// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]764//765vuint16m2_t test_vwaddu_wx_u16m2_m(vbool8_t mask, vuint16m2_t op1, uint8_t op2, size_t vl) {766 return __riscv_vwaddu_wx_u16m2_m(mask, op1, op2, vl);767}768 769// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vwaddu_vv_u16m4_m770// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {771// CHECK-RV64-NEXT: entry:772// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwaddu.mask.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> [[OP1]], <vscale x 16 x i8> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3)773// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]774//775vuint16m4_t test_vwaddu_vv_u16m4_m(vbool4_t mask, vuint8m2_t op1, vuint8m2_t op2, size_t vl) {776 return __riscv_vwaddu_vv_u16m4_m(mask, op1, op2, vl);777}778 779// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vwaddu_vx_u16m4_m780// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {781// CHECK-RV64-NEXT: entry:782// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwaddu.mask.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> [[OP1]], i8 [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3)783// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]784//785vuint16m4_t test_vwaddu_vx_u16m4_m(vbool4_t mask, vuint8m2_t op1, uint8_t op2, size_t vl) {786 return __riscv_vwaddu_vx_u16m4_m(mask, op1, op2, vl);787}788 789// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vwaddu_wv_u16m4_m790// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {791// CHECK-RV64-NEXT: entry:792// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwaddu.w.mask.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> [[OP1]], <vscale x 16 x i8> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3)793// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]794//795vuint16m4_t test_vwaddu_wv_u16m4_m(vbool4_t mask, vuint16m4_t op1, vuint8m2_t op2, size_t vl) {796 return __riscv_vwaddu_wv_u16m4_m(mask, op1, op2, vl);797}798 799// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vwaddu_wx_u16m4_m800// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {801// CHECK-RV64-NEXT: entry:802// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwaddu.w.mask.nxv16i16.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> [[OP1]], i8 [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3)803// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]804//805vuint16m4_t test_vwaddu_wx_u16m4_m(vbool4_t mask, vuint16m4_t op1, uint8_t op2, size_t vl) {806 return __riscv_vwaddu_wx_u16m4_m(mask, op1, op2, vl);807}808 809// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vwaddu_vv_u16m8_m810// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {811// CHECK-RV64-NEXT: entry:812// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwaddu.mask.nxv32i16.nxv32i8.nxv32i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> [[OP1]], <vscale x 32 x i8> [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3)813// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]814//815vuint16m8_t test_vwaddu_vv_u16m8_m(vbool2_t mask, vuint8m4_t op1, vuint8m4_t op2, size_t vl) {816 return __riscv_vwaddu_vv_u16m8_m(mask, op1, op2, vl);817}818 819// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vwaddu_vx_u16m8_m820// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {821// CHECK-RV64-NEXT: entry:822// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwaddu.mask.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> [[OP1]], i8 [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3)823// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]824//825vuint16m8_t test_vwaddu_vx_u16m8_m(vbool2_t mask, vuint8m4_t op1, uint8_t op2, size_t vl) {826 return __riscv_vwaddu_vx_u16m8_m(mask, op1, op2, vl);827}828 829// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vwaddu_wv_u16m8_m830// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {831// CHECK-RV64-NEXT: entry:832// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwaddu.w.mask.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> [[OP1]], <vscale x 32 x i8> [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3)833// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]834//835vuint16m8_t test_vwaddu_wv_u16m8_m(vbool2_t mask, vuint16m8_t op1, vuint8m4_t op2, size_t vl) {836 return __riscv_vwaddu_wv_u16m8_m(mask, op1, op2, vl);837}838 839// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vwaddu_wx_u16m8_m840// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {841// CHECK-RV64-NEXT: entry:842// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwaddu.w.mask.nxv32i16.i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> [[OP1]], i8 [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3)843// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]844//845vuint16m8_t test_vwaddu_wx_u16m8_m(vbool2_t mask, vuint16m8_t op1, uint8_t op2, size_t vl) {846 return __riscv_vwaddu_wx_u16m8_m(mask, op1, op2, vl);847}848 849// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vwaddu_vv_u32mf2_m850// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {851// CHECK-RV64-NEXT: entry:852// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwaddu.mask.nxv1i32.nxv1i16.nxv1i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> [[OP1]], <vscale x 1 x i16> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)853// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]854//855vuint32mf2_t test_vwaddu_vv_u32mf2_m(vbool64_t mask, vuint16mf4_t op1, vuint16mf4_t op2, size_t vl) {856 return __riscv_vwaddu_vv_u32mf2_m(mask, op1, op2, vl);857}858 859// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vwaddu_vx_u32mf2_m860// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {861// CHECK-RV64-NEXT: entry:862// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwaddu.mask.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> [[OP1]], i16 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)863// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]864//865vuint32mf2_t test_vwaddu_vx_u32mf2_m(vbool64_t mask, vuint16mf4_t op1, uint16_t op2, size_t vl) {866 return __riscv_vwaddu_vx_u32mf2_m(mask, op1, op2, vl);867}868 869// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vwaddu_wv_u32mf2_m870// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {871// CHECK-RV64-NEXT: entry:872// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwaddu.w.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[OP1]], <vscale x 1 x i16> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)873// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]874//875vuint32mf2_t test_vwaddu_wv_u32mf2_m(vbool64_t mask, vuint32mf2_t op1, vuint16mf4_t op2, size_t vl) {876 return __riscv_vwaddu_wv_u32mf2_m(mask, op1, op2, vl);877}878 879// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vwaddu_wx_u32mf2_m880// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {881// CHECK-RV64-NEXT: entry:882// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwaddu.w.mask.nxv1i32.i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[OP1]], i16 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)883// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]884//885vuint32mf2_t test_vwaddu_wx_u32mf2_m(vbool64_t mask, vuint32mf2_t op1, uint16_t op2, size_t vl) {886 return __riscv_vwaddu_wx_u32mf2_m(mask, op1, op2, vl);887}888 889// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vwaddu_vv_u32m1_m890// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {891// CHECK-RV64-NEXT: entry:892// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwaddu.mask.nxv2i32.nxv2i16.nxv2i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> [[OP1]], <vscale x 2 x i16> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)893// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]894//895vuint32m1_t test_vwaddu_vv_u32m1_m(vbool32_t mask, vuint16mf2_t op1, vuint16mf2_t op2, size_t vl) {896 return __riscv_vwaddu_vv_u32m1_m(mask, op1, op2, vl);897}898 899// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vwaddu_vx_u32m1_m900// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {901// CHECK-RV64-NEXT: entry:902// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwaddu.mask.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> [[OP1]], i16 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)903// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]904//905vuint32m1_t test_vwaddu_vx_u32m1_m(vbool32_t mask, vuint16mf2_t op1, uint16_t op2, size_t vl) {906 return __riscv_vwaddu_vx_u32m1_m(mask, op1, op2, vl);907}908 909// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vwaddu_wv_u32m1_m910// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {911// CHECK-RV64-NEXT: entry:912// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwaddu.w.mask.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[OP1]], <vscale x 2 x i16> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)913// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]914//915vuint32m1_t test_vwaddu_wv_u32m1_m(vbool32_t mask, vuint32m1_t op1, vuint16mf2_t op2, size_t vl) {916 return __riscv_vwaddu_wv_u32m1_m(mask, op1, op2, vl);917}918 919// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vwaddu_wx_u32m1_m920// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {921// CHECK-RV64-NEXT: entry:922// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwaddu.w.mask.nxv2i32.i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[OP1]], i16 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)923// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]924//925vuint32m1_t test_vwaddu_wx_u32m1_m(vbool32_t mask, vuint32m1_t op1, uint16_t op2, size_t vl) {926 return __riscv_vwaddu_wx_u32m1_m(mask, op1, op2, vl);927}928 929// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vwaddu_vv_u32m2_m930// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {931// CHECK-RV64-NEXT: entry:932// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwaddu.mask.nxv4i32.nxv4i16.nxv4i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> [[OP1]], <vscale x 4 x i16> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)933// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]934//935vuint32m2_t test_vwaddu_vv_u32m2_m(vbool16_t mask, vuint16m1_t op1, vuint16m1_t op2, size_t vl) {936 return __riscv_vwaddu_vv_u32m2_m(mask, op1, op2, vl);937}938 939// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vwaddu_vx_u32m2_m940// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {941// CHECK-RV64-NEXT: entry:942// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwaddu.mask.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> [[OP1]], i16 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)943// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]944//945vuint32m2_t test_vwaddu_vx_u32m2_m(vbool16_t mask, vuint16m1_t op1, uint16_t op2, size_t vl) {946 return __riscv_vwaddu_vx_u32m2_m(mask, op1, op2, vl);947}948 949// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vwaddu_wv_u32m2_m950// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {951// CHECK-RV64-NEXT: entry:952// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwaddu.w.mask.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> [[OP1]], <vscale x 4 x i16> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)953// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]954//955vuint32m2_t test_vwaddu_wv_u32m2_m(vbool16_t mask, vuint32m2_t op1, vuint16m1_t op2, size_t vl) {956 return __riscv_vwaddu_wv_u32m2_m(mask, op1, op2, vl);957}958 959// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vwaddu_wx_u32m2_m960// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {961// CHECK-RV64-NEXT: entry:962// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwaddu.w.mask.nxv4i32.i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> [[OP1]], i16 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)963// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]964//965vuint32m2_t test_vwaddu_wx_u32m2_m(vbool16_t mask, vuint32m2_t op1, uint16_t op2, size_t vl) {966 return __riscv_vwaddu_wx_u32m2_m(mask, op1, op2, vl);967}968 969// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vwaddu_vv_u32m4_m970// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {971// CHECK-RV64-NEXT: entry:972// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwaddu.mask.nxv8i32.nxv8i16.nxv8i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> [[OP1]], <vscale x 8 x i16> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)973// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]974//975vuint32m4_t test_vwaddu_vv_u32m4_m(vbool8_t mask, vuint16m2_t op1, vuint16m2_t op2, size_t vl) {976 return __riscv_vwaddu_vv_u32m4_m(mask, op1, op2, vl);977}978 979// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vwaddu_vx_u32m4_m980// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {981// CHECK-RV64-NEXT: entry:982// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwaddu.mask.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> [[OP1]], i16 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)983// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]984//985vuint32m4_t test_vwaddu_vx_u32m4_m(vbool8_t mask, vuint16m2_t op1, uint16_t op2, size_t vl) {986 return __riscv_vwaddu_vx_u32m4_m(mask, op1, op2, vl);987}988 989// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vwaddu_wv_u32m4_m990// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {991// CHECK-RV64-NEXT: entry:992// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwaddu.w.mask.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> [[OP1]], <vscale x 8 x i16> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)993// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]994//995vuint32m4_t test_vwaddu_wv_u32m4_m(vbool8_t mask, vuint32m4_t op1, vuint16m2_t op2, size_t vl) {996 return __riscv_vwaddu_wv_u32m4_m(mask, op1, op2, vl);997}998 999// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vwaddu_wx_u32m4_m1000// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1001// CHECK-RV64-NEXT: entry:1002// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwaddu.w.mask.nxv8i32.i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> [[OP1]], i16 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)1003// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]1004//1005vuint32m4_t test_vwaddu_wx_u32m4_m(vbool8_t mask, vuint32m4_t op1, uint16_t op2, size_t vl) {1006 return __riscv_vwaddu_wx_u32m4_m(mask, op1, op2, vl);1007}1008 1009// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vwaddu_vv_u32m8_m1010// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1011// CHECK-RV64-NEXT: entry:1012// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwaddu.mask.nxv16i32.nxv16i16.nxv16i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> [[OP1]], <vscale x 16 x i16> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3)1013// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]1014//1015vuint32m8_t test_vwaddu_vv_u32m8_m(vbool4_t mask, vuint16m4_t op1, vuint16m4_t op2, size_t vl) {1016 return __riscv_vwaddu_vv_u32m8_m(mask, op1, op2, vl);1017}1018 1019// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vwaddu_vx_u32m8_m1020// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1021// CHECK-RV64-NEXT: entry:1022// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwaddu.mask.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> [[OP1]], i16 [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3)1023// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]1024//1025vuint32m8_t test_vwaddu_vx_u32m8_m(vbool4_t mask, vuint16m4_t op1, uint16_t op2, size_t vl) {1026 return __riscv_vwaddu_vx_u32m8_m(mask, op1, op2, vl);1027}1028 1029// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vwaddu_wv_u32m8_m1030// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1031// CHECK-RV64-NEXT: entry:1032// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwaddu.w.mask.nxv16i32.nxv16i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> [[OP1]], <vscale x 16 x i16> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3)1033// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]1034//1035vuint32m8_t test_vwaddu_wv_u32m8_m(vbool4_t mask, vuint32m8_t op1, vuint16m4_t op2, size_t vl) {1036 return __riscv_vwaddu_wv_u32m8_m(mask, op1, op2, vl);1037}1038 1039// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vwaddu_wx_u32m8_m1040// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1041// CHECK-RV64-NEXT: entry:1042// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwaddu.w.mask.nxv16i32.i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> [[OP1]], i16 [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3)1043// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]1044//1045vuint32m8_t test_vwaddu_wx_u32m8_m(vbool4_t mask, vuint32m8_t op1, uint16_t op2, size_t vl) {1046 return __riscv_vwaddu_wx_u32m8_m(mask, op1, op2, vl);1047}1048 1049// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vwaddu_vv_u64m1_m1050// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1051// CHECK-RV64-NEXT: entry:1052// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwaddu.mask.nxv1i64.nxv1i32.nxv1i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> [[OP1]], <vscale x 1 x i32> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)1053// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]1054//1055vuint64m1_t test_vwaddu_vv_u64m1_m(vbool64_t mask, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {1056 return __riscv_vwaddu_vv_u64m1_m(mask, op1, op2, vl);1057}1058 1059// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vwaddu_vx_u64m1_m1060// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1061// CHECK-RV64-NEXT: entry:1062// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwaddu.mask.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> [[OP1]], i32 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)1063// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]1064//1065vuint64m1_t test_vwaddu_vx_u64m1_m(vbool64_t mask, vuint32mf2_t op1, uint32_t op2, size_t vl) {1066 return __riscv_vwaddu_vx_u64m1_m(mask, op1, op2, vl);1067}1068 1069// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vwaddu_wv_u64m1_m1070// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1071// CHECK-RV64-NEXT: entry:1072// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwaddu.w.mask.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> [[OP1]], <vscale x 1 x i32> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)1073// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]1074//1075vuint64m1_t test_vwaddu_wv_u64m1_m(vbool64_t mask, vuint64m1_t op1, vuint32mf2_t op2, size_t vl) {1076 return __riscv_vwaddu_wv_u64m1_m(mask, op1, op2, vl);1077}1078 1079// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vwaddu_wx_u64m1_m1080// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1081// CHECK-RV64-NEXT: entry:1082// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwaddu.w.mask.nxv1i64.i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> [[OP1]], i32 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)1083// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]1084//1085vuint64m1_t test_vwaddu_wx_u64m1_m(vbool64_t mask, vuint64m1_t op1, uint32_t op2, size_t vl) {1086 return __riscv_vwaddu_wx_u64m1_m(mask, op1, op2, vl);1087}1088 1089// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vwaddu_vv_u64m2_m1090// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1091// CHECK-RV64-NEXT: entry:1092// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwaddu.mask.nxv2i64.nxv2i32.nxv2i32.i64(<vscale x 2 x i64> poison, <vscale x 2 x i32> [[OP1]], <vscale x 2 x i32> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)1093// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]1094//1095vuint64m2_t test_vwaddu_vv_u64m2_m(vbool32_t mask, vuint32m1_t op1, vuint32m1_t op2, size_t vl) {1096 return __riscv_vwaddu_vv_u64m2_m(mask, op1, op2, vl);1097}1098 1099// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vwaddu_vx_u64m2_m1100// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1101// CHECK-RV64-NEXT: entry:1102// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwaddu.mask.nxv2i64.nxv2i32.i32.i64(<vscale x 2 x i64> poison, <vscale x 2 x i32> [[OP1]], i32 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)1103// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]1104//1105vuint64m2_t test_vwaddu_vx_u64m2_m(vbool32_t mask, vuint32m1_t op1, uint32_t op2, size_t vl) {1106 return __riscv_vwaddu_vx_u64m2_m(mask, op1, op2, vl);1107}1108 1109// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vwaddu_wv_u64m2_m1110// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1111// CHECK-RV64-NEXT: entry:1112// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwaddu.w.mask.nxv2i64.nxv2i32.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> [[OP1]], <vscale x 2 x i32> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)1113// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]1114//1115vuint64m2_t test_vwaddu_wv_u64m2_m(vbool32_t mask, vuint64m2_t op1, vuint32m1_t op2, size_t vl) {1116 return __riscv_vwaddu_wv_u64m2_m(mask, op1, op2, vl);1117}1118 1119// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vwaddu_wx_u64m2_m1120// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1121// CHECK-RV64-NEXT: entry:1122// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwaddu.w.mask.nxv2i64.i32.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> [[OP1]], i32 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)1123// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]1124//1125vuint64m2_t test_vwaddu_wx_u64m2_m(vbool32_t mask, vuint64m2_t op1, uint32_t op2, size_t vl) {1126 return __riscv_vwaddu_wx_u64m2_m(mask, op1, op2, vl);1127}1128 1129// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vwaddu_vv_u64m4_m1130// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1131// CHECK-RV64-NEXT: entry:1132// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwaddu.mask.nxv4i64.nxv4i32.nxv4i32.i64(<vscale x 4 x i64> poison, <vscale x 4 x i32> [[OP1]], <vscale x 4 x i32> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)1133// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]1134//1135vuint64m4_t test_vwaddu_vv_u64m4_m(vbool16_t mask, vuint32m2_t op1, vuint32m2_t op2, size_t vl) {1136 return __riscv_vwaddu_vv_u64m4_m(mask, op1, op2, vl);1137}1138 1139// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vwaddu_vx_u64m4_m1140// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1141// CHECK-RV64-NEXT: entry:1142// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwaddu.mask.nxv4i64.nxv4i32.i32.i64(<vscale x 4 x i64> poison, <vscale x 4 x i32> [[OP1]], i32 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)1143// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]1144//1145vuint64m4_t test_vwaddu_vx_u64m4_m(vbool16_t mask, vuint32m2_t op1, uint32_t op2, size_t vl) {1146 return __riscv_vwaddu_vx_u64m4_m(mask, op1, op2, vl);1147}1148 1149// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vwaddu_wv_u64m4_m1150// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1151// CHECK-RV64-NEXT: entry:1152// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwaddu.w.mask.nxv4i64.nxv4i32.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> [[OP1]], <vscale x 4 x i32> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)1153// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]1154//1155vuint64m4_t test_vwaddu_wv_u64m4_m(vbool16_t mask, vuint64m4_t op1, vuint32m2_t op2, size_t vl) {1156 return __riscv_vwaddu_wv_u64m4_m(mask, op1, op2, vl);1157}1158 1159// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vwaddu_wx_u64m4_m1160// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1161// CHECK-RV64-NEXT: entry:1162// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwaddu.w.mask.nxv4i64.i32.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> [[OP1]], i32 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)1163// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]1164//1165vuint64m4_t test_vwaddu_wx_u64m4_m(vbool16_t mask, vuint64m4_t op1, uint32_t op2, size_t vl) {1166 return __riscv_vwaddu_wx_u64m4_m(mask, op1, op2, vl);1167}1168 1169// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vwaddu_vv_u64m8_m1170// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1171// CHECK-RV64-NEXT: entry:1172// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwaddu.mask.nxv8i64.nxv8i32.nxv8i32.i64(<vscale x 8 x i64> poison, <vscale x 8 x i32> [[OP1]], <vscale x 8 x i32> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)1173// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]1174//1175vuint64m8_t test_vwaddu_vv_u64m8_m(vbool8_t mask, vuint32m4_t op1, vuint32m4_t op2, size_t vl) {1176 return __riscv_vwaddu_vv_u64m8_m(mask, op1, op2, vl);1177}1178 1179// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vwaddu_vx_u64m8_m1180// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1181// CHECK-RV64-NEXT: entry:1182// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwaddu.mask.nxv8i64.nxv8i32.i32.i64(<vscale x 8 x i64> poison, <vscale x 8 x i32> [[OP1]], i32 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)1183// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]1184//1185vuint64m8_t test_vwaddu_vx_u64m8_m(vbool8_t mask, vuint32m4_t op1, uint32_t op2, size_t vl) {1186 return __riscv_vwaddu_vx_u64m8_m(mask, op1, op2, vl);1187}1188 1189// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vwaddu_wv_u64m8_m1190// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1191// CHECK-RV64-NEXT: entry:1192// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwaddu.w.mask.nxv8i64.nxv8i32.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> [[OP1]], <vscale x 8 x i32> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)1193// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]1194//1195vuint64m8_t test_vwaddu_wv_u64m8_m(vbool8_t mask, vuint64m8_t op1, vuint32m4_t op2, size_t vl) {1196 return __riscv_vwaddu_wv_u64m8_m(mask, op1, op2, vl);1197}1198 1199// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vwaddu_wx_u64m8_m1200// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1201// CHECK-RV64-NEXT: entry:1202// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwaddu.w.mask.nxv8i64.i32.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> [[OP1]], i32 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)1203// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]1204//1205vuint64m8_t test_vwaddu_wx_u64m8_m(vbool8_t mask, vuint64m8_t op1, uint32_t op2, size_t vl) {1206 return __riscv_vwaddu_wx_u64m8_m(mask, op1, op2, vl);1207}1208 1209