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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 22// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone \4// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \5// RUN: FileCheck --check-prefix=CHECK-RV64 %s6 7#include <riscv_vector.h>8 9// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vzext_vf4_u32mf210// CHECK-RV64-SAME: (<vscale x 1 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {11// CHECK-RV64-NEXT: entry:12// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> poison, <vscale x 1 x i8> [[OP1]], i64 [[VL]])13// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]14//15vuint32mf2_t test_vzext_vf4_u32mf2(vuint8mf8_t op1, size_t vl) {16 return __riscv_vzext_vf4_u32mf2(op1, vl);17}18 19// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vzext_vf4_u32m120// CHECK-RV64-SAME: (<vscale x 2 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {21// CHECK-RV64-NEXT: entry:22// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> poison, <vscale x 2 x i8> [[OP1]], i64 [[VL]])23// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]24//25vuint32m1_t test_vzext_vf4_u32m1(vuint8mf4_t op1, size_t vl) {26 return __riscv_vzext_vf4_u32m1(op1, vl);27}28 29// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vzext_vf4_u32m230// CHECK-RV64-SAME: (<vscale x 4 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {31// CHECK-RV64-NEXT: entry:32// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> poison, <vscale x 4 x i8> [[OP1]], i64 [[VL]])33// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]34//35vuint32m2_t test_vzext_vf4_u32m2(vuint8mf2_t op1, size_t vl) {36 return __riscv_vzext_vf4_u32m2(op1, vl);37}38 39// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vzext_vf4_u32m440// CHECK-RV64-SAME: (<vscale x 8 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {41// CHECK-RV64-NEXT: entry:42// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> poison, <vscale x 8 x i8> [[OP1]], i64 [[VL]])43// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]44//45vuint32m4_t test_vzext_vf4_u32m4(vuint8m1_t op1, size_t vl) {46 return __riscv_vzext_vf4_u32m4(op1, vl);47}48 49// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vzext_vf4_u32m850// CHECK-RV64-SAME: (<vscale x 16 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {51// CHECK-RV64-NEXT: entry:52// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> poison, <vscale x 16 x i8> [[OP1]], i64 [[VL]])53// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]54//55vuint32m8_t test_vzext_vf4_u32m8(vuint8m2_t op1, size_t vl) {56 return __riscv_vzext_vf4_u32m8(op1, vl);57}58 59// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vzext_vf4_u64m160// CHECK-RV64-SAME: (<vscale x 1 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {61// CHECK-RV64-NEXT: entry:62// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> poison, <vscale x 1 x i16> [[OP1]], i64 [[VL]])63// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]64//65vuint64m1_t test_vzext_vf4_u64m1(vuint16mf4_t op1, size_t vl) {66 return __riscv_vzext_vf4_u64m1(op1, vl);67}68 69// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vzext_vf4_u64m270// CHECK-RV64-SAME: (<vscale x 2 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {71// CHECK-RV64-NEXT: entry:72// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> poison, <vscale x 2 x i16> [[OP1]], i64 [[VL]])73// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]74//75vuint64m2_t test_vzext_vf4_u64m2(vuint16mf2_t op1, size_t vl) {76 return __riscv_vzext_vf4_u64m2(op1, vl);77}78 79// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vzext_vf4_u64m480// CHECK-RV64-SAME: (<vscale x 4 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {81// CHECK-RV64-NEXT: entry:82// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> poison, <vscale x 4 x i16> [[OP1]], i64 [[VL]])83// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]84//85vuint64m4_t test_vzext_vf4_u64m4(vuint16m1_t op1, size_t vl) {86 return __riscv_vzext_vf4_u64m4(op1, vl);87}88 89// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vzext_vf4_u64m890// CHECK-RV64-SAME: (<vscale x 8 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {91// CHECK-RV64-NEXT: entry:92// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> poison, <vscale x 8 x i16> [[OP1]], i64 [[VL]])93// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]94//95vuint64m8_t test_vzext_vf4_u64m8(vuint16m2_t op1, size_t vl) {96 return __riscv_vzext_vf4_u64m8(op1, vl);97}98 99// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vzext_vf4_u32mf2_m100// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {101// CHECK-RV64-NEXT: entry:102// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vzext.mask.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> poison, <vscale x 1 x i8> [[OP1]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)103// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]104//105vuint32mf2_t test_vzext_vf4_u32mf2_m(vbool64_t mask, vuint8mf8_t op1, size_t vl) {106 return __riscv_vzext_vf4_u32mf2_m(mask, op1, vl);107}108 109// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vzext_vf4_u32m1_m110// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {111// CHECK-RV64-NEXT: entry:112// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzext.mask.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> poison, <vscale x 2 x i8> [[OP1]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)113// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]114//115vuint32m1_t test_vzext_vf4_u32m1_m(vbool32_t mask, vuint8mf4_t op1, size_t vl) {116 return __riscv_vzext_vf4_u32m1_m(mask, op1, vl);117}118 119// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vzext_vf4_u32m2_m120// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {121// CHECK-RV64-NEXT: entry:122// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzext.mask.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> poison, <vscale x 4 x i8> [[OP1]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)123// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]124//125vuint32m2_t test_vzext_vf4_u32m2_m(vbool16_t mask, vuint8mf2_t op1, size_t vl) {126 return __riscv_vzext_vf4_u32m2_m(mask, op1, vl);127}128 129// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vzext_vf4_u32m4_m130// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {131// CHECK-RV64-NEXT: entry:132// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzext.mask.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> poison, <vscale x 8 x i8> [[OP1]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)133// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]134//135vuint32m4_t test_vzext_vf4_u32m4_m(vbool8_t mask, vuint8m1_t op1, size_t vl) {136 return __riscv_vzext_vf4_u32m4_m(mask, op1, vl);137}138 139// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vzext_vf4_u32m8_m140// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {141// CHECK-RV64-NEXT: entry:142// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzext.mask.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> poison, <vscale x 16 x i8> [[OP1]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3)143// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]144//145vuint32m8_t test_vzext_vf4_u32m8_m(vbool4_t mask, vuint8m2_t op1, size_t vl) {146 return __riscv_vzext_vf4_u32m8_m(mask, op1, vl);147}148 149// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vzext_vf4_u64m1_m150// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {151// CHECK-RV64-NEXT: entry:152// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> poison, <vscale x 1 x i16> [[OP1]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)153// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]154//155vuint64m1_t test_vzext_vf4_u64m1_m(vbool64_t mask, vuint16mf4_t op1, size_t vl) {156 return __riscv_vzext_vf4_u64m1_m(mask, op1, vl);157}158 159// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vzext_vf4_u64m2_m160// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {161// CHECK-RV64-NEXT: entry:162// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> poison, <vscale x 2 x i16> [[OP1]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)163// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]164//165vuint64m2_t test_vzext_vf4_u64m2_m(vbool32_t mask, vuint16mf2_t op1, size_t vl) {166 return __riscv_vzext_vf4_u64m2_m(mask, op1, vl);167}168 169// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vzext_vf4_u64m4_m170// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {171// CHECK-RV64-NEXT: entry:172// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> poison, <vscale x 4 x i16> [[OP1]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)173// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]174//175vuint64m4_t test_vzext_vf4_u64m4_m(vbool16_t mask, vuint16m1_t op1, size_t vl) {176 return __riscv_vzext_vf4_u64m4_m(mask, op1, vl);177}178 179// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vzext_vf4_u64m8_m180// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {181// CHECK-RV64-NEXT: entry:182// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> poison, <vscale x 8 x i16> [[OP1]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)183// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]184//185vuint64m8_t test_vzext_vf4_u64m8_m(vbool8_t mask, vuint16m2_t op1, size_t vl) {186 return __riscv_vzext_vf4_u64m8_m(mask, op1, vl);187}188 189