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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 22// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \4// RUN: -target-feature +zvfh -disable-O0-optnone \5// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \6// RUN: FileCheck --check-prefix=CHECK-RV64 %s7 8#include <riscv_vector.h>9 10// CHECK-RV64-LABEL: define dso_local i64 @test_vcpop_m_b111// CHECK-RV64-SAME: (<vscale x 64 x i1> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {12// CHECK-RV64-NEXT: entry:13// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vcpop.nxv64i1.i64(<vscale x 64 x i1> [[OP1]], i64 [[VL]])14// CHECK-RV64-NEXT: ret i64 [[TMP0]]15//16unsigned long test_vcpop_m_b1(vbool1_t op1, size_t vl) {17 return __riscv_vcpop(op1, vl);18}19 20// CHECK-RV64-LABEL: define dso_local i64 @test_vcpop_m_b221// CHECK-RV64-SAME: (<vscale x 32 x i1> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {22// CHECK-RV64-NEXT: entry:23// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vcpop.nxv32i1.i64(<vscale x 32 x i1> [[OP1]], i64 [[VL]])24// CHECK-RV64-NEXT: ret i64 [[TMP0]]25//26unsigned long test_vcpop_m_b2(vbool2_t op1, size_t vl) {27 return __riscv_vcpop(op1, vl);28}29 30// CHECK-RV64-LABEL: define dso_local i64 @test_vcpop_m_b431// CHECK-RV64-SAME: (<vscale x 16 x i1> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {32// CHECK-RV64-NEXT: entry:33// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vcpop.nxv16i1.i64(<vscale x 16 x i1> [[OP1]], i64 [[VL]])34// CHECK-RV64-NEXT: ret i64 [[TMP0]]35//36unsigned long test_vcpop_m_b4(vbool4_t op1, size_t vl) {37 return __riscv_vcpop(op1, vl);38}39 40// CHECK-RV64-LABEL: define dso_local i64 @test_vcpop_m_b841// CHECK-RV64-SAME: (<vscale x 8 x i1> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {42// CHECK-RV64-NEXT: entry:43// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vcpop.nxv8i1.i64(<vscale x 8 x i1> [[OP1]], i64 [[VL]])44// CHECK-RV64-NEXT: ret i64 [[TMP0]]45//46unsigned long test_vcpop_m_b8(vbool8_t op1, size_t vl) {47 return __riscv_vcpop(op1, vl);48}49 50// CHECK-RV64-LABEL: define dso_local i64 @test_vcpop_m_b1651// CHECK-RV64-SAME: (<vscale x 4 x i1> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {52// CHECK-RV64-NEXT: entry:53// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vcpop.nxv4i1.i64(<vscale x 4 x i1> [[OP1]], i64 [[VL]])54// CHECK-RV64-NEXT: ret i64 [[TMP0]]55//56unsigned long test_vcpop_m_b16(vbool16_t op1, size_t vl) {57 return __riscv_vcpop(op1, vl);58}59 60// CHECK-RV64-LABEL: define dso_local i64 @test_vcpop_m_b3261// CHECK-RV64-SAME: (<vscale x 2 x i1> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {62// CHECK-RV64-NEXT: entry:63// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vcpop.nxv2i1.i64(<vscale x 2 x i1> [[OP1]], i64 [[VL]])64// CHECK-RV64-NEXT: ret i64 [[TMP0]]65//66unsigned long test_vcpop_m_b32(vbool32_t op1, size_t vl) {67 return __riscv_vcpop(op1, vl);68}69 70// CHECK-RV64-LABEL: define dso_local i64 @test_vcpop_m_b6471// CHECK-RV64-SAME: (<vscale x 1 x i1> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {72// CHECK-RV64-NEXT: entry:73// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vcpop.nxv1i1.i64(<vscale x 1 x i1> [[OP1]], i64 [[VL]])74// CHECK-RV64-NEXT: ret i64 [[TMP0]]75//76unsigned long test_vcpop_m_b64(vbool64_t op1, size_t vl) {77 return __riscv_vcpop(op1, vl);78}79 80// CHECK-RV64-LABEL: define dso_local i64 @test_vcpop_m_b1_m81// CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i1> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {82// CHECK-RV64-NEXT: entry:83// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vcpop.mask.nxv64i1.i64(<vscale x 64 x i1> [[OP1]], <vscale x 64 x i1> [[MASK]], i64 [[VL]])84// CHECK-RV64-NEXT: ret i64 [[TMP0]]85//86unsigned long test_vcpop_m_b1_m(vbool1_t mask, vbool1_t op1, size_t vl) {87 return __riscv_vcpop(mask, op1, vl);88}89 90// CHECK-RV64-LABEL: define dso_local i64 @test_vcpop_m_b2_m91// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i1> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {92// CHECK-RV64-NEXT: entry:93// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vcpop.mask.nxv32i1.i64(<vscale x 32 x i1> [[OP1]], <vscale x 32 x i1> [[MASK]], i64 [[VL]])94// CHECK-RV64-NEXT: ret i64 [[TMP0]]95//96unsigned long test_vcpop_m_b2_m(vbool2_t mask, vbool2_t op1, size_t vl) {97 return __riscv_vcpop(mask, op1, vl);98}99 100// CHECK-RV64-LABEL: define dso_local i64 @test_vcpop_m_b4_m101// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i1> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {102// CHECK-RV64-NEXT: entry:103// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vcpop.mask.nxv16i1.i64(<vscale x 16 x i1> [[OP1]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])104// CHECK-RV64-NEXT: ret i64 [[TMP0]]105//106unsigned long test_vcpop_m_b4_m(vbool4_t mask, vbool4_t op1, size_t vl) {107 return __riscv_vcpop(mask, op1, vl);108}109 110// CHECK-RV64-LABEL: define dso_local i64 @test_vcpop_m_b8_m111// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i1> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {112// CHECK-RV64-NEXT: entry:113// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vcpop.mask.nxv8i1.i64(<vscale x 8 x i1> [[OP1]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])114// CHECK-RV64-NEXT: ret i64 [[TMP0]]115//116unsigned long test_vcpop_m_b8_m(vbool8_t mask, vbool8_t op1, size_t vl) {117 return __riscv_vcpop(mask, op1, vl);118}119 120// CHECK-RV64-LABEL: define dso_local i64 @test_vcpop_m_b16_m121// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i1> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {122// CHECK-RV64-NEXT: entry:123// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vcpop.mask.nxv4i1.i64(<vscale x 4 x i1> [[OP1]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])124// CHECK-RV64-NEXT: ret i64 [[TMP0]]125//126unsigned long test_vcpop_m_b16_m(vbool16_t mask, vbool16_t op1, size_t vl) {127 return __riscv_vcpop(mask, op1, vl);128}129 130// CHECK-RV64-LABEL: define dso_local i64 @test_vcpop_m_b32_m131// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i1> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {132// CHECK-RV64-NEXT: entry:133// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vcpop.mask.nxv2i1.i64(<vscale x 2 x i1> [[OP1]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])134// CHECK-RV64-NEXT: ret i64 [[TMP0]]135//136unsigned long test_vcpop_m_b32_m(vbool32_t mask, vbool32_t op1, size_t vl) {137 return __riscv_vcpop(mask, op1, vl);138}139 140// CHECK-RV64-LABEL: define dso_local i64 @test_vcpop_m_b64_m141// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {142// CHECK-RV64-NEXT: entry:143// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vcpop.mask.nxv1i1.i64(<vscale x 1 x i1> [[OP1]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])144// CHECK-RV64-NEXT: ret i64 [[TMP0]]145//146unsigned long test_vcpop_m_b64_m(vbool64_t mask, vbool64_t op1, size_t vl) {147 return __riscv_vcpop(mask, op1, vl);148}149 150