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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 22// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \4// RUN: -target-feature +zvfh -disable-O0-optnone \5// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \6// RUN: FileCheck --check-prefix=CHECK-RV64 %s7 8#include <riscv_vector.h>9 10// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vfcvt_x_f_v_i16mf411// CHECK-RV64-SAME: (<vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {12// CHECK-RV64-NEXT: entry:13// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> [[SRC]], i64 7, i64 [[VL]])14// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]15//16vint16mf4_t test_vfcvt_x_f_v_i16mf4(vfloat16mf4_t src, size_t vl) {17 return __riscv_vfcvt_x(src, vl);18}19 20// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vfcvt_x_f_v_i16mf221// CHECK-RV64-SAME: (<vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {22// CHECK-RV64-NEXT: entry:23// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> [[SRC]], i64 7, i64 [[VL]])24// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]25//26vint16mf2_t test_vfcvt_x_f_v_i16mf2(vfloat16mf2_t src, size_t vl) {27 return __riscv_vfcvt_x(src, vl);28}29 30// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfcvt_x_f_v_i16m131// CHECK-RV64-SAME: (<vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {32// CHECK-RV64-NEXT: entry:33// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> [[SRC]], i64 7, i64 [[VL]])34// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]35//36vint16m1_t test_vfcvt_x_f_v_i16m1(vfloat16m1_t src, size_t vl) {37 return __riscv_vfcvt_x(src, vl);38}39 40// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfcvt_x_f_v_i16m241// CHECK-RV64-SAME: (<vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {42// CHECK-RV64-NEXT: entry:43// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> [[SRC]], i64 7, i64 [[VL]])44// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]45//46vint16m2_t test_vfcvt_x_f_v_i16m2(vfloat16m2_t src, size_t vl) {47 return __riscv_vfcvt_x(src, vl);48}49 50// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfcvt_x_f_v_i16m451// CHECK-RV64-SAME: (<vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {52// CHECK-RV64-NEXT: entry:53// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> [[SRC]], i64 7, i64 [[VL]])54// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]55//56vint16m4_t test_vfcvt_x_f_v_i16m4(vfloat16m4_t src, size_t vl) {57 return __riscv_vfcvt_x(src, vl);58}59 60// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vfcvt_x_f_v_i16m861// CHECK-RV64-SAME: (<vscale x 32 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {62// CHECK-RV64-NEXT: entry:63// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> [[SRC]], i64 7, i64 [[VL]])64// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]65//66vint16m8_t test_vfcvt_x_f_v_i16m8(vfloat16m8_t src, size_t vl) {67 return __riscv_vfcvt_x(src, vl);68}69 70// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vfcvt_xu_f_v_u16mf471// CHECK-RV64-SAME: (<vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {72// CHECK-RV64-NEXT: entry:73// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> [[SRC]], i64 7, i64 [[VL]])74// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]75//76vuint16mf4_t test_vfcvt_xu_f_v_u16mf4(vfloat16mf4_t src, size_t vl) {77 return __riscv_vfcvt_xu(src, vl);78}79 80// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vfcvt_xu_f_v_u16mf281// CHECK-RV64-SAME: (<vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {82// CHECK-RV64-NEXT: entry:83// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> [[SRC]], i64 7, i64 [[VL]])84// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]85//86vuint16mf2_t test_vfcvt_xu_f_v_u16mf2(vfloat16mf2_t src, size_t vl) {87 return __riscv_vfcvt_xu(src, vl);88}89 90// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfcvt_xu_f_v_u16m191// CHECK-RV64-SAME: (<vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {92// CHECK-RV64-NEXT: entry:93// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> [[SRC]], i64 7, i64 [[VL]])94// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]95//96vuint16m1_t test_vfcvt_xu_f_v_u16m1(vfloat16m1_t src, size_t vl) {97 return __riscv_vfcvt_xu(src, vl);98}99 100// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfcvt_xu_f_v_u16m2101// CHECK-RV64-SAME: (<vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {102// CHECK-RV64-NEXT: entry:103// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> [[SRC]], i64 7, i64 [[VL]])104// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]105//106vuint16m2_t test_vfcvt_xu_f_v_u16m2(vfloat16m2_t src, size_t vl) {107 return __riscv_vfcvt_xu(src, vl);108}109 110// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfcvt_xu_f_v_u16m4111// CHECK-RV64-SAME: (<vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {112// CHECK-RV64-NEXT: entry:113// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> [[SRC]], i64 7, i64 [[VL]])114// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]115//116vuint16m4_t test_vfcvt_xu_f_v_u16m4(vfloat16m4_t src, size_t vl) {117 return __riscv_vfcvt_xu(src, vl);118}119 120// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vfcvt_xu_f_v_u16m8121// CHECK-RV64-SAME: (<vscale x 32 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {122// CHECK-RV64-NEXT: entry:123// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> [[SRC]], i64 7, i64 [[VL]])124// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]125//126vuint16m8_t test_vfcvt_xu_f_v_u16m8(vfloat16m8_t src, size_t vl) {127 return __riscv_vfcvt_xu(src, vl);128}129 130// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfcvt_f_x_v_f16mf4131// CHECK-RV64-SAME: (<vscale x 1 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {132// CHECK-RV64-NEXT: entry:133// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfcvt.f.x.v.nxv1f16.nxv1i16.i64(<vscale x 1 x half> poison, <vscale x 1 x i16> [[SRC]], i64 7, i64 [[VL]])134// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]135//136vfloat16mf4_t test_vfcvt_f_x_v_f16mf4(vint16mf4_t src, size_t vl) {137 return __riscv_vfcvt_f(src, vl);138}139 140// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfcvt_f_x_v_f16mf2141// CHECK-RV64-SAME: (<vscale x 2 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {142// CHECK-RV64-NEXT: entry:143// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfcvt.f.x.v.nxv2f16.nxv2i16.i64(<vscale x 2 x half> poison, <vscale x 2 x i16> [[SRC]], i64 7, i64 [[VL]])144// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]145//146vfloat16mf2_t test_vfcvt_f_x_v_f16mf2(vint16mf2_t src, size_t vl) {147 return __riscv_vfcvt_f(src, vl);148}149 150// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfcvt_f_x_v_f16m1151// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {152// CHECK-RV64-NEXT: entry:153// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfcvt.f.x.v.nxv4f16.nxv4i16.i64(<vscale x 4 x half> poison, <vscale x 4 x i16> [[SRC]], i64 7, i64 [[VL]])154// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]155//156vfloat16m1_t test_vfcvt_f_x_v_f16m1(vint16m1_t src, size_t vl) {157 return __riscv_vfcvt_f(src, vl);158}159 160// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfcvt_f_x_v_f16m2161// CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {162// CHECK-RV64-NEXT: entry:163// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfcvt.f.x.v.nxv8f16.nxv8i16.i64(<vscale x 8 x half> poison, <vscale x 8 x i16> [[SRC]], i64 7, i64 [[VL]])164// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]165//166vfloat16m2_t test_vfcvt_f_x_v_f16m2(vint16m2_t src, size_t vl) {167 return __riscv_vfcvt_f(src, vl);168}169 170// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfcvt_f_x_v_f16m4171// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {172// CHECK-RV64-NEXT: entry:173// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfcvt.f.x.v.nxv16f16.nxv16i16.i64(<vscale x 16 x half> poison, <vscale x 16 x i16> [[SRC]], i64 7, i64 [[VL]])174// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]175//176vfloat16m4_t test_vfcvt_f_x_v_f16m4(vint16m4_t src, size_t vl) {177 return __riscv_vfcvt_f(src, vl);178}179 180// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfcvt_f_x_v_f16m8181// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {182// CHECK-RV64-NEXT: entry:183// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfcvt.f.x.v.nxv32f16.nxv32i16.i64(<vscale x 32 x half> poison, <vscale x 32 x i16> [[SRC]], i64 7, i64 [[VL]])184// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]185//186vfloat16m8_t test_vfcvt_f_x_v_f16m8(vint16m8_t src, size_t vl) {187 return __riscv_vfcvt_f(src, vl);188}189 190// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfcvt_f_xu_v_f16mf4191// CHECK-RV64-SAME: (<vscale x 1 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {192// CHECK-RV64-NEXT: entry:193// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfcvt.f.xu.v.nxv1f16.nxv1i16.i64(<vscale x 1 x half> poison, <vscale x 1 x i16> [[SRC]], i64 7, i64 [[VL]])194// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]195//196vfloat16mf4_t test_vfcvt_f_xu_v_f16mf4(vuint16mf4_t src, size_t vl) {197 return __riscv_vfcvt_f(src, vl);198}199 200// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfcvt_f_xu_v_f16mf2201// CHECK-RV64-SAME: (<vscale x 2 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {202// CHECK-RV64-NEXT: entry:203// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfcvt.f.xu.v.nxv2f16.nxv2i16.i64(<vscale x 2 x half> poison, <vscale x 2 x i16> [[SRC]], i64 7, i64 [[VL]])204// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]205//206vfloat16mf2_t test_vfcvt_f_xu_v_f16mf2(vuint16mf2_t src, size_t vl) {207 return __riscv_vfcvt_f(src, vl);208}209 210// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfcvt_f_xu_v_f16m1211// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {212// CHECK-RV64-NEXT: entry:213// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfcvt.f.xu.v.nxv4f16.nxv4i16.i64(<vscale x 4 x half> poison, <vscale x 4 x i16> [[SRC]], i64 7, i64 [[VL]])214// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]215//216vfloat16m1_t test_vfcvt_f_xu_v_f16m1(vuint16m1_t src, size_t vl) {217 return __riscv_vfcvt_f(src, vl);218}219 220// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfcvt_f_xu_v_f16m2221// CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {222// CHECK-RV64-NEXT: entry:223// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfcvt.f.xu.v.nxv8f16.nxv8i16.i64(<vscale x 8 x half> poison, <vscale x 8 x i16> [[SRC]], i64 7, i64 [[VL]])224// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]225//226vfloat16m2_t test_vfcvt_f_xu_v_f16m2(vuint16m2_t src, size_t vl) {227 return __riscv_vfcvt_f(src, vl);228}229 230// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfcvt_f_xu_v_f16m4231// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {232// CHECK-RV64-NEXT: entry:233// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfcvt.f.xu.v.nxv16f16.nxv16i16.i64(<vscale x 16 x half> poison, <vscale x 16 x i16> [[SRC]], i64 7, i64 [[VL]])234// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]235//236vfloat16m4_t test_vfcvt_f_xu_v_f16m4(vuint16m4_t src, size_t vl) {237 return __riscv_vfcvt_f(src, vl);238}239 240// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfcvt_f_xu_v_f16m8241// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {242// CHECK-RV64-NEXT: entry:243// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfcvt.f.xu.v.nxv32f16.nxv32i16.i64(<vscale x 32 x half> poison, <vscale x 32 x i16> [[SRC]], i64 7, i64 [[VL]])244// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]245//246vfloat16m8_t test_vfcvt_f_xu_v_f16m8(vuint16m8_t src, size_t vl) {247 return __riscv_vfcvt_f(src, vl);248}249 250// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfcvt_x_f_v_i32mf2251// CHECK-RV64-SAME: (<vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {252// CHECK-RV64-NEXT: entry:253// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfcvt.x.f.v.nxv1i32.nxv1f32.i64(<vscale x 1 x i32> poison, <vscale x 1 x float> [[SRC]], i64 7, i64 [[VL]])254// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]255//256vint32mf2_t test_vfcvt_x_f_v_i32mf2(vfloat32mf2_t src, size_t vl) {257 return __riscv_vfcvt_x(src, vl);258}259 260// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfcvt_x_f_v_i32m1261// CHECK-RV64-SAME: (<vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {262// CHECK-RV64-NEXT: entry:263// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfcvt.x.f.v.nxv2i32.nxv2f32.i64(<vscale x 2 x i32> poison, <vscale x 2 x float> [[SRC]], i64 7, i64 [[VL]])264// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]265//266vint32m1_t test_vfcvt_x_f_v_i32m1(vfloat32m1_t src, size_t vl) {267 return __riscv_vfcvt_x(src, vl);268}269 270// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfcvt_x_f_v_i32m2271// CHECK-RV64-SAME: (<vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {272// CHECK-RV64-NEXT: entry:273// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfcvt.x.f.v.nxv4i32.nxv4f32.i64(<vscale x 4 x i32> poison, <vscale x 4 x float> [[SRC]], i64 7, i64 [[VL]])274// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]275//276vint32m2_t test_vfcvt_x_f_v_i32m2(vfloat32m2_t src, size_t vl) {277 return __riscv_vfcvt_x(src, vl);278}279 280// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfcvt_x_f_v_i32m4281// CHECK-RV64-SAME: (<vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {282// CHECK-RV64-NEXT: entry:283// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfcvt.x.f.v.nxv8i32.nxv8f32.i64(<vscale x 8 x i32> poison, <vscale x 8 x float> [[SRC]], i64 7, i64 [[VL]])284// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]285//286vint32m4_t test_vfcvt_x_f_v_i32m4(vfloat32m4_t src, size_t vl) {287 return __riscv_vfcvt_x(src, vl);288}289 290// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfcvt_x_f_v_i32m8291// CHECK-RV64-SAME: (<vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {292// CHECK-RV64-NEXT: entry:293// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfcvt.x.f.v.nxv16i32.nxv16f32.i64(<vscale x 16 x i32> poison, <vscale x 16 x float> [[SRC]], i64 7, i64 [[VL]])294// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]295//296vint32m8_t test_vfcvt_x_f_v_i32m8(vfloat32m8_t src, size_t vl) {297 return __riscv_vfcvt_x(src, vl);298}299 300// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfcvt_xu_f_v_u32mf2301// CHECK-RV64-SAME: (<vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {302// CHECK-RV64-NEXT: entry:303// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv1i32.nxv1f32.i64(<vscale x 1 x i32> poison, <vscale x 1 x float> [[SRC]], i64 7, i64 [[VL]])304// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]305//306vuint32mf2_t test_vfcvt_xu_f_v_u32mf2(vfloat32mf2_t src, size_t vl) {307 return __riscv_vfcvt_xu(src, vl);308}309 310// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfcvt_xu_f_v_u32m1311// CHECK-RV64-SAME: (<vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {312// CHECK-RV64-NEXT: entry:313// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv2i32.nxv2f32.i64(<vscale x 2 x i32> poison, <vscale x 2 x float> [[SRC]], i64 7, i64 [[VL]])314// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]315//316vuint32m1_t test_vfcvt_xu_f_v_u32m1(vfloat32m1_t src, size_t vl) {317 return __riscv_vfcvt_xu(src, vl);318}319 320// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfcvt_xu_f_v_u32m2321// CHECK-RV64-SAME: (<vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {322// CHECK-RV64-NEXT: entry:323// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv4i32.nxv4f32.i64(<vscale x 4 x i32> poison, <vscale x 4 x float> [[SRC]], i64 7, i64 [[VL]])324// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]325//326vuint32m2_t test_vfcvt_xu_f_v_u32m2(vfloat32m2_t src, size_t vl) {327 return __riscv_vfcvt_xu(src, vl);328}329 330// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfcvt_xu_f_v_u32m4331// CHECK-RV64-SAME: (<vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {332// CHECK-RV64-NEXT: entry:333// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv8i32.nxv8f32.i64(<vscale x 8 x i32> poison, <vscale x 8 x float> [[SRC]], i64 7, i64 [[VL]])334// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]335//336vuint32m4_t test_vfcvt_xu_f_v_u32m4(vfloat32m4_t src, size_t vl) {337 return __riscv_vfcvt_xu(src, vl);338}339 340// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfcvt_xu_f_v_u32m8341// CHECK-RV64-SAME: (<vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {342// CHECK-RV64-NEXT: entry:343// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv16i32.nxv16f32.i64(<vscale x 16 x i32> poison, <vscale x 16 x float> [[SRC]], i64 7, i64 [[VL]])344// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]345//346vuint32m8_t test_vfcvt_xu_f_v_u32m8(vfloat32m8_t src, size_t vl) {347 return __riscv_vfcvt_xu(src, vl);348}349 350// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfcvt_f_x_v_f32mf2351// CHECK-RV64-SAME: (<vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {352// CHECK-RV64-NEXT: entry:353// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfcvt.f.x.v.nxv1f32.nxv1i32.i64(<vscale x 1 x float> poison, <vscale x 1 x i32> [[SRC]], i64 7, i64 [[VL]])354// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]355//356vfloat32mf2_t test_vfcvt_f_x_v_f32mf2(vint32mf2_t src, size_t vl) {357 return __riscv_vfcvt_f(src, vl);358}359 360// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfcvt_f_x_v_f32m1361// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {362// CHECK-RV64-NEXT: entry:363// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfcvt.f.x.v.nxv2f32.nxv2i32.i64(<vscale x 2 x float> poison, <vscale x 2 x i32> [[SRC]], i64 7, i64 [[VL]])364// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]365//366vfloat32m1_t test_vfcvt_f_x_v_f32m1(vint32m1_t src, size_t vl) {367 return __riscv_vfcvt_f(src, vl);368}369 370// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfcvt_f_x_v_f32m2371// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {372// CHECK-RV64-NEXT: entry:373// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfcvt.f.x.v.nxv4f32.nxv4i32.i64(<vscale x 4 x float> poison, <vscale x 4 x i32> [[SRC]], i64 7, i64 [[VL]])374// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]375//376vfloat32m2_t test_vfcvt_f_x_v_f32m2(vint32m2_t src, size_t vl) {377 return __riscv_vfcvt_f(src, vl);378}379 380// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfcvt_f_x_v_f32m4381// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {382// CHECK-RV64-NEXT: entry:383// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfcvt.f.x.v.nxv8f32.nxv8i32.i64(<vscale x 8 x float> poison, <vscale x 8 x i32> [[SRC]], i64 7, i64 [[VL]])384// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]385//386vfloat32m4_t test_vfcvt_f_x_v_f32m4(vint32m4_t src, size_t vl) {387 return __riscv_vfcvt_f(src, vl);388}389 390// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfcvt_f_x_v_f32m8391// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {392// CHECK-RV64-NEXT: entry:393// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfcvt.f.x.v.nxv16f32.nxv16i32.i64(<vscale x 16 x float> poison, <vscale x 16 x i32> [[SRC]], i64 7, i64 [[VL]])394// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]395//396vfloat32m8_t test_vfcvt_f_x_v_f32m8(vint32m8_t src, size_t vl) {397 return __riscv_vfcvt_f(src, vl);398}399 400// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfcvt_f_xu_v_f32mf2401// CHECK-RV64-SAME: (<vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {402// CHECK-RV64-NEXT: entry:403// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfcvt.f.xu.v.nxv1f32.nxv1i32.i64(<vscale x 1 x float> poison, <vscale x 1 x i32> [[SRC]], i64 7, i64 [[VL]])404// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]405//406vfloat32mf2_t test_vfcvt_f_xu_v_f32mf2(vuint32mf2_t src, size_t vl) {407 return __riscv_vfcvt_f(src, vl);408}409 410// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfcvt_f_xu_v_f32m1411// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {412// CHECK-RV64-NEXT: entry:413// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfcvt.f.xu.v.nxv2f32.nxv2i32.i64(<vscale x 2 x float> poison, <vscale x 2 x i32> [[SRC]], i64 7, i64 [[VL]])414// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]415//416vfloat32m1_t test_vfcvt_f_xu_v_f32m1(vuint32m1_t src, size_t vl) {417 return __riscv_vfcvt_f(src, vl);418}419 420// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfcvt_f_xu_v_f32m2421// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {422// CHECK-RV64-NEXT: entry:423// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfcvt.f.xu.v.nxv4f32.nxv4i32.i64(<vscale x 4 x float> poison, <vscale x 4 x i32> [[SRC]], i64 7, i64 [[VL]])424// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]425//426vfloat32m2_t test_vfcvt_f_xu_v_f32m2(vuint32m2_t src, size_t vl) {427 return __riscv_vfcvt_f(src, vl);428}429 430// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfcvt_f_xu_v_f32m4431// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {432// CHECK-RV64-NEXT: entry:433// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfcvt.f.xu.v.nxv8f32.nxv8i32.i64(<vscale x 8 x float> poison, <vscale x 8 x i32> [[SRC]], i64 7, i64 [[VL]])434// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]435//436vfloat32m4_t test_vfcvt_f_xu_v_f32m4(vuint32m4_t src, size_t vl) {437 return __riscv_vfcvt_f(src, vl);438}439 440// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfcvt_f_xu_v_f32m8441// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {442// CHECK-RV64-NEXT: entry:443// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfcvt.f.xu.v.nxv16f32.nxv16i32.i64(<vscale x 16 x float> poison, <vscale x 16 x i32> [[SRC]], i64 7, i64 [[VL]])444// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]445//446vfloat32m8_t test_vfcvt_f_xu_v_f32m8(vuint32m8_t src, size_t vl) {447 return __riscv_vfcvt_f(src, vl);448}449 450// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfcvt_x_f_v_i64m1451// CHECK-RV64-SAME: (<vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {452// CHECK-RV64-NEXT: entry:453// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfcvt.x.f.v.nxv1i64.nxv1f64.i64(<vscale x 1 x i64> poison, <vscale x 1 x double> [[SRC]], i64 7, i64 [[VL]])454// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]455//456vint64m1_t test_vfcvt_x_f_v_i64m1(vfloat64m1_t src, size_t vl) {457 return __riscv_vfcvt_x(src, vl);458}459 460// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfcvt_x_f_v_i64m2461// CHECK-RV64-SAME: (<vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {462// CHECK-RV64-NEXT: entry:463// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfcvt.x.f.v.nxv2i64.nxv2f64.i64(<vscale x 2 x i64> poison, <vscale x 2 x double> [[SRC]], i64 7, i64 [[VL]])464// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]465//466vint64m2_t test_vfcvt_x_f_v_i64m2(vfloat64m2_t src, size_t vl) {467 return __riscv_vfcvt_x(src, vl);468}469 470// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfcvt_x_f_v_i64m4471// CHECK-RV64-SAME: (<vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {472// CHECK-RV64-NEXT: entry:473// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfcvt.x.f.v.nxv4i64.nxv4f64.i64(<vscale x 4 x i64> poison, <vscale x 4 x double> [[SRC]], i64 7, i64 [[VL]])474// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]475//476vint64m4_t test_vfcvt_x_f_v_i64m4(vfloat64m4_t src, size_t vl) {477 return __riscv_vfcvt_x(src, vl);478}479 480// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfcvt_x_f_v_i64m8481// CHECK-RV64-SAME: (<vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {482// CHECK-RV64-NEXT: entry:483// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfcvt.x.f.v.nxv8i64.nxv8f64.i64(<vscale x 8 x i64> poison, <vscale x 8 x double> [[SRC]], i64 7, i64 [[VL]])484// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]485//486vint64m8_t test_vfcvt_x_f_v_i64m8(vfloat64m8_t src, size_t vl) {487 return __riscv_vfcvt_x(src, vl);488}489 490// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfcvt_xu_f_v_u64m1491// CHECK-RV64-SAME: (<vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {492// CHECK-RV64-NEXT: entry:493// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv1i64.nxv1f64.i64(<vscale x 1 x i64> poison, <vscale x 1 x double> [[SRC]], i64 7, i64 [[VL]])494// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]495//496vuint64m1_t test_vfcvt_xu_f_v_u64m1(vfloat64m1_t src, size_t vl) {497 return __riscv_vfcvt_xu(src, vl);498}499 500// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfcvt_xu_f_v_u64m2501// CHECK-RV64-SAME: (<vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {502// CHECK-RV64-NEXT: entry:503// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv2i64.nxv2f64.i64(<vscale x 2 x i64> poison, <vscale x 2 x double> [[SRC]], i64 7, i64 [[VL]])504// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]505//506vuint64m2_t test_vfcvt_xu_f_v_u64m2(vfloat64m2_t src, size_t vl) {507 return __riscv_vfcvt_xu(src, vl);508}509 510// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfcvt_xu_f_v_u64m4511// CHECK-RV64-SAME: (<vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {512// CHECK-RV64-NEXT: entry:513// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv4i64.nxv4f64.i64(<vscale x 4 x i64> poison, <vscale x 4 x double> [[SRC]], i64 7, i64 [[VL]])514// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]515//516vuint64m4_t test_vfcvt_xu_f_v_u64m4(vfloat64m4_t src, size_t vl) {517 return __riscv_vfcvt_xu(src, vl);518}519 520// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfcvt_xu_f_v_u64m8521// CHECK-RV64-SAME: (<vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {522// CHECK-RV64-NEXT: entry:523// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv8i64.nxv8f64.i64(<vscale x 8 x i64> poison, <vscale x 8 x double> [[SRC]], i64 7, i64 [[VL]])524// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]525//526vuint64m8_t test_vfcvt_xu_f_v_u64m8(vfloat64m8_t src, size_t vl) {527 return __riscv_vfcvt_xu(src, vl);528}529 530// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfcvt_f_x_v_f64m1531// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {532// CHECK-RV64-NEXT: entry:533// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfcvt.f.x.v.nxv1f64.nxv1i64.i64(<vscale x 1 x double> poison, <vscale x 1 x i64> [[SRC]], i64 7, i64 [[VL]])534// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]535//536vfloat64m1_t test_vfcvt_f_x_v_f64m1(vint64m1_t src, size_t vl) {537 return __riscv_vfcvt_f(src, vl);538}539 540// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfcvt_f_x_v_f64m2541// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {542// CHECK-RV64-NEXT: entry:543// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfcvt.f.x.v.nxv2f64.nxv2i64.i64(<vscale x 2 x double> poison, <vscale x 2 x i64> [[SRC]], i64 7, i64 [[VL]])544// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]545//546vfloat64m2_t test_vfcvt_f_x_v_f64m2(vint64m2_t src, size_t vl) {547 return __riscv_vfcvt_f(src, vl);548}549 550// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfcvt_f_x_v_f64m4551// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {552// CHECK-RV64-NEXT: entry:553// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfcvt.f.x.v.nxv4f64.nxv4i64.i64(<vscale x 4 x double> poison, <vscale x 4 x i64> [[SRC]], i64 7, i64 [[VL]])554// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]555//556vfloat64m4_t test_vfcvt_f_x_v_f64m4(vint64m4_t src, size_t vl) {557 return __riscv_vfcvt_f(src, vl);558}559 560// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfcvt_f_x_v_f64m8561// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {562// CHECK-RV64-NEXT: entry:563// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfcvt.f.x.v.nxv8f64.nxv8i64.i64(<vscale x 8 x double> poison, <vscale x 8 x i64> [[SRC]], i64 7, i64 [[VL]])564// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]565//566vfloat64m8_t test_vfcvt_f_x_v_f64m8(vint64m8_t src, size_t vl) {567 return __riscv_vfcvt_f(src, vl);568}569 570// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfcvt_f_xu_v_f64m1571// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {572// CHECK-RV64-NEXT: entry:573// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfcvt.f.xu.v.nxv1f64.nxv1i64.i64(<vscale x 1 x double> poison, <vscale x 1 x i64> [[SRC]], i64 7, i64 [[VL]])574// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]575//576vfloat64m1_t test_vfcvt_f_xu_v_f64m1(vuint64m1_t src, size_t vl) {577 return __riscv_vfcvt_f(src, vl);578}579 580// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfcvt_f_xu_v_f64m2581// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {582// CHECK-RV64-NEXT: entry:583// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfcvt.f.xu.v.nxv2f64.nxv2i64.i64(<vscale x 2 x double> poison, <vscale x 2 x i64> [[SRC]], i64 7, i64 [[VL]])584// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]585//586vfloat64m2_t test_vfcvt_f_xu_v_f64m2(vuint64m2_t src, size_t vl) {587 return __riscv_vfcvt_f(src, vl);588}589 590// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfcvt_f_xu_v_f64m4591// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {592// CHECK-RV64-NEXT: entry:593// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfcvt.f.xu.v.nxv4f64.nxv4i64.i64(<vscale x 4 x double> poison, <vscale x 4 x i64> [[SRC]], i64 7, i64 [[VL]])594// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]595//596vfloat64m4_t test_vfcvt_f_xu_v_f64m4(vuint64m4_t src, size_t vl) {597 return __riscv_vfcvt_f(src, vl);598}599 600// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfcvt_f_xu_v_f64m8601// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {602// CHECK-RV64-NEXT: entry:603// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfcvt.f.xu.v.nxv8f64.nxv8i64.i64(<vscale x 8 x double> poison, <vscale x 8 x i64> [[SRC]], i64 7, i64 [[VL]])604// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]605//606vfloat64m8_t test_vfcvt_f_xu_v_f64m8(vuint64m8_t src, size_t vl) {607 return __riscv_vfcvt_f(src, vl);608}609 610// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vfcvt_x_f_v_i16mf4_m611// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {612// CHECK-RV64-NEXT: entry:613// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)614// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]615//616vint16mf4_t test_vfcvt_x_f_v_i16mf4_m(vbool64_t mask, vfloat16mf4_t src, size_t vl) {617 return __riscv_vfcvt_x(mask, src, vl);618}619 620// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vfcvt_x_f_v_i16mf2_m621// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {622// CHECK-RV64-NEXT: entry:623// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)624// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]625//626vint16mf2_t test_vfcvt_x_f_v_i16mf2_m(vbool32_t mask, vfloat16mf2_t src, size_t vl) {627 return __riscv_vfcvt_x(mask, src, vl);628}629 630// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfcvt_x_f_v_i16m1_m631// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {632// CHECK-RV64-NEXT: entry:633// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)634// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]635//636vint16m1_t test_vfcvt_x_f_v_i16m1_m(vbool16_t mask, vfloat16m1_t src, size_t vl) {637 return __riscv_vfcvt_x(mask, src, vl);638}639 640// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfcvt_x_f_v_i16m2_m641// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {642// CHECK-RV64-NEXT: entry:643// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)644// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]645//646vint16m2_t test_vfcvt_x_f_v_i16m2_m(vbool8_t mask, vfloat16m2_t src, size_t vl) {647 return __riscv_vfcvt_x(mask, src, vl);648}649 650// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfcvt_x_f_v_i16m4_m651// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {652// CHECK-RV64-NEXT: entry:653// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)654// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]655//656vint16m4_t test_vfcvt_x_f_v_i16m4_m(vbool4_t mask, vfloat16m4_t src, size_t vl) {657 return __riscv_vfcvt_x(mask, src, vl);658}659 660// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vfcvt_x_f_v_i16m8_m661// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {662// CHECK-RV64-NEXT: entry:663// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)664// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]665//666vint16m8_t test_vfcvt_x_f_v_i16m8_m(vbool2_t mask, vfloat16m8_t src, size_t vl) {667 return __riscv_vfcvt_x(mask, src, vl);668}669 670// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vfcvt_xu_f_v_u16mf4_m671// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {672// CHECK-RV64-NEXT: entry:673// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)674// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]675//676vuint16mf4_t test_vfcvt_xu_f_v_u16mf4_m(vbool64_t mask, vfloat16mf4_t src, size_t vl) {677 return __riscv_vfcvt_xu(mask, src, vl);678}679 680// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vfcvt_xu_f_v_u16mf2_m681// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {682// CHECK-RV64-NEXT: entry:683// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)684// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]685//686vuint16mf2_t test_vfcvt_xu_f_v_u16mf2_m(vbool32_t mask, vfloat16mf2_t src, size_t vl) {687 return __riscv_vfcvt_xu(mask, src, vl);688}689 690// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfcvt_xu_f_v_u16m1_m691// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {692// CHECK-RV64-NEXT: entry:693// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)694// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]695//696vuint16m1_t test_vfcvt_xu_f_v_u16m1_m(vbool16_t mask, vfloat16m1_t src, size_t vl) {697 return __riscv_vfcvt_xu(mask, src, vl);698}699 700// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfcvt_xu_f_v_u16m2_m701// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {702// CHECK-RV64-NEXT: entry:703// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)704// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]705//706vuint16m2_t test_vfcvt_xu_f_v_u16m2_m(vbool8_t mask, vfloat16m2_t src, size_t vl) {707 return __riscv_vfcvt_xu(mask, src, vl);708}709 710// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfcvt_xu_f_v_u16m4_m711// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {712// CHECK-RV64-NEXT: entry:713// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)714// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]715//716vuint16m4_t test_vfcvt_xu_f_v_u16m4_m(vbool4_t mask, vfloat16m4_t src, size_t vl) {717 return __riscv_vfcvt_xu(mask, src, vl);718}719 720// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vfcvt_xu_f_v_u16m8_m721// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {722// CHECK-RV64-NEXT: entry:723// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)724// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]725//726vuint16m8_t test_vfcvt_xu_f_v_u16m8_m(vbool2_t mask, vfloat16m8_t src, size_t vl) {727 return __riscv_vfcvt_xu(mask, src, vl);728}729 730// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfcvt_f_x_v_f16mf4_m731// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {732// CHECK-RV64-NEXT: entry:733// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv1f16.nxv1i16.i64(<vscale x 1 x half> poison, <vscale x 1 x i16> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)734// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]735//736vfloat16mf4_t test_vfcvt_f_x_v_f16mf4_m(vbool64_t mask, vint16mf4_t src, size_t vl) {737 return __riscv_vfcvt_f(mask, src, vl);738}739 740// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfcvt_f_x_v_f16mf2_m741// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {742// CHECK-RV64-NEXT: entry:743// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv2f16.nxv2i16.i64(<vscale x 2 x half> poison, <vscale x 2 x i16> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)744// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]745//746vfloat16mf2_t test_vfcvt_f_x_v_f16mf2_m(vbool32_t mask, vint16mf2_t src, size_t vl) {747 return __riscv_vfcvt_f(mask, src, vl);748}749 750// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfcvt_f_x_v_f16m1_m751// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {752// CHECK-RV64-NEXT: entry:753// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv4f16.nxv4i16.i64(<vscale x 4 x half> poison, <vscale x 4 x i16> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)754// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]755//756vfloat16m1_t test_vfcvt_f_x_v_f16m1_m(vbool16_t mask, vint16m1_t src, size_t vl) {757 return __riscv_vfcvt_f(mask, src, vl);758}759 760// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfcvt_f_x_v_f16m2_m761// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {762// CHECK-RV64-NEXT: entry:763// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv8f16.nxv8i16.i64(<vscale x 8 x half> poison, <vscale x 8 x i16> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)764// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]765//766vfloat16m2_t test_vfcvt_f_x_v_f16m2_m(vbool8_t mask, vint16m2_t src, size_t vl) {767 return __riscv_vfcvt_f(mask, src, vl);768}769 770// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfcvt_f_x_v_f16m4_m771// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {772// CHECK-RV64-NEXT: entry:773// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv16f16.nxv16i16.i64(<vscale x 16 x half> poison, <vscale x 16 x i16> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)774// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]775//776vfloat16m4_t test_vfcvt_f_x_v_f16m4_m(vbool4_t mask, vint16m4_t src, size_t vl) {777 return __riscv_vfcvt_f(mask, src, vl);778}779 780// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfcvt_f_x_v_f16m8_m781// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {782// CHECK-RV64-NEXT: entry:783// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv32f16.nxv32i16.i64(<vscale x 32 x half> poison, <vscale x 32 x i16> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)784// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]785//786vfloat16m8_t test_vfcvt_f_x_v_f16m8_m(vbool2_t mask, vint16m8_t src, size_t vl) {787 return __riscv_vfcvt_f(mask, src, vl);788}789 790// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfcvt_f_xu_v_f16mf4_m791// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {792// CHECK-RV64-NEXT: entry:793// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv1f16.nxv1i16.i64(<vscale x 1 x half> poison, <vscale x 1 x i16> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)794// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]795//796vfloat16mf4_t test_vfcvt_f_xu_v_f16mf4_m(vbool64_t mask, vuint16mf4_t src, size_t vl) {797 return __riscv_vfcvt_f(mask, src, vl);798}799 800// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfcvt_f_xu_v_f16mf2_m801// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {802// CHECK-RV64-NEXT: entry:803// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv2f16.nxv2i16.i64(<vscale x 2 x half> poison, <vscale x 2 x i16> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)804// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]805//806vfloat16mf2_t test_vfcvt_f_xu_v_f16mf2_m(vbool32_t mask, vuint16mf2_t src, size_t vl) {807 return __riscv_vfcvt_f(mask, src, vl);808}809 810// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfcvt_f_xu_v_f16m1_m811// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {812// CHECK-RV64-NEXT: entry:813// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv4f16.nxv4i16.i64(<vscale x 4 x half> poison, <vscale x 4 x i16> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)814// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]815//816vfloat16m1_t test_vfcvt_f_xu_v_f16m1_m(vbool16_t mask, vuint16m1_t src, size_t vl) {817 return __riscv_vfcvt_f(mask, src, vl);818}819 820// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfcvt_f_xu_v_f16m2_m821// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {822// CHECK-RV64-NEXT: entry:823// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv8f16.nxv8i16.i64(<vscale x 8 x half> poison, <vscale x 8 x i16> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)824// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]825//826vfloat16m2_t test_vfcvt_f_xu_v_f16m2_m(vbool8_t mask, vuint16m2_t src, size_t vl) {827 return __riscv_vfcvt_f(mask, src, vl);828}829 830// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfcvt_f_xu_v_f16m4_m831// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {832// CHECK-RV64-NEXT: entry:833// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv16f16.nxv16i16.i64(<vscale x 16 x half> poison, <vscale x 16 x i16> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)834// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]835//836vfloat16m4_t test_vfcvt_f_xu_v_f16m4_m(vbool4_t mask, vuint16m4_t src, size_t vl) {837 return __riscv_vfcvt_f(mask, src, vl);838}839 840// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfcvt_f_xu_v_f16m8_m841// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {842// CHECK-RV64-NEXT: entry:843// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv32f16.nxv32i16.i64(<vscale x 32 x half> poison, <vscale x 32 x i16> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)844// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]845//846vfloat16m8_t test_vfcvt_f_xu_v_f16m8_m(vbool2_t mask, vuint16m8_t src, size_t vl) {847 return __riscv_vfcvt_f(mask, src, vl);848}849 850// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfcvt_x_f_v_i32mf2_m851// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {852// CHECK-RV64-NEXT: entry:853// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv1i32.nxv1f32.i64(<vscale x 1 x i32> poison, <vscale x 1 x float> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)854// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]855//856vint32mf2_t test_vfcvt_x_f_v_i32mf2_m(vbool64_t mask, vfloat32mf2_t src, size_t vl) {857 return __riscv_vfcvt_x(mask, src, vl);858}859 860// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfcvt_x_f_v_i32m1_m861// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {862// CHECK-RV64-NEXT: entry:863// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv2i32.nxv2f32.i64(<vscale x 2 x i32> poison, <vscale x 2 x float> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)864// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]865//866vint32m1_t test_vfcvt_x_f_v_i32m1_m(vbool32_t mask, vfloat32m1_t src, size_t vl) {867 return __riscv_vfcvt_x(mask, src, vl);868}869 870// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfcvt_x_f_v_i32m2_m871// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {872// CHECK-RV64-NEXT: entry:873// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv4i32.nxv4f32.i64(<vscale x 4 x i32> poison, <vscale x 4 x float> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)874// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]875//876vint32m2_t test_vfcvt_x_f_v_i32m2_m(vbool16_t mask, vfloat32m2_t src, size_t vl) {877 return __riscv_vfcvt_x(mask, src, vl);878}879 880// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfcvt_x_f_v_i32m4_m881// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {882// CHECK-RV64-NEXT: entry:883// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv8i32.nxv8f32.i64(<vscale x 8 x i32> poison, <vscale x 8 x float> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)884// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]885//886vint32m4_t test_vfcvt_x_f_v_i32m4_m(vbool8_t mask, vfloat32m4_t src, size_t vl) {887 return __riscv_vfcvt_x(mask, src, vl);888}889 890// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfcvt_x_f_v_i32m8_m891// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {892// CHECK-RV64-NEXT: entry:893// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv16i32.nxv16f32.i64(<vscale x 16 x i32> poison, <vscale x 16 x float> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)894// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]895//896vint32m8_t test_vfcvt_x_f_v_i32m8_m(vbool4_t mask, vfloat32m8_t src, size_t vl) {897 return __riscv_vfcvt_x(mask, src, vl);898}899 900// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfcvt_xu_f_v_u32mf2_m901// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {902// CHECK-RV64-NEXT: entry:903// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i32.nxv1f32.i64(<vscale x 1 x i32> poison, <vscale x 1 x float> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)904// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]905//906vuint32mf2_t test_vfcvt_xu_f_v_u32mf2_m(vbool64_t mask, vfloat32mf2_t src, size_t vl) {907 return __riscv_vfcvt_xu(mask, src, vl);908}909 910// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfcvt_xu_f_v_u32m1_m911// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {912// CHECK-RV64-NEXT: entry:913// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i32.nxv2f32.i64(<vscale x 2 x i32> poison, <vscale x 2 x float> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)914// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]915//916vuint32m1_t test_vfcvt_xu_f_v_u32m1_m(vbool32_t mask, vfloat32m1_t src, size_t vl) {917 return __riscv_vfcvt_xu(mask, src, vl);918}919 920// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfcvt_xu_f_v_u32m2_m921// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {922// CHECK-RV64-NEXT: entry:923// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i32.nxv4f32.i64(<vscale x 4 x i32> poison, <vscale x 4 x float> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)924// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]925//926vuint32m2_t test_vfcvt_xu_f_v_u32m2_m(vbool16_t mask, vfloat32m2_t src, size_t vl) {927 return __riscv_vfcvt_xu(mask, src, vl);928}929 930// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfcvt_xu_f_v_u32m4_m931// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {932// CHECK-RV64-NEXT: entry:933// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i32.nxv8f32.i64(<vscale x 8 x i32> poison, <vscale x 8 x float> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)934// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]935//936vuint32m4_t test_vfcvt_xu_f_v_u32m4_m(vbool8_t mask, vfloat32m4_t src, size_t vl) {937 return __riscv_vfcvt_xu(mask, src, vl);938}939 940// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfcvt_xu_f_v_u32m8_m941// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {942// CHECK-RV64-NEXT: entry:943// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv16i32.nxv16f32.i64(<vscale x 16 x i32> poison, <vscale x 16 x float> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)944// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]945//946vuint32m8_t test_vfcvt_xu_f_v_u32m8_m(vbool4_t mask, vfloat32m8_t src, size_t vl) {947 return __riscv_vfcvt_xu(mask, src, vl);948}949 950// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfcvt_f_x_v_f32mf2_m951// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {952// CHECK-RV64-NEXT: entry:953// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv1f32.nxv1i32.i64(<vscale x 1 x float> poison, <vscale x 1 x i32> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)954// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]955//956vfloat32mf2_t test_vfcvt_f_x_v_f32mf2_m(vbool64_t mask, vint32mf2_t src, size_t vl) {957 return __riscv_vfcvt_f(mask, src, vl);958}959 960// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfcvt_f_x_v_f32m1_m961// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {962// CHECK-RV64-NEXT: entry:963// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv2f32.nxv2i32.i64(<vscale x 2 x float> poison, <vscale x 2 x i32> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)964// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]965//966vfloat32m1_t test_vfcvt_f_x_v_f32m1_m(vbool32_t mask, vint32m1_t src, size_t vl) {967 return __riscv_vfcvt_f(mask, src, vl);968}969 970// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfcvt_f_x_v_f32m2_m971// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {972// CHECK-RV64-NEXT: entry:973// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv4f32.nxv4i32.i64(<vscale x 4 x float> poison, <vscale x 4 x i32> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)974// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]975//976vfloat32m2_t test_vfcvt_f_x_v_f32m2_m(vbool16_t mask, vint32m2_t src, size_t vl) {977 return __riscv_vfcvt_f(mask, src, vl);978}979 980// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfcvt_f_x_v_f32m4_m981// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {982// CHECK-RV64-NEXT: entry:983// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv8f32.nxv8i32.i64(<vscale x 8 x float> poison, <vscale x 8 x i32> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)984// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]985//986vfloat32m4_t test_vfcvt_f_x_v_f32m4_m(vbool8_t mask, vint32m4_t src, size_t vl) {987 return __riscv_vfcvt_f(mask, src, vl);988}989 990// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfcvt_f_x_v_f32m8_m991// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {992// CHECK-RV64-NEXT: entry:993// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv16f32.nxv16i32.i64(<vscale x 16 x float> poison, <vscale x 16 x i32> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)994// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]995//996vfloat32m8_t test_vfcvt_f_x_v_f32m8_m(vbool4_t mask, vint32m8_t src, size_t vl) {997 return __riscv_vfcvt_f(mask, src, vl);998}999 1000// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfcvt_f_xu_v_f32mf2_m1001// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1002// CHECK-RV64-NEXT: entry:1003// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv1f32.nxv1i32.i64(<vscale x 1 x float> poison, <vscale x 1 x i32> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)1004// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]1005//1006vfloat32mf2_t test_vfcvt_f_xu_v_f32mf2_m(vbool64_t mask, vuint32mf2_t src, size_t vl) {1007 return __riscv_vfcvt_f(mask, src, vl);1008}1009 1010// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfcvt_f_xu_v_f32m1_m1011// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1012// CHECK-RV64-NEXT: entry:1013// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv2f32.nxv2i32.i64(<vscale x 2 x float> poison, <vscale x 2 x i32> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)1014// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]1015//1016vfloat32m1_t test_vfcvt_f_xu_v_f32m1_m(vbool32_t mask, vuint32m1_t src, size_t vl) {1017 return __riscv_vfcvt_f(mask, src, vl);1018}1019 1020// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfcvt_f_xu_v_f32m2_m1021// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1022// CHECK-RV64-NEXT: entry:1023// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv4f32.nxv4i32.i64(<vscale x 4 x float> poison, <vscale x 4 x i32> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)1024// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]1025//1026vfloat32m2_t test_vfcvt_f_xu_v_f32m2_m(vbool16_t mask, vuint32m2_t src, size_t vl) {1027 return __riscv_vfcvt_f(mask, src, vl);1028}1029 1030// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfcvt_f_xu_v_f32m4_m1031// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1032// CHECK-RV64-NEXT: entry:1033// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv8f32.nxv8i32.i64(<vscale x 8 x float> poison, <vscale x 8 x i32> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)1034// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]1035//1036vfloat32m4_t test_vfcvt_f_xu_v_f32m4_m(vbool8_t mask, vuint32m4_t src, size_t vl) {1037 return __riscv_vfcvt_f(mask, src, vl);1038}1039 1040// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfcvt_f_xu_v_f32m8_m1041// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1042// CHECK-RV64-NEXT: entry:1043// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv16f32.nxv16i32.i64(<vscale x 16 x float> poison, <vscale x 16 x i32> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)1044// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]1045//1046vfloat32m8_t test_vfcvt_f_xu_v_f32m8_m(vbool4_t mask, vuint32m8_t src, size_t vl) {1047 return __riscv_vfcvt_f(mask, src, vl);1048}1049 1050// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfcvt_x_f_v_i64m1_m1051// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1052// CHECK-RV64-NEXT: entry:1053// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfcvt.x.f.v.mask.nxv1i64.nxv1f64.i64(<vscale x 1 x i64> poison, <vscale x 1 x double> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)1054// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]1055//1056vint64m1_t test_vfcvt_x_f_v_i64m1_m(vbool64_t mask, vfloat64m1_t src, size_t vl) {1057 return __riscv_vfcvt_x(mask, src, vl);1058}1059 1060// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfcvt_x_f_v_i64m2_m1061// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1062// CHECK-RV64-NEXT: entry:1063// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfcvt.x.f.v.mask.nxv2i64.nxv2f64.i64(<vscale x 2 x i64> poison, <vscale x 2 x double> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)1064// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]1065//1066vint64m2_t test_vfcvt_x_f_v_i64m2_m(vbool32_t mask, vfloat64m2_t src, size_t vl) {1067 return __riscv_vfcvt_x(mask, src, vl);1068}1069 1070// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfcvt_x_f_v_i64m4_m1071// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1072// CHECK-RV64-NEXT: entry:1073// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfcvt.x.f.v.mask.nxv4i64.nxv4f64.i64(<vscale x 4 x i64> poison, <vscale x 4 x double> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)1074// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]1075//1076vint64m4_t test_vfcvt_x_f_v_i64m4_m(vbool16_t mask, vfloat64m4_t src, size_t vl) {1077 return __riscv_vfcvt_x(mask, src, vl);1078}1079 1080// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfcvt_x_f_v_i64m8_m1081// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1082// CHECK-RV64-NEXT: entry:1083// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfcvt.x.f.v.mask.nxv8i64.nxv8f64.i64(<vscale x 8 x i64> poison, <vscale x 8 x double> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)1084// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]1085//1086vint64m8_t test_vfcvt_x_f_v_i64m8_m(vbool8_t mask, vfloat64m8_t src, size_t vl) {1087 return __riscv_vfcvt_x(mask, src, vl);1088}1089 1090// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfcvt_xu_f_v_u64m1_m1091// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1092// CHECK-RV64-NEXT: entry:1093// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i64.nxv1f64.i64(<vscale x 1 x i64> poison, <vscale x 1 x double> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)1094// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]1095//1096vuint64m1_t test_vfcvt_xu_f_v_u64m1_m(vbool64_t mask, vfloat64m1_t src, size_t vl) {1097 return __riscv_vfcvt_xu(mask, src, vl);1098}1099 1100// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfcvt_xu_f_v_u64m2_m1101// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1102// CHECK-RV64-NEXT: entry:1103// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i64.nxv2f64.i64(<vscale x 2 x i64> poison, <vscale x 2 x double> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)1104// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]1105//1106vuint64m2_t test_vfcvt_xu_f_v_u64m2_m(vbool32_t mask, vfloat64m2_t src, size_t vl) {1107 return __riscv_vfcvt_xu(mask, src, vl);1108}1109 1110// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfcvt_xu_f_v_u64m4_m1111// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1112// CHECK-RV64-NEXT: entry:1113// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i64.nxv4f64.i64(<vscale x 4 x i64> poison, <vscale x 4 x double> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)1114// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]1115//1116vuint64m4_t test_vfcvt_xu_f_v_u64m4_m(vbool16_t mask, vfloat64m4_t src, size_t vl) {1117 return __riscv_vfcvt_xu(mask, src, vl);1118}1119 1120// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfcvt_xu_f_v_u64m8_m1121// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1122// CHECK-RV64-NEXT: entry:1123// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i64.nxv8f64.i64(<vscale x 8 x i64> poison, <vscale x 8 x double> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)1124// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]1125//1126vuint64m8_t test_vfcvt_xu_f_v_u64m8_m(vbool8_t mask, vfloat64m8_t src, size_t vl) {1127 return __riscv_vfcvt_xu(mask, src, vl);1128}1129 1130// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfcvt_f_x_v_f64m1_m1131// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1132// CHECK-RV64-NEXT: entry:1133// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfcvt.f.x.v.mask.nxv1f64.nxv1i64.i64(<vscale x 1 x double> poison, <vscale x 1 x i64> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)1134// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]1135//1136vfloat64m1_t test_vfcvt_f_x_v_f64m1_m(vbool64_t mask, vint64m1_t src, size_t vl) {1137 return __riscv_vfcvt_f(mask, src, vl);1138}1139 1140// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfcvt_f_x_v_f64m2_m1141// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1142// CHECK-RV64-NEXT: entry:1143// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfcvt.f.x.v.mask.nxv2f64.nxv2i64.i64(<vscale x 2 x double> poison, <vscale x 2 x i64> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)1144// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]1145//1146vfloat64m2_t test_vfcvt_f_x_v_f64m2_m(vbool32_t mask, vint64m2_t src, size_t vl) {1147 return __riscv_vfcvt_f(mask, src, vl);1148}1149 1150// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfcvt_f_x_v_f64m4_m1151// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1152// CHECK-RV64-NEXT: entry:1153// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfcvt.f.x.v.mask.nxv4f64.nxv4i64.i64(<vscale x 4 x double> poison, <vscale x 4 x i64> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)1154// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]1155//1156vfloat64m4_t test_vfcvt_f_x_v_f64m4_m(vbool16_t mask, vint64m4_t src, size_t vl) {1157 return __riscv_vfcvt_f(mask, src, vl);1158}1159 1160// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfcvt_f_x_v_f64m8_m1161// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1162// CHECK-RV64-NEXT: entry:1163// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfcvt.f.x.v.mask.nxv8f64.nxv8i64.i64(<vscale x 8 x double> poison, <vscale x 8 x i64> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)1164// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]1165//1166vfloat64m8_t test_vfcvt_f_x_v_f64m8_m(vbool8_t mask, vint64m8_t src, size_t vl) {1167 return __riscv_vfcvt_f(mask, src, vl);1168}1169 1170// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfcvt_f_xu_v_f64m1_m1171// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1172// CHECK-RV64-NEXT: entry:1173// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfcvt.f.xu.v.mask.nxv1f64.nxv1i64.i64(<vscale x 1 x double> poison, <vscale x 1 x i64> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)1174// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]1175//1176vfloat64m1_t test_vfcvt_f_xu_v_f64m1_m(vbool64_t mask, vuint64m1_t src, size_t vl) {1177 return __riscv_vfcvt_f(mask, src, vl);1178}1179 1180// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfcvt_f_xu_v_f64m2_m1181// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1182// CHECK-RV64-NEXT: entry:1183// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfcvt.f.xu.v.mask.nxv2f64.nxv2i64.i64(<vscale x 2 x double> poison, <vscale x 2 x i64> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)1184// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]1185//1186vfloat64m2_t test_vfcvt_f_xu_v_f64m2_m(vbool32_t mask, vuint64m2_t src, size_t vl) {1187 return __riscv_vfcvt_f(mask, src, vl);1188}1189 1190// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfcvt_f_xu_v_f64m4_m1191// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1192// CHECK-RV64-NEXT: entry:1193// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfcvt.f.xu.v.mask.nxv4f64.nxv4i64.i64(<vscale x 4 x double> poison, <vscale x 4 x i64> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)1194// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]1195//1196vfloat64m4_t test_vfcvt_f_xu_v_f64m4_m(vbool16_t mask, vuint64m4_t src, size_t vl) {1197 return __riscv_vfcvt_f(mask, src, vl);1198}1199 1200// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfcvt_f_xu_v_f64m8_m1201// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1202// CHECK-RV64-NEXT: entry:1203// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfcvt.f.xu.v.mask.nxv8f64.nxv8i64.i64(<vscale x 8 x double> poison, <vscale x 8 x i64> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)1204// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]1205//1206vfloat64m8_t test_vfcvt_f_xu_v_f64m8_m(vbool8_t mask, vuint64m8_t src, size_t vl) {1207 return __riscv_vfcvt_f(mask, src, vl);1208}1209 1210// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vfcvt_x_f_v_i16mf4_rm1211// CHECK-RV64-SAME: (<vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1212// CHECK-RV64-NEXT: entry:1213// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> [[SRC]], i64 0, i64 [[VL]])1214// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]1215//1216vint16mf4_t test_vfcvt_x_f_v_i16mf4_rm(vfloat16mf4_t src, size_t vl) {1217 return __riscv_vfcvt_x(src, __RISCV_FRM_RNE, vl);1218}1219 1220// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vfcvt_x_f_v_i16mf2_rm1221// CHECK-RV64-SAME: (<vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1222// CHECK-RV64-NEXT: entry:1223// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> [[SRC]], i64 0, i64 [[VL]])1224// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]1225//1226vint16mf2_t test_vfcvt_x_f_v_i16mf2_rm(vfloat16mf2_t src, size_t vl) {1227 return __riscv_vfcvt_x(src, __RISCV_FRM_RNE, vl);1228}1229 1230// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfcvt_x_f_v_i16m1_rm1231// CHECK-RV64-SAME: (<vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1232// CHECK-RV64-NEXT: entry:1233// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> [[SRC]], i64 0, i64 [[VL]])1234// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]1235//1236vint16m1_t test_vfcvt_x_f_v_i16m1_rm(vfloat16m1_t src, size_t vl) {1237 return __riscv_vfcvt_x(src, __RISCV_FRM_RNE, vl);1238}1239 1240// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfcvt_x_f_v_i16m2_rm1241// CHECK-RV64-SAME: (<vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1242// CHECK-RV64-NEXT: entry:1243// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> [[SRC]], i64 0, i64 [[VL]])1244// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]1245//1246vint16m2_t test_vfcvt_x_f_v_i16m2_rm(vfloat16m2_t src, size_t vl) {1247 return __riscv_vfcvt_x(src, __RISCV_FRM_RNE, vl);1248}1249 1250// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfcvt_x_f_v_i16m4_rm1251// CHECK-RV64-SAME: (<vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1252// CHECK-RV64-NEXT: entry:1253// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> [[SRC]], i64 0, i64 [[VL]])1254// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]1255//1256vint16m4_t test_vfcvt_x_f_v_i16m4_rm(vfloat16m4_t src, size_t vl) {1257 return __riscv_vfcvt_x(src, __RISCV_FRM_RNE, vl);1258}1259 1260// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vfcvt_x_f_v_i16m8_rm1261// CHECK-RV64-SAME: (<vscale x 32 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1262// CHECK-RV64-NEXT: entry:1263// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> [[SRC]], i64 0, i64 [[VL]])1264// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]1265//1266vint16m8_t test_vfcvt_x_f_v_i16m8_rm(vfloat16m8_t src, size_t vl) {1267 return __riscv_vfcvt_x(src, __RISCV_FRM_RNE, vl);1268}1269 1270// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vfcvt_xu_f_v_u16mf4_rm1271// CHECK-RV64-SAME: (<vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1272// CHECK-RV64-NEXT: entry:1273// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> [[SRC]], i64 0, i64 [[VL]])1274// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]1275//1276vuint16mf4_t test_vfcvt_xu_f_v_u16mf4_rm(vfloat16mf4_t src, size_t vl) {1277 return __riscv_vfcvt_xu(src, __RISCV_FRM_RNE, vl);1278}1279 1280// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vfcvt_xu_f_v_u16mf2_rm1281// CHECK-RV64-SAME: (<vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1282// CHECK-RV64-NEXT: entry:1283// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> [[SRC]], i64 0, i64 [[VL]])1284// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]1285//1286vuint16mf2_t test_vfcvt_xu_f_v_u16mf2_rm(vfloat16mf2_t src, size_t vl) {1287 return __riscv_vfcvt_xu(src, __RISCV_FRM_RNE, vl);1288}1289 1290// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfcvt_xu_f_v_u16m1_rm1291// CHECK-RV64-SAME: (<vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1292// CHECK-RV64-NEXT: entry:1293// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> [[SRC]], i64 0, i64 [[VL]])1294// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]1295//1296vuint16m1_t test_vfcvt_xu_f_v_u16m1_rm(vfloat16m1_t src, size_t vl) {1297 return __riscv_vfcvt_xu(src, __RISCV_FRM_RNE, vl);1298}1299 1300// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfcvt_xu_f_v_u16m2_rm1301// CHECK-RV64-SAME: (<vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1302// CHECK-RV64-NEXT: entry:1303// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> [[SRC]], i64 0, i64 [[VL]])1304// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]1305//1306vuint16m2_t test_vfcvt_xu_f_v_u16m2_rm(vfloat16m2_t src, size_t vl) {1307 return __riscv_vfcvt_xu(src, __RISCV_FRM_RNE, vl);1308}1309 1310// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfcvt_xu_f_v_u16m4_rm1311// CHECK-RV64-SAME: (<vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1312// CHECK-RV64-NEXT: entry:1313// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> [[SRC]], i64 0, i64 [[VL]])1314// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]1315//1316vuint16m4_t test_vfcvt_xu_f_v_u16m4_rm(vfloat16m4_t src, size_t vl) {1317 return __riscv_vfcvt_xu(src, __RISCV_FRM_RNE, vl);1318}1319 1320// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vfcvt_xu_f_v_u16m8_rm1321// CHECK-RV64-SAME: (<vscale x 32 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1322// CHECK-RV64-NEXT: entry:1323// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> [[SRC]], i64 0, i64 [[VL]])1324// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]1325//1326vuint16m8_t test_vfcvt_xu_f_v_u16m8_rm(vfloat16m8_t src, size_t vl) {1327 return __riscv_vfcvt_xu(src, __RISCV_FRM_RNE, vl);1328}1329 1330// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfcvt_f_x_v_f16mf4_rm1331// CHECK-RV64-SAME: (<vscale x 1 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1332// CHECK-RV64-NEXT: entry:1333// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfcvt.f.x.v.nxv1f16.nxv1i16.i64(<vscale x 1 x half> poison, <vscale x 1 x i16> [[SRC]], i64 0, i64 [[VL]])1334// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]1335//1336vfloat16mf4_t test_vfcvt_f_x_v_f16mf4_rm(vint16mf4_t src, size_t vl) {1337 return __riscv_vfcvt_f(src, __RISCV_FRM_RNE, vl);1338}1339 1340// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfcvt_f_x_v_f16mf2_rm1341// CHECK-RV64-SAME: (<vscale x 2 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1342// CHECK-RV64-NEXT: entry:1343// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfcvt.f.x.v.nxv2f16.nxv2i16.i64(<vscale x 2 x half> poison, <vscale x 2 x i16> [[SRC]], i64 0, i64 [[VL]])1344// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]1345//1346vfloat16mf2_t test_vfcvt_f_x_v_f16mf2_rm(vint16mf2_t src, size_t vl) {1347 return __riscv_vfcvt_f(src, __RISCV_FRM_RNE, vl);1348}1349 1350// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfcvt_f_x_v_f16m1_rm1351// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1352// CHECK-RV64-NEXT: entry:1353// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfcvt.f.x.v.nxv4f16.nxv4i16.i64(<vscale x 4 x half> poison, <vscale x 4 x i16> [[SRC]], i64 0, i64 [[VL]])1354// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]1355//1356vfloat16m1_t test_vfcvt_f_x_v_f16m1_rm(vint16m1_t src, size_t vl) {1357 return __riscv_vfcvt_f(src, __RISCV_FRM_RNE, vl);1358}1359 1360// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfcvt_f_x_v_f16m2_rm1361// CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1362// CHECK-RV64-NEXT: entry:1363// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfcvt.f.x.v.nxv8f16.nxv8i16.i64(<vscale x 8 x half> poison, <vscale x 8 x i16> [[SRC]], i64 0, i64 [[VL]])1364// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]1365//1366vfloat16m2_t test_vfcvt_f_x_v_f16m2_rm(vint16m2_t src, size_t vl) {1367 return __riscv_vfcvt_f(src, __RISCV_FRM_RNE, vl);1368}1369 1370// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfcvt_f_x_v_f16m4_rm1371// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1372// CHECK-RV64-NEXT: entry:1373// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfcvt.f.x.v.nxv16f16.nxv16i16.i64(<vscale x 16 x half> poison, <vscale x 16 x i16> [[SRC]], i64 0, i64 [[VL]])1374// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]1375//1376vfloat16m4_t test_vfcvt_f_x_v_f16m4_rm(vint16m4_t src, size_t vl) {1377 return __riscv_vfcvt_f(src, __RISCV_FRM_RNE, vl);1378}1379 1380// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfcvt_f_x_v_f16m8_rm1381// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1382// CHECK-RV64-NEXT: entry:1383// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfcvt.f.x.v.nxv32f16.nxv32i16.i64(<vscale x 32 x half> poison, <vscale x 32 x i16> [[SRC]], i64 0, i64 [[VL]])1384// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]1385//1386vfloat16m8_t test_vfcvt_f_x_v_f16m8_rm(vint16m8_t src, size_t vl) {1387 return __riscv_vfcvt_f(src, __RISCV_FRM_RNE, vl);1388}1389 1390// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfcvt_f_xu_v_f16mf4_rm1391// CHECK-RV64-SAME: (<vscale x 1 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1392// CHECK-RV64-NEXT: entry:1393// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfcvt.f.xu.v.nxv1f16.nxv1i16.i64(<vscale x 1 x half> poison, <vscale x 1 x i16> [[SRC]], i64 0, i64 [[VL]])1394// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]1395//1396vfloat16mf4_t test_vfcvt_f_xu_v_f16mf4_rm(vuint16mf4_t src, size_t vl) {1397 return __riscv_vfcvt_f(src, __RISCV_FRM_RNE, vl);1398}1399 1400// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfcvt_f_xu_v_f16mf2_rm1401// CHECK-RV64-SAME: (<vscale x 2 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1402// CHECK-RV64-NEXT: entry:1403// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfcvt.f.xu.v.nxv2f16.nxv2i16.i64(<vscale x 2 x half> poison, <vscale x 2 x i16> [[SRC]], i64 0, i64 [[VL]])1404// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]1405//1406vfloat16mf2_t test_vfcvt_f_xu_v_f16mf2_rm(vuint16mf2_t src, size_t vl) {1407 return __riscv_vfcvt_f(src, __RISCV_FRM_RNE, vl);1408}1409 1410// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfcvt_f_xu_v_f16m1_rm1411// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1412// CHECK-RV64-NEXT: entry:1413// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfcvt.f.xu.v.nxv4f16.nxv4i16.i64(<vscale x 4 x half> poison, <vscale x 4 x i16> [[SRC]], i64 0, i64 [[VL]])1414// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]1415//1416vfloat16m1_t test_vfcvt_f_xu_v_f16m1_rm(vuint16m1_t src, size_t vl) {1417 return __riscv_vfcvt_f(src, __RISCV_FRM_RNE, vl);1418}1419 1420// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfcvt_f_xu_v_f16m2_rm1421// CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1422// CHECK-RV64-NEXT: entry:1423// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfcvt.f.xu.v.nxv8f16.nxv8i16.i64(<vscale x 8 x half> poison, <vscale x 8 x i16> [[SRC]], i64 0, i64 [[VL]])1424// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]1425//1426vfloat16m2_t test_vfcvt_f_xu_v_f16m2_rm(vuint16m2_t src, size_t vl) {1427 return __riscv_vfcvt_f(src, __RISCV_FRM_RNE, vl);1428}1429 1430// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfcvt_f_xu_v_f16m4_rm1431// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1432// CHECK-RV64-NEXT: entry:1433// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfcvt.f.xu.v.nxv16f16.nxv16i16.i64(<vscale x 16 x half> poison, <vscale x 16 x i16> [[SRC]], i64 0, i64 [[VL]])1434// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]1435//1436vfloat16m4_t test_vfcvt_f_xu_v_f16m4_rm(vuint16m4_t src, size_t vl) {1437 return __riscv_vfcvt_f(src, __RISCV_FRM_RNE, vl);1438}1439 1440// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfcvt_f_xu_v_f16m8_rm1441// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1442// CHECK-RV64-NEXT: entry:1443// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfcvt.f.xu.v.nxv32f16.nxv32i16.i64(<vscale x 32 x half> poison, <vscale x 32 x i16> [[SRC]], i64 0, i64 [[VL]])1444// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]1445//1446vfloat16m8_t test_vfcvt_f_xu_v_f16m8_rm(vuint16m8_t src, size_t vl) {1447 return __riscv_vfcvt_f(src, __RISCV_FRM_RNE, vl);1448}1449 1450// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfcvt_x_f_v_i32mf2_rm1451// CHECK-RV64-SAME: (<vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1452// CHECK-RV64-NEXT: entry:1453// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfcvt.x.f.v.nxv1i32.nxv1f32.i64(<vscale x 1 x i32> poison, <vscale x 1 x float> [[SRC]], i64 0, i64 [[VL]])1454// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]1455//1456vint32mf2_t test_vfcvt_x_f_v_i32mf2_rm(vfloat32mf2_t src, size_t vl) {1457 return __riscv_vfcvt_x(src, __RISCV_FRM_RNE, vl);1458}1459 1460// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfcvt_x_f_v_i32m1_rm1461// CHECK-RV64-SAME: (<vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1462// CHECK-RV64-NEXT: entry:1463// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfcvt.x.f.v.nxv2i32.nxv2f32.i64(<vscale x 2 x i32> poison, <vscale x 2 x float> [[SRC]], i64 0, i64 [[VL]])1464// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]1465//1466vint32m1_t test_vfcvt_x_f_v_i32m1_rm(vfloat32m1_t src, size_t vl) {1467 return __riscv_vfcvt_x(src, __RISCV_FRM_RNE, vl);1468}1469 1470// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfcvt_x_f_v_i32m2_rm1471// CHECK-RV64-SAME: (<vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1472// CHECK-RV64-NEXT: entry:1473// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfcvt.x.f.v.nxv4i32.nxv4f32.i64(<vscale x 4 x i32> poison, <vscale x 4 x float> [[SRC]], i64 0, i64 [[VL]])1474// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]1475//1476vint32m2_t test_vfcvt_x_f_v_i32m2_rm(vfloat32m2_t src, size_t vl) {1477 return __riscv_vfcvt_x(src, __RISCV_FRM_RNE, vl);1478}1479 1480// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfcvt_x_f_v_i32m4_rm1481// CHECK-RV64-SAME: (<vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1482// CHECK-RV64-NEXT: entry:1483// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfcvt.x.f.v.nxv8i32.nxv8f32.i64(<vscale x 8 x i32> poison, <vscale x 8 x float> [[SRC]], i64 0, i64 [[VL]])1484// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]1485//1486vint32m4_t test_vfcvt_x_f_v_i32m4_rm(vfloat32m4_t src, size_t vl) {1487 return __riscv_vfcvt_x(src, __RISCV_FRM_RNE, vl);1488}1489 1490// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfcvt_x_f_v_i32m8_rm1491// CHECK-RV64-SAME: (<vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1492// CHECK-RV64-NEXT: entry:1493// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfcvt.x.f.v.nxv16i32.nxv16f32.i64(<vscale x 16 x i32> poison, <vscale x 16 x float> [[SRC]], i64 0, i64 [[VL]])1494// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]1495//1496vint32m8_t test_vfcvt_x_f_v_i32m8_rm(vfloat32m8_t src, size_t vl) {1497 return __riscv_vfcvt_x(src, __RISCV_FRM_RNE, vl);1498}1499 1500// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfcvt_xu_f_v_u32mf2_rm1501// CHECK-RV64-SAME: (<vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1502// CHECK-RV64-NEXT: entry:1503// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv1i32.nxv1f32.i64(<vscale x 1 x i32> poison, <vscale x 1 x float> [[SRC]], i64 0, i64 [[VL]])1504// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]1505//1506vuint32mf2_t test_vfcvt_xu_f_v_u32mf2_rm(vfloat32mf2_t src, size_t vl) {1507 return __riscv_vfcvt_xu(src, __RISCV_FRM_RNE, vl);1508}1509 1510// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfcvt_xu_f_v_u32m1_rm1511// CHECK-RV64-SAME: (<vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1512// CHECK-RV64-NEXT: entry:1513// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv2i32.nxv2f32.i64(<vscale x 2 x i32> poison, <vscale x 2 x float> [[SRC]], i64 0, i64 [[VL]])1514// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]1515//1516vuint32m1_t test_vfcvt_xu_f_v_u32m1_rm(vfloat32m1_t src, size_t vl) {1517 return __riscv_vfcvt_xu(src, __RISCV_FRM_RNE, vl);1518}1519 1520// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfcvt_xu_f_v_u32m2_rm1521// CHECK-RV64-SAME: (<vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1522// CHECK-RV64-NEXT: entry:1523// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv4i32.nxv4f32.i64(<vscale x 4 x i32> poison, <vscale x 4 x float> [[SRC]], i64 0, i64 [[VL]])1524// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]1525//1526vuint32m2_t test_vfcvt_xu_f_v_u32m2_rm(vfloat32m2_t src, size_t vl) {1527 return __riscv_vfcvt_xu(src, __RISCV_FRM_RNE, vl);1528}1529 1530// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfcvt_xu_f_v_u32m4_rm1531// CHECK-RV64-SAME: (<vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1532// CHECK-RV64-NEXT: entry:1533// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv8i32.nxv8f32.i64(<vscale x 8 x i32> poison, <vscale x 8 x float> [[SRC]], i64 0, i64 [[VL]])1534// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]1535//1536vuint32m4_t test_vfcvt_xu_f_v_u32m4_rm(vfloat32m4_t src, size_t vl) {1537 return __riscv_vfcvt_xu(src, __RISCV_FRM_RNE, vl);1538}1539 1540// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfcvt_xu_f_v_u32m8_rm1541// CHECK-RV64-SAME: (<vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1542// CHECK-RV64-NEXT: entry:1543// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv16i32.nxv16f32.i64(<vscale x 16 x i32> poison, <vscale x 16 x float> [[SRC]], i64 0, i64 [[VL]])1544// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]1545//1546vuint32m8_t test_vfcvt_xu_f_v_u32m8_rm(vfloat32m8_t src, size_t vl) {1547 return __riscv_vfcvt_xu(src, __RISCV_FRM_RNE, vl);1548}1549 1550// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfcvt_f_x_v_f32mf2_rm1551// CHECK-RV64-SAME: (<vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1552// CHECK-RV64-NEXT: entry:1553// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfcvt.f.x.v.nxv1f32.nxv1i32.i64(<vscale x 1 x float> poison, <vscale x 1 x i32> [[SRC]], i64 0, i64 [[VL]])1554// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]1555//1556vfloat32mf2_t test_vfcvt_f_x_v_f32mf2_rm(vint32mf2_t src, size_t vl) {1557 return __riscv_vfcvt_f(src, __RISCV_FRM_RNE, vl);1558}1559 1560// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfcvt_f_x_v_f32m1_rm1561// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1562// CHECK-RV64-NEXT: entry:1563// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfcvt.f.x.v.nxv2f32.nxv2i32.i64(<vscale x 2 x float> poison, <vscale x 2 x i32> [[SRC]], i64 0, i64 [[VL]])1564// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]1565//1566vfloat32m1_t test_vfcvt_f_x_v_f32m1_rm(vint32m1_t src, size_t vl) {1567 return __riscv_vfcvt_f(src, __RISCV_FRM_RNE, vl);1568}1569 1570// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfcvt_f_x_v_f32m2_rm1571// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1572// CHECK-RV64-NEXT: entry:1573// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfcvt.f.x.v.nxv4f32.nxv4i32.i64(<vscale x 4 x float> poison, <vscale x 4 x i32> [[SRC]], i64 0, i64 [[VL]])1574// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]1575//1576vfloat32m2_t test_vfcvt_f_x_v_f32m2_rm(vint32m2_t src, size_t vl) {1577 return __riscv_vfcvt_f(src, __RISCV_FRM_RNE, vl);1578}1579 1580// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfcvt_f_x_v_f32m4_rm1581// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1582// CHECK-RV64-NEXT: entry:1583// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfcvt.f.x.v.nxv8f32.nxv8i32.i64(<vscale x 8 x float> poison, <vscale x 8 x i32> [[SRC]], i64 0, i64 [[VL]])1584// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]1585//1586vfloat32m4_t test_vfcvt_f_x_v_f32m4_rm(vint32m4_t src, size_t vl) {1587 return __riscv_vfcvt_f(src, __RISCV_FRM_RNE, vl);1588}1589 1590// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfcvt_f_x_v_f32m8_rm1591// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1592// CHECK-RV64-NEXT: entry:1593// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfcvt.f.x.v.nxv16f32.nxv16i32.i64(<vscale x 16 x float> poison, <vscale x 16 x i32> [[SRC]], i64 0, i64 [[VL]])1594// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]1595//1596vfloat32m8_t test_vfcvt_f_x_v_f32m8_rm(vint32m8_t src, size_t vl) {1597 return __riscv_vfcvt_f(src, __RISCV_FRM_RNE, vl);1598}1599 1600// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfcvt_f_xu_v_f32mf2_rm1601// CHECK-RV64-SAME: (<vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1602// CHECK-RV64-NEXT: entry:1603// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfcvt.f.xu.v.nxv1f32.nxv1i32.i64(<vscale x 1 x float> poison, <vscale x 1 x i32> [[SRC]], i64 0, i64 [[VL]])1604// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]1605//1606vfloat32mf2_t test_vfcvt_f_xu_v_f32mf2_rm(vuint32mf2_t src, size_t vl) {1607 return __riscv_vfcvt_f(src, __RISCV_FRM_RNE, vl);1608}1609 1610// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfcvt_f_xu_v_f32m1_rm1611// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1612// CHECK-RV64-NEXT: entry:1613// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfcvt.f.xu.v.nxv2f32.nxv2i32.i64(<vscale x 2 x float> poison, <vscale x 2 x i32> [[SRC]], i64 0, i64 [[VL]])1614// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]1615//1616vfloat32m1_t test_vfcvt_f_xu_v_f32m1_rm(vuint32m1_t src, size_t vl) {1617 return __riscv_vfcvt_f(src, __RISCV_FRM_RNE, vl);1618}1619 1620// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfcvt_f_xu_v_f32m2_rm1621// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1622// CHECK-RV64-NEXT: entry:1623// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfcvt.f.xu.v.nxv4f32.nxv4i32.i64(<vscale x 4 x float> poison, <vscale x 4 x i32> [[SRC]], i64 0, i64 [[VL]])1624// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]1625//1626vfloat32m2_t test_vfcvt_f_xu_v_f32m2_rm(vuint32m2_t src, size_t vl) {1627 return __riscv_vfcvt_f(src, __RISCV_FRM_RNE, vl);1628}1629 1630// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfcvt_f_xu_v_f32m4_rm1631// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1632// CHECK-RV64-NEXT: entry:1633// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfcvt.f.xu.v.nxv8f32.nxv8i32.i64(<vscale x 8 x float> poison, <vscale x 8 x i32> [[SRC]], i64 0, i64 [[VL]])1634// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]1635//1636vfloat32m4_t test_vfcvt_f_xu_v_f32m4_rm(vuint32m4_t src, size_t vl) {1637 return __riscv_vfcvt_f(src, __RISCV_FRM_RNE, vl);1638}1639 1640// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfcvt_f_xu_v_f32m8_rm1641// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1642// CHECK-RV64-NEXT: entry:1643// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfcvt.f.xu.v.nxv16f32.nxv16i32.i64(<vscale x 16 x float> poison, <vscale x 16 x i32> [[SRC]], i64 0, i64 [[VL]])1644// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]1645//1646vfloat32m8_t test_vfcvt_f_xu_v_f32m8_rm(vuint32m8_t src, size_t vl) {1647 return __riscv_vfcvt_f(src, __RISCV_FRM_RNE, vl);1648}1649 1650// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfcvt_x_f_v_i64m1_rm1651// CHECK-RV64-SAME: (<vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1652// CHECK-RV64-NEXT: entry:1653// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfcvt.x.f.v.nxv1i64.nxv1f64.i64(<vscale x 1 x i64> poison, <vscale x 1 x double> [[SRC]], i64 0, i64 [[VL]])1654// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]1655//1656vint64m1_t test_vfcvt_x_f_v_i64m1_rm(vfloat64m1_t src, size_t vl) {1657 return __riscv_vfcvt_x(src, __RISCV_FRM_RNE, vl);1658}1659 1660// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfcvt_x_f_v_i64m2_rm1661// CHECK-RV64-SAME: (<vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1662// CHECK-RV64-NEXT: entry:1663// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfcvt.x.f.v.nxv2i64.nxv2f64.i64(<vscale x 2 x i64> poison, <vscale x 2 x double> [[SRC]], i64 0, i64 [[VL]])1664// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]1665//1666vint64m2_t test_vfcvt_x_f_v_i64m2_rm(vfloat64m2_t src, size_t vl) {1667 return __riscv_vfcvt_x(src, __RISCV_FRM_RNE, vl);1668}1669 1670// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfcvt_x_f_v_i64m4_rm1671// CHECK-RV64-SAME: (<vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1672// CHECK-RV64-NEXT: entry:1673// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfcvt.x.f.v.nxv4i64.nxv4f64.i64(<vscale x 4 x i64> poison, <vscale x 4 x double> [[SRC]], i64 0, i64 [[VL]])1674// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]1675//1676vint64m4_t test_vfcvt_x_f_v_i64m4_rm(vfloat64m4_t src, size_t vl) {1677 return __riscv_vfcvt_x(src, __RISCV_FRM_RNE, vl);1678}1679 1680// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfcvt_x_f_v_i64m8_rm1681// CHECK-RV64-SAME: (<vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1682// CHECK-RV64-NEXT: entry:1683// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfcvt.x.f.v.nxv8i64.nxv8f64.i64(<vscale x 8 x i64> poison, <vscale x 8 x double> [[SRC]], i64 0, i64 [[VL]])1684// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]1685//1686vint64m8_t test_vfcvt_x_f_v_i64m8_rm(vfloat64m8_t src, size_t vl) {1687 return __riscv_vfcvt_x(src, __RISCV_FRM_RNE, vl);1688}1689 1690// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfcvt_xu_f_v_u64m1_rm1691// CHECK-RV64-SAME: (<vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1692// CHECK-RV64-NEXT: entry:1693// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv1i64.nxv1f64.i64(<vscale x 1 x i64> poison, <vscale x 1 x double> [[SRC]], i64 0, i64 [[VL]])1694// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]1695//1696vuint64m1_t test_vfcvt_xu_f_v_u64m1_rm(vfloat64m1_t src, size_t vl) {1697 return __riscv_vfcvt_xu(src, __RISCV_FRM_RNE, vl);1698}1699 1700// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfcvt_xu_f_v_u64m2_rm1701// CHECK-RV64-SAME: (<vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1702// CHECK-RV64-NEXT: entry:1703// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv2i64.nxv2f64.i64(<vscale x 2 x i64> poison, <vscale x 2 x double> [[SRC]], i64 0, i64 [[VL]])1704// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]1705//1706vuint64m2_t test_vfcvt_xu_f_v_u64m2_rm(vfloat64m2_t src, size_t vl) {1707 return __riscv_vfcvt_xu(src, __RISCV_FRM_RNE, vl);1708}1709 1710// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfcvt_xu_f_v_u64m4_rm1711// CHECK-RV64-SAME: (<vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1712// CHECK-RV64-NEXT: entry:1713// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv4i64.nxv4f64.i64(<vscale x 4 x i64> poison, <vscale x 4 x double> [[SRC]], i64 0, i64 [[VL]])1714// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]1715//1716vuint64m4_t test_vfcvt_xu_f_v_u64m4_rm(vfloat64m4_t src, size_t vl) {1717 return __riscv_vfcvt_xu(src, __RISCV_FRM_RNE, vl);1718}1719 1720// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfcvt_xu_f_v_u64m8_rm1721// CHECK-RV64-SAME: (<vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1722// CHECK-RV64-NEXT: entry:1723// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv8i64.nxv8f64.i64(<vscale x 8 x i64> poison, <vscale x 8 x double> [[SRC]], i64 0, i64 [[VL]])1724// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]1725//1726vuint64m8_t test_vfcvt_xu_f_v_u64m8_rm(vfloat64m8_t src, size_t vl) {1727 return __riscv_vfcvt_xu(src, __RISCV_FRM_RNE, vl);1728}1729 1730// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfcvt_f_x_v_f64m1_rm1731// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1732// CHECK-RV64-NEXT: entry:1733// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfcvt.f.x.v.nxv1f64.nxv1i64.i64(<vscale x 1 x double> poison, <vscale x 1 x i64> [[SRC]], i64 0, i64 [[VL]])1734// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]1735//1736vfloat64m1_t test_vfcvt_f_x_v_f64m1_rm(vint64m1_t src, size_t vl) {1737 return __riscv_vfcvt_f(src, __RISCV_FRM_RNE, vl);1738}1739 1740// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfcvt_f_x_v_f64m2_rm1741// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1742// CHECK-RV64-NEXT: entry:1743// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfcvt.f.x.v.nxv2f64.nxv2i64.i64(<vscale x 2 x double> poison, <vscale x 2 x i64> [[SRC]], i64 0, i64 [[VL]])1744// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]1745//1746vfloat64m2_t test_vfcvt_f_x_v_f64m2_rm(vint64m2_t src, size_t vl) {1747 return __riscv_vfcvt_f(src, __RISCV_FRM_RNE, vl);1748}1749 1750// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfcvt_f_x_v_f64m4_rm1751// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1752// CHECK-RV64-NEXT: entry:1753// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfcvt.f.x.v.nxv4f64.nxv4i64.i64(<vscale x 4 x double> poison, <vscale x 4 x i64> [[SRC]], i64 0, i64 [[VL]])1754// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]1755//1756vfloat64m4_t test_vfcvt_f_x_v_f64m4_rm(vint64m4_t src, size_t vl) {1757 return __riscv_vfcvt_f(src, __RISCV_FRM_RNE, vl);1758}1759 1760// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfcvt_f_x_v_f64m8_rm1761// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1762// CHECK-RV64-NEXT: entry:1763// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfcvt.f.x.v.nxv8f64.nxv8i64.i64(<vscale x 8 x double> poison, <vscale x 8 x i64> [[SRC]], i64 0, i64 [[VL]])1764// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]1765//1766vfloat64m8_t test_vfcvt_f_x_v_f64m8_rm(vint64m8_t src, size_t vl) {1767 return __riscv_vfcvt_f(src, __RISCV_FRM_RNE, vl);1768}1769 1770// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfcvt_f_xu_v_f64m1_rm1771// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1772// CHECK-RV64-NEXT: entry:1773// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfcvt.f.xu.v.nxv1f64.nxv1i64.i64(<vscale x 1 x double> poison, <vscale x 1 x i64> [[SRC]], i64 0, i64 [[VL]])1774// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]1775//1776vfloat64m1_t test_vfcvt_f_xu_v_f64m1_rm(vuint64m1_t src, size_t vl) {1777 return __riscv_vfcvt_f(src, __RISCV_FRM_RNE, vl);1778}1779 1780// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfcvt_f_xu_v_f64m2_rm1781// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1782// CHECK-RV64-NEXT: entry:1783// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfcvt.f.xu.v.nxv2f64.nxv2i64.i64(<vscale x 2 x double> poison, <vscale x 2 x i64> [[SRC]], i64 0, i64 [[VL]])1784// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]1785//1786vfloat64m2_t test_vfcvt_f_xu_v_f64m2_rm(vuint64m2_t src, size_t vl) {1787 return __riscv_vfcvt_f(src, __RISCV_FRM_RNE, vl);1788}1789 1790// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfcvt_f_xu_v_f64m4_rm1791// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1792// CHECK-RV64-NEXT: entry:1793// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfcvt.f.xu.v.nxv4f64.nxv4i64.i64(<vscale x 4 x double> poison, <vscale x 4 x i64> [[SRC]], i64 0, i64 [[VL]])1794// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]1795//1796vfloat64m4_t test_vfcvt_f_xu_v_f64m4_rm(vuint64m4_t src, size_t vl) {1797 return __riscv_vfcvt_f(src, __RISCV_FRM_RNE, vl);1798}1799 1800// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfcvt_f_xu_v_f64m8_rm1801// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1802// CHECK-RV64-NEXT: entry:1803// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfcvt.f.xu.v.nxv8f64.nxv8i64.i64(<vscale x 8 x double> poison, <vscale x 8 x i64> [[SRC]], i64 0, i64 [[VL]])1804// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]1805//1806vfloat64m8_t test_vfcvt_f_xu_v_f64m8_rm(vuint64m8_t src, size_t vl) {1807 return __riscv_vfcvt_f(src, __RISCV_FRM_RNE, vl);1808}1809 1810// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vfcvt_x_f_v_i16mf4_rm_m1811// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1812// CHECK-RV64-NEXT: entry:1813// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1814// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]1815//1816vint16mf4_t test_vfcvt_x_f_v_i16mf4_rm_m(vbool64_t mask, vfloat16mf4_t src, size_t vl) {1817 return __riscv_vfcvt_x(mask, src, __RISCV_FRM_RNE, vl);1818}1819 1820// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vfcvt_x_f_v_i16mf2_rm_m1821// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1822// CHECK-RV64-NEXT: entry:1823// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1824// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]1825//1826vint16mf2_t test_vfcvt_x_f_v_i16mf2_rm_m(vbool32_t mask, vfloat16mf2_t src, size_t vl) {1827 return __riscv_vfcvt_x(mask, src, __RISCV_FRM_RNE, vl);1828}1829 1830// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfcvt_x_f_v_i16m1_rm_m1831// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1832// CHECK-RV64-NEXT: entry:1833// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1834// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]1835//1836vint16m1_t test_vfcvt_x_f_v_i16m1_rm_m(vbool16_t mask, vfloat16m1_t src, size_t vl) {1837 return __riscv_vfcvt_x(mask, src, __RISCV_FRM_RNE, vl);1838}1839 1840// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfcvt_x_f_v_i16m2_rm_m1841// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1842// CHECK-RV64-NEXT: entry:1843// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1844// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]1845//1846vint16m2_t test_vfcvt_x_f_v_i16m2_rm_m(vbool8_t mask, vfloat16m2_t src, size_t vl) {1847 return __riscv_vfcvt_x(mask, src, __RISCV_FRM_RNE, vl);1848}1849 1850// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfcvt_x_f_v_i16m4_rm_m1851// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1852// CHECK-RV64-NEXT: entry:1853// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1854// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]1855//1856vint16m4_t test_vfcvt_x_f_v_i16m4_rm_m(vbool4_t mask, vfloat16m4_t src, size_t vl) {1857 return __riscv_vfcvt_x(mask, src, __RISCV_FRM_RNE, vl);1858}1859 1860// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vfcvt_x_f_v_i16m8_rm_m1861// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1862// CHECK-RV64-NEXT: entry:1863// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1864// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]1865//1866vint16m8_t test_vfcvt_x_f_v_i16m8_rm_m(vbool2_t mask, vfloat16m8_t src, size_t vl) {1867 return __riscv_vfcvt_x(mask, src, __RISCV_FRM_RNE, vl);1868}1869 1870// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vfcvt_xu_f_v_u16mf4_rm_m1871// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1872// CHECK-RV64-NEXT: entry:1873// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1874// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]1875//1876vuint16mf4_t test_vfcvt_xu_f_v_u16mf4_rm_m(vbool64_t mask, vfloat16mf4_t src, size_t vl) {1877 return __riscv_vfcvt_xu(mask, src, __RISCV_FRM_RNE, vl);1878}1879 1880// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vfcvt_xu_f_v_u16mf2_rm_m1881// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1882// CHECK-RV64-NEXT: entry:1883// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1884// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]1885//1886vuint16mf2_t test_vfcvt_xu_f_v_u16mf2_rm_m(vbool32_t mask, vfloat16mf2_t src, size_t vl) {1887 return __riscv_vfcvt_xu(mask, src, __RISCV_FRM_RNE, vl);1888}1889 1890// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfcvt_xu_f_v_u16m1_rm_m1891// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1892// CHECK-RV64-NEXT: entry:1893// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1894// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]1895//1896vuint16m1_t test_vfcvt_xu_f_v_u16m1_rm_m(vbool16_t mask, vfloat16m1_t src, size_t vl) {1897 return __riscv_vfcvt_xu(mask, src, __RISCV_FRM_RNE, vl);1898}1899 1900// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfcvt_xu_f_v_u16m2_rm_m1901// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1902// CHECK-RV64-NEXT: entry:1903// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1904// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]1905//1906vuint16m2_t test_vfcvt_xu_f_v_u16m2_rm_m(vbool8_t mask, vfloat16m2_t src, size_t vl) {1907 return __riscv_vfcvt_xu(mask, src, __RISCV_FRM_RNE, vl);1908}1909 1910// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfcvt_xu_f_v_u16m4_rm_m1911// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1912// CHECK-RV64-NEXT: entry:1913// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1914// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]1915//1916vuint16m4_t test_vfcvt_xu_f_v_u16m4_rm_m(vbool4_t mask, vfloat16m4_t src, size_t vl) {1917 return __riscv_vfcvt_xu(mask, src, __RISCV_FRM_RNE, vl);1918}1919 1920// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vfcvt_xu_f_v_u16m8_rm_m1921// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1922// CHECK-RV64-NEXT: entry:1923// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1924// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]1925//1926vuint16m8_t test_vfcvt_xu_f_v_u16m8_rm_m(vbool2_t mask, vfloat16m8_t src, size_t vl) {1927 return __riscv_vfcvt_xu(mask, src, __RISCV_FRM_RNE, vl);1928}1929 1930// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfcvt_f_x_v_f16mf4_rm_m1931// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1932// CHECK-RV64-NEXT: entry:1933// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv1f16.nxv1i16.i64(<vscale x 1 x half> poison, <vscale x 1 x i16> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1934// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]1935//1936vfloat16mf4_t test_vfcvt_f_x_v_f16mf4_rm_m(vbool64_t mask, vint16mf4_t src, size_t vl) {1937 return __riscv_vfcvt_f(mask, src, __RISCV_FRM_RNE, vl);1938}1939 1940// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfcvt_f_x_v_f16mf2_rm_m1941// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1942// CHECK-RV64-NEXT: entry:1943// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv2f16.nxv2i16.i64(<vscale x 2 x half> poison, <vscale x 2 x i16> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1944// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]1945//1946vfloat16mf2_t test_vfcvt_f_x_v_f16mf2_rm_m(vbool32_t mask, vint16mf2_t src, size_t vl) {1947 return __riscv_vfcvt_f(mask, src, __RISCV_FRM_RNE, vl);1948}1949 1950// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfcvt_f_x_v_f16m1_rm_m1951// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1952// CHECK-RV64-NEXT: entry:1953// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv4f16.nxv4i16.i64(<vscale x 4 x half> poison, <vscale x 4 x i16> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1954// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]1955//1956vfloat16m1_t test_vfcvt_f_x_v_f16m1_rm_m(vbool16_t mask, vint16m1_t src, size_t vl) {1957 return __riscv_vfcvt_f(mask, src, __RISCV_FRM_RNE, vl);1958}1959 1960// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfcvt_f_x_v_f16m2_rm_m1961// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1962// CHECK-RV64-NEXT: entry:1963// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv8f16.nxv8i16.i64(<vscale x 8 x half> poison, <vscale x 8 x i16> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1964// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]1965//1966vfloat16m2_t test_vfcvt_f_x_v_f16m2_rm_m(vbool8_t mask, vint16m2_t src, size_t vl) {1967 return __riscv_vfcvt_f(mask, src, __RISCV_FRM_RNE, vl);1968}1969 1970// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfcvt_f_x_v_f16m4_rm_m1971// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1972// CHECK-RV64-NEXT: entry:1973// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv16f16.nxv16i16.i64(<vscale x 16 x half> poison, <vscale x 16 x i16> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1974// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]1975//1976vfloat16m4_t test_vfcvt_f_x_v_f16m4_rm_m(vbool4_t mask, vint16m4_t src, size_t vl) {1977 return __riscv_vfcvt_f(mask, src, __RISCV_FRM_RNE, vl);1978}1979 1980// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfcvt_f_x_v_f16m8_rm_m1981// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1982// CHECK-RV64-NEXT: entry:1983// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv32f16.nxv32i16.i64(<vscale x 32 x half> poison, <vscale x 32 x i16> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1984// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]1985//1986vfloat16m8_t test_vfcvt_f_x_v_f16m8_rm_m(vbool2_t mask, vint16m8_t src, size_t vl) {1987 return __riscv_vfcvt_f(mask, src, __RISCV_FRM_RNE, vl);1988}1989 1990// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfcvt_f_xu_v_f16mf4_rm_m1991// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1992// CHECK-RV64-NEXT: entry:1993// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv1f16.nxv1i16.i64(<vscale x 1 x half> poison, <vscale x 1 x i16> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)1994// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]1995//1996vfloat16mf4_t test_vfcvt_f_xu_v_f16mf4_rm_m(vbool64_t mask, vuint16mf4_t src, size_t vl) {1997 return __riscv_vfcvt_f(mask, src, __RISCV_FRM_RNE, vl);1998}1999 2000// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfcvt_f_xu_v_f16mf2_rm_m2001// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2002// CHECK-RV64-NEXT: entry:2003// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv2f16.nxv2i16.i64(<vscale x 2 x half> poison, <vscale x 2 x i16> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)2004// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]2005//2006vfloat16mf2_t test_vfcvt_f_xu_v_f16mf2_rm_m(vbool32_t mask, vuint16mf2_t src, size_t vl) {2007 return __riscv_vfcvt_f(mask, src, __RISCV_FRM_RNE, vl);2008}2009 2010// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfcvt_f_xu_v_f16m1_rm_m2011// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2012// CHECK-RV64-NEXT: entry:2013// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv4f16.nxv4i16.i64(<vscale x 4 x half> poison, <vscale x 4 x i16> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)2014// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]2015//2016vfloat16m1_t test_vfcvt_f_xu_v_f16m1_rm_m(vbool16_t mask, vuint16m1_t src, size_t vl) {2017 return __riscv_vfcvt_f(mask, src, __RISCV_FRM_RNE, vl);2018}2019 2020// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfcvt_f_xu_v_f16m2_rm_m2021// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2022// CHECK-RV64-NEXT: entry:2023// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv8f16.nxv8i16.i64(<vscale x 8 x half> poison, <vscale x 8 x i16> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)2024// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]2025//2026vfloat16m2_t test_vfcvt_f_xu_v_f16m2_rm_m(vbool8_t mask, vuint16m2_t src, size_t vl) {2027 return __riscv_vfcvt_f(mask, src, __RISCV_FRM_RNE, vl);2028}2029 2030// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfcvt_f_xu_v_f16m4_rm_m2031// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2032// CHECK-RV64-NEXT: entry:2033// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv16f16.nxv16i16.i64(<vscale x 16 x half> poison, <vscale x 16 x i16> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)2034// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]2035//2036vfloat16m4_t test_vfcvt_f_xu_v_f16m4_rm_m(vbool4_t mask, vuint16m4_t src, size_t vl) {2037 return __riscv_vfcvt_f(mask, src, __RISCV_FRM_RNE, vl);2038}2039 2040// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfcvt_f_xu_v_f16m8_rm_m2041// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2042// CHECK-RV64-NEXT: entry:2043// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv32f16.nxv32i16.i64(<vscale x 32 x half> poison, <vscale x 32 x i16> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)2044// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]2045//2046vfloat16m8_t test_vfcvt_f_xu_v_f16m8_rm_m(vbool2_t mask, vuint16m8_t src, size_t vl) {2047 return __riscv_vfcvt_f(mask, src, __RISCV_FRM_RNE, vl);2048}2049 2050// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfcvt_x_f_v_i32mf2_rm_m2051// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2052// CHECK-RV64-NEXT: entry:2053// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv1i32.nxv1f32.i64(<vscale x 1 x i32> poison, <vscale x 1 x float> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)2054// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]2055//2056vint32mf2_t test_vfcvt_x_f_v_i32mf2_rm_m(vbool64_t mask, vfloat32mf2_t src, size_t vl) {2057 return __riscv_vfcvt_x(mask, src, __RISCV_FRM_RNE, vl);2058}2059 2060// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfcvt_x_f_v_i32m1_rm_m2061// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2062// CHECK-RV64-NEXT: entry:2063// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv2i32.nxv2f32.i64(<vscale x 2 x i32> poison, <vscale x 2 x float> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)2064// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]2065//2066vint32m1_t test_vfcvt_x_f_v_i32m1_rm_m(vbool32_t mask, vfloat32m1_t src, size_t vl) {2067 return __riscv_vfcvt_x(mask, src, __RISCV_FRM_RNE, vl);2068}2069 2070// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfcvt_x_f_v_i32m2_rm_m2071// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2072// CHECK-RV64-NEXT: entry:2073// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv4i32.nxv4f32.i64(<vscale x 4 x i32> poison, <vscale x 4 x float> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)2074// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]2075//2076vint32m2_t test_vfcvt_x_f_v_i32m2_rm_m(vbool16_t mask, vfloat32m2_t src, size_t vl) {2077 return __riscv_vfcvt_x(mask, src, __RISCV_FRM_RNE, vl);2078}2079 2080// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfcvt_x_f_v_i32m4_rm_m2081// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2082// CHECK-RV64-NEXT: entry:2083// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv8i32.nxv8f32.i64(<vscale x 8 x i32> poison, <vscale x 8 x float> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)2084// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]2085//2086vint32m4_t test_vfcvt_x_f_v_i32m4_rm_m(vbool8_t mask, vfloat32m4_t src, size_t vl) {2087 return __riscv_vfcvt_x(mask, src, __RISCV_FRM_RNE, vl);2088}2089 2090// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfcvt_x_f_v_i32m8_rm_m2091// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2092// CHECK-RV64-NEXT: entry:2093// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv16i32.nxv16f32.i64(<vscale x 16 x i32> poison, <vscale x 16 x float> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)2094// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]2095//2096vint32m8_t test_vfcvt_x_f_v_i32m8_rm_m(vbool4_t mask, vfloat32m8_t src, size_t vl) {2097 return __riscv_vfcvt_x(mask, src, __RISCV_FRM_RNE, vl);2098}2099 2100// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfcvt_xu_f_v_u32mf2_rm_m2101// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2102// CHECK-RV64-NEXT: entry:2103// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i32.nxv1f32.i64(<vscale x 1 x i32> poison, <vscale x 1 x float> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)2104// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]2105//2106vuint32mf2_t test_vfcvt_xu_f_v_u32mf2_rm_m(vbool64_t mask, vfloat32mf2_t src, size_t vl) {2107 return __riscv_vfcvt_xu(mask, src, __RISCV_FRM_RNE, vl);2108}2109 2110// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfcvt_xu_f_v_u32m1_rm_m2111// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2112// CHECK-RV64-NEXT: entry:2113// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i32.nxv2f32.i64(<vscale x 2 x i32> poison, <vscale x 2 x float> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)2114// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]2115//2116vuint32m1_t test_vfcvt_xu_f_v_u32m1_rm_m(vbool32_t mask, vfloat32m1_t src, size_t vl) {2117 return __riscv_vfcvt_xu(mask, src, __RISCV_FRM_RNE, vl);2118}2119 2120// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfcvt_xu_f_v_u32m2_rm_m2121// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2122// CHECK-RV64-NEXT: entry:2123// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i32.nxv4f32.i64(<vscale x 4 x i32> poison, <vscale x 4 x float> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)2124// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]2125//2126vuint32m2_t test_vfcvt_xu_f_v_u32m2_rm_m(vbool16_t mask, vfloat32m2_t src, size_t vl) {2127 return __riscv_vfcvt_xu(mask, src, __RISCV_FRM_RNE, vl);2128}2129 2130// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfcvt_xu_f_v_u32m4_rm_m2131// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2132// CHECK-RV64-NEXT: entry:2133// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i32.nxv8f32.i64(<vscale x 8 x i32> poison, <vscale x 8 x float> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)2134// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]2135//2136vuint32m4_t test_vfcvt_xu_f_v_u32m4_rm_m(vbool8_t mask, vfloat32m4_t src, size_t vl) {2137 return __riscv_vfcvt_xu(mask, src, __RISCV_FRM_RNE, vl);2138}2139 2140// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfcvt_xu_f_v_u32m8_rm_m2141// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2142// CHECK-RV64-NEXT: entry:2143// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv16i32.nxv16f32.i64(<vscale x 16 x i32> poison, <vscale x 16 x float> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)2144// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]2145//2146vuint32m8_t test_vfcvt_xu_f_v_u32m8_rm_m(vbool4_t mask, vfloat32m8_t src, size_t vl) {2147 return __riscv_vfcvt_xu(mask, src, __RISCV_FRM_RNE, vl);2148}2149 2150// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfcvt_f_x_v_f32mf2_rm_m2151// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2152// CHECK-RV64-NEXT: entry:2153// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv1f32.nxv1i32.i64(<vscale x 1 x float> poison, <vscale x 1 x i32> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)2154// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]2155//2156vfloat32mf2_t test_vfcvt_f_x_v_f32mf2_rm_m(vbool64_t mask, vint32mf2_t src, size_t vl) {2157 return __riscv_vfcvt_f(mask, src, __RISCV_FRM_RNE, vl);2158}2159 2160// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfcvt_f_x_v_f32m1_rm_m2161// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2162// CHECK-RV64-NEXT: entry:2163// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv2f32.nxv2i32.i64(<vscale x 2 x float> poison, <vscale x 2 x i32> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)2164// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]2165//2166vfloat32m1_t test_vfcvt_f_x_v_f32m1_rm_m(vbool32_t mask, vint32m1_t src, size_t vl) {2167 return __riscv_vfcvt_f(mask, src, __RISCV_FRM_RNE, vl);2168}2169 2170// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfcvt_f_x_v_f32m2_rm_m2171// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2172// CHECK-RV64-NEXT: entry:2173// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv4f32.nxv4i32.i64(<vscale x 4 x float> poison, <vscale x 4 x i32> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)2174// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]2175//2176vfloat32m2_t test_vfcvt_f_x_v_f32m2_rm_m(vbool16_t mask, vint32m2_t src, size_t vl) {2177 return __riscv_vfcvt_f(mask, src, __RISCV_FRM_RNE, vl);2178}2179 2180// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfcvt_f_x_v_f32m4_rm_m2181// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2182// CHECK-RV64-NEXT: entry:2183// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv8f32.nxv8i32.i64(<vscale x 8 x float> poison, <vscale x 8 x i32> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)2184// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]2185//2186vfloat32m4_t test_vfcvt_f_x_v_f32m4_rm_m(vbool8_t mask, vint32m4_t src, size_t vl) {2187 return __riscv_vfcvt_f(mask, src, __RISCV_FRM_RNE, vl);2188}2189 2190// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfcvt_f_x_v_f32m8_rm_m2191// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2192// CHECK-RV64-NEXT: entry:2193// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv16f32.nxv16i32.i64(<vscale x 16 x float> poison, <vscale x 16 x i32> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)2194// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]2195//2196vfloat32m8_t test_vfcvt_f_x_v_f32m8_rm_m(vbool4_t mask, vint32m8_t src, size_t vl) {2197 return __riscv_vfcvt_f(mask, src, __RISCV_FRM_RNE, vl);2198}2199 2200// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfcvt_f_xu_v_f32mf2_rm_m2201// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2202// CHECK-RV64-NEXT: entry:2203// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv1f32.nxv1i32.i64(<vscale x 1 x float> poison, <vscale x 1 x i32> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)2204// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]2205//2206vfloat32mf2_t test_vfcvt_f_xu_v_f32mf2_rm_m(vbool64_t mask, vuint32mf2_t src, size_t vl) {2207 return __riscv_vfcvt_f(mask, src, __RISCV_FRM_RNE, vl);2208}2209 2210// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfcvt_f_xu_v_f32m1_rm_m2211// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2212// CHECK-RV64-NEXT: entry:2213// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv2f32.nxv2i32.i64(<vscale x 2 x float> poison, <vscale x 2 x i32> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)2214// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]2215//2216vfloat32m1_t test_vfcvt_f_xu_v_f32m1_rm_m(vbool32_t mask, vuint32m1_t src, size_t vl) {2217 return __riscv_vfcvt_f(mask, src, __RISCV_FRM_RNE, vl);2218}2219 2220// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfcvt_f_xu_v_f32m2_rm_m2221// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2222// CHECK-RV64-NEXT: entry:2223// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv4f32.nxv4i32.i64(<vscale x 4 x float> poison, <vscale x 4 x i32> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)2224// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]2225//2226vfloat32m2_t test_vfcvt_f_xu_v_f32m2_rm_m(vbool16_t mask, vuint32m2_t src, size_t vl) {2227 return __riscv_vfcvt_f(mask, src, __RISCV_FRM_RNE, vl);2228}2229 2230// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfcvt_f_xu_v_f32m4_rm_m2231// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2232// CHECK-RV64-NEXT: entry:2233// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv8f32.nxv8i32.i64(<vscale x 8 x float> poison, <vscale x 8 x i32> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)2234// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]2235//2236vfloat32m4_t test_vfcvt_f_xu_v_f32m4_rm_m(vbool8_t mask, vuint32m4_t src, size_t vl) {2237 return __riscv_vfcvt_f(mask, src, __RISCV_FRM_RNE, vl);2238}2239 2240// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfcvt_f_xu_v_f32m8_rm_m2241// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2242// CHECK-RV64-NEXT: entry:2243// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv16f32.nxv16i32.i64(<vscale x 16 x float> poison, <vscale x 16 x i32> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)2244// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]2245//2246vfloat32m8_t test_vfcvt_f_xu_v_f32m8_rm_m(vbool4_t mask, vuint32m8_t src, size_t vl) {2247 return __riscv_vfcvt_f(mask, src, __RISCV_FRM_RNE, vl);2248}2249 2250// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfcvt_x_f_v_i64m1_rm_m2251// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2252// CHECK-RV64-NEXT: entry:2253// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfcvt.x.f.v.mask.nxv1i64.nxv1f64.i64(<vscale x 1 x i64> poison, <vscale x 1 x double> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)2254// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]2255//2256vint64m1_t test_vfcvt_x_f_v_i64m1_rm_m(vbool64_t mask, vfloat64m1_t src, size_t vl) {2257 return __riscv_vfcvt_x(mask, src, __RISCV_FRM_RNE, vl);2258}2259 2260// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfcvt_x_f_v_i64m2_rm_m2261// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2262// CHECK-RV64-NEXT: entry:2263// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfcvt.x.f.v.mask.nxv2i64.nxv2f64.i64(<vscale x 2 x i64> poison, <vscale x 2 x double> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)2264// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]2265//2266vint64m2_t test_vfcvt_x_f_v_i64m2_rm_m(vbool32_t mask, vfloat64m2_t src, size_t vl) {2267 return __riscv_vfcvt_x(mask, src, __RISCV_FRM_RNE, vl);2268}2269 2270// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfcvt_x_f_v_i64m4_rm_m2271// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2272// CHECK-RV64-NEXT: entry:2273// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfcvt.x.f.v.mask.nxv4i64.nxv4f64.i64(<vscale x 4 x i64> poison, <vscale x 4 x double> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)2274// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]2275//2276vint64m4_t test_vfcvt_x_f_v_i64m4_rm_m(vbool16_t mask, vfloat64m4_t src, size_t vl) {2277 return __riscv_vfcvt_x(mask, src, __RISCV_FRM_RNE, vl);2278}2279 2280// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfcvt_x_f_v_i64m8_rm_m2281// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2282// CHECK-RV64-NEXT: entry:2283// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfcvt.x.f.v.mask.nxv8i64.nxv8f64.i64(<vscale x 8 x i64> poison, <vscale x 8 x double> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)2284// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]2285//2286vint64m8_t test_vfcvt_x_f_v_i64m8_rm_m(vbool8_t mask, vfloat64m8_t src, size_t vl) {2287 return __riscv_vfcvt_x(mask, src, __RISCV_FRM_RNE, vl);2288}2289 2290// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfcvt_xu_f_v_u64m1_rm_m2291// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2292// CHECK-RV64-NEXT: entry:2293// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i64.nxv1f64.i64(<vscale x 1 x i64> poison, <vscale x 1 x double> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)2294// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]2295//2296vuint64m1_t test_vfcvt_xu_f_v_u64m1_rm_m(vbool64_t mask, vfloat64m1_t src, size_t vl) {2297 return __riscv_vfcvt_xu(mask, src, __RISCV_FRM_RNE, vl);2298}2299 2300// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfcvt_xu_f_v_u64m2_rm_m2301// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2302// CHECK-RV64-NEXT: entry:2303// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i64.nxv2f64.i64(<vscale x 2 x i64> poison, <vscale x 2 x double> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)2304// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]2305//2306vuint64m2_t test_vfcvt_xu_f_v_u64m2_rm_m(vbool32_t mask, vfloat64m2_t src, size_t vl) {2307 return __riscv_vfcvt_xu(mask, src, __RISCV_FRM_RNE, vl);2308}2309 2310// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfcvt_xu_f_v_u64m4_rm_m2311// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2312// CHECK-RV64-NEXT: entry:2313// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i64.nxv4f64.i64(<vscale x 4 x i64> poison, <vscale x 4 x double> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)2314// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]2315//2316vuint64m4_t test_vfcvt_xu_f_v_u64m4_rm_m(vbool16_t mask, vfloat64m4_t src, size_t vl) {2317 return __riscv_vfcvt_xu(mask, src, __RISCV_FRM_RNE, vl);2318}2319 2320// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfcvt_xu_f_v_u64m8_rm_m2321// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2322// CHECK-RV64-NEXT: entry:2323// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i64.nxv8f64.i64(<vscale x 8 x i64> poison, <vscale x 8 x double> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)2324// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]2325//2326vuint64m8_t test_vfcvt_xu_f_v_u64m8_rm_m(vbool8_t mask, vfloat64m8_t src, size_t vl) {2327 return __riscv_vfcvt_xu(mask, src, __RISCV_FRM_RNE, vl);2328}2329 2330// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfcvt_f_x_v_f64m1_rm_m2331// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2332// CHECK-RV64-NEXT: entry:2333// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfcvt.f.x.v.mask.nxv1f64.nxv1i64.i64(<vscale x 1 x double> poison, <vscale x 1 x i64> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)2334// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]2335//2336vfloat64m1_t test_vfcvt_f_x_v_f64m1_rm_m(vbool64_t mask, vint64m1_t src, size_t vl) {2337 return __riscv_vfcvt_f(mask, src, __RISCV_FRM_RNE, vl);2338}2339 2340// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfcvt_f_x_v_f64m2_rm_m2341// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2342// CHECK-RV64-NEXT: entry:2343// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfcvt.f.x.v.mask.nxv2f64.nxv2i64.i64(<vscale x 2 x double> poison, <vscale x 2 x i64> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)2344// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]2345//2346vfloat64m2_t test_vfcvt_f_x_v_f64m2_rm_m(vbool32_t mask, vint64m2_t src, size_t vl) {2347 return __riscv_vfcvt_f(mask, src, __RISCV_FRM_RNE, vl);2348}2349 2350// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfcvt_f_x_v_f64m4_rm_m2351// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2352// CHECK-RV64-NEXT: entry:2353// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfcvt.f.x.v.mask.nxv4f64.nxv4i64.i64(<vscale x 4 x double> poison, <vscale x 4 x i64> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)2354// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]2355//2356vfloat64m4_t test_vfcvt_f_x_v_f64m4_rm_m(vbool16_t mask, vint64m4_t src, size_t vl) {2357 return __riscv_vfcvt_f(mask, src, __RISCV_FRM_RNE, vl);2358}2359 2360// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfcvt_f_x_v_f64m8_rm_m2361// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2362// CHECK-RV64-NEXT: entry:2363// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfcvt.f.x.v.mask.nxv8f64.nxv8i64.i64(<vscale x 8 x double> poison, <vscale x 8 x i64> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)2364// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]2365//2366vfloat64m8_t test_vfcvt_f_x_v_f64m8_rm_m(vbool8_t mask, vint64m8_t src, size_t vl) {2367 return __riscv_vfcvt_f(mask, src, __RISCV_FRM_RNE, vl);2368}2369 2370// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfcvt_f_xu_v_f64m1_rm_m2371// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2372// CHECK-RV64-NEXT: entry:2373// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfcvt.f.xu.v.mask.nxv1f64.nxv1i64.i64(<vscale x 1 x double> poison, <vscale x 1 x i64> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)2374// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]2375//2376vfloat64m1_t test_vfcvt_f_xu_v_f64m1_rm_m(vbool64_t mask, vuint64m1_t src, size_t vl) {2377 return __riscv_vfcvt_f(mask, src, __RISCV_FRM_RNE, vl);2378}2379 2380// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfcvt_f_xu_v_f64m2_rm_m2381// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2382// CHECK-RV64-NEXT: entry:2383// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfcvt.f.xu.v.mask.nxv2f64.nxv2i64.i64(<vscale x 2 x double> poison, <vscale x 2 x i64> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)2384// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]2385//2386vfloat64m2_t test_vfcvt_f_xu_v_f64m2_rm_m(vbool32_t mask, vuint64m2_t src, size_t vl) {2387 return __riscv_vfcvt_f(mask, src, __RISCV_FRM_RNE, vl);2388}2389 2390// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfcvt_f_xu_v_f64m4_rm_m2391// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2392// CHECK-RV64-NEXT: entry:2393// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfcvt.f.xu.v.mask.nxv4f64.nxv4i64.i64(<vscale x 4 x double> poison, <vscale x 4 x i64> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)2394// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]2395//2396vfloat64m4_t test_vfcvt_f_xu_v_f64m4_rm_m(vbool16_t mask, vuint64m4_t src, size_t vl) {2397 return __riscv_vfcvt_f(mask, src, __RISCV_FRM_RNE, vl);2398}2399 2400// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfcvt_f_xu_v_f64m8_rm_m2401// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2402// CHECK-RV64-NEXT: entry:2403// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfcvt.f.xu.v.mask.nxv8f64.nxv8i64.i64(<vscale x 8 x double> poison, <vscale x 8 x i64> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)2404// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]2405//2406vfloat64m8_t test_vfcvt_f_xu_v_f64m8_rm_m(vbool8_t mask, vuint64m8_t src, size_t vl) {2407 return __riscv_vfcvt_f(mask, src, __RISCV_FRM_RNE, vl);2408}2409 2410