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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 22// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \4// RUN: -target-feature +zvfh -disable-O0-optnone \5// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \6// RUN: FileCheck --check-prefix=CHECK-RV64 %s7 8#include <riscv_vector.h>9 10// CHECK-RV64-LABEL: define dso_local half @test_vfmv_f_s_f16mf4_f1611// CHECK-RV64-SAME: (<vscale x 1 x half> [[SRC:%.*]]) #[[ATTR0:[0-9]+]] {12// CHECK-RV64-NEXT: entry:13// CHECK-RV64-NEXT: [[TMP0:%.*]] = call half @llvm.riscv.vfmv.f.s.nxv1f16(<vscale x 1 x half> [[SRC]])14// CHECK-RV64-NEXT: ret half [[TMP0]]15//16_Float16 test_vfmv_f_s_f16mf4_f16(vfloat16mf4_t src) {17 return __riscv_vfmv_f(src);18}19 20// CHECK-RV64-LABEL: define dso_local half @test_vfmv_f_s_f16mf2_f1621// CHECK-RV64-SAME: (<vscale x 2 x half> [[SRC:%.*]]) #[[ATTR0]] {22// CHECK-RV64-NEXT: entry:23// CHECK-RV64-NEXT: [[TMP0:%.*]] = call half @llvm.riscv.vfmv.f.s.nxv2f16(<vscale x 2 x half> [[SRC]])24// CHECK-RV64-NEXT: ret half [[TMP0]]25//26_Float16 test_vfmv_f_s_f16mf2_f16(vfloat16mf2_t src) {27 return __riscv_vfmv_f(src);28}29 30// CHECK-RV64-LABEL: define dso_local half @test_vfmv_f_s_f16m1_f1631// CHECK-RV64-SAME: (<vscale x 4 x half> [[SRC:%.*]]) #[[ATTR0]] {32// CHECK-RV64-NEXT: entry:33// CHECK-RV64-NEXT: [[TMP0:%.*]] = call half @llvm.riscv.vfmv.f.s.nxv4f16(<vscale x 4 x half> [[SRC]])34// CHECK-RV64-NEXT: ret half [[TMP0]]35//36_Float16 test_vfmv_f_s_f16m1_f16(vfloat16m1_t src) {37 return __riscv_vfmv_f(src);38}39 40// CHECK-RV64-LABEL: define dso_local half @test_vfmv_f_s_f16m2_f1641// CHECK-RV64-SAME: (<vscale x 8 x half> [[SRC:%.*]]) #[[ATTR0]] {42// CHECK-RV64-NEXT: entry:43// CHECK-RV64-NEXT: [[TMP0:%.*]] = call half @llvm.riscv.vfmv.f.s.nxv8f16(<vscale x 8 x half> [[SRC]])44// CHECK-RV64-NEXT: ret half [[TMP0]]45//46_Float16 test_vfmv_f_s_f16m2_f16(vfloat16m2_t src) {47 return __riscv_vfmv_f(src);48}49 50// CHECK-RV64-LABEL: define dso_local half @test_vfmv_f_s_f16m4_f1651// CHECK-RV64-SAME: (<vscale x 16 x half> [[SRC:%.*]]) #[[ATTR0]] {52// CHECK-RV64-NEXT: entry:53// CHECK-RV64-NEXT: [[TMP0:%.*]] = call half @llvm.riscv.vfmv.f.s.nxv16f16(<vscale x 16 x half> [[SRC]])54// CHECK-RV64-NEXT: ret half [[TMP0]]55//56_Float16 test_vfmv_f_s_f16m4_f16(vfloat16m4_t src) {57 return __riscv_vfmv_f(src);58}59 60// CHECK-RV64-LABEL: define dso_local half @test_vfmv_f_s_f16m8_f1661// CHECK-RV64-SAME: (<vscale x 32 x half> [[SRC:%.*]]) #[[ATTR0]] {62// CHECK-RV64-NEXT: entry:63// CHECK-RV64-NEXT: [[TMP0:%.*]] = call half @llvm.riscv.vfmv.f.s.nxv32f16(<vscale x 32 x half> [[SRC]])64// CHECK-RV64-NEXT: ret half [[TMP0]]65//66_Float16 test_vfmv_f_s_f16m8_f16(vfloat16m8_t src) {67 return __riscv_vfmv_f(src);68}69 70// CHECK-RV64-LABEL: define dso_local float @test_vfmv_f_s_f32mf2_f3271// CHECK-RV64-SAME: (<vscale x 1 x float> [[SRC:%.*]]) #[[ATTR0]] {72// CHECK-RV64-NEXT: entry:73// CHECK-RV64-NEXT: [[TMP0:%.*]] = call float @llvm.riscv.vfmv.f.s.nxv1f32(<vscale x 1 x float> [[SRC]])74// CHECK-RV64-NEXT: ret float [[TMP0]]75//76float test_vfmv_f_s_f32mf2_f32(vfloat32mf2_t src) {77 return __riscv_vfmv_f(src);78}79 80// CHECK-RV64-LABEL: define dso_local float @test_vfmv_f_s_f32m1_f3281// CHECK-RV64-SAME: (<vscale x 2 x float> [[SRC:%.*]]) #[[ATTR0]] {82// CHECK-RV64-NEXT: entry:83// CHECK-RV64-NEXT: [[TMP0:%.*]] = call float @llvm.riscv.vfmv.f.s.nxv2f32(<vscale x 2 x float> [[SRC]])84// CHECK-RV64-NEXT: ret float [[TMP0]]85//86float test_vfmv_f_s_f32m1_f32(vfloat32m1_t src) {87 return __riscv_vfmv_f(src);88}89 90// CHECK-RV64-LABEL: define dso_local float @test_vfmv_f_s_f32m2_f3291// CHECK-RV64-SAME: (<vscale x 4 x float> [[SRC:%.*]]) #[[ATTR0]] {92// CHECK-RV64-NEXT: entry:93// CHECK-RV64-NEXT: [[TMP0:%.*]] = call float @llvm.riscv.vfmv.f.s.nxv4f32(<vscale x 4 x float> [[SRC]])94// CHECK-RV64-NEXT: ret float [[TMP0]]95//96float test_vfmv_f_s_f32m2_f32(vfloat32m2_t src) {97 return __riscv_vfmv_f(src);98}99 100// CHECK-RV64-LABEL: define dso_local float @test_vfmv_f_s_f32m4_f32101// CHECK-RV64-SAME: (<vscale x 8 x float> [[SRC:%.*]]) #[[ATTR0]] {102// CHECK-RV64-NEXT: entry:103// CHECK-RV64-NEXT: [[TMP0:%.*]] = call float @llvm.riscv.vfmv.f.s.nxv8f32(<vscale x 8 x float> [[SRC]])104// CHECK-RV64-NEXT: ret float [[TMP0]]105//106float test_vfmv_f_s_f32m4_f32(vfloat32m4_t src) {107 return __riscv_vfmv_f(src);108}109 110// CHECK-RV64-LABEL: define dso_local float @test_vfmv_f_s_f32m8_f32111// CHECK-RV64-SAME: (<vscale x 16 x float> [[SRC:%.*]]) #[[ATTR0]] {112// CHECK-RV64-NEXT: entry:113// CHECK-RV64-NEXT: [[TMP0:%.*]] = call float @llvm.riscv.vfmv.f.s.nxv16f32(<vscale x 16 x float> [[SRC]])114// CHECK-RV64-NEXT: ret float [[TMP0]]115//116float test_vfmv_f_s_f32m8_f32(vfloat32m8_t src) {117 return __riscv_vfmv_f(src);118}119 120// CHECK-RV64-LABEL: define dso_local double @test_vfmv_f_s_f64m1_f64121// CHECK-RV64-SAME: (<vscale x 1 x double> [[SRC:%.*]]) #[[ATTR0]] {122// CHECK-RV64-NEXT: entry:123// CHECK-RV64-NEXT: [[TMP0:%.*]] = call double @llvm.riscv.vfmv.f.s.nxv1f64(<vscale x 1 x double> [[SRC]])124// CHECK-RV64-NEXT: ret double [[TMP0]]125//126double test_vfmv_f_s_f64m1_f64(vfloat64m1_t src) {127 return __riscv_vfmv_f(src);128}129 130// CHECK-RV64-LABEL: define dso_local double @test_vfmv_f_s_f64m2_f64131// CHECK-RV64-SAME: (<vscale x 2 x double> [[SRC:%.*]]) #[[ATTR0]] {132// CHECK-RV64-NEXT: entry:133// CHECK-RV64-NEXT: [[TMP0:%.*]] = call double @llvm.riscv.vfmv.f.s.nxv2f64(<vscale x 2 x double> [[SRC]])134// CHECK-RV64-NEXT: ret double [[TMP0]]135//136double test_vfmv_f_s_f64m2_f64(vfloat64m2_t src) {137 return __riscv_vfmv_f(src);138}139 140// CHECK-RV64-LABEL: define dso_local double @test_vfmv_f_s_f64m4_f64141// CHECK-RV64-SAME: (<vscale x 4 x double> [[SRC:%.*]]) #[[ATTR0]] {142// CHECK-RV64-NEXT: entry:143// CHECK-RV64-NEXT: [[TMP0:%.*]] = call double @llvm.riscv.vfmv.f.s.nxv4f64(<vscale x 4 x double> [[SRC]])144// CHECK-RV64-NEXT: ret double [[TMP0]]145//146double test_vfmv_f_s_f64m4_f64(vfloat64m4_t src) {147 return __riscv_vfmv_f(src);148}149 150// CHECK-RV64-LABEL: define dso_local double @test_vfmv_f_s_f64m8_f64151// CHECK-RV64-SAME: (<vscale x 8 x double> [[SRC:%.*]]) #[[ATTR0]] {152// CHECK-RV64-NEXT: entry:153// CHECK-RV64-NEXT: [[TMP0:%.*]] = call double @llvm.riscv.vfmv.f.s.nxv8f64(<vscale x 8 x double> [[SRC]])154// CHECK-RV64-NEXT: ret double [[TMP0]]155//156double test_vfmv_f_s_f64m8_f64(vfloat64m8_t src) {157 return __riscv_vfmv_f(src);158}159 160