1360 lines · c
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 22// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \4// RUN: -target-feature +zvfhmin -disable-O0-optnone \5// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \6// RUN: FileCheck --check-prefix=CHECK-RV64 %s7 8#include <riscv_vector.h>9 10// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vlmul_ext_v_f16mf4_f16mf211// CHECK-RV64-SAME: (<vscale x 1 x half> [[OP1:%.*]]) #[[ATTR0:[0-9]+]] {12// CHECK-RV64-NEXT: entry:13// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.vector.insert.nxv2f16.nxv1f16(<vscale x 2 x half> poison, <vscale x 1 x half> [[OP1]], i64 0)14// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]15//16vfloat16mf2_t test_vlmul_ext_v_f16mf4_f16mf2(vfloat16mf4_t op1) {17 return __riscv_vlmul_ext_f16mf2(op1);18}19 20// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vlmul_ext_v_f16mf4_f16m121// CHECK-RV64-SAME: (<vscale x 1 x half> [[OP1:%.*]]) #[[ATTR0]] {22// CHECK-RV64-NEXT: entry:23// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv1f16(<vscale x 4 x half> poison, <vscale x 1 x half> [[OP1]], i64 0)24// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]25//26vfloat16m1_t test_vlmul_ext_v_f16mf4_f16m1(vfloat16mf4_t op1) {27 return __riscv_vlmul_ext_f16m1(op1);28}29 30// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vlmul_ext_v_f16mf4_f16m231// CHECK-RV64-SAME: (<vscale x 1 x half> [[OP1:%.*]]) #[[ATTR0]] {32// CHECK-RV64-NEXT: entry:33// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv1f16(<vscale x 8 x half> poison, <vscale x 1 x half> [[OP1]], i64 0)34// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]35//36vfloat16m2_t test_vlmul_ext_v_f16mf4_f16m2(vfloat16mf4_t op1) {37 return __riscv_vlmul_ext_f16m2(op1);38}39 40// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vlmul_ext_v_f16mf4_f16m441// CHECK-RV64-SAME: (<vscale x 1 x half> [[OP1:%.*]]) #[[ATTR0]] {42// CHECK-RV64-NEXT: entry:43// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv1f16(<vscale x 16 x half> poison, <vscale x 1 x half> [[OP1]], i64 0)44// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]45//46vfloat16m4_t test_vlmul_ext_v_f16mf4_f16m4(vfloat16mf4_t op1) {47 return __riscv_vlmul_ext_f16m4(op1);48}49 50// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vlmul_ext_v_f16mf4_f16m851// CHECK-RV64-SAME: (<vscale x 1 x half> [[OP1:%.*]]) #[[ATTR0]] {52// CHECK-RV64-NEXT: entry:53// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv1f16(<vscale x 32 x half> poison, <vscale x 1 x half> [[OP1]], i64 0)54// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]55//56vfloat16m8_t test_vlmul_ext_v_f16mf4_f16m8(vfloat16mf4_t op1) {57 return __riscv_vlmul_ext_f16m8(op1);58}59 60// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vlmul_ext_v_f16mf2_f16m161// CHECK-RV64-SAME: (<vscale x 2 x half> [[OP1:%.*]]) #[[ATTR0]] {62// CHECK-RV64-NEXT: entry:63// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv2f16(<vscale x 4 x half> poison, <vscale x 2 x half> [[OP1]], i64 0)64// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]65//66vfloat16m1_t test_vlmul_ext_v_f16mf2_f16m1(vfloat16mf2_t op1) {67 return __riscv_vlmul_ext_f16m1(op1);68}69 70// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vlmul_ext_v_f16mf2_f16m271// CHECK-RV64-SAME: (<vscale x 2 x half> [[OP1:%.*]]) #[[ATTR0]] {72// CHECK-RV64-NEXT: entry:73// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv2f16(<vscale x 8 x half> poison, <vscale x 2 x half> [[OP1]], i64 0)74// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]75//76vfloat16m2_t test_vlmul_ext_v_f16mf2_f16m2(vfloat16mf2_t op1) {77 return __riscv_vlmul_ext_f16m2(op1);78}79 80// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vlmul_ext_v_f16mf2_f16m481// CHECK-RV64-SAME: (<vscale x 2 x half> [[OP1:%.*]]) #[[ATTR0]] {82// CHECK-RV64-NEXT: entry:83// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv2f16(<vscale x 16 x half> poison, <vscale x 2 x half> [[OP1]], i64 0)84// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]85//86vfloat16m4_t test_vlmul_ext_v_f16mf2_f16m4(vfloat16mf2_t op1) {87 return __riscv_vlmul_ext_f16m4(op1);88}89 90// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vlmul_ext_v_f16mf2_f16m891// CHECK-RV64-SAME: (<vscale x 2 x half> [[OP1:%.*]]) #[[ATTR0]] {92// CHECK-RV64-NEXT: entry:93// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv2f16(<vscale x 32 x half> poison, <vscale x 2 x half> [[OP1]], i64 0)94// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]95//96vfloat16m8_t test_vlmul_ext_v_f16mf2_f16m8(vfloat16mf2_t op1) {97 return __riscv_vlmul_ext_f16m8(op1);98}99 100// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vlmul_ext_v_f16m1_f16m2101// CHECK-RV64-SAME: (<vscale x 4 x half> [[OP1:%.*]]) #[[ATTR0]] {102// CHECK-RV64-NEXT: entry:103// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half> poison, <vscale x 4 x half> [[OP1]], i64 0)104// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]105//106vfloat16m2_t test_vlmul_ext_v_f16m1_f16m2(vfloat16m1_t op1) {107 return __riscv_vlmul_ext_f16m2(op1);108}109 110// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vlmul_ext_v_f16m1_f16m4111// CHECK-RV64-SAME: (<vscale x 4 x half> [[OP1:%.*]]) #[[ATTR0]] {112// CHECK-RV64-NEXT: entry:113// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half> poison, <vscale x 4 x half> [[OP1]], i64 0)114// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]115//116vfloat16m4_t test_vlmul_ext_v_f16m1_f16m4(vfloat16m1_t op1) {117 return __riscv_vlmul_ext_f16m4(op1);118}119 120// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vlmul_ext_v_f16m1_f16m8121// CHECK-RV64-SAME: (<vscale x 4 x half> [[OP1:%.*]]) #[[ATTR0]] {122// CHECK-RV64-NEXT: entry:123// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> poison, <vscale x 4 x half> [[OP1]], i64 0)124// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]125//126vfloat16m8_t test_vlmul_ext_v_f16m1_f16m8(vfloat16m1_t op1) {127 return __riscv_vlmul_ext_f16m8(op1);128}129 130// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vlmul_ext_v_f16m2_f16m4131// CHECK-RV64-SAME: (<vscale x 8 x half> [[OP1:%.*]]) #[[ATTR0]] {132// CHECK-RV64-NEXT: entry:133// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half> poison, <vscale x 8 x half> [[OP1]], i64 0)134// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]135//136vfloat16m4_t test_vlmul_ext_v_f16m2_f16m4(vfloat16m2_t op1) {137 return __riscv_vlmul_ext_f16m4(op1);138}139 140// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vlmul_ext_v_f16m2_f16m8141// CHECK-RV64-SAME: (<vscale x 8 x half> [[OP1:%.*]]) #[[ATTR0]] {142// CHECK-RV64-NEXT: entry:143// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half> poison, <vscale x 8 x half> [[OP1]], i64 0)144// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]145//146vfloat16m8_t test_vlmul_ext_v_f16m2_f16m8(vfloat16m2_t op1) {147 return __riscv_vlmul_ext_f16m8(op1);148}149 150// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vlmul_ext_v_f16m4_f16m8151// CHECK-RV64-SAME: (<vscale x 16 x half> [[OP1:%.*]]) #[[ATTR0]] {152// CHECK-RV64-NEXT: entry:153// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv16f16(<vscale x 32 x half> poison, <vscale x 16 x half> [[OP1]], i64 0)154// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]155//156vfloat16m8_t test_vlmul_ext_v_f16m4_f16m8(vfloat16m4_t op1) {157 return __riscv_vlmul_ext_f16m8(op1);158}159 160// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vlmul_ext_v_f32mf2_f32m1161// CHECK-RV64-SAME: (<vscale x 1 x float> [[OP1:%.*]]) #[[ATTR0]] {162// CHECK-RV64-NEXT: entry:163// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.vector.insert.nxv2f32.nxv1f32(<vscale x 2 x float> poison, <vscale x 1 x float> [[OP1]], i64 0)164// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]165//166vfloat32m1_t test_vlmul_ext_v_f32mf2_f32m1(vfloat32mf2_t op1) {167 return __riscv_vlmul_ext_f32m1(op1);168}169 170// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vlmul_ext_v_f32mf2_f32m2171// CHECK-RV64-SAME: (<vscale x 1 x float> [[OP1:%.*]]) #[[ATTR0]] {172// CHECK-RV64-NEXT: entry:173// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv1f32(<vscale x 4 x float> poison, <vscale x 1 x float> [[OP1]], i64 0)174// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]175//176vfloat32m2_t test_vlmul_ext_v_f32mf2_f32m2(vfloat32mf2_t op1) {177 return __riscv_vlmul_ext_f32m2(op1);178}179 180// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vlmul_ext_v_f32mf2_f32m4181// CHECK-RV64-SAME: (<vscale x 1 x float> [[OP1:%.*]]) #[[ATTR0]] {182// CHECK-RV64-NEXT: entry:183// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv1f32(<vscale x 8 x float> poison, <vscale x 1 x float> [[OP1]], i64 0)184// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]185//186vfloat32m4_t test_vlmul_ext_v_f32mf2_f32m4(vfloat32mf2_t op1) {187 return __riscv_vlmul_ext_f32m4(op1);188}189 190// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vlmul_ext_v_f32mf2_f32m8191// CHECK-RV64-SAME: (<vscale x 1 x float> [[OP1:%.*]]) #[[ATTR0]] {192// CHECK-RV64-NEXT: entry:193// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.vector.insert.nxv16f32.nxv1f32(<vscale x 16 x float> poison, <vscale x 1 x float> [[OP1]], i64 0)194// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]195//196vfloat32m8_t test_vlmul_ext_v_f32mf2_f32m8(vfloat32mf2_t op1) {197 return __riscv_vlmul_ext_f32m8(op1);198}199 200// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vlmul_ext_v_f32m1_f32m2201// CHECK-RV64-SAME: (<vscale x 2 x float> [[OP1:%.*]]) #[[ATTR0]] {202// CHECK-RV64-NEXT: entry:203// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv2f32(<vscale x 4 x float> poison, <vscale x 2 x float> [[OP1]], i64 0)204// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]205//206vfloat32m2_t test_vlmul_ext_v_f32m1_f32m2(vfloat32m1_t op1) {207 return __riscv_vlmul_ext_f32m2(op1);208}209 210// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vlmul_ext_v_f32m1_f32m4211// CHECK-RV64-SAME: (<vscale x 2 x float> [[OP1:%.*]]) #[[ATTR0]] {212// CHECK-RV64-NEXT: entry:213// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv2f32(<vscale x 8 x float> poison, <vscale x 2 x float> [[OP1]], i64 0)214// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]215//216vfloat32m4_t test_vlmul_ext_v_f32m1_f32m4(vfloat32m1_t op1) {217 return __riscv_vlmul_ext_f32m4(op1);218}219 220// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vlmul_ext_v_f32m1_f32m8221// CHECK-RV64-SAME: (<vscale x 2 x float> [[OP1:%.*]]) #[[ATTR0]] {222// CHECK-RV64-NEXT: entry:223// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.vector.insert.nxv16f32.nxv2f32(<vscale x 16 x float> poison, <vscale x 2 x float> [[OP1]], i64 0)224// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]225//226vfloat32m8_t test_vlmul_ext_v_f32m1_f32m8(vfloat32m1_t op1) {227 return __riscv_vlmul_ext_f32m8(op1);228}229 230// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vlmul_ext_v_f32m2_f32m4231// CHECK-RV64-SAME: (<vscale x 4 x float> [[OP1:%.*]]) #[[ATTR0]] {232// CHECK-RV64-NEXT: entry:233// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv4f32(<vscale x 8 x float> poison, <vscale x 4 x float> [[OP1]], i64 0)234// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]235//236vfloat32m4_t test_vlmul_ext_v_f32m2_f32m4(vfloat32m2_t op1) {237 return __riscv_vlmul_ext_f32m4(op1);238}239 240// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vlmul_ext_v_f32m2_f32m8241// CHECK-RV64-SAME: (<vscale x 4 x float> [[OP1:%.*]]) #[[ATTR0]] {242// CHECK-RV64-NEXT: entry:243// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.vector.insert.nxv16f32.nxv4f32(<vscale x 16 x float> poison, <vscale x 4 x float> [[OP1]], i64 0)244// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]245//246vfloat32m8_t test_vlmul_ext_v_f32m2_f32m8(vfloat32m2_t op1) {247 return __riscv_vlmul_ext_f32m8(op1);248}249 250// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vlmul_ext_v_f32m4_f32m8251// CHECK-RV64-SAME: (<vscale x 8 x float> [[OP1:%.*]]) #[[ATTR0]] {252// CHECK-RV64-NEXT: entry:253// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.vector.insert.nxv16f32.nxv8f32(<vscale x 16 x float> poison, <vscale x 8 x float> [[OP1]], i64 0)254// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]255//256vfloat32m8_t test_vlmul_ext_v_f32m4_f32m8(vfloat32m4_t op1) {257 return __riscv_vlmul_ext_f32m8(op1);258}259 260// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vlmul_ext_v_f64m1_f64m2261// CHECK-RV64-SAME: (<vscale x 1 x double> [[OP1:%.*]]) #[[ATTR0]] {262// CHECK-RV64-NEXT: entry:263// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.vector.insert.nxv2f64.nxv1f64(<vscale x 2 x double> poison, <vscale x 1 x double> [[OP1]], i64 0)264// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]265//266vfloat64m2_t test_vlmul_ext_v_f64m1_f64m2(vfloat64m1_t op1) {267 return __riscv_vlmul_ext_f64m2(op1);268}269 270// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vlmul_ext_v_f64m1_f64m4271// CHECK-RV64-SAME: (<vscale x 1 x double> [[OP1:%.*]]) #[[ATTR0]] {272// CHECK-RV64-NEXT: entry:273// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.vector.insert.nxv4f64.nxv1f64(<vscale x 4 x double> poison, <vscale x 1 x double> [[OP1]], i64 0)274// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]275//276vfloat64m4_t test_vlmul_ext_v_f64m1_f64m4(vfloat64m1_t op1) {277 return __riscv_vlmul_ext_f64m4(op1);278}279 280// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vlmul_ext_v_f64m1_f64m8281// CHECK-RV64-SAME: (<vscale x 1 x double> [[OP1:%.*]]) #[[ATTR0]] {282// CHECK-RV64-NEXT: entry:283// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.vector.insert.nxv8f64.nxv1f64(<vscale x 8 x double> poison, <vscale x 1 x double> [[OP1]], i64 0)284// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]285//286vfloat64m8_t test_vlmul_ext_v_f64m1_f64m8(vfloat64m1_t op1) {287 return __riscv_vlmul_ext_f64m8(op1);288}289 290// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vlmul_ext_v_f64m2_f64m4291// CHECK-RV64-SAME: (<vscale x 2 x double> [[OP1:%.*]]) #[[ATTR0]] {292// CHECK-RV64-NEXT: entry:293// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.vector.insert.nxv4f64.nxv2f64(<vscale x 4 x double> poison, <vscale x 2 x double> [[OP1]], i64 0)294// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]295//296vfloat64m4_t test_vlmul_ext_v_f64m2_f64m4(vfloat64m2_t op1) {297 return __riscv_vlmul_ext_f64m4(op1);298}299 300// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vlmul_ext_v_f64m2_f64m8301// CHECK-RV64-SAME: (<vscale x 2 x double> [[OP1:%.*]]) #[[ATTR0]] {302// CHECK-RV64-NEXT: entry:303// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.vector.insert.nxv8f64.nxv2f64(<vscale x 8 x double> poison, <vscale x 2 x double> [[OP1]], i64 0)304// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]305//306vfloat64m8_t test_vlmul_ext_v_f64m2_f64m8(vfloat64m2_t op1) {307 return __riscv_vlmul_ext_f64m8(op1);308}309 310// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vlmul_ext_v_f64m4_f64m8311// CHECK-RV64-SAME: (<vscale x 4 x double> [[OP1:%.*]]) #[[ATTR0]] {312// CHECK-RV64-NEXT: entry:313// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.vector.insert.nxv8f64.nxv4f64(<vscale x 8 x double> poison, <vscale x 4 x double> [[OP1]], i64 0)314// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]315//316vfloat64m8_t test_vlmul_ext_v_f64m4_f64m8(vfloat64m4_t op1) {317 return __riscv_vlmul_ext_f64m8(op1);318}319 320// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vlmul_ext_v_i8mf8_i8mf4321// CHECK-RV64-SAME: (<vscale x 1 x i8> [[OP1:%.*]]) #[[ATTR0]] {322// CHECK-RV64-NEXT: entry:323// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.nxv1i8(<vscale x 2 x i8> poison, <vscale x 1 x i8> [[OP1]], i64 0)324// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]325//326vint8mf4_t test_vlmul_ext_v_i8mf8_i8mf4(vint8mf8_t op1) {327 return __riscv_vlmul_ext_i8mf4(op1);328}329 330// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vlmul_ext_v_i8mf8_i8mf2331// CHECK-RV64-SAME: (<vscale x 1 x i8> [[OP1:%.*]]) #[[ATTR0]] {332// CHECK-RV64-NEXT: entry:333// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.vector.insert.nxv4i8.nxv1i8(<vscale x 4 x i8> poison, <vscale x 1 x i8> [[OP1]], i64 0)334// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]335//336vint8mf2_t test_vlmul_ext_v_i8mf8_i8mf2(vint8mf8_t op1) {337 return __riscv_vlmul_ext_i8mf2(op1);338}339 340// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vlmul_ext_v_i8mf8_i8m1341// CHECK-RV64-SAME: (<vscale x 1 x i8> [[OP1:%.*]]) #[[ATTR0]] {342// CHECK-RV64-NEXT: entry:343// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.nxv1i8(<vscale x 8 x i8> poison, <vscale x 1 x i8> [[OP1]], i64 0)344// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]345//346vint8m1_t test_vlmul_ext_v_i8mf8_i8m1(vint8mf8_t op1) {347 return __riscv_vlmul_ext_i8m1(op1);348}349 350// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vlmul_ext_v_i8mf8_i8m2351// CHECK-RV64-SAME: (<vscale x 1 x i8> [[OP1:%.*]]) #[[ATTR0]] {352// CHECK-RV64-NEXT: entry:353// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv1i8(<vscale x 16 x i8> poison, <vscale x 1 x i8> [[OP1]], i64 0)354// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]355//356vint8m2_t test_vlmul_ext_v_i8mf8_i8m2(vint8mf8_t op1) {357 return __riscv_vlmul_ext_i8m2(op1);358}359 360// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vlmul_ext_v_i8mf8_i8m4361// CHECK-RV64-SAME: (<vscale x 1 x i8> [[OP1:%.*]]) #[[ATTR0]] {362// CHECK-RV64-NEXT: entry:363// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv1i8(<vscale x 32 x i8> poison, <vscale x 1 x i8> [[OP1]], i64 0)364// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]365//366vint8m4_t test_vlmul_ext_v_i8mf8_i8m4(vint8mf8_t op1) {367 return __riscv_vlmul_ext_i8m4(op1);368}369 370// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vlmul_ext_v_i8mf8_i8m8371// CHECK-RV64-SAME: (<vscale x 1 x i8> [[OP1:%.*]]) #[[ATTR0]] {372// CHECK-RV64-NEXT: entry:373// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv1i8(<vscale x 64 x i8> poison, <vscale x 1 x i8> [[OP1]], i64 0)374// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]375//376vint8m8_t test_vlmul_ext_v_i8mf8_i8m8(vint8mf8_t op1) {377 return __riscv_vlmul_ext_i8m8(op1);378}379 380// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vlmul_ext_v_i8mf4_i8mf2381// CHECK-RV64-SAME: (<vscale x 2 x i8> [[OP1:%.*]]) #[[ATTR0]] {382// CHECK-RV64-NEXT: entry:383// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.vector.insert.nxv4i8.nxv2i8(<vscale x 4 x i8> poison, <vscale x 2 x i8> [[OP1]], i64 0)384// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]385//386vint8mf2_t test_vlmul_ext_v_i8mf4_i8mf2(vint8mf4_t op1) {387 return __riscv_vlmul_ext_i8mf2(op1);388}389 390// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vlmul_ext_v_i8mf4_i8m1391// CHECK-RV64-SAME: (<vscale x 2 x i8> [[OP1:%.*]]) #[[ATTR0]] {392// CHECK-RV64-NEXT: entry:393// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.nxv2i8(<vscale x 8 x i8> poison, <vscale x 2 x i8> [[OP1]], i64 0)394// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]395//396vint8m1_t test_vlmul_ext_v_i8mf4_i8m1(vint8mf4_t op1) {397 return __riscv_vlmul_ext_i8m1(op1);398}399 400// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vlmul_ext_v_i8mf4_i8m2401// CHECK-RV64-SAME: (<vscale x 2 x i8> [[OP1:%.*]]) #[[ATTR0]] {402// CHECK-RV64-NEXT: entry:403// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv2i8(<vscale x 16 x i8> poison, <vscale x 2 x i8> [[OP1]], i64 0)404// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]405//406vint8m2_t test_vlmul_ext_v_i8mf4_i8m2(vint8mf4_t op1) {407 return __riscv_vlmul_ext_i8m2(op1);408}409 410// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vlmul_ext_v_i8mf4_i8m4411// CHECK-RV64-SAME: (<vscale x 2 x i8> [[OP1:%.*]]) #[[ATTR0]] {412// CHECK-RV64-NEXT: entry:413// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv2i8(<vscale x 32 x i8> poison, <vscale x 2 x i8> [[OP1]], i64 0)414// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]415//416vint8m4_t test_vlmul_ext_v_i8mf4_i8m4(vint8mf4_t op1) {417 return __riscv_vlmul_ext_i8m4(op1);418}419 420// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vlmul_ext_v_i8mf4_i8m8421// CHECK-RV64-SAME: (<vscale x 2 x i8> [[OP1:%.*]]) #[[ATTR0]] {422// CHECK-RV64-NEXT: entry:423// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv2i8(<vscale x 64 x i8> poison, <vscale x 2 x i8> [[OP1]], i64 0)424// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]425//426vint8m8_t test_vlmul_ext_v_i8mf4_i8m8(vint8mf4_t op1) {427 return __riscv_vlmul_ext_i8m8(op1);428}429 430// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vlmul_ext_v_i8mf2_i8m1431// CHECK-RV64-SAME: (<vscale x 4 x i8> [[OP1:%.*]]) #[[ATTR0]] {432// CHECK-RV64-NEXT: entry:433// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.nxv4i8(<vscale x 8 x i8> poison, <vscale x 4 x i8> [[OP1]], i64 0)434// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]435//436vint8m1_t test_vlmul_ext_v_i8mf2_i8m1(vint8mf2_t op1) {437 return __riscv_vlmul_ext_i8m1(op1);438}439 440// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vlmul_ext_v_i8mf2_i8m2441// CHECK-RV64-SAME: (<vscale x 4 x i8> [[OP1:%.*]]) #[[ATTR0]] {442// CHECK-RV64-NEXT: entry:443// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv4i8(<vscale x 16 x i8> poison, <vscale x 4 x i8> [[OP1]], i64 0)444// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]445//446vint8m2_t test_vlmul_ext_v_i8mf2_i8m2(vint8mf2_t op1) {447 return __riscv_vlmul_ext_i8m2(op1);448}449 450// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vlmul_ext_v_i8mf2_i8m4451// CHECK-RV64-SAME: (<vscale x 4 x i8> [[OP1:%.*]]) #[[ATTR0]] {452// CHECK-RV64-NEXT: entry:453// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv4i8(<vscale x 32 x i8> poison, <vscale x 4 x i8> [[OP1]], i64 0)454// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]455//456vint8m4_t test_vlmul_ext_v_i8mf2_i8m4(vint8mf2_t op1) {457 return __riscv_vlmul_ext_i8m4(op1);458}459 460// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vlmul_ext_v_i8mf2_i8m8461// CHECK-RV64-SAME: (<vscale x 4 x i8> [[OP1:%.*]]) #[[ATTR0]] {462// CHECK-RV64-NEXT: entry:463// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv4i8(<vscale x 64 x i8> poison, <vscale x 4 x i8> [[OP1]], i64 0)464// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]465//466vint8m8_t test_vlmul_ext_v_i8mf2_i8m8(vint8mf2_t op1) {467 return __riscv_vlmul_ext_i8m8(op1);468}469 470// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vlmul_ext_v_i8m1_i8m2471// CHECK-RV64-SAME: (<vscale x 8 x i8> [[OP1:%.*]]) #[[ATTR0]] {472// CHECK-RV64-NEXT: entry:473// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8> poison, <vscale x 8 x i8> [[OP1]], i64 0)474// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]475//476vint8m2_t test_vlmul_ext_v_i8m1_i8m2(vint8m1_t op1) {477 return __riscv_vlmul_ext_i8m2(op1);478}479 480// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vlmul_ext_v_i8m1_i8m4481// CHECK-RV64-SAME: (<vscale x 8 x i8> [[OP1:%.*]]) #[[ATTR0]] {482// CHECK-RV64-NEXT: entry:483// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv8i8(<vscale x 32 x i8> poison, <vscale x 8 x i8> [[OP1]], i64 0)484// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]485//486vint8m4_t test_vlmul_ext_v_i8m1_i8m4(vint8m1_t op1) {487 return __riscv_vlmul_ext_i8m4(op1);488}489 490// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vlmul_ext_v_i8m1_i8m8491// CHECK-RV64-SAME: (<vscale x 8 x i8> [[OP1:%.*]]) #[[ATTR0]] {492// CHECK-RV64-NEXT: entry:493// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv8i8(<vscale x 64 x i8> poison, <vscale x 8 x i8> [[OP1]], i64 0)494// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]495//496vint8m8_t test_vlmul_ext_v_i8m1_i8m8(vint8m1_t op1) {497 return __riscv_vlmul_ext_i8m8(op1);498}499 500// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vlmul_ext_v_i8m2_i8m4501// CHECK-RV64-SAME: (<vscale x 16 x i8> [[OP1:%.*]]) #[[ATTR0]] {502// CHECK-RV64-NEXT: entry:503// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv16i8(<vscale x 32 x i8> poison, <vscale x 16 x i8> [[OP1]], i64 0)504// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]505//506vint8m4_t test_vlmul_ext_v_i8m2_i8m4(vint8m2_t op1) {507 return __riscv_vlmul_ext_i8m4(op1);508}509 510// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vlmul_ext_v_i8m2_i8m8511// CHECK-RV64-SAME: (<vscale x 16 x i8> [[OP1:%.*]]) #[[ATTR0]] {512// CHECK-RV64-NEXT: entry:513// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv16i8(<vscale x 64 x i8> poison, <vscale x 16 x i8> [[OP1]], i64 0)514// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]515//516vint8m8_t test_vlmul_ext_v_i8m2_i8m8(vint8m2_t op1) {517 return __riscv_vlmul_ext_i8m8(op1);518}519 520// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vlmul_ext_v_i8m4_i8m8521// CHECK-RV64-SAME: (<vscale x 32 x i8> [[OP1:%.*]]) #[[ATTR0]] {522// CHECK-RV64-NEXT: entry:523// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv32i8(<vscale x 64 x i8> poison, <vscale x 32 x i8> [[OP1]], i64 0)524// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]525//526vint8m8_t test_vlmul_ext_v_i8m4_i8m8(vint8m4_t op1) {527 return __riscv_vlmul_ext_i8m8(op1);528}529 530// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vlmul_ext_v_i16mf4_i16mf2531// CHECK-RV64-SAME: (<vscale x 1 x i16> [[OP1:%.*]]) #[[ATTR0]] {532// CHECK-RV64-NEXT: entry:533// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.vector.insert.nxv2i16.nxv1i16(<vscale x 2 x i16> poison, <vscale x 1 x i16> [[OP1]], i64 0)534// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]535//536vint16mf2_t test_vlmul_ext_v_i16mf4_i16mf2(vint16mf4_t op1) {537 return __riscv_vlmul_ext_i16mf2(op1);538}539 540// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vlmul_ext_v_i16mf4_i16m1541// CHECK-RV64-SAME: (<vscale x 1 x i16> [[OP1:%.*]]) #[[ATTR0]] {542// CHECK-RV64-NEXT: entry:543// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.nxv1i16(<vscale x 4 x i16> poison, <vscale x 1 x i16> [[OP1]], i64 0)544// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]545//546vint16m1_t test_vlmul_ext_v_i16mf4_i16m1(vint16mf4_t op1) {547 return __riscv_vlmul_ext_i16m1(op1);548}549 550// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vlmul_ext_v_i16mf4_i16m2551// CHECK-RV64-SAME: (<vscale x 1 x i16> [[OP1:%.*]]) #[[ATTR0]] {552// CHECK-RV64-NEXT: entry:553// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> [[OP1]], i64 0)554// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]555//556vint16m2_t test_vlmul_ext_v_i16mf4_i16m2(vint16mf4_t op1) {557 return __riscv_vlmul_ext_i16m2(op1);558}559 560// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vlmul_ext_v_i16mf4_i16m4561// CHECK-RV64-SAME: (<vscale x 1 x i16> [[OP1:%.*]]) #[[ATTR0]] {562// CHECK-RV64-NEXT: entry:563// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.vector.insert.nxv16i16.nxv1i16(<vscale x 16 x i16> poison, <vscale x 1 x i16> [[OP1]], i64 0)564// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]565//566vint16m4_t test_vlmul_ext_v_i16mf4_i16m4(vint16mf4_t op1) {567 return __riscv_vlmul_ext_i16m4(op1);568}569 570// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vlmul_ext_v_i16mf4_i16m8571// CHECK-RV64-SAME: (<vscale x 1 x i16> [[OP1:%.*]]) #[[ATTR0]] {572// CHECK-RV64-NEXT: entry:573// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv1i16(<vscale x 32 x i16> poison, <vscale x 1 x i16> [[OP1]], i64 0)574// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]575//576vint16m8_t test_vlmul_ext_v_i16mf4_i16m8(vint16mf4_t op1) {577 return __riscv_vlmul_ext_i16m8(op1);578}579 580// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vlmul_ext_v_i16mf2_i16m1581// CHECK-RV64-SAME: (<vscale x 2 x i16> [[OP1:%.*]]) #[[ATTR0]] {582// CHECK-RV64-NEXT: entry:583// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.nxv2i16(<vscale x 4 x i16> poison, <vscale x 2 x i16> [[OP1]], i64 0)584// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]585//586vint16m1_t test_vlmul_ext_v_i16mf2_i16m1(vint16mf2_t op1) {587 return __riscv_vlmul_ext_i16m1(op1);588}589 590// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vlmul_ext_v_i16mf2_i16m2591// CHECK-RV64-SAME: (<vscale x 2 x i16> [[OP1:%.*]]) #[[ATTR0]] {592// CHECK-RV64-NEXT: entry:593// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv2i16(<vscale x 8 x i16> poison, <vscale x 2 x i16> [[OP1]], i64 0)594// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]595//596vint16m2_t test_vlmul_ext_v_i16mf2_i16m2(vint16mf2_t op1) {597 return __riscv_vlmul_ext_i16m2(op1);598}599 600// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vlmul_ext_v_i16mf2_i16m4601// CHECK-RV64-SAME: (<vscale x 2 x i16> [[OP1:%.*]]) #[[ATTR0]] {602// CHECK-RV64-NEXT: entry:603// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.vector.insert.nxv16i16.nxv2i16(<vscale x 16 x i16> poison, <vscale x 2 x i16> [[OP1]], i64 0)604// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]605//606vint16m4_t test_vlmul_ext_v_i16mf2_i16m4(vint16mf2_t op1) {607 return __riscv_vlmul_ext_i16m4(op1);608}609 610// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vlmul_ext_v_i16mf2_i16m8611// CHECK-RV64-SAME: (<vscale x 2 x i16> [[OP1:%.*]]) #[[ATTR0]] {612// CHECK-RV64-NEXT: entry:613// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv2i16(<vscale x 32 x i16> poison, <vscale x 2 x i16> [[OP1]], i64 0)614// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]615//616vint16m8_t test_vlmul_ext_v_i16mf2_i16m8(vint16mf2_t op1) {617 return __riscv_vlmul_ext_i16m8(op1);618}619 620// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vlmul_ext_v_i16m1_i16m2621// CHECK-RV64-SAME: (<vscale x 4 x i16> [[OP1:%.*]]) #[[ATTR0]] {622// CHECK-RV64-NEXT: entry:623// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv4i16(<vscale x 8 x i16> poison, <vscale x 4 x i16> [[OP1]], i64 0)624// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]625//626vint16m2_t test_vlmul_ext_v_i16m1_i16m2(vint16m1_t op1) {627 return __riscv_vlmul_ext_i16m2(op1);628}629 630// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vlmul_ext_v_i16m1_i16m4631// CHECK-RV64-SAME: (<vscale x 4 x i16> [[OP1:%.*]]) #[[ATTR0]] {632// CHECK-RV64-NEXT: entry:633// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.vector.insert.nxv16i16.nxv4i16(<vscale x 16 x i16> poison, <vscale x 4 x i16> [[OP1]], i64 0)634// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]635//636vint16m4_t test_vlmul_ext_v_i16m1_i16m4(vint16m1_t op1) {637 return __riscv_vlmul_ext_i16m4(op1);638}639 640// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vlmul_ext_v_i16m1_i16m8641// CHECK-RV64-SAME: (<vscale x 4 x i16> [[OP1:%.*]]) #[[ATTR0]] {642// CHECK-RV64-NEXT: entry:643// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv4i16(<vscale x 32 x i16> poison, <vscale x 4 x i16> [[OP1]], i64 0)644// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]645//646vint16m8_t test_vlmul_ext_v_i16m1_i16m8(vint16m1_t op1) {647 return __riscv_vlmul_ext_i16m8(op1);648}649 650// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vlmul_ext_v_i16m2_i16m4651// CHECK-RV64-SAME: (<vscale x 8 x i16> [[OP1:%.*]]) #[[ATTR0]] {652// CHECK-RV64-NEXT: entry:653// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.vector.insert.nxv16i16.nxv8i16(<vscale x 16 x i16> poison, <vscale x 8 x i16> [[OP1]], i64 0)654// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]655//656vint16m4_t test_vlmul_ext_v_i16m2_i16m4(vint16m2_t op1) {657 return __riscv_vlmul_ext_i16m4(op1);658}659 660// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vlmul_ext_v_i16m2_i16m8661// CHECK-RV64-SAME: (<vscale x 8 x i16> [[OP1:%.*]]) #[[ATTR0]] {662// CHECK-RV64-NEXT: entry:663// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv8i16(<vscale x 32 x i16> poison, <vscale x 8 x i16> [[OP1]], i64 0)664// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]665//666vint16m8_t test_vlmul_ext_v_i16m2_i16m8(vint16m2_t op1) {667 return __riscv_vlmul_ext_i16m8(op1);668}669 670// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vlmul_ext_v_i16m4_i16m8671// CHECK-RV64-SAME: (<vscale x 16 x i16> [[OP1:%.*]]) #[[ATTR0]] {672// CHECK-RV64-NEXT: entry:673// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv16i16(<vscale x 32 x i16> poison, <vscale x 16 x i16> [[OP1]], i64 0)674// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]675//676vint16m8_t test_vlmul_ext_v_i16m4_i16m8(vint16m4_t op1) {677 return __riscv_vlmul_ext_i16m8(op1);678}679 680// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vlmul_ext_v_i32mf2_i32m1681// CHECK-RV64-SAME: (<vscale x 1 x i32> [[OP1:%.*]]) #[[ATTR0]] {682// CHECK-RV64-NEXT: entry:683// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.nxv1i32(<vscale x 2 x i32> poison, <vscale x 1 x i32> [[OP1]], i64 0)684// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]685//686vint32m1_t test_vlmul_ext_v_i32mf2_i32m1(vint32mf2_t op1) {687 return __riscv_vlmul_ext_i32m1(op1);688}689 690// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vlmul_ext_v_i32mf2_i32m2691// CHECK-RV64-SAME: (<vscale x 1 x i32> [[OP1:%.*]]) #[[ATTR0]] {692// CHECK-RV64-NEXT: entry:693// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.nxv1i32(<vscale x 4 x i32> poison, <vscale x 1 x i32> [[OP1]], i64 0)694// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]695//696vint32m2_t test_vlmul_ext_v_i32mf2_i32m2(vint32mf2_t op1) {697 return __riscv_vlmul_ext_i32m2(op1);698}699 700// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vlmul_ext_v_i32mf2_i32m4701// CHECK-RV64-SAME: (<vscale x 1 x i32> [[OP1:%.*]]) #[[ATTR0]] {702// CHECK-RV64-NEXT: entry:703// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv1i32(<vscale x 8 x i32> poison, <vscale x 1 x i32> [[OP1]], i64 0)704// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]705//706vint32m4_t test_vlmul_ext_v_i32mf2_i32m4(vint32mf2_t op1) {707 return __riscv_vlmul_ext_i32m4(op1);708}709 710// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vlmul_ext_v_i32mf2_i32m8711// CHECK-RV64-SAME: (<vscale x 1 x i32> [[OP1:%.*]]) #[[ATTR0]] {712// CHECK-RV64-NEXT: entry:713// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv1i32(<vscale x 16 x i32> poison, <vscale x 1 x i32> [[OP1]], i64 0)714// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]715//716vint32m8_t test_vlmul_ext_v_i32mf2_i32m8(vint32mf2_t op1) {717 return __riscv_vlmul_ext_i32m8(op1);718}719 720// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vlmul_ext_v_i32m1_i32m2721// CHECK-RV64-SAME: (<vscale x 2 x i32> [[OP1:%.*]]) #[[ATTR0]] {722// CHECK-RV64-NEXT: entry:723// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.nxv2i32(<vscale x 4 x i32> poison, <vscale x 2 x i32> [[OP1]], i64 0)724// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]725//726vint32m2_t test_vlmul_ext_v_i32m1_i32m2(vint32m1_t op1) {727 return __riscv_vlmul_ext_i32m2(op1);728}729 730// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vlmul_ext_v_i32m1_i32m4731// CHECK-RV64-SAME: (<vscale x 2 x i32> [[OP1:%.*]]) #[[ATTR0]] {732// CHECK-RV64-NEXT: entry:733// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv2i32(<vscale x 8 x i32> poison, <vscale x 2 x i32> [[OP1]], i64 0)734// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]735//736vint32m4_t test_vlmul_ext_v_i32m1_i32m4(vint32m1_t op1) {737 return __riscv_vlmul_ext_i32m4(op1);738}739 740// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vlmul_ext_v_i32m1_i32m8741// CHECK-RV64-SAME: (<vscale x 2 x i32> [[OP1:%.*]]) #[[ATTR0]] {742// CHECK-RV64-NEXT: entry:743// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv2i32(<vscale x 16 x i32> poison, <vscale x 2 x i32> [[OP1]], i64 0)744// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]745//746vint32m8_t test_vlmul_ext_v_i32m1_i32m8(vint32m1_t op1) {747 return __riscv_vlmul_ext_i32m8(op1);748}749 750// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vlmul_ext_v_i32m2_i32m4751// CHECK-RV64-SAME: (<vscale x 4 x i32> [[OP1:%.*]]) #[[ATTR0]] {752// CHECK-RV64-NEXT: entry:753// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv4i32(<vscale x 8 x i32> poison, <vscale x 4 x i32> [[OP1]], i64 0)754// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]755//756vint32m4_t test_vlmul_ext_v_i32m2_i32m4(vint32m2_t op1) {757 return __riscv_vlmul_ext_i32m4(op1);758}759 760// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vlmul_ext_v_i32m2_i32m8761// CHECK-RV64-SAME: (<vscale x 4 x i32> [[OP1:%.*]]) #[[ATTR0]] {762// CHECK-RV64-NEXT: entry:763// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32> poison, <vscale x 4 x i32> [[OP1]], i64 0)764// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]765//766vint32m8_t test_vlmul_ext_v_i32m2_i32m8(vint32m2_t op1) {767 return __riscv_vlmul_ext_i32m8(op1);768}769 770// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vlmul_ext_v_i32m4_i32m8771// CHECK-RV64-SAME: (<vscale x 8 x i32> [[OP1:%.*]]) #[[ATTR0]] {772// CHECK-RV64-NEXT: entry:773// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv8i32(<vscale x 16 x i32> poison, <vscale x 8 x i32> [[OP1]], i64 0)774// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]775//776vint32m8_t test_vlmul_ext_v_i32m4_i32m8(vint32m4_t op1) {777 return __riscv_vlmul_ext_i32m8(op1);778}779 780// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vlmul_ext_v_i64m1_i64m2781// CHECK-RV64-SAME: (<vscale x 1 x i64> [[OP1:%.*]]) #[[ATTR0]] {782// CHECK-RV64-NEXT: entry:783// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.nxv1i64(<vscale x 2 x i64> poison, <vscale x 1 x i64> [[OP1]], i64 0)784// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]785//786vint64m2_t test_vlmul_ext_v_i64m1_i64m2(vint64m1_t op1) {787 return __riscv_vlmul_ext_i64m2(op1);788}789 790// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vlmul_ext_v_i64m1_i64m4791// CHECK-RV64-SAME: (<vscale x 1 x i64> [[OP1:%.*]]) #[[ATTR0]] {792// CHECK-RV64-NEXT: entry:793// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.vector.insert.nxv4i64.nxv1i64(<vscale x 4 x i64> poison, <vscale x 1 x i64> [[OP1]], i64 0)794// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]795//796vint64m4_t test_vlmul_ext_v_i64m1_i64m4(vint64m1_t op1) {797 return __riscv_vlmul_ext_i64m4(op1);798}799 800// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vlmul_ext_v_i64m1_i64m8801// CHECK-RV64-SAME: (<vscale x 1 x i64> [[OP1:%.*]]) #[[ATTR0]] {802// CHECK-RV64-NEXT: entry:803// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.vector.insert.nxv8i64.nxv1i64(<vscale x 8 x i64> poison, <vscale x 1 x i64> [[OP1]], i64 0)804// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]805//806vint64m8_t test_vlmul_ext_v_i64m1_i64m8(vint64m1_t op1) {807 return __riscv_vlmul_ext_i64m8(op1);808}809 810// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vlmul_ext_v_i64m2_i64m4811// CHECK-RV64-SAME: (<vscale x 2 x i64> [[OP1:%.*]]) #[[ATTR0]] {812// CHECK-RV64-NEXT: entry:813// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.vector.insert.nxv4i64.nxv2i64(<vscale x 4 x i64> poison, <vscale x 2 x i64> [[OP1]], i64 0)814// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]815//816vint64m4_t test_vlmul_ext_v_i64m2_i64m4(vint64m2_t op1) {817 return __riscv_vlmul_ext_i64m4(op1);818}819 820// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vlmul_ext_v_i64m2_i64m8821// CHECK-RV64-SAME: (<vscale x 2 x i64> [[OP1:%.*]]) #[[ATTR0]] {822// CHECK-RV64-NEXT: entry:823// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.vector.insert.nxv8i64.nxv2i64(<vscale x 8 x i64> poison, <vscale x 2 x i64> [[OP1]], i64 0)824// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]825//826vint64m8_t test_vlmul_ext_v_i64m2_i64m8(vint64m2_t op1) {827 return __riscv_vlmul_ext_i64m8(op1);828}829 830// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vlmul_ext_v_i64m4_i64m8831// CHECK-RV64-SAME: (<vscale x 4 x i64> [[OP1:%.*]]) #[[ATTR0]] {832// CHECK-RV64-NEXT: entry:833// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.vector.insert.nxv8i64.nxv4i64(<vscale x 8 x i64> poison, <vscale x 4 x i64> [[OP1]], i64 0)834// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]835//836vint64m8_t test_vlmul_ext_v_i64m4_i64m8(vint64m4_t op1) {837 return __riscv_vlmul_ext_i64m8(op1);838}839 840// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vlmul_ext_v_u8mf8_u8mf4841// CHECK-RV64-SAME: (<vscale x 1 x i8> [[OP1:%.*]]) #[[ATTR0]] {842// CHECK-RV64-NEXT: entry:843// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.nxv1i8(<vscale x 2 x i8> poison, <vscale x 1 x i8> [[OP1]], i64 0)844// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]845//846vuint8mf4_t test_vlmul_ext_v_u8mf8_u8mf4(vuint8mf8_t op1) {847 return __riscv_vlmul_ext_u8mf4(op1);848}849 850// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vlmul_ext_v_u8mf8_u8mf2851// CHECK-RV64-SAME: (<vscale x 1 x i8> [[OP1:%.*]]) #[[ATTR0]] {852// CHECK-RV64-NEXT: entry:853// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.vector.insert.nxv4i8.nxv1i8(<vscale x 4 x i8> poison, <vscale x 1 x i8> [[OP1]], i64 0)854// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]855//856vuint8mf2_t test_vlmul_ext_v_u8mf8_u8mf2(vuint8mf8_t op1) {857 return __riscv_vlmul_ext_u8mf2(op1);858}859 860// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vlmul_ext_v_u8mf8_u8m1861// CHECK-RV64-SAME: (<vscale x 1 x i8> [[OP1:%.*]]) #[[ATTR0]] {862// CHECK-RV64-NEXT: entry:863// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.nxv1i8(<vscale x 8 x i8> poison, <vscale x 1 x i8> [[OP1]], i64 0)864// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]865//866vuint8m1_t test_vlmul_ext_v_u8mf8_u8m1(vuint8mf8_t op1) {867 return __riscv_vlmul_ext_u8m1(op1);868}869 870// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vlmul_ext_v_u8mf8_u8m2871// CHECK-RV64-SAME: (<vscale x 1 x i8> [[OP1:%.*]]) #[[ATTR0]] {872// CHECK-RV64-NEXT: entry:873// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv1i8(<vscale x 16 x i8> poison, <vscale x 1 x i8> [[OP1]], i64 0)874// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]875//876vuint8m2_t test_vlmul_ext_v_u8mf8_u8m2(vuint8mf8_t op1) {877 return __riscv_vlmul_ext_u8m2(op1);878}879 880// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vlmul_ext_v_u8mf8_u8m4881// CHECK-RV64-SAME: (<vscale x 1 x i8> [[OP1:%.*]]) #[[ATTR0]] {882// CHECK-RV64-NEXT: entry:883// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv1i8(<vscale x 32 x i8> poison, <vscale x 1 x i8> [[OP1]], i64 0)884// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]885//886vuint8m4_t test_vlmul_ext_v_u8mf8_u8m4(vuint8mf8_t op1) {887 return __riscv_vlmul_ext_u8m4(op1);888}889 890// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vlmul_ext_v_u8mf8_u8m8891// CHECK-RV64-SAME: (<vscale x 1 x i8> [[OP1:%.*]]) #[[ATTR0]] {892// CHECK-RV64-NEXT: entry:893// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv1i8(<vscale x 64 x i8> poison, <vscale x 1 x i8> [[OP1]], i64 0)894// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]895//896vuint8m8_t test_vlmul_ext_v_u8mf8_u8m8(vuint8mf8_t op1) {897 return __riscv_vlmul_ext_u8m8(op1);898}899 900// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vlmul_ext_v_u8mf4_u8mf2901// CHECK-RV64-SAME: (<vscale x 2 x i8> [[OP1:%.*]]) #[[ATTR0]] {902// CHECK-RV64-NEXT: entry:903// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.vector.insert.nxv4i8.nxv2i8(<vscale x 4 x i8> poison, <vscale x 2 x i8> [[OP1]], i64 0)904// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]905//906vuint8mf2_t test_vlmul_ext_v_u8mf4_u8mf2(vuint8mf4_t op1) {907 return __riscv_vlmul_ext_u8mf2(op1);908}909 910// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vlmul_ext_v_u8mf4_u8m1911// CHECK-RV64-SAME: (<vscale x 2 x i8> [[OP1:%.*]]) #[[ATTR0]] {912// CHECK-RV64-NEXT: entry:913// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.nxv2i8(<vscale x 8 x i8> poison, <vscale x 2 x i8> [[OP1]], i64 0)914// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]915//916vuint8m1_t test_vlmul_ext_v_u8mf4_u8m1(vuint8mf4_t op1) {917 return __riscv_vlmul_ext_u8m1(op1);918}919 920// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vlmul_ext_v_u8mf4_u8m2921// CHECK-RV64-SAME: (<vscale x 2 x i8> [[OP1:%.*]]) #[[ATTR0]] {922// CHECK-RV64-NEXT: entry:923// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv2i8(<vscale x 16 x i8> poison, <vscale x 2 x i8> [[OP1]], i64 0)924// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]925//926vuint8m2_t test_vlmul_ext_v_u8mf4_u8m2(vuint8mf4_t op1) {927 return __riscv_vlmul_ext_u8m2(op1);928}929 930// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vlmul_ext_v_u8mf4_u8m4931// CHECK-RV64-SAME: (<vscale x 2 x i8> [[OP1:%.*]]) #[[ATTR0]] {932// CHECK-RV64-NEXT: entry:933// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv2i8(<vscale x 32 x i8> poison, <vscale x 2 x i8> [[OP1]], i64 0)934// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]935//936vuint8m4_t test_vlmul_ext_v_u8mf4_u8m4(vuint8mf4_t op1) {937 return __riscv_vlmul_ext_u8m4(op1);938}939 940// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vlmul_ext_v_u8mf4_u8m8941// CHECK-RV64-SAME: (<vscale x 2 x i8> [[OP1:%.*]]) #[[ATTR0]] {942// CHECK-RV64-NEXT: entry:943// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv2i8(<vscale x 64 x i8> poison, <vscale x 2 x i8> [[OP1]], i64 0)944// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]945//946vuint8m8_t test_vlmul_ext_v_u8mf4_u8m8(vuint8mf4_t op1) {947 return __riscv_vlmul_ext_u8m8(op1);948}949 950// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vlmul_ext_v_u8mf2_u8m1951// CHECK-RV64-SAME: (<vscale x 4 x i8> [[OP1:%.*]]) #[[ATTR0]] {952// CHECK-RV64-NEXT: entry:953// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.nxv4i8(<vscale x 8 x i8> poison, <vscale x 4 x i8> [[OP1]], i64 0)954// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]955//956vuint8m1_t test_vlmul_ext_v_u8mf2_u8m1(vuint8mf2_t op1) {957 return __riscv_vlmul_ext_u8m1(op1);958}959 960// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vlmul_ext_v_u8mf2_u8m2961// CHECK-RV64-SAME: (<vscale x 4 x i8> [[OP1:%.*]]) #[[ATTR0]] {962// CHECK-RV64-NEXT: entry:963// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv4i8(<vscale x 16 x i8> poison, <vscale x 4 x i8> [[OP1]], i64 0)964// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]965//966vuint8m2_t test_vlmul_ext_v_u8mf2_u8m2(vuint8mf2_t op1) {967 return __riscv_vlmul_ext_u8m2(op1);968}969 970// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vlmul_ext_v_u8mf2_u8m4971// CHECK-RV64-SAME: (<vscale x 4 x i8> [[OP1:%.*]]) #[[ATTR0]] {972// CHECK-RV64-NEXT: entry:973// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv4i8(<vscale x 32 x i8> poison, <vscale x 4 x i8> [[OP1]], i64 0)974// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]975//976vuint8m4_t test_vlmul_ext_v_u8mf2_u8m4(vuint8mf2_t op1) {977 return __riscv_vlmul_ext_u8m4(op1);978}979 980// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vlmul_ext_v_u8mf2_u8m8981// CHECK-RV64-SAME: (<vscale x 4 x i8> [[OP1:%.*]]) #[[ATTR0]] {982// CHECK-RV64-NEXT: entry:983// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv4i8(<vscale x 64 x i8> poison, <vscale x 4 x i8> [[OP1]], i64 0)984// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]985//986vuint8m8_t test_vlmul_ext_v_u8mf2_u8m8(vuint8mf2_t op1) {987 return __riscv_vlmul_ext_u8m8(op1);988}989 990// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vlmul_ext_v_u8m1_u8m2991// CHECK-RV64-SAME: (<vscale x 8 x i8> [[OP1:%.*]]) #[[ATTR0]] {992// CHECK-RV64-NEXT: entry:993// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8> poison, <vscale x 8 x i8> [[OP1]], i64 0)994// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]995//996vuint8m2_t test_vlmul_ext_v_u8m1_u8m2(vuint8m1_t op1) {997 return __riscv_vlmul_ext_u8m2(op1);998}999 1000// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vlmul_ext_v_u8m1_u8m41001// CHECK-RV64-SAME: (<vscale x 8 x i8> [[OP1:%.*]]) #[[ATTR0]] {1002// CHECK-RV64-NEXT: entry:1003// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv8i8(<vscale x 32 x i8> poison, <vscale x 8 x i8> [[OP1]], i64 0)1004// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]1005//1006vuint8m4_t test_vlmul_ext_v_u8m1_u8m4(vuint8m1_t op1) {1007 return __riscv_vlmul_ext_u8m4(op1);1008}1009 1010// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vlmul_ext_v_u8m1_u8m81011// CHECK-RV64-SAME: (<vscale x 8 x i8> [[OP1:%.*]]) #[[ATTR0]] {1012// CHECK-RV64-NEXT: entry:1013// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv8i8(<vscale x 64 x i8> poison, <vscale x 8 x i8> [[OP1]], i64 0)1014// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]1015//1016vuint8m8_t test_vlmul_ext_v_u8m1_u8m8(vuint8m1_t op1) {1017 return __riscv_vlmul_ext_u8m8(op1);1018}1019 1020// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vlmul_ext_v_u8m2_u8m41021// CHECK-RV64-SAME: (<vscale x 16 x i8> [[OP1:%.*]]) #[[ATTR0]] {1022// CHECK-RV64-NEXT: entry:1023// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv16i8(<vscale x 32 x i8> poison, <vscale x 16 x i8> [[OP1]], i64 0)1024// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]1025//1026vuint8m4_t test_vlmul_ext_v_u8m2_u8m4(vuint8m2_t op1) {1027 return __riscv_vlmul_ext_u8m4(op1);1028}1029 1030// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vlmul_ext_v_u8m2_u8m81031// CHECK-RV64-SAME: (<vscale x 16 x i8> [[OP1:%.*]]) #[[ATTR0]] {1032// CHECK-RV64-NEXT: entry:1033// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv16i8(<vscale x 64 x i8> poison, <vscale x 16 x i8> [[OP1]], i64 0)1034// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]1035//1036vuint8m8_t test_vlmul_ext_v_u8m2_u8m8(vuint8m2_t op1) {1037 return __riscv_vlmul_ext_u8m8(op1);1038}1039 1040// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vlmul_ext_v_u8m4_u8m81041// CHECK-RV64-SAME: (<vscale x 32 x i8> [[OP1:%.*]]) #[[ATTR0]] {1042// CHECK-RV64-NEXT: entry:1043// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv32i8(<vscale x 64 x i8> poison, <vscale x 32 x i8> [[OP1]], i64 0)1044// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]1045//1046vuint8m8_t test_vlmul_ext_v_u8m4_u8m8(vuint8m4_t op1) {1047 return __riscv_vlmul_ext_u8m8(op1);1048}1049 1050// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vlmul_ext_v_u16mf4_u16mf21051// CHECK-RV64-SAME: (<vscale x 1 x i16> [[OP1:%.*]]) #[[ATTR0]] {1052// CHECK-RV64-NEXT: entry:1053// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.vector.insert.nxv2i16.nxv1i16(<vscale x 2 x i16> poison, <vscale x 1 x i16> [[OP1]], i64 0)1054// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]1055//1056vuint16mf2_t test_vlmul_ext_v_u16mf4_u16mf2(vuint16mf4_t op1) {1057 return __riscv_vlmul_ext_u16mf2(op1);1058}1059 1060// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vlmul_ext_v_u16mf4_u16m11061// CHECK-RV64-SAME: (<vscale x 1 x i16> [[OP1:%.*]]) #[[ATTR0]] {1062// CHECK-RV64-NEXT: entry:1063// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.nxv1i16(<vscale x 4 x i16> poison, <vscale x 1 x i16> [[OP1]], i64 0)1064// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]1065//1066vuint16m1_t test_vlmul_ext_v_u16mf4_u16m1(vuint16mf4_t op1) {1067 return __riscv_vlmul_ext_u16m1(op1);1068}1069 1070// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vlmul_ext_v_u16mf4_u16m21071// CHECK-RV64-SAME: (<vscale x 1 x i16> [[OP1:%.*]]) #[[ATTR0]] {1072// CHECK-RV64-NEXT: entry:1073// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> [[OP1]], i64 0)1074// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]1075//1076vuint16m2_t test_vlmul_ext_v_u16mf4_u16m2(vuint16mf4_t op1) {1077 return __riscv_vlmul_ext_u16m2(op1);1078}1079 1080// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vlmul_ext_v_u16mf4_u16m41081// CHECK-RV64-SAME: (<vscale x 1 x i16> [[OP1:%.*]]) #[[ATTR0]] {1082// CHECK-RV64-NEXT: entry:1083// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.vector.insert.nxv16i16.nxv1i16(<vscale x 16 x i16> poison, <vscale x 1 x i16> [[OP1]], i64 0)1084// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]1085//1086vuint16m4_t test_vlmul_ext_v_u16mf4_u16m4(vuint16mf4_t op1) {1087 return __riscv_vlmul_ext_u16m4(op1);1088}1089 1090// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vlmul_ext_v_u16mf4_u16m81091// CHECK-RV64-SAME: (<vscale x 1 x i16> [[OP1:%.*]]) #[[ATTR0]] {1092// CHECK-RV64-NEXT: entry:1093// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv1i16(<vscale x 32 x i16> poison, <vscale x 1 x i16> [[OP1]], i64 0)1094// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]1095//1096vuint16m8_t test_vlmul_ext_v_u16mf4_u16m8(vuint16mf4_t op1) {1097 return __riscv_vlmul_ext_u16m8(op1);1098}1099 1100// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vlmul_ext_v_u16mf2_u16m11101// CHECK-RV64-SAME: (<vscale x 2 x i16> [[OP1:%.*]]) #[[ATTR0]] {1102// CHECK-RV64-NEXT: entry:1103// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.nxv2i16(<vscale x 4 x i16> poison, <vscale x 2 x i16> [[OP1]], i64 0)1104// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]1105//1106vuint16m1_t test_vlmul_ext_v_u16mf2_u16m1(vuint16mf2_t op1) {1107 return __riscv_vlmul_ext_u16m1(op1);1108}1109 1110// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vlmul_ext_v_u16mf2_u16m21111// CHECK-RV64-SAME: (<vscale x 2 x i16> [[OP1:%.*]]) #[[ATTR0]] {1112// CHECK-RV64-NEXT: entry:1113// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv2i16(<vscale x 8 x i16> poison, <vscale x 2 x i16> [[OP1]], i64 0)1114// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]1115//1116vuint16m2_t test_vlmul_ext_v_u16mf2_u16m2(vuint16mf2_t op1) {1117 return __riscv_vlmul_ext_u16m2(op1);1118}1119 1120// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vlmul_ext_v_u16mf2_u16m41121// CHECK-RV64-SAME: (<vscale x 2 x i16> [[OP1:%.*]]) #[[ATTR0]] {1122// CHECK-RV64-NEXT: entry:1123// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.vector.insert.nxv16i16.nxv2i16(<vscale x 16 x i16> poison, <vscale x 2 x i16> [[OP1]], i64 0)1124// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]1125//1126vuint16m4_t test_vlmul_ext_v_u16mf2_u16m4(vuint16mf2_t op1) {1127 return __riscv_vlmul_ext_u16m4(op1);1128}1129 1130// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vlmul_ext_v_u16mf2_u16m81131// CHECK-RV64-SAME: (<vscale x 2 x i16> [[OP1:%.*]]) #[[ATTR0]] {1132// CHECK-RV64-NEXT: entry:1133// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv2i16(<vscale x 32 x i16> poison, <vscale x 2 x i16> [[OP1]], i64 0)1134// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]1135//1136vuint16m8_t test_vlmul_ext_v_u16mf2_u16m8(vuint16mf2_t op1) {1137 return __riscv_vlmul_ext_u16m8(op1);1138}1139 1140// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vlmul_ext_v_u16m1_u16m21141// CHECK-RV64-SAME: (<vscale x 4 x i16> [[OP1:%.*]]) #[[ATTR0]] {1142// CHECK-RV64-NEXT: entry:1143// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv4i16(<vscale x 8 x i16> poison, <vscale x 4 x i16> [[OP1]], i64 0)1144// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]1145//1146vuint16m2_t test_vlmul_ext_v_u16m1_u16m2(vuint16m1_t op1) {1147 return __riscv_vlmul_ext_u16m2(op1);1148}1149 1150// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vlmul_ext_v_u16m1_u16m41151// CHECK-RV64-SAME: (<vscale x 4 x i16> [[OP1:%.*]]) #[[ATTR0]] {1152// CHECK-RV64-NEXT: entry:1153// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.vector.insert.nxv16i16.nxv4i16(<vscale x 16 x i16> poison, <vscale x 4 x i16> [[OP1]], i64 0)1154// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]1155//1156vuint16m4_t test_vlmul_ext_v_u16m1_u16m4(vuint16m1_t op1) {1157 return __riscv_vlmul_ext_u16m4(op1);1158}1159 1160// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vlmul_ext_v_u16m1_u16m81161// CHECK-RV64-SAME: (<vscale x 4 x i16> [[OP1:%.*]]) #[[ATTR0]] {1162// CHECK-RV64-NEXT: entry:1163// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv4i16(<vscale x 32 x i16> poison, <vscale x 4 x i16> [[OP1]], i64 0)1164// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]1165//1166vuint16m8_t test_vlmul_ext_v_u16m1_u16m8(vuint16m1_t op1) {1167 return __riscv_vlmul_ext_u16m8(op1);1168}1169 1170// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vlmul_ext_v_u16m2_u16m41171// CHECK-RV64-SAME: (<vscale x 8 x i16> [[OP1:%.*]]) #[[ATTR0]] {1172// CHECK-RV64-NEXT: entry:1173// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.vector.insert.nxv16i16.nxv8i16(<vscale x 16 x i16> poison, <vscale x 8 x i16> [[OP1]], i64 0)1174// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]1175//1176vuint16m4_t test_vlmul_ext_v_u16m2_u16m4(vuint16m2_t op1) {1177 return __riscv_vlmul_ext_u16m4(op1);1178}1179 1180// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vlmul_ext_v_u16m2_u16m81181// CHECK-RV64-SAME: (<vscale x 8 x i16> [[OP1:%.*]]) #[[ATTR0]] {1182// CHECK-RV64-NEXT: entry:1183// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv8i16(<vscale x 32 x i16> poison, <vscale x 8 x i16> [[OP1]], i64 0)1184// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]1185//1186vuint16m8_t test_vlmul_ext_v_u16m2_u16m8(vuint16m2_t op1) {1187 return __riscv_vlmul_ext_u16m8(op1);1188}1189 1190// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vlmul_ext_v_u16m4_u16m81191// CHECK-RV64-SAME: (<vscale x 16 x i16> [[OP1:%.*]]) #[[ATTR0]] {1192// CHECK-RV64-NEXT: entry:1193// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.vector.insert.nxv32i16.nxv16i16(<vscale x 32 x i16> poison, <vscale x 16 x i16> [[OP1]], i64 0)1194// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]1195//1196vuint16m8_t test_vlmul_ext_v_u16m4_u16m8(vuint16m4_t op1) {1197 return __riscv_vlmul_ext_u16m8(op1);1198}1199 1200// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vlmul_ext_v_u32mf2_u32m11201// CHECK-RV64-SAME: (<vscale x 1 x i32> [[OP1:%.*]]) #[[ATTR0]] {1202// CHECK-RV64-NEXT: entry:1203// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.nxv1i32(<vscale x 2 x i32> poison, <vscale x 1 x i32> [[OP1]], i64 0)1204// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]1205//1206vuint32m1_t test_vlmul_ext_v_u32mf2_u32m1(vuint32mf2_t op1) {1207 return __riscv_vlmul_ext_u32m1(op1);1208}1209 1210// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vlmul_ext_v_u32mf2_u32m21211// CHECK-RV64-SAME: (<vscale x 1 x i32> [[OP1:%.*]]) #[[ATTR0]] {1212// CHECK-RV64-NEXT: entry:1213// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.nxv1i32(<vscale x 4 x i32> poison, <vscale x 1 x i32> [[OP1]], i64 0)1214// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]1215//1216vuint32m2_t test_vlmul_ext_v_u32mf2_u32m2(vuint32mf2_t op1) {1217 return __riscv_vlmul_ext_u32m2(op1);1218}1219 1220// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vlmul_ext_v_u32mf2_u32m41221// CHECK-RV64-SAME: (<vscale x 1 x i32> [[OP1:%.*]]) #[[ATTR0]] {1222// CHECK-RV64-NEXT: entry:1223// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv1i32(<vscale x 8 x i32> poison, <vscale x 1 x i32> [[OP1]], i64 0)1224// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]1225//1226vuint32m4_t test_vlmul_ext_v_u32mf2_u32m4(vuint32mf2_t op1) {1227 return __riscv_vlmul_ext_u32m4(op1);1228}1229 1230// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vlmul_ext_v_u32mf2_u32m81231// CHECK-RV64-SAME: (<vscale x 1 x i32> [[OP1:%.*]]) #[[ATTR0]] {1232// CHECK-RV64-NEXT: entry:1233// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv1i32(<vscale x 16 x i32> poison, <vscale x 1 x i32> [[OP1]], i64 0)1234// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]1235//1236vuint32m8_t test_vlmul_ext_v_u32mf2_u32m8(vuint32mf2_t op1) {1237 return __riscv_vlmul_ext_u32m8(op1);1238}1239 1240// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vlmul_ext_v_u32m1_u32m21241// CHECK-RV64-SAME: (<vscale x 2 x i32> [[OP1:%.*]]) #[[ATTR0]] {1242// CHECK-RV64-NEXT: entry:1243// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.nxv2i32(<vscale x 4 x i32> poison, <vscale x 2 x i32> [[OP1]], i64 0)1244// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]1245//1246vuint32m2_t test_vlmul_ext_v_u32m1_u32m2(vuint32m1_t op1) {1247 return __riscv_vlmul_ext_u32m2(op1);1248}1249 1250// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vlmul_ext_v_u32m1_u32m41251// CHECK-RV64-SAME: (<vscale x 2 x i32> [[OP1:%.*]]) #[[ATTR0]] {1252// CHECK-RV64-NEXT: entry:1253// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv2i32(<vscale x 8 x i32> poison, <vscale x 2 x i32> [[OP1]], i64 0)1254// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]1255//1256vuint32m4_t test_vlmul_ext_v_u32m1_u32m4(vuint32m1_t op1) {1257 return __riscv_vlmul_ext_u32m4(op1);1258}1259 1260// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vlmul_ext_v_u32m1_u32m81261// CHECK-RV64-SAME: (<vscale x 2 x i32> [[OP1:%.*]]) #[[ATTR0]] {1262// CHECK-RV64-NEXT: entry:1263// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv2i32(<vscale x 16 x i32> poison, <vscale x 2 x i32> [[OP1]], i64 0)1264// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]1265//1266vuint32m8_t test_vlmul_ext_v_u32m1_u32m8(vuint32m1_t op1) {1267 return __riscv_vlmul_ext_u32m8(op1);1268}1269 1270// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vlmul_ext_v_u32m2_u32m41271// CHECK-RV64-SAME: (<vscale x 4 x i32> [[OP1:%.*]]) #[[ATTR0]] {1272// CHECK-RV64-NEXT: entry:1273// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv4i32(<vscale x 8 x i32> poison, <vscale x 4 x i32> [[OP1]], i64 0)1274// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]1275//1276vuint32m4_t test_vlmul_ext_v_u32m2_u32m4(vuint32m2_t op1) {1277 return __riscv_vlmul_ext_u32m4(op1);1278}1279 1280// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vlmul_ext_v_u32m2_u32m81281// CHECK-RV64-SAME: (<vscale x 4 x i32> [[OP1:%.*]]) #[[ATTR0]] {1282// CHECK-RV64-NEXT: entry:1283// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32> poison, <vscale x 4 x i32> [[OP1]], i64 0)1284// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]1285//1286vuint32m8_t test_vlmul_ext_v_u32m2_u32m8(vuint32m2_t op1) {1287 return __riscv_vlmul_ext_u32m8(op1);1288}1289 1290// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vlmul_ext_v_u32m4_u32m81291// CHECK-RV64-SAME: (<vscale x 8 x i32> [[OP1:%.*]]) #[[ATTR0]] {1292// CHECK-RV64-NEXT: entry:1293// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv8i32(<vscale x 16 x i32> poison, <vscale x 8 x i32> [[OP1]], i64 0)1294// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]1295//1296vuint32m8_t test_vlmul_ext_v_u32m4_u32m8(vuint32m4_t op1) {1297 return __riscv_vlmul_ext_u32m8(op1);1298}1299 1300// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vlmul_ext_v_u64m1_u64m21301// CHECK-RV64-SAME: (<vscale x 1 x i64> [[OP1:%.*]]) #[[ATTR0]] {1302// CHECK-RV64-NEXT: entry:1303// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.nxv1i64(<vscale x 2 x i64> poison, <vscale x 1 x i64> [[OP1]], i64 0)1304// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]1305//1306vuint64m2_t test_vlmul_ext_v_u64m1_u64m2(vuint64m1_t op1) {1307 return __riscv_vlmul_ext_u64m2(op1);1308}1309 1310// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vlmul_ext_v_u64m1_u64m41311// CHECK-RV64-SAME: (<vscale x 1 x i64> [[OP1:%.*]]) #[[ATTR0]] {1312// CHECK-RV64-NEXT: entry:1313// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.vector.insert.nxv4i64.nxv1i64(<vscale x 4 x i64> poison, <vscale x 1 x i64> [[OP1]], i64 0)1314// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]1315//1316vuint64m4_t test_vlmul_ext_v_u64m1_u64m4(vuint64m1_t op1) {1317 return __riscv_vlmul_ext_u64m4(op1);1318}1319 1320// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vlmul_ext_v_u64m1_u64m81321// CHECK-RV64-SAME: (<vscale x 1 x i64> [[OP1:%.*]]) #[[ATTR0]] {1322// CHECK-RV64-NEXT: entry:1323// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.vector.insert.nxv8i64.nxv1i64(<vscale x 8 x i64> poison, <vscale x 1 x i64> [[OP1]], i64 0)1324// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]1325//1326vuint64m8_t test_vlmul_ext_v_u64m1_u64m8(vuint64m1_t op1) {1327 return __riscv_vlmul_ext_u64m8(op1);1328}1329 1330// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vlmul_ext_v_u64m2_u64m41331// CHECK-RV64-SAME: (<vscale x 2 x i64> [[OP1:%.*]]) #[[ATTR0]] {1332// CHECK-RV64-NEXT: entry:1333// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.vector.insert.nxv4i64.nxv2i64(<vscale x 4 x i64> poison, <vscale x 2 x i64> [[OP1]], i64 0)1334// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]1335//1336vuint64m4_t test_vlmul_ext_v_u64m2_u64m4(vuint64m2_t op1) {1337 return __riscv_vlmul_ext_u64m4(op1);1338}1339 1340// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vlmul_ext_v_u64m2_u64m81341// CHECK-RV64-SAME: (<vscale x 2 x i64> [[OP1:%.*]]) #[[ATTR0]] {1342// CHECK-RV64-NEXT: entry:1343// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.vector.insert.nxv8i64.nxv2i64(<vscale x 8 x i64> poison, <vscale x 2 x i64> [[OP1]], i64 0)1344// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]1345//1346vuint64m8_t test_vlmul_ext_v_u64m2_u64m8(vuint64m2_t op1) {1347 return __riscv_vlmul_ext_u64m8(op1);1348}1349 1350// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vlmul_ext_v_u64m4_u64m81351// CHECK-RV64-SAME: (<vscale x 4 x i64> [[OP1:%.*]]) #[[ATTR0]] {1352// CHECK-RV64-NEXT: entry:1353// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.vector.insert.nxv8i64.nxv4i64(<vscale x 8 x i64> poison, <vscale x 4 x i64> [[OP1]], i64 0)1354// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]1355//1356vuint64m8_t test_vlmul_ext_v_u64m4_u64m8(vuint64m4_t op1) {1357 return __riscv_vlmul_ext_u64m8(op1);1358}1359 1360