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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 22// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone \4// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \5// RUN: FileCheck --check-prefix=CHECK-RV64 %s6 7#include <riscv_vector.h>8 9// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8_v_i8mf8x3_m10// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {11// CHECK-RV64-NEXT: entry:12// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3, i64 3)13// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) [[TMP0]]14//15vint8mf8x3_t test_vlseg3e8_v_i8mf8x3_m(vbool64_t mask, const int8_t *base, size_t vl) {16 return __riscv_vlseg3e8(mask, base, vl);17}18 19// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8_v_i8mf4x3_m20// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {21// CHECK-RV64-NEXT: entry:22// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr [[BASE]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3, i64 3)23// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) [[TMP0]]24//25vint8mf4x3_t test_vlseg3e8_v_i8mf4x3_m(vbool32_t mask, const int8_t *base, size_t vl) {26 return __riscv_vlseg3e8(mask, base, vl);27}28 29// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8_v_i8mf2x3_m30// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {31// CHECK-RV64-NEXT: entry:32// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr [[BASE]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3, i64 3)33// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[TMP0]]34//35vint8mf2x3_t test_vlseg3e8_v_i8mf2x3_m(vbool16_t mask, const int8_t *base, size_t vl) {36 return __riscv_vlseg3e8(mask, base, vl);37}38 39// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e8_v_i8m1x3_m40// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {41// CHECK-RV64-NEXT: entry:42// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr [[BASE]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3, i64 3)43// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) [[TMP0]]44//45vint8m1x3_t test_vlseg3e8_v_i8m1x3_m(vbool8_t mask, const int8_t *base, size_t vl) {46 return __riscv_vlseg3e8(mask, base, vl);47}48 49// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e8_v_i8m2x3_m50// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {51// CHECK-RV64-NEXT: entry:52// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr [[BASE]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3, i64 3)53// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) [[TMP0]]54//55vint8m2x3_t test_vlseg3e8_v_i8m2x3_m(vbool4_t mask, const int8_t *base, size_t vl) {56 return __riscv_vlseg3e8(mask, base, vl);57}58 59// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8_v_u8mf8x3_m60// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {61// CHECK-RV64-NEXT: entry:62// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3, i64 3)63// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) [[TMP0]]64//65vuint8mf8x3_t test_vlseg3e8_v_u8mf8x3_m(vbool64_t mask, const uint8_t *base, size_t vl) {66 return __riscv_vlseg3e8(mask, base, vl);67}68 69// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8_v_u8mf4x3_m70// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {71// CHECK-RV64-NEXT: entry:72// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr [[BASE]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3, i64 3)73// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) [[TMP0]]74//75vuint8mf4x3_t test_vlseg3e8_v_u8mf4x3_m(vbool32_t mask, const uint8_t *base, size_t vl) {76 return __riscv_vlseg3e8(mask, base, vl);77}78 79// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8_v_u8mf2x3_m80// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {81// CHECK-RV64-NEXT: entry:82// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr [[BASE]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3, i64 3)83// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[TMP0]]84//85vuint8mf2x3_t test_vlseg3e8_v_u8mf2x3_m(vbool16_t mask, const uint8_t *base, size_t vl) {86 return __riscv_vlseg3e8(mask, base, vl);87}88 89// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e8_v_u8m1x3_m90// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {91// CHECK-RV64-NEXT: entry:92// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr [[BASE]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3, i64 3)93// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) [[TMP0]]94//95vuint8m1x3_t test_vlseg3e8_v_u8m1x3_m(vbool8_t mask, const uint8_t *base, size_t vl) {96 return __riscv_vlseg3e8(mask, base, vl);97}98 99// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e8_v_u8m2x3_m100// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {101// CHECK-RV64-NEXT: entry:102// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr [[BASE]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3, i64 3)103// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) [[TMP0]]104//105vuint8m2x3_t test_vlseg3e8_v_u8m2x3_m(vbool4_t mask, const uint8_t *base, size_t vl) {106 return __riscv_vlseg3e8(mask, base, vl);107}108 109