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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 22// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone \4// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \5// RUN: FileCheck --check-prefix=CHECK-RV64 %s6 7#include <riscv_vector.h>8 9// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i1> @test_vmnand_mm_b110// CHECK-RV64-SAME: (<vscale x 64 x i1> [[OP1:%.*]], <vscale x 64 x i1> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {11// CHECK-RV64-NEXT: entry:12// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1> [[OP1]], <vscale x 64 x i1> [[OP2]], i64 [[VL]])13// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]14//15vbool1_t test_vmnand_mm_b1(vbool1_t op1, vbool1_t op2, size_t vl) {16 return __riscv_vmnand(op1, op2, vl);17}18 19// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vmnand_mm_b220// CHECK-RV64-SAME: (<vscale x 32 x i1> [[OP1:%.*]], <vscale x 32 x i1> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {21// CHECK-RV64-NEXT: entry:22// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1.i64(<vscale x 32 x i1> [[OP1]], <vscale x 32 x i1> [[OP2]], i64 [[VL]])23// CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]24//25vbool2_t test_vmnand_mm_b2(vbool2_t op1, vbool2_t op2, size_t vl) {26 return __riscv_vmnand(op1, op2, vl);27}28 29// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmnand_mm_b430// CHECK-RV64-SAME: (<vscale x 16 x i1> [[OP1:%.*]], <vscale x 16 x i1> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {31// CHECK-RV64-NEXT: entry:32// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1.i64(<vscale x 16 x i1> [[OP1]], <vscale x 16 x i1> [[OP2]], i64 [[VL]])33// CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]34//35vbool4_t test_vmnand_mm_b4(vbool4_t op1, vbool4_t op2, size_t vl) {36 return __riscv_vmnand(op1, op2, vl);37}38 39// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmnand_mm_b840// CHECK-RV64-SAME: (<vscale x 8 x i1> [[OP1:%.*]], <vscale x 8 x i1> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {41// CHECK-RV64-NEXT: entry:42// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1.i64(<vscale x 8 x i1> [[OP1]], <vscale x 8 x i1> [[OP2]], i64 [[VL]])43// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]44//45vbool8_t test_vmnand_mm_b8(vbool8_t op1, vbool8_t op2, size_t vl) {46 return __riscv_vmnand(op1, op2, vl);47}48 49// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmnand_mm_b1650// CHECK-RV64-SAME: (<vscale x 4 x i1> [[OP1:%.*]], <vscale x 4 x i1> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {51// CHECK-RV64-NEXT: entry:52// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1.i64(<vscale x 4 x i1> [[OP1]], <vscale x 4 x i1> [[OP2]], i64 [[VL]])53// CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]54//55vbool16_t test_vmnand_mm_b16(vbool16_t op1, vbool16_t op2, size_t vl) {56 return __riscv_vmnand(op1, op2, vl);57}58 59// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmnand_mm_b3260// CHECK-RV64-SAME: (<vscale x 2 x i1> [[OP1:%.*]], <vscale x 2 x i1> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {61// CHECK-RV64-NEXT: entry:62// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1.i64(<vscale x 2 x i1> [[OP1]], <vscale x 2 x i1> [[OP2]], i64 [[VL]])63// CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]64//65vbool32_t test_vmnand_mm_b32(vbool32_t op1, vbool32_t op2, size_t vl) {66 return __riscv_vmnand(op1, op2, vl);67}68 69// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmnand_mm_b6470// CHECK-RV64-SAME: (<vscale x 1 x i1> [[OP1:%.*]], <vscale x 1 x i1> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {71// CHECK-RV64-NEXT: entry:72// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1.i64(<vscale x 1 x i1> [[OP1]], <vscale x 1 x i1> [[OP2]], i64 [[VL]])73// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]74//75vbool64_t test_vmnand_mm_b64(vbool64_t op1, vbool64_t op2, size_t vl) {76 return __riscv_vmnand(op1, op2, vl);77}78 79