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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 22// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \4// RUN: -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone \5// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \6// RUN: FileCheck --check-prefix=CHECK-RV64 %s7 8#include <riscv_vector.h>9 10// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vmv_v_v_i8mf811// CHECK-RV64-SAME: (<vscale x 1 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {12// CHECK-RV64-NEXT: entry:13// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> [[SRC]], i64 [[VL]])14// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]15//16vint8mf8_t test_vmv_v_v_i8mf8(vint8mf8_t src, size_t vl) {17 return __riscv_vmv_v(src, vl);18}19 20// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vmv_v_v_i8mf421// CHECK-RV64-SAME: (<vscale x 2 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {22// CHECK-RV64-NEXT: entry:23// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> [[SRC]], i64 [[VL]])24// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]25//26vint8mf4_t test_vmv_v_v_i8mf4(vint8mf4_t src, size_t vl) {27 return __riscv_vmv_v(src, vl);28}29 30// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vmv_v_v_i8mf231// CHECK-RV64-SAME: (<vscale x 4 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {32// CHECK-RV64-NEXT: entry:33// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> [[SRC]], i64 [[VL]])34// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]35//36vint8mf2_t test_vmv_v_v_i8mf2(vint8mf2_t src, size_t vl) {37 return __riscv_vmv_v(src, vl);38}39 40// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vmv_v_v_i8m141// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {42// CHECK-RV64-NEXT: entry:43// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> [[SRC]], i64 [[VL]])44// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]45//46vint8m1_t test_vmv_v_v_i8m1(vint8m1_t src, size_t vl) {47 return __riscv_vmv_v(src, vl);48}49 50// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vmv_v_v_i8m251// CHECK-RV64-SAME: (<vscale x 16 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {52// CHECK-RV64-NEXT: entry:53// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> [[SRC]], i64 [[VL]])54// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]55//56vint8m2_t test_vmv_v_v_i8m2(vint8m2_t src, size_t vl) {57 return __riscv_vmv_v(src, vl);58}59 60// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vmv_v_v_i8m461// CHECK-RV64-SAME: (<vscale x 32 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {62// CHECK-RV64-NEXT: entry:63// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmv.v.v.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> [[SRC]], i64 [[VL]])64// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]65//66vint8m4_t test_vmv_v_v_i8m4(vint8m4_t src, size_t vl) {67 return __riscv_vmv_v(src, vl);68}69 70// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vmv_v_v_i8m871// CHECK-RV64-SAME: (<vscale x 64 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {72// CHECK-RV64-NEXT: entry:73// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmv.v.v.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> [[SRC]], i64 [[VL]])74// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]75//76vint8m8_t test_vmv_v_v_i8m8(vint8m8_t src, size_t vl) {77 return __riscv_vmv_v(src, vl);78}79 80// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vmv_v_v_i16mf481// CHECK-RV64-SAME: (<vscale x 1 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {82// CHECK-RV64-NEXT: entry:83// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmv.v.v.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[SRC]], i64 [[VL]])84// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]85//86vint16mf4_t test_vmv_v_v_i16mf4(vint16mf4_t src, size_t vl) {87 return __riscv_vmv_v(src, vl);88}89 90// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vmv_v_v_i16mf291// CHECK-RV64-SAME: (<vscale x 2 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {92// CHECK-RV64-NEXT: entry:93// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmv.v.v.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> [[SRC]], i64 [[VL]])94// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]95//96vint16mf2_t test_vmv_v_v_i16mf2(vint16mf2_t src, size_t vl) {97 return __riscv_vmv_v(src, vl);98}99 100// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vmv_v_v_i16m1101// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {102// CHECK-RV64-NEXT: entry:103// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmv.v.v.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> [[SRC]], i64 [[VL]])104// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]105//106vint16m1_t test_vmv_v_v_i16m1(vint16m1_t src, size_t vl) {107 return __riscv_vmv_v(src, vl);108}109 110// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vmv_v_v_i16m2111// CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {112// CHECK-RV64-NEXT: entry:113// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmv.v.v.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> [[SRC]], i64 [[VL]])114// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]115//116vint16m2_t test_vmv_v_v_i16m2(vint16m2_t src, size_t vl) {117 return __riscv_vmv_v(src, vl);118}119 120// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vmv_v_v_i16m4121// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {122// CHECK-RV64-NEXT: entry:123// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmv.v.v.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> [[SRC]], i64 [[VL]])124// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]125//126vint16m4_t test_vmv_v_v_i16m4(vint16m4_t src, size_t vl) {127 return __riscv_vmv_v(src, vl);128}129 130// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vmv_v_v_i16m8131// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {132// CHECK-RV64-NEXT: entry:133// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmv.v.v.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> [[SRC]], i64 [[VL]])134// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]135//136vint16m8_t test_vmv_v_v_i16m8(vint16m8_t src, size_t vl) {137 return __riscv_vmv_v(src, vl);138}139 140// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vmv_v_v_i32mf2141// CHECK-RV64-SAME: (<vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {142// CHECK-RV64-NEXT: entry:143// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmv.v.v.nxv1i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[SRC]], i64 [[VL]])144// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]145//146vint32mf2_t test_vmv_v_v_i32mf2(vint32mf2_t src, size_t vl) {147 return __riscv_vmv_v(src, vl);148}149 150// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vmv_v_v_i32m1151// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {152// CHECK-RV64-NEXT: entry:153// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmv.v.v.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[SRC]], i64 [[VL]])154// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]155//156vint32m1_t test_vmv_v_v_i32m1(vint32m1_t src, size_t vl) {157 return __riscv_vmv_v(src, vl);158}159 160// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vmv_v_v_i32m2161// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {162// CHECK-RV64-NEXT: entry:163// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmv.v.v.nxv4i32.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> [[SRC]], i64 [[VL]])164// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]165//166vint32m2_t test_vmv_v_v_i32m2(vint32m2_t src, size_t vl) {167 return __riscv_vmv_v(src, vl);168}169 170// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vmv_v_v_i32m4171// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {172// CHECK-RV64-NEXT: entry:173// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmv.v.v.nxv8i32.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> [[SRC]], i64 [[VL]])174// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]175//176vint32m4_t test_vmv_v_v_i32m4(vint32m4_t src, size_t vl) {177 return __riscv_vmv_v(src, vl);178}179 180// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vmv_v_v_i32m8181// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {182// CHECK-RV64-NEXT: entry:183// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmv.v.v.nxv16i32.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> [[SRC]], i64 [[VL]])184// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]185//186vint32m8_t test_vmv_v_v_i32m8(vint32m8_t src, size_t vl) {187 return __riscv_vmv_v(src, vl);188}189 190// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vmv_v_v_i64m1191// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {192// CHECK-RV64-NEXT: entry:193// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmv.v.v.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> [[SRC]], i64 [[VL]])194// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]195//196vint64m1_t test_vmv_v_v_i64m1(vint64m1_t src, size_t vl) {197 return __riscv_vmv_v(src, vl);198}199 200// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vmv_v_v_i64m2201// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {202// CHECK-RV64-NEXT: entry:203// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmv.v.v.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> [[SRC]], i64 [[VL]])204// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]205//206vint64m2_t test_vmv_v_v_i64m2(vint64m2_t src, size_t vl) {207 return __riscv_vmv_v(src, vl);208}209 210// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vmv_v_v_i64m4211// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {212// CHECK-RV64-NEXT: entry:213// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmv.v.v.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> [[SRC]], i64 [[VL]])214// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]215//216vint64m4_t test_vmv_v_v_i64m4(vint64m4_t src, size_t vl) {217 return __riscv_vmv_v(src, vl);218}219 220// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vmv_v_v_i64m8221// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {222// CHECK-RV64-NEXT: entry:223// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmv.v.v.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> [[SRC]], i64 [[VL]])224// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]225//226vint64m8_t test_vmv_v_v_i64m8(vint64m8_t src, size_t vl) {227 return __riscv_vmv_v(src, vl);228}229 230// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vmv_v_v_u8mf8231// CHECK-RV64-SAME: (<vscale x 1 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {232// CHECK-RV64-NEXT: entry:233// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> [[SRC]], i64 [[VL]])234// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]235//236vuint8mf8_t test_vmv_v_v_u8mf8(vuint8mf8_t src, size_t vl) {237 return __riscv_vmv_v(src, vl);238}239 240// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vmv_v_v_u8mf4241// CHECK-RV64-SAME: (<vscale x 2 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {242// CHECK-RV64-NEXT: entry:243// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> [[SRC]], i64 [[VL]])244// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]245//246vuint8mf4_t test_vmv_v_v_u8mf4(vuint8mf4_t src, size_t vl) {247 return __riscv_vmv_v(src, vl);248}249 250// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vmv_v_v_u8mf2251// CHECK-RV64-SAME: (<vscale x 4 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {252// CHECK-RV64-NEXT: entry:253// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> [[SRC]], i64 [[VL]])254// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]255//256vuint8mf2_t test_vmv_v_v_u8mf2(vuint8mf2_t src, size_t vl) {257 return __riscv_vmv_v(src, vl);258}259 260// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vmv_v_v_u8m1261// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {262// CHECK-RV64-NEXT: entry:263// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> [[SRC]], i64 [[VL]])264// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]265//266vuint8m1_t test_vmv_v_v_u8m1(vuint8m1_t src, size_t vl) {267 return __riscv_vmv_v(src, vl);268}269 270// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vmv_v_v_u8m2271// CHECK-RV64-SAME: (<vscale x 16 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {272// CHECK-RV64-NEXT: entry:273// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> [[SRC]], i64 [[VL]])274// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]275//276vuint8m2_t test_vmv_v_v_u8m2(vuint8m2_t src, size_t vl) {277 return __riscv_vmv_v(src, vl);278}279 280// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vmv_v_v_u8m4281// CHECK-RV64-SAME: (<vscale x 32 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {282// CHECK-RV64-NEXT: entry:283// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmv.v.v.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> [[SRC]], i64 [[VL]])284// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]285//286vuint8m4_t test_vmv_v_v_u8m4(vuint8m4_t src, size_t vl) {287 return __riscv_vmv_v(src, vl);288}289 290// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vmv_v_v_u8m8291// CHECK-RV64-SAME: (<vscale x 64 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {292// CHECK-RV64-NEXT: entry:293// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmv.v.v.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> [[SRC]], i64 [[VL]])294// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]295//296vuint8m8_t test_vmv_v_v_u8m8(vuint8m8_t src, size_t vl) {297 return __riscv_vmv_v(src, vl);298}299 300// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vmv_v_v_u16mf4301// CHECK-RV64-SAME: (<vscale x 1 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {302// CHECK-RV64-NEXT: entry:303// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmv.v.v.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[SRC]], i64 [[VL]])304// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]305//306vuint16mf4_t test_vmv_v_v_u16mf4(vuint16mf4_t src, size_t vl) {307 return __riscv_vmv_v(src, vl);308}309 310// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vmv_v_v_u16mf2311// CHECK-RV64-SAME: (<vscale x 2 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {312// CHECK-RV64-NEXT: entry:313// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmv.v.v.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> [[SRC]], i64 [[VL]])314// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]315//316vuint16mf2_t test_vmv_v_v_u16mf2(vuint16mf2_t src, size_t vl) {317 return __riscv_vmv_v(src, vl);318}319 320// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vmv_v_v_u16m1321// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {322// CHECK-RV64-NEXT: entry:323// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmv.v.v.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> [[SRC]], i64 [[VL]])324// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]325//326vuint16m1_t test_vmv_v_v_u16m1(vuint16m1_t src, size_t vl) {327 return __riscv_vmv_v(src, vl);328}329 330// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vmv_v_v_u16m2331// CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {332// CHECK-RV64-NEXT: entry:333// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmv.v.v.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> [[SRC]], i64 [[VL]])334// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]335//336vuint16m2_t test_vmv_v_v_u16m2(vuint16m2_t src, size_t vl) {337 return __riscv_vmv_v(src, vl);338}339 340// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vmv_v_v_u16m4341// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {342// CHECK-RV64-NEXT: entry:343// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmv.v.v.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> [[SRC]], i64 [[VL]])344// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]345//346vuint16m4_t test_vmv_v_v_u16m4(vuint16m4_t src, size_t vl) {347 return __riscv_vmv_v(src, vl);348}349 350// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vmv_v_v_u16m8351// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {352// CHECK-RV64-NEXT: entry:353// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmv.v.v.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> [[SRC]], i64 [[VL]])354// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]355//356vuint16m8_t test_vmv_v_v_u16m8(vuint16m8_t src, size_t vl) {357 return __riscv_vmv_v(src, vl);358}359 360// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vmv_v_v_u32mf2361// CHECK-RV64-SAME: (<vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {362// CHECK-RV64-NEXT: entry:363// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmv.v.v.nxv1i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[SRC]], i64 [[VL]])364// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]365//366vuint32mf2_t test_vmv_v_v_u32mf2(vuint32mf2_t src, size_t vl) {367 return __riscv_vmv_v(src, vl);368}369 370// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vmv_v_v_u32m1371// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {372// CHECK-RV64-NEXT: entry:373// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmv.v.v.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[SRC]], i64 [[VL]])374// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]375//376vuint32m1_t test_vmv_v_v_u32m1(vuint32m1_t src, size_t vl) {377 return __riscv_vmv_v(src, vl);378}379 380// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vmv_v_v_u32m2381// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {382// CHECK-RV64-NEXT: entry:383// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmv.v.v.nxv4i32.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> [[SRC]], i64 [[VL]])384// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]385//386vuint32m2_t test_vmv_v_v_u32m2(vuint32m2_t src, size_t vl) {387 return __riscv_vmv_v(src, vl);388}389 390// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vmv_v_v_u32m4391// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {392// CHECK-RV64-NEXT: entry:393// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmv.v.v.nxv8i32.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> [[SRC]], i64 [[VL]])394// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]395//396vuint32m4_t test_vmv_v_v_u32m4(vuint32m4_t src, size_t vl) {397 return __riscv_vmv_v(src, vl);398}399 400// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vmv_v_v_u32m8401// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {402// CHECK-RV64-NEXT: entry:403// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmv.v.v.nxv16i32.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> [[SRC]], i64 [[VL]])404// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]405//406vuint32m8_t test_vmv_v_v_u32m8(vuint32m8_t src, size_t vl) {407 return __riscv_vmv_v(src, vl);408}409 410// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vmv_v_v_u64m1411// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {412// CHECK-RV64-NEXT: entry:413// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmv.v.v.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> [[SRC]], i64 [[VL]])414// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]415//416vuint64m1_t test_vmv_v_v_u64m1(vuint64m1_t src, size_t vl) {417 return __riscv_vmv_v(src, vl);418}419 420// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vmv_v_v_u64m2421// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {422// CHECK-RV64-NEXT: entry:423// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmv.v.v.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> [[SRC]], i64 [[VL]])424// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]425//426vuint64m2_t test_vmv_v_v_u64m2(vuint64m2_t src, size_t vl) {427 return __riscv_vmv_v(src, vl);428}429 430// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vmv_v_v_u64m4431// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {432// CHECK-RV64-NEXT: entry:433// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmv.v.v.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> [[SRC]], i64 [[VL]])434// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]435//436vuint64m4_t test_vmv_v_v_u64m4(vuint64m4_t src, size_t vl) {437 return __riscv_vmv_v(src, vl);438}439 440// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vmv_v_v_u64m8441// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {442// CHECK-RV64-NEXT: entry:443// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmv.v.v.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> [[SRC]], i64 [[VL]])444// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]445//446vuint64m8_t test_vmv_v_v_u64m8(vuint64m8_t src, size_t vl) {447 return __riscv_vmv_v(src, vl);448}449 450// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vmv_v_v_f16mf4451// CHECK-RV64-SAME: (<vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {452// CHECK-RV64-NEXT: entry:453// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vmv.v.v.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> [[SRC]], i64 [[VL]])454// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]455//456vfloat16mf4_t test_vmv_v_v_f16mf4(vfloat16mf4_t src, size_t vl) {457 return __riscv_vmv_v(src, vl);458}459 460// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vmv_v_v_f16mf2461// CHECK-RV64-SAME: (<vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {462// CHECK-RV64-NEXT: entry:463// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vmv.v.v.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> [[SRC]], i64 [[VL]])464// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]465//466vfloat16mf2_t test_vmv_v_v_f16mf2(vfloat16mf2_t src, size_t vl) {467 return __riscv_vmv_v(src, vl);468}469 470// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vmv_v_v_f16m1471// CHECK-RV64-SAME: (<vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {472// CHECK-RV64-NEXT: entry:473// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vmv.v.v.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> [[SRC]], i64 [[VL]])474// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]475//476vfloat16m1_t test_vmv_v_v_f16m1(vfloat16m1_t src, size_t vl) {477 return __riscv_vmv_v(src, vl);478}479 480// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vmv_v_v_f16m2481// CHECK-RV64-SAME: (<vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {482// CHECK-RV64-NEXT: entry:483// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vmv.v.v.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> [[SRC]], i64 [[VL]])484// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]485//486vfloat16m2_t test_vmv_v_v_f16m2(vfloat16m2_t src, size_t vl) {487 return __riscv_vmv_v(src, vl);488}489 490// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vmv_v_v_f16m4491// CHECK-RV64-SAME: (<vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {492// CHECK-RV64-NEXT: entry:493// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vmv.v.v.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> [[SRC]], i64 [[VL]])494// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]495//496vfloat16m4_t test_vmv_v_v_f16m4(vfloat16m4_t src, size_t vl) {497 return __riscv_vmv_v(src, vl);498}499 500// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vmv_v_v_f16m8501// CHECK-RV64-SAME: (<vscale x 32 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {502// CHECK-RV64-NEXT: entry:503// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vmv.v.v.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> [[SRC]], i64 [[VL]])504// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]505//506vfloat16m8_t test_vmv_v_v_f16m8(vfloat16m8_t src, size_t vl) {507 return __riscv_vmv_v(src, vl);508}509 510// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vmv_v_v_f32mf2511// CHECK-RV64-SAME: (<vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {512// CHECK-RV64-NEXT: entry:513// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vmv.v.v.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> [[SRC]], i64 [[VL]])514// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]515//516vfloat32mf2_t test_vmv_v_v_f32mf2(vfloat32mf2_t src, size_t vl) {517 return __riscv_vmv_v(src, vl);518}519 520// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vmv_v_v_f32m1521// CHECK-RV64-SAME: (<vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {522// CHECK-RV64-NEXT: entry:523// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vmv.v.v.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> [[SRC]], i64 [[VL]])524// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]525//526vfloat32m1_t test_vmv_v_v_f32m1(vfloat32m1_t src, size_t vl) {527 return __riscv_vmv_v(src, vl);528}529 530// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vmv_v_v_f32m2531// CHECK-RV64-SAME: (<vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {532// CHECK-RV64-NEXT: entry:533// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vmv.v.v.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> [[SRC]], i64 [[VL]])534// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]535//536vfloat32m2_t test_vmv_v_v_f32m2(vfloat32m2_t src, size_t vl) {537 return __riscv_vmv_v(src, vl);538}539 540// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vmv_v_v_f32m4541// CHECK-RV64-SAME: (<vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {542// CHECK-RV64-NEXT: entry:543// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vmv.v.v.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> [[SRC]], i64 [[VL]])544// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]545//546vfloat32m4_t test_vmv_v_v_f32m4(vfloat32m4_t src, size_t vl) {547 return __riscv_vmv_v(src, vl);548}549 550// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vmv_v_v_f32m8551// CHECK-RV64-SAME: (<vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {552// CHECK-RV64-NEXT: entry:553// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vmv.v.v.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> [[SRC]], i64 [[VL]])554// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]555//556vfloat32m8_t test_vmv_v_v_f32m8(vfloat32m8_t src, size_t vl) {557 return __riscv_vmv_v(src, vl);558}559 560// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vmv_v_v_f64m1561// CHECK-RV64-SAME: (<vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {562// CHECK-RV64-NEXT: entry:563// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vmv.v.v.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> [[SRC]], i64 [[VL]])564// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]565//566vfloat64m1_t test_vmv_v_v_f64m1(vfloat64m1_t src, size_t vl) {567 return __riscv_vmv_v(src, vl);568}569 570// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vmv_v_v_f64m2571// CHECK-RV64-SAME: (<vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {572// CHECK-RV64-NEXT: entry:573// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vmv.v.v.nxv2f64.i64(<vscale x 2 x double> poison, <vscale x 2 x double> [[SRC]], i64 [[VL]])574// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]575//576vfloat64m2_t test_vmv_v_v_f64m2(vfloat64m2_t src, size_t vl) {577 return __riscv_vmv_v(src, vl);578}579 580// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vmv_v_v_f64m4581// CHECK-RV64-SAME: (<vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {582// CHECK-RV64-NEXT: entry:583// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vmv.v.v.nxv4f64.i64(<vscale x 4 x double> poison, <vscale x 4 x double> [[SRC]], i64 [[VL]])584// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]585//586vfloat64m4_t test_vmv_v_v_f64m4(vfloat64m4_t src, size_t vl) {587 return __riscv_vmv_v(src, vl);588}589 590// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vmv_v_v_f64m8591// CHECK-RV64-SAME: (<vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {592// CHECK-RV64-NEXT: entry:593// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vmv.v.v.nxv8f64.i64(<vscale x 8 x double> poison, <vscale x 8 x double> [[SRC]], i64 [[VL]])594// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]595//596vfloat64m8_t test_vmv_v_v_f64m8(vfloat64m8_t src, size_t vl) {597 return __riscv_vmv_v(src, vl);598}599 600// CHECK-RV64-LABEL: define dso_local signext i8 @test_vmv_x_s_i8mf8_i8601// CHECK-RV64-SAME: (<vscale x 1 x i8> [[SRC:%.*]]) #[[ATTR0]] {602// CHECK-RV64-NEXT: entry:603// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv1i8(<vscale x 1 x i8> [[SRC]])604// CHECK-RV64-NEXT: ret i8 [[TMP0]]605//606int8_t test_vmv_x_s_i8mf8_i8(vint8mf8_t src) {607 return __riscv_vmv_x(src);608}609 610// CHECK-RV64-LABEL: define dso_local signext i8 @test_vmv_x_s_i8mf4_i8611// CHECK-RV64-SAME: (<vscale x 2 x i8> [[SRC:%.*]]) #[[ATTR0]] {612// CHECK-RV64-NEXT: entry:613// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv2i8(<vscale x 2 x i8> [[SRC]])614// CHECK-RV64-NEXT: ret i8 [[TMP0]]615//616int8_t test_vmv_x_s_i8mf4_i8(vint8mf4_t src) {617 return __riscv_vmv_x(src);618}619 620// CHECK-RV64-LABEL: define dso_local signext i8 @test_vmv_x_s_i8mf2_i8621// CHECK-RV64-SAME: (<vscale x 4 x i8> [[SRC:%.*]]) #[[ATTR0]] {622// CHECK-RV64-NEXT: entry:623// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv4i8(<vscale x 4 x i8> [[SRC]])624// CHECK-RV64-NEXT: ret i8 [[TMP0]]625//626int8_t test_vmv_x_s_i8mf2_i8(vint8mf2_t src) {627 return __riscv_vmv_x(src);628}629 630// CHECK-RV64-LABEL: define dso_local signext i8 @test_vmv_x_s_i8m1_i8631// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {632// CHECK-RV64-NEXT: entry:633// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv8i8(<vscale x 8 x i8> [[SRC]])634// CHECK-RV64-NEXT: ret i8 [[TMP0]]635//636int8_t test_vmv_x_s_i8m1_i8(vint8m1_t src) {637 return __riscv_vmv_x(src);638}639 640// CHECK-RV64-LABEL: define dso_local signext i8 @test_vmv_x_s_i8m2_i8641// CHECK-RV64-SAME: (<vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {642// CHECK-RV64-NEXT: entry:643// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv16i8(<vscale x 16 x i8> [[SRC]])644// CHECK-RV64-NEXT: ret i8 [[TMP0]]645//646int8_t test_vmv_x_s_i8m2_i8(vint8m2_t src) {647 return __riscv_vmv_x(src);648}649 650// CHECK-RV64-LABEL: define dso_local signext i8 @test_vmv_x_s_i8m4_i8651// CHECK-RV64-SAME: (<vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {652// CHECK-RV64-NEXT: entry:653// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv32i8(<vscale x 32 x i8> [[SRC]])654// CHECK-RV64-NEXT: ret i8 [[TMP0]]655//656int8_t test_vmv_x_s_i8m4_i8(vint8m4_t src) {657 return __riscv_vmv_x(src);658}659 660// CHECK-RV64-LABEL: define dso_local signext i8 @test_vmv_x_s_i8m8_i8661// CHECK-RV64-SAME: (<vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {662// CHECK-RV64-NEXT: entry:663// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv64i8(<vscale x 64 x i8> [[SRC]])664// CHECK-RV64-NEXT: ret i8 [[TMP0]]665//666int8_t test_vmv_x_s_i8m8_i8(vint8m8_t src) {667 return __riscv_vmv_x(src);668}669 670// CHECK-RV64-LABEL: define dso_local signext i16 @test_vmv_x_s_i16mf4_i16671// CHECK-RV64-SAME: (<vscale x 1 x i16> [[SRC:%.*]]) #[[ATTR0]] {672// CHECK-RV64-NEXT: entry:673// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv1i16(<vscale x 1 x i16> [[SRC]])674// CHECK-RV64-NEXT: ret i16 [[TMP0]]675//676int16_t test_vmv_x_s_i16mf4_i16(vint16mf4_t src) {677 return __riscv_vmv_x(src);678}679 680// CHECK-RV64-LABEL: define dso_local signext i16 @test_vmv_x_s_i16mf2_i16681// CHECK-RV64-SAME: (<vscale x 2 x i16> [[SRC:%.*]]) #[[ATTR0]] {682// CHECK-RV64-NEXT: entry:683// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv2i16(<vscale x 2 x i16> [[SRC]])684// CHECK-RV64-NEXT: ret i16 [[TMP0]]685//686int16_t test_vmv_x_s_i16mf2_i16(vint16mf2_t src) {687 return __riscv_vmv_x(src);688}689 690// CHECK-RV64-LABEL: define dso_local signext i16 @test_vmv_x_s_i16m1_i16691// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {692// CHECK-RV64-NEXT: entry:693// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv4i16(<vscale x 4 x i16> [[SRC]])694// CHECK-RV64-NEXT: ret i16 [[TMP0]]695//696int16_t test_vmv_x_s_i16m1_i16(vint16m1_t src) {697 return __riscv_vmv_x(src);698}699 700// CHECK-RV64-LABEL: define dso_local signext i16 @test_vmv_x_s_i16m2_i16701// CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {702// CHECK-RV64-NEXT: entry:703// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv8i16(<vscale x 8 x i16> [[SRC]])704// CHECK-RV64-NEXT: ret i16 [[TMP0]]705//706int16_t test_vmv_x_s_i16m2_i16(vint16m2_t src) {707 return __riscv_vmv_x(src);708}709 710// CHECK-RV64-LABEL: define dso_local signext i16 @test_vmv_x_s_i16m4_i16711// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {712// CHECK-RV64-NEXT: entry:713// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv16i16(<vscale x 16 x i16> [[SRC]])714// CHECK-RV64-NEXT: ret i16 [[TMP0]]715//716int16_t test_vmv_x_s_i16m4_i16(vint16m4_t src) {717 return __riscv_vmv_x(src);718}719 720// CHECK-RV64-LABEL: define dso_local signext i16 @test_vmv_x_s_i16m8_i16721// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {722// CHECK-RV64-NEXT: entry:723// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv32i16(<vscale x 32 x i16> [[SRC]])724// CHECK-RV64-NEXT: ret i16 [[TMP0]]725//726int16_t test_vmv_x_s_i16m8_i16(vint16m8_t src) {727 return __riscv_vmv_x(src);728}729 730// CHECK-RV64-LABEL: define dso_local signext i32 @test_vmv_x_s_i32mf2_i32731// CHECK-RV64-SAME: (<vscale x 1 x i32> [[SRC:%.*]]) #[[ATTR0]] {732// CHECK-RV64-NEXT: entry:733// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv1i32(<vscale x 1 x i32> [[SRC]])734// CHECK-RV64-NEXT: ret i32 [[TMP0]]735//736int32_t test_vmv_x_s_i32mf2_i32(vint32mf2_t src) {737 return __riscv_vmv_x(src);738}739 740// CHECK-RV64-LABEL: define dso_local signext i32 @test_vmv_x_s_i32m1_i32741// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {742// CHECK-RV64-NEXT: entry:743// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv2i32(<vscale x 2 x i32> [[SRC]])744// CHECK-RV64-NEXT: ret i32 [[TMP0]]745//746int32_t test_vmv_x_s_i32m1_i32(vint32m1_t src) {747 return __riscv_vmv_x(src);748}749 750// CHECK-RV64-LABEL: define dso_local signext i32 @test_vmv_x_s_i32m2_i32751// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {752// CHECK-RV64-NEXT: entry:753// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv4i32(<vscale x 4 x i32> [[SRC]])754// CHECK-RV64-NEXT: ret i32 [[TMP0]]755//756int32_t test_vmv_x_s_i32m2_i32(vint32m2_t src) {757 return __riscv_vmv_x(src);758}759 760// CHECK-RV64-LABEL: define dso_local signext i32 @test_vmv_x_s_i32m4_i32761// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {762// CHECK-RV64-NEXT: entry:763// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv8i32(<vscale x 8 x i32> [[SRC]])764// CHECK-RV64-NEXT: ret i32 [[TMP0]]765//766int32_t test_vmv_x_s_i32m4_i32(vint32m4_t src) {767 return __riscv_vmv_x(src);768}769 770// CHECK-RV64-LABEL: define dso_local signext i32 @test_vmv_x_s_i32m8_i32771// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {772// CHECK-RV64-NEXT: entry:773// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv16i32(<vscale x 16 x i32> [[SRC]])774// CHECK-RV64-NEXT: ret i32 [[TMP0]]775//776int32_t test_vmv_x_s_i32m8_i32(vint32m8_t src) {777 return __riscv_vmv_x(src);778}779 780// CHECK-RV64-LABEL: define dso_local i64 @test_vmv_x_s_i64m1_i64781// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {782// CHECK-RV64-NEXT: entry:783// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vmv.x.s.nxv1i64(<vscale x 1 x i64> [[SRC]])784// CHECK-RV64-NEXT: ret i64 [[TMP0]]785//786int64_t test_vmv_x_s_i64m1_i64(vint64m1_t src) {787 return __riscv_vmv_x(src);788}789 790// CHECK-RV64-LABEL: define dso_local i64 @test_vmv_x_s_i64m2_i64791// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {792// CHECK-RV64-NEXT: entry:793// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vmv.x.s.nxv2i64(<vscale x 2 x i64> [[SRC]])794// CHECK-RV64-NEXT: ret i64 [[TMP0]]795//796int64_t test_vmv_x_s_i64m2_i64(vint64m2_t src) {797 return __riscv_vmv_x(src);798}799 800// CHECK-RV64-LABEL: define dso_local i64 @test_vmv_x_s_i64m4_i64801// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {802// CHECK-RV64-NEXT: entry:803// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vmv.x.s.nxv4i64(<vscale x 4 x i64> [[SRC]])804// CHECK-RV64-NEXT: ret i64 [[TMP0]]805//806int64_t test_vmv_x_s_i64m4_i64(vint64m4_t src) {807 return __riscv_vmv_x(src);808}809 810// CHECK-RV64-LABEL: define dso_local i64 @test_vmv_x_s_i64m8_i64811// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {812// CHECK-RV64-NEXT: entry:813// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vmv.x.s.nxv8i64(<vscale x 8 x i64> [[SRC]])814// CHECK-RV64-NEXT: ret i64 [[TMP0]]815//816int64_t test_vmv_x_s_i64m8_i64(vint64m8_t src) {817 return __riscv_vmv_x(src);818}819 820// CHECK-RV64-LABEL: define dso_local zeroext i8 @test_vmv_x_s_u8mf8_u8821// CHECK-RV64-SAME: (<vscale x 1 x i8> [[SRC:%.*]]) #[[ATTR0]] {822// CHECK-RV64-NEXT: entry:823// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv1i8(<vscale x 1 x i8> [[SRC]])824// CHECK-RV64-NEXT: ret i8 [[TMP0]]825//826uint8_t test_vmv_x_s_u8mf8_u8(vuint8mf8_t src) {827 return __riscv_vmv_x(src);828}829 830// CHECK-RV64-LABEL: define dso_local zeroext i8 @test_vmv_x_s_u8mf4_u8831// CHECK-RV64-SAME: (<vscale x 2 x i8> [[SRC:%.*]]) #[[ATTR0]] {832// CHECK-RV64-NEXT: entry:833// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv2i8(<vscale x 2 x i8> [[SRC]])834// CHECK-RV64-NEXT: ret i8 [[TMP0]]835//836uint8_t test_vmv_x_s_u8mf4_u8(vuint8mf4_t src) {837 return __riscv_vmv_x(src);838}839 840// CHECK-RV64-LABEL: define dso_local zeroext i8 @test_vmv_x_s_u8mf2_u8841// CHECK-RV64-SAME: (<vscale x 4 x i8> [[SRC:%.*]]) #[[ATTR0]] {842// CHECK-RV64-NEXT: entry:843// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv4i8(<vscale x 4 x i8> [[SRC]])844// CHECK-RV64-NEXT: ret i8 [[TMP0]]845//846uint8_t test_vmv_x_s_u8mf2_u8(vuint8mf2_t src) {847 return __riscv_vmv_x(src);848}849 850// CHECK-RV64-LABEL: define dso_local zeroext i8 @test_vmv_x_s_u8m1_u8851// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {852// CHECK-RV64-NEXT: entry:853// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv8i8(<vscale x 8 x i8> [[SRC]])854// CHECK-RV64-NEXT: ret i8 [[TMP0]]855//856uint8_t test_vmv_x_s_u8m1_u8(vuint8m1_t src) {857 return __riscv_vmv_x(src);858}859 860// CHECK-RV64-LABEL: define dso_local zeroext i8 @test_vmv_x_s_u8m2_u8861// CHECK-RV64-SAME: (<vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {862// CHECK-RV64-NEXT: entry:863// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv16i8(<vscale x 16 x i8> [[SRC]])864// CHECK-RV64-NEXT: ret i8 [[TMP0]]865//866uint8_t test_vmv_x_s_u8m2_u8(vuint8m2_t src) {867 return __riscv_vmv_x(src);868}869 870// CHECK-RV64-LABEL: define dso_local zeroext i8 @test_vmv_x_s_u8m4_u8871// CHECK-RV64-SAME: (<vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {872// CHECK-RV64-NEXT: entry:873// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv32i8(<vscale x 32 x i8> [[SRC]])874// CHECK-RV64-NEXT: ret i8 [[TMP0]]875//876uint8_t test_vmv_x_s_u8m4_u8(vuint8m4_t src) {877 return __riscv_vmv_x(src);878}879 880// CHECK-RV64-LABEL: define dso_local zeroext i8 @test_vmv_x_s_u8m8_u8881// CHECK-RV64-SAME: (<vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {882// CHECK-RV64-NEXT: entry:883// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i8 @llvm.riscv.vmv.x.s.nxv64i8(<vscale x 64 x i8> [[SRC]])884// CHECK-RV64-NEXT: ret i8 [[TMP0]]885//886uint8_t test_vmv_x_s_u8m8_u8(vuint8m8_t src) {887 return __riscv_vmv_x(src);888}889 890// CHECK-RV64-LABEL: define dso_local zeroext i16 @test_vmv_x_s_u16mf4_u16891// CHECK-RV64-SAME: (<vscale x 1 x i16> [[SRC:%.*]]) #[[ATTR0]] {892// CHECK-RV64-NEXT: entry:893// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv1i16(<vscale x 1 x i16> [[SRC]])894// CHECK-RV64-NEXT: ret i16 [[TMP0]]895//896uint16_t test_vmv_x_s_u16mf4_u16(vuint16mf4_t src) {897 return __riscv_vmv_x(src);898}899 900// CHECK-RV64-LABEL: define dso_local zeroext i16 @test_vmv_x_s_u16mf2_u16901// CHECK-RV64-SAME: (<vscale x 2 x i16> [[SRC:%.*]]) #[[ATTR0]] {902// CHECK-RV64-NEXT: entry:903// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv2i16(<vscale x 2 x i16> [[SRC]])904// CHECK-RV64-NEXT: ret i16 [[TMP0]]905//906uint16_t test_vmv_x_s_u16mf2_u16(vuint16mf2_t src) {907 return __riscv_vmv_x(src);908}909 910// CHECK-RV64-LABEL: define dso_local zeroext i16 @test_vmv_x_s_u16m1_u16911// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {912// CHECK-RV64-NEXT: entry:913// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv4i16(<vscale x 4 x i16> [[SRC]])914// CHECK-RV64-NEXT: ret i16 [[TMP0]]915//916uint16_t test_vmv_x_s_u16m1_u16(vuint16m1_t src) {917 return __riscv_vmv_x(src);918}919 920// CHECK-RV64-LABEL: define dso_local zeroext i16 @test_vmv_x_s_u16m2_u16921// CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {922// CHECK-RV64-NEXT: entry:923// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv8i16(<vscale x 8 x i16> [[SRC]])924// CHECK-RV64-NEXT: ret i16 [[TMP0]]925//926uint16_t test_vmv_x_s_u16m2_u16(vuint16m2_t src) {927 return __riscv_vmv_x(src);928}929 930// CHECK-RV64-LABEL: define dso_local zeroext i16 @test_vmv_x_s_u16m4_u16931// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {932// CHECK-RV64-NEXT: entry:933// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv16i16(<vscale x 16 x i16> [[SRC]])934// CHECK-RV64-NEXT: ret i16 [[TMP0]]935//936uint16_t test_vmv_x_s_u16m4_u16(vuint16m4_t src) {937 return __riscv_vmv_x(src);938}939 940// CHECK-RV64-LABEL: define dso_local zeroext i16 @test_vmv_x_s_u16m8_u16941// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {942// CHECK-RV64-NEXT: entry:943// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i16 @llvm.riscv.vmv.x.s.nxv32i16(<vscale x 32 x i16> [[SRC]])944// CHECK-RV64-NEXT: ret i16 [[TMP0]]945//946uint16_t test_vmv_x_s_u16m8_u16(vuint16m8_t src) {947 return __riscv_vmv_x(src);948}949 950// CHECK-RV64-LABEL: define dso_local signext i32 @test_vmv_x_s_u32mf2_u32951// CHECK-RV64-SAME: (<vscale x 1 x i32> [[SRC:%.*]]) #[[ATTR0]] {952// CHECK-RV64-NEXT: entry:953// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv1i32(<vscale x 1 x i32> [[SRC]])954// CHECK-RV64-NEXT: ret i32 [[TMP0]]955//956uint32_t test_vmv_x_s_u32mf2_u32(vuint32mf2_t src) {957 return __riscv_vmv_x(src);958}959 960// CHECK-RV64-LABEL: define dso_local signext i32 @test_vmv_x_s_u32m1_u32961// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {962// CHECK-RV64-NEXT: entry:963// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv2i32(<vscale x 2 x i32> [[SRC]])964// CHECK-RV64-NEXT: ret i32 [[TMP0]]965//966uint32_t test_vmv_x_s_u32m1_u32(vuint32m1_t src) {967 return __riscv_vmv_x(src);968}969 970// CHECK-RV64-LABEL: define dso_local signext i32 @test_vmv_x_s_u32m2_u32971// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {972// CHECK-RV64-NEXT: entry:973// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv4i32(<vscale x 4 x i32> [[SRC]])974// CHECK-RV64-NEXT: ret i32 [[TMP0]]975//976uint32_t test_vmv_x_s_u32m2_u32(vuint32m2_t src) {977 return __riscv_vmv_x(src);978}979 980// CHECK-RV64-LABEL: define dso_local signext i32 @test_vmv_x_s_u32m4_u32981// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {982// CHECK-RV64-NEXT: entry:983// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv8i32(<vscale x 8 x i32> [[SRC]])984// CHECK-RV64-NEXT: ret i32 [[TMP0]]985//986uint32_t test_vmv_x_s_u32m4_u32(vuint32m4_t src) {987 return __riscv_vmv_x(src);988}989 990// CHECK-RV64-LABEL: define dso_local signext i32 @test_vmv_x_s_u32m8_u32991// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {992// CHECK-RV64-NEXT: entry:993// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.vmv.x.s.nxv16i32(<vscale x 16 x i32> [[SRC]])994// CHECK-RV64-NEXT: ret i32 [[TMP0]]995//996uint32_t test_vmv_x_s_u32m8_u32(vuint32m8_t src) {997 return __riscv_vmv_x(src);998}999 1000// CHECK-RV64-LABEL: define dso_local i64 @test_vmv_x_s_u64m1_u641001// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {1002// CHECK-RV64-NEXT: entry:1003// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vmv.x.s.nxv1i64(<vscale x 1 x i64> [[SRC]])1004// CHECK-RV64-NEXT: ret i64 [[TMP0]]1005//1006uint64_t test_vmv_x_s_u64m1_u64(vuint64m1_t src) {1007 return __riscv_vmv_x(src);1008}1009 1010// CHECK-RV64-LABEL: define dso_local i64 @test_vmv_x_s_u64m2_u641011// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {1012// CHECK-RV64-NEXT: entry:1013// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vmv.x.s.nxv2i64(<vscale x 2 x i64> [[SRC]])1014// CHECK-RV64-NEXT: ret i64 [[TMP0]]1015//1016uint64_t test_vmv_x_s_u64m2_u64(vuint64m2_t src) {1017 return __riscv_vmv_x(src);1018}1019 1020// CHECK-RV64-LABEL: define dso_local i64 @test_vmv_x_s_u64m4_u641021// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {1022// CHECK-RV64-NEXT: entry:1023// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vmv.x.s.nxv4i64(<vscale x 4 x i64> [[SRC]])1024// CHECK-RV64-NEXT: ret i64 [[TMP0]]1025//1026uint64_t test_vmv_x_s_u64m4_u64(vuint64m4_t src) {1027 return __riscv_vmv_x(src);1028}1029 1030// CHECK-RV64-LABEL: define dso_local i64 @test_vmv_x_s_u64m8_u641031// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {1032// CHECK-RV64-NEXT: entry:1033// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vmv.x.s.nxv8i64(<vscale x 8 x i64> [[SRC]])1034// CHECK-RV64-NEXT: ret i64 [[TMP0]]1035//1036uint64_t test_vmv_x_s_u64m8_u64(vuint64m8_t src) {1037 return __riscv_vmv_x(src);1038}1039 1040// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vmv_v_v_bf16mf41041// CHECK-RV64-SAME: (<vscale x 1 x bfloat> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1042// CHECK-RV64-NEXT: entry:1043// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vmv.v.v.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> [[SRC]], i64 [[VL]])1044// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]1045//1046vbfloat16mf4_t test_vmv_v_v_bf16mf4(vbfloat16mf4_t src, size_t vl) {1047 return __riscv_vmv_v(src, vl);1048}1049 1050// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vmv_v_v_bf16mf21051// CHECK-RV64-SAME: (<vscale x 2 x bfloat> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1052// CHECK-RV64-NEXT: entry:1053// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vmv.v.v.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> [[SRC]], i64 [[VL]])1054// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]1055//1056vbfloat16mf2_t test_vmv_v_v_bf16mf2(vbfloat16mf2_t src, size_t vl) {1057 return __riscv_vmv_v(src, vl);1058}1059 1060// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vmv_v_v_bf16m11061// CHECK-RV64-SAME: (<vscale x 4 x bfloat> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1062// CHECK-RV64-NEXT: entry:1063// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vmv.v.v.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> [[SRC]], i64 [[VL]])1064// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]1065//1066vbfloat16m1_t test_vmv_v_v_bf16m1(vbfloat16m1_t src, size_t vl) {1067 return __riscv_vmv_v(src, vl);1068}1069 1070// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vmv_v_v_bf16m21071// CHECK-RV64-SAME: (<vscale x 8 x bfloat> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1072// CHECK-RV64-NEXT: entry:1073// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vmv.v.v.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> [[SRC]], i64 [[VL]])1074// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]1075//1076vbfloat16m2_t test_vmv_v_v_bf16m2(vbfloat16m2_t src, size_t vl) {1077 return __riscv_vmv_v(src, vl);1078}1079 1080// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vmv_v_v_bf16m41081// CHECK-RV64-SAME: (<vscale x 16 x bfloat> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1082// CHECK-RV64-NEXT: entry:1083// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vmv.v.v.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> [[SRC]], i64 [[VL]])1084// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]1085//1086vbfloat16m4_t test_vmv_v_v_bf16m4(vbfloat16m4_t src, size_t vl) {1087 return __riscv_vmv_v(src, vl);1088}1089 1090// CHECK-RV64-LABEL: define dso_local <vscale x 32 x bfloat> @test_vmv_v_v_bf16m81091// CHECK-RV64-SAME: (<vscale x 32 x bfloat> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1092// CHECK-RV64-NEXT: entry:1093// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x bfloat> @llvm.riscv.vmv.v.v.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> [[SRC]], i64 [[VL]])1094// CHECK-RV64-NEXT: ret <vscale x 32 x bfloat> [[TMP0]]1095//1096vbfloat16m8_t test_vmv_v_v_bf16m8(vbfloat16m8_t src, size_t vl) {1097 return __riscv_vmv_v(src, vl);1098}1099 1100