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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 22// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone \4// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \5// RUN: FileCheck --check-prefix=CHECK-RV64 %s6 7#include <riscv_vector.h>8 9// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf8_u8m110// CHECK-RV64-SAME: (<vscale x 1 x i8> [[VECTOR:%.*]], <vscale x 8 x i8> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {11// CHECK-RV64-NEXT: entry:12// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> [[VECTOR]], <vscale x 8 x i8> [[SCALAR]], i64 [[VL]])13// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]14//15vuint8m1_t test_vredminu_vs_u8mf8_u8m1(vuint8mf8_t vector, vuint8m1_t scalar, size_t vl) {16 return __riscv_vredminu(vector, scalar, vl);17}18 19// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf4_u8m120// CHECK-RV64-SAME: (<vscale x 2 x i8> [[VECTOR:%.*]], <vscale x 8 x i8> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {21// CHECK-RV64-NEXT: entry:22// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> [[VECTOR]], <vscale x 8 x i8> [[SCALAR]], i64 [[VL]])23// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]24//25vuint8m1_t test_vredminu_vs_u8mf4_u8m1(vuint8mf4_t vector, vuint8m1_t scalar, size_t vl) {26 return __riscv_vredminu(vector, scalar, vl);27}28 29// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf2_u8m130// CHECK-RV64-SAME: (<vscale x 4 x i8> [[VECTOR:%.*]], <vscale x 8 x i8> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {31// CHECK-RV64-NEXT: entry:32// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> [[VECTOR]], <vscale x 8 x i8> [[SCALAR]], i64 [[VL]])33// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]34//35vuint8m1_t test_vredminu_vs_u8mf2_u8m1(vuint8mf2_t vector, vuint8m1_t scalar, size_t vl) {36 return __riscv_vredminu(vector, scalar, vl);37}38 39// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m1_u8m140// CHECK-RV64-SAME: (<vscale x 8 x i8> [[VECTOR:%.*]], <vscale x 8 x i8> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {41// CHECK-RV64-NEXT: entry:42// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> [[VECTOR]], <vscale x 8 x i8> [[SCALAR]], i64 [[VL]])43// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]44//45vuint8m1_t test_vredminu_vs_u8m1_u8m1(vuint8m1_t vector, vuint8m1_t scalar, size_t vl) {46 return __riscv_vredminu(vector, scalar, vl);47}48 49// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m2_u8m150// CHECK-RV64-SAME: (<vscale x 16 x i8> [[VECTOR:%.*]], <vscale x 8 x i8> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {51// CHECK-RV64-NEXT: entry:52// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> [[VECTOR]], <vscale x 8 x i8> [[SCALAR]], i64 [[VL]])53// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]54//55vuint8m1_t test_vredminu_vs_u8m2_u8m1(vuint8m2_t vector, vuint8m1_t scalar, size_t vl) {56 return __riscv_vredminu(vector, scalar, vl);57}58 59// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m4_u8m160// CHECK-RV64-SAME: (<vscale x 32 x i8> [[VECTOR:%.*]], <vscale x 8 x i8> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {61// CHECK-RV64-NEXT: entry:62// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> [[VECTOR]], <vscale x 8 x i8> [[SCALAR]], i64 [[VL]])63// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]64//65vuint8m1_t test_vredminu_vs_u8m4_u8m1(vuint8m4_t vector, vuint8m1_t scalar, size_t vl) {66 return __riscv_vredminu(vector, scalar, vl);67}68 69// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m8_u8m170// CHECK-RV64-SAME: (<vscale x 64 x i8> [[VECTOR:%.*]], <vscale x 8 x i8> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {71// CHECK-RV64-NEXT: entry:72// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> [[VECTOR]], <vscale x 8 x i8> [[SCALAR]], i64 [[VL]])73// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]74//75vuint8m1_t test_vredminu_vs_u8m8_u8m1(vuint8m8_t vector, vuint8m1_t scalar, size_t vl) {76 return __riscv_vredminu(vector, scalar, vl);77}78 79// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vredminu_vs_u16mf4_u16m180// CHECK-RV64-SAME: (<vscale x 1 x i16> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {81// CHECK-RV64-NEXT: entry:82// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> [[VECTOR]], <vscale x 4 x i16> [[SCALAR]], i64 [[VL]])83// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]84//85vuint16m1_t test_vredminu_vs_u16mf4_u16m1(vuint16mf4_t vector, vuint16m1_t scalar, size_t vl) {86 return __riscv_vredminu(vector, scalar, vl);87}88 89// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vredminu_vs_u16mf2_u16m190// CHECK-RV64-SAME: (<vscale x 2 x i16> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {91// CHECK-RV64-NEXT: entry:92// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> [[VECTOR]], <vscale x 4 x i16> [[SCALAR]], i64 [[VL]])93// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]94//95vuint16m1_t test_vredminu_vs_u16mf2_u16m1(vuint16mf2_t vector, vuint16m1_t scalar, size_t vl) {96 return __riscv_vredminu(vector, scalar, vl);97}98 99// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vredminu_vs_u16m1_u16m1100// CHECK-RV64-SAME: (<vscale x 4 x i16> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {101// CHECK-RV64-NEXT: entry:102// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> [[VECTOR]], <vscale x 4 x i16> [[SCALAR]], i64 [[VL]])103// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]104//105vuint16m1_t test_vredminu_vs_u16m1_u16m1(vuint16m1_t vector, vuint16m1_t scalar, size_t vl) {106 return __riscv_vredminu(vector, scalar, vl);107}108 109// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vredminu_vs_u16m2_u16m1110// CHECK-RV64-SAME: (<vscale x 8 x i16> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {111// CHECK-RV64-NEXT: entry:112// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv8i16.i64(<vscale x 4 x i16> poison, <vscale x 8 x i16> [[VECTOR]], <vscale x 4 x i16> [[SCALAR]], i64 [[VL]])113// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]114//115vuint16m1_t test_vredminu_vs_u16m2_u16m1(vuint16m2_t vector, vuint16m1_t scalar, size_t vl) {116 return __riscv_vredminu(vector, scalar, vl);117}118 119// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vredminu_vs_u16m4_u16m1120// CHECK-RV64-SAME: (<vscale x 16 x i16> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {121// CHECK-RV64-NEXT: entry:122// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv16i16.i64(<vscale x 4 x i16> poison, <vscale x 16 x i16> [[VECTOR]], <vscale x 4 x i16> [[SCALAR]], i64 [[VL]])123// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]124//125vuint16m1_t test_vredminu_vs_u16m4_u16m1(vuint16m4_t vector, vuint16m1_t scalar, size_t vl) {126 return __riscv_vredminu(vector, scalar, vl);127}128 129// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vredminu_vs_u16m8_u16m1130// CHECK-RV64-SAME: (<vscale x 32 x i16> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {131// CHECK-RV64-NEXT: entry:132// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv32i16.i64(<vscale x 4 x i16> poison, <vscale x 32 x i16> [[VECTOR]], <vscale x 4 x i16> [[SCALAR]], i64 [[VL]])133// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]134//135vuint16m1_t test_vredminu_vs_u16m8_u16m1(vuint16m8_t vector, vuint16m1_t scalar, size_t vl) {136 return __riscv_vredminu(vector, scalar, vl);137}138 139// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vredminu_vs_u32mf2_u32m1140// CHECK-RV64-SAME: (<vscale x 1 x i32> [[VECTOR:%.*]], <vscale x 2 x i32> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {141// CHECK-RV64-NEXT: entry:142// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> poison, <vscale x 1 x i32> [[VECTOR]], <vscale x 2 x i32> [[SCALAR]], i64 [[VL]])143// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]144//145vuint32m1_t test_vredminu_vs_u32mf2_u32m1(vuint32mf2_t vector, vuint32m1_t scalar, size_t vl) {146 return __riscv_vredminu(vector, scalar, vl);147}148 149// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vredminu_vs_u32m1_u32m1150// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VECTOR:%.*]], <vscale x 2 x i32> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {151// CHECK-RV64-NEXT: entry:152// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[VECTOR]], <vscale x 2 x i32> [[SCALAR]], i64 [[VL]])153// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]154//155vuint32m1_t test_vredminu_vs_u32m1_u32m1(vuint32m1_t vector, vuint32m1_t scalar, size_t vl) {156 return __riscv_vredminu(vector, scalar, vl);157}158 159// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vredminu_vs_u32m2_u32m1160// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VECTOR:%.*]], <vscale x 2 x i32> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {161// CHECK-RV64-NEXT: entry:162// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv4i32.i64(<vscale x 2 x i32> poison, <vscale x 4 x i32> [[VECTOR]], <vscale x 2 x i32> [[SCALAR]], i64 [[VL]])163// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]164//165vuint32m1_t test_vredminu_vs_u32m2_u32m1(vuint32m2_t vector, vuint32m1_t scalar, size_t vl) {166 return __riscv_vredminu(vector, scalar, vl);167}168 169// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vredminu_vs_u32m4_u32m1170// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VECTOR:%.*]], <vscale x 2 x i32> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {171// CHECK-RV64-NEXT: entry:172// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv8i32.i64(<vscale x 2 x i32> poison, <vscale x 8 x i32> [[VECTOR]], <vscale x 2 x i32> [[SCALAR]], i64 [[VL]])173// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]174//175vuint32m1_t test_vredminu_vs_u32m4_u32m1(vuint32m4_t vector, vuint32m1_t scalar, size_t vl) {176 return __riscv_vredminu(vector, scalar, vl);177}178 179// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vredminu_vs_u32m8_u32m1180// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VECTOR:%.*]], <vscale x 2 x i32> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {181// CHECK-RV64-NEXT: entry:182// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv16i32.i64(<vscale x 2 x i32> poison, <vscale x 16 x i32> [[VECTOR]], <vscale x 2 x i32> [[SCALAR]], i64 [[VL]])183// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]184//185vuint32m1_t test_vredminu_vs_u32m8_u32m1(vuint32m8_t vector, vuint32m1_t scalar, size_t vl) {186 return __riscv_vredminu(vector, scalar, vl);187}188 189// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vredminu_vs_u64m1_u64m1190// CHECK-RV64-SAME: (<vscale x 1 x i64> [[VECTOR:%.*]], <vscale x 1 x i64> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {191// CHECK-RV64-NEXT: entry:192// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> [[VECTOR]], <vscale x 1 x i64> [[SCALAR]], i64 [[VL]])193// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]194//195vuint64m1_t test_vredminu_vs_u64m1_u64m1(vuint64m1_t vector, vuint64m1_t scalar, size_t vl) {196 return __riscv_vredminu(vector, scalar, vl);197}198 199// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vredminu_vs_u64m2_u64m1200// CHECK-RV64-SAME: (<vscale x 2 x i64> [[VECTOR:%.*]], <vscale x 1 x i64> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {201// CHECK-RV64-NEXT: entry:202// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv2i64.i64(<vscale x 1 x i64> poison, <vscale x 2 x i64> [[VECTOR]], <vscale x 1 x i64> [[SCALAR]], i64 [[VL]])203// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]204//205vuint64m1_t test_vredminu_vs_u64m2_u64m1(vuint64m2_t vector, vuint64m1_t scalar, size_t vl) {206 return __riscv_vredminu(vector, scalar, vl);207}208 209// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vredminu_vs_u64m4_u64m1210// CHECK-RV64-SAME: (<vscale x 4 x i64> [[VECTOR:%.*]], <vscale x 1 x i64> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {211// CHECK-RV64-NEXT: entry:212// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv4i64.i64(<vscale x 1 x i64> poison, <vscale x 4 x i64> [[VECTOR]], <vscale x 1 x i64> [[SCALAR]], i64 [[VL]])213// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]214//215vuint64m1_t test_vredminu_vs_u64m4_u64m1(vuint64m4_t vector, vuint64m1_t scalar, size_t vl) {216 return __riscv_vredminu(vector, scalar, vl);217}218 219// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vredminu_vs_u64m8_u64m1220// CHECK-RV64-SAME: (<vscale x 8 x i64> [[VECTOR:%.*]], <vscale x 1 x i64> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {221// CHECK-RV64-NEXT: entry:222// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv8i64.i64(<vscale x 1 x i64> poison, <vscale x 8 x i64> [[VECTOR]], <vscale x 1 x i64> [[SCALAR]], i64 [[VL]])223// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]224//225vuint64m1_t test_vredminu_vs_u64m8_u64m1(vuint64m8_t vector, vuint64m1_t scalar, size_t vl) {226 return __riscv_vredminu(vector, scalar, vl);227}228 229// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf8_u8m1_m230// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[VECTOR:%.*]], <vscale x 8 x i8> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {231// CHECK-RV64-NEXT: entry:232// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> [[VECTOR]], <vscale x 8 x i8> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])233// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]234//235vuint8m1_t test_vredminu_vs_u8mf8_u8m1_m(vbool64_t mask, vuint8mf8_t vector, vuint8m1_t scalar, size_t vl) {236 return __riscv_vredminu(mask, vector, scalar, vl);237}238 239// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf4_u8m1_m240// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[VECTOR:%.*]], <vscale x 8 x i8> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {241// CHECK-RV64-NEXT: entry:242// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> [[VECTOR]], <vscale x 8 x i8> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])243// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]244//245vuint8m1_t test_vredminu_vs_u8mf4_u8m1_m(vbool32_t mask, vuint8mf4_t vector, vuint8m1_t scalar, size_t vl) {246 return __riscv_vredminu(mask, vector, scalar, vl);247}248 249// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf2_u8m1_m250// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[VECTOR:%.*]], <vscale x 8 x i8> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {251// CHECK-RV64-NEXT: entry:252// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> [[VECTOR]], <vscale x 8 x i8> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])253// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]254//255vuint8m1_t test_vredminu_vs_u8mf2_u8m1_m(vbool16_t mask, vuint8mf2_t vector, vuint8m1_t scalar, size_t vl) {256 return __riscv_vredminu(mask, vector, scalar, vl);257}258 259// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m1_u8m1_m260// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[VECTOR:%.*]], <vscale x 8 x i8> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {261// CHECK-RV64-NEXT: entry:262// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> [[VECTOR]], <vscale x 8 x i8> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])263// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]264//265vuint8m1_t test_vredminu_vs_u8m1_u8m1_m(vbool8_t mask, vuint8m1_t vector, vuint8m1_t scalar, size_t vl) {266 return __riscv_vredminu(mask, vector, scalar, vl);267}268 269// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m2_u8m1_m270// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[VECTOR:%.*]], <vscale x 8 x i8> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {271// CHECK-RV64-NEXT: entry:272// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> [[VECTOR]], <vscale x 8 x i8> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])273// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]274//275vuint8m1_t test_vredminu_vs_u8m2_u8m1_m(vbool4_t mask, vuint8m2_t vector, vuint8m1_t scalar, size_t vl) {276 return __riscv_vredminu(mask, vector, scalar, vl);277}278 279// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m4_u8m1_m280// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[VECTOR:%.*]], <vscale x 8 x i8> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {281// CHECK-RV64-NEXT: entry:282// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> [[VECTOR]], <vscale x 8 x i8> [[SCALAR]], <vscale x 32 x i1> [[MASK]], i64 [[VL]])283// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]284//285vuint8m1_t test_vredminu_vs_u8m4_u8m1_m(vbool2_t mask, vuint8m4_t vector, vuint8m1_t scalar, size_t vl) {286 return __riscv_vredminu(mask, vector, scalar, vl);287}288 289// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m8_u8m1_m290// CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[VECTOR:%.*]], <vscale x 8 x i8> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {291// CHECK-RV64-NEXT: entry:292// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> [[VECTOR]], <vscale x 8 x i8> [[SCALAR]], <vscale x 64 x i1> [[MASK]], i64 [[VL]])293// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]294//295vuint8m1_t test_vredminu_vs_u8m8_u8m1_m(vbool1_t mask, vuint8m8_t vector, vuint8m1_t scalar, size_t vl) {296 return __riscv_vredminu(mask, vector, scalar, vl);297}298 299// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vredminu_vs_u16mf4_u16m1_m300// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {301// CHECK-RV64-NEXT: entry:302// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> [[VECTOR]], <vscale x 4 x i16> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])303// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]304//305vuint16m1_t test_vredminu_vs_u16mf4_u16m1_m(vbool64_t mask, vuint16mf4_t vector, vuint16m1_t scalar, size_t vl) {306 return __riscv_vredminu(mask, vector, scalar, vl);307}308 309// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vredminu_vs_u16mf2_u16m1_m310// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {311// CHECK-RV64-NEXT: entry:312// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> [[VECTOR]], <vscale x 4 x i16> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])313// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]314//315vuint16m1_t test_vredminu_vs_u16mf2_u16m1_m(vbool32_t mask, vuint16mf2_t vector, vuint16m1_t scalar, size_t vl) {316 return __riscv_vredminu(mask, vector, scalar, vl);317}318 319// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vredminu_vs_u16m1_u16m1_m320// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {321// CHECK-RV64-NEXT: entry:322// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> [[VECTOR]], <vscale x 4 x i16> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])323// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]324//325vuint16m1_t test_vredminu_vs_u16m1_u16m1_m(vbool16_t mask, vuint16m1_t vector, vuint16m1_t scalar, size_t vl) {326 return __riscv_vredminu(mask, vector, scalar, vl);327}328 329// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vredminu_vs_u16m2_u16m1_m330// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {331// CHECK-RV64-NEXT: entry:332// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv8i16.i64(<vscale x 4 x i16> poison, <vscale x 8 x i16> [[VECTOR]], <vscale x 4 x i16> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])333// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]334//335vuint16m1_t test_vredminu_vs_u16m2_u16m1_m(vbool8_t mask, vuint16m2_t vector, vuint16m1_t scalar, size_t vl) {336 return __riscv_vredminu(mask, vector, scalar, vl);337}338 339// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vredminu_vs_u16m4_u16m1_m340// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {341// CHECK-RV64-NEXT: entry:342// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv16i16.i64(<vscale x 4 x i16> poison, <vscale x 16 x i16> [[VECTOR]], <vscale x 4 x i16> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])343// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]344//345vuint16m1_t test_vredminu_vs_u16m4_u16m1_m(vbool4_t mask, vuint16m4_t vector, vuint16m1_t scalar, size_t vl) {346 return __riscv_vredminu(mask, vector, scalar, vl);347}348 349// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vredminu_vs_u16m8_u16m1_m350// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {351// CHECK-RV64-NEXT: entry:352// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv32i16.i64(<vscale x 4 x i16> poison, <vscale x 32 x i16> [[VECTOR]], <vscale x 4 x i16> [[SCALAR]], <vscale x 32 x i1> [[MASK]], i64 [[VL]])353// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]354//355vuint16m1_t test_vredminu_vs_u16m8_u16m1_m(vbool2_t mask, vuint16m8_t vector, vuint16m1_t scalar, size_t vl) {356 return __riscv_vredminu(mask, vector, scalar, vl);357}358 359// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vredminu_vs_u32mf2_u32m1_m360// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[VECTOR:%.*]], <vscale x 2 x i32> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {361// CHECK-RV64-NEXT: entry:362// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> poison, <vscale x 1 x i32> [[VECTOR]], <vscale x 2 x i32> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])363// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]364//365vuint32m1_t test_vredminu_vs_u32mf2_u32m1_m(vbool64_t mask, vuint32mf2_t vector, vuint32m1_t scalar, size_t vl) {366 return __riscv_vredminu(mask, vector, scalar, vl);367}368 369// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vredminu_vs_u32m1_u32m1_m370// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[VECTOR:%.*]], <vscale x 2 x i32> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {371// CHECK-RV64-NEXT: entry:372// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[VECTOR]], <vscale x 2 x i32> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])373// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]374//375vuint32m1_t test_vredminu_vs_u32m1_u32m1_m(vbool32_t mask, vuint32m1_t vector, vuint32m1_t scalar, size_t vl) {376 return __riscv_vredminu(mask, vector, scalar, vl);377}378 379// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vredminu_vs_u32m2_u32m1_m380// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[VECTOR:%.*]], <vscale x 2 x i32> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {381// CHECK-RV64-NEXT: entry:382// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv4i32.i64(<vscale x 2 x i32> poison, <vscale x 4 x i32> [[VECTOR]], <vscale x 2 x i32> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])383// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]384//385vuint32m1_t test_vredminu_vs_u32m2_u32m1_m(vbool16_t mask, vuint32m2_t vector, vuint32m1_t scalar, size_t vl) {386 return __riscv_vredminu(mask, vector, scalar, vl);387}388 389// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vredminu_vs_u32m4_u32m1_m390// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[VECTOR:%.*]], <vscale x 2 x i32> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {391// CHECK-RV64-NEXT: entry:392// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv8i32.i64(<vscale x 2 x i32> poison, <vscale x 8 x i32> [[VECTOR]], <vscale x 2 x i32> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])393// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]394//395vuint32m1_t test_vredminu_vs_u32m4_u32m1_m(vbool8_t mask, vuint32m4_t vector, vuint32m1_t scalar, size_t vl) {396 return __riscv_vredminu(mask, vector, scalar, vl);397}398 399// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vredminu_vs_u32m8_u32m1_m400// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[VECTOR:%.*]], <vscale x 2 x i32> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {401// CHECK-RV64-NEXT: entry:402// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv16i32.i64(<vscale x 2 x i32> poison, <vscale x 16 x i32> [[VECTOR]], <vscale x 2 x i32> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])403// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]404//405vuint32m1_t test_vredminu_vs_u32m8_u32m1_m(vbool4_t mask, vuint32m8_t vector, vuint32m1_t scalar, size_t vl) {406 return __riscv_vredminu(mask, vector, scalar, vl);407}408 409// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vredminu_vs_u64m1_u64m1_m410// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[VECTOR:%.*]], <vscale x 1 x i64> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {411// CHECK-RV64-NEXT: entry:412// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> [[VECTOR]], <vscale x 1 x i64> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])413// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]414//415vuint64m1_t test_vredminu_vs_u64m1_u64m1_m(vbool64_t mask, vuint64m1_t vector, vuint64m1_t scalar, size_t vl) {416 return __riscv_vredminu(mask, vector, scalar, vl);417}418 419// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vredminu_vs_u64m2_u64m1_m420// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[VECTOR:%.*]], <vscale x 1 x i64> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {421// CHECK-RV64-NEXT: entry:422// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv2i64.i64(<vscale x 1 x i64> poison, <vscale x 2 x i64> [[VECTOR]], <vscale x 1 x i64> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])423// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]424//425vuint64m1_t test_vredminu_vs_u64m2_u64m1_m(vbool32_t mask, vuint64m2_t vector, vuint64m1_t scalar, size_t vl) {426 return __riscv_vredminu(mask, vector, scalar, vl);427}428 429// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vredminu_vs_u64m4_u64m1_m430// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[VECTOR:%.*]], <vscale x 1 x i64> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {431// CHECK-RV64-NEXT: entry:432// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv4i64.i64(<vscale x 1 x i64> poison, <vscale x 4 x i64> [[VECTOR]], <vscale x 1 x i64> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])433// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]434//435vuint64m1_t test_vredminu_vs_u64m4_u64m1_m(vbool16_t mask, vuint64m4_t vector, vuint64m1_t scalar, size_t vl) {436 return __riscv_vredminu(mask, vector, scalar, vl);437}438 439// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vredminu_vs_u64m8_u64m1_m440// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[VECTOR:%.*]], <vscale x 1 x i64> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {441// CHECK-RV64-NEXT: entry:442// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv8i64.i64(<vscale x 1 x i64> poison, <vscale x 8 x i64> [[VECTOR]], <vscale x 1 x i64> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])443// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]444//445vuint64m1_t test_vredminu_vs_u64m8_u64m1_m(vbool8_t mask, vuint64m8_t vector, vuint64m1_t scalar, size_t vl) {446 return __riscv_vredminu(mask, vector, scalar, vl);447}448 449