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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 22// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone \4// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \5// RUN: FileCheck --check-prefix=CHECK-RV64 %s6 7#include <riscv_vector.h>8 9// CHECK-RV64-LABEL: define dso_local void @test_vsm_v_b110// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], <vscale x 64 x i1> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {11// CHECK-RV64-NEXT: entry:12// CHECK-RV64-NEXT: call void @llvm.riscv.vsm.nxv64i1.p0.i64(<vscale x 64 x i1> [[VALUE]], ptr [[BASE]], i64 [[VL]])13// CHECK-RV64-NEXT: ret void14//15void test_vsm_v_b1(uint8_t *base, vbool1_t value, size_t vl) {16 return __riscv_vsm(base, value, vl);17}18 19// CHECK-RV64-LABEL: define dso_local void @test_vsm_v_b220// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], <vscale x 32 x i1> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {21// CHECK-RV64-NEXT: entry:22// CHECK-RV64-NEXT: call void @llvm.riscv.vsm.nxv32i1.p0.i64(<vscale x 32 x i1> [[VALUE]], ptr [[BASE]], i64 [[VL]])23// CHECK-RV64-NEXT: ret void24//25void test_vsm_v_b2(uint8_t *base, vbool2_t value, size_t vl) {26 return __riscv_vsm(base, value, vl);27}28 29// CHECK-RV64-LABEL: define dso_local void @test_vsm_v_b430// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], <vscale x 16 x i1> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {31// CHECK-RV64-NEXT: entry:32// CHECK-RV64-NEXT: call void @llvm.riscv.vsm.nxv16i1.p0.i64(<vscale x 16 x i1> [[VALUE]], ptr [[BASE]], i64 [[VL]])33// CHECK-RV64-NEXT: ret void34//35void test_vsm_v_b4(uint8_t *base, vbool4_t value, size_t vl) {36 return __riscv_vsm(base, value, vl);37}38 39// CHECK-RV64-LABEL: define dso_local void @test_vsm_v_b840// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], <vscale x 8 x i1> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {41// CHECK-RV64-NEXT: entry:42// CHECK-RV64-NEXT: call void @llvm.riscv.vsm.nxv8i1.p0.i64(<vscale x 8 x i1> [[VALUE]], ptr [[BASE]], i64 [[VL]])43// CHECK-RV64-NEXT: ret void44//45void test_vsm_v_b8(uint8_t *base, vbool8_t value, size_t vl) {46 return __riscv_vsm(base, value, vl);47}48 49// CHECK-RV64-LABEL: define dso_local void @test_vsm_v_b1650// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], <vscale x 4 x i1> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {51// CHECK-RV64-NEXT: entry:52// CHECK-RV64-NEXT: call void @llvm.riscv.vsm.nxv4i1.p0.i64(<vscale x 4 x i1> [[VALUE]], ptr [[BASE]], i64 [[VL]])53// CHECK-RV64-NEXT: ret void54//55void test_vsm_v_b16(uint8_t *base, vbool16_t value, size_t vl) {56 return __riscv_vsm(base, value, vl);57}58 59// CHECK-RV64-LABEL: define dso_local void @test_vsm_v_b3260// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], <vscale x 2 x i1> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {61// CHECK-RV64-NEXT: entry:62// CHECK-RV64-NEXT: call void @llvm.riscv.vsm.nxv2i1.p0.i64(<vscale x 2 x i1> [[VALUE]], ptr [[BASE]], i64 [[VL]])63// CHECK-RV64-NEXT: ret void64//65void test_vsm_v_b32(uint8_t *base, vbool32_t value, size_t vl) {66 return __riscv_vsm(base, value, vl);67}68 69// CHECK-RV64-LABEL: define dso_local void @test_vsm_v_b6470// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], <vscale x 1 x i1> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {71// CHECK-RV64-NEXT: entry:72// CHECK-RV64-NEXT: call void @llvm.riscv.vsm.nxv1i1.p0.i64(<vscale x 1 x i1> [[VALUE]], ptr [[BASE]], i64 [[VL]])73// CHECK-RV64-NEXT: ret void74//75void test_vsm_v_b64(uint8_t *base, vbool64_t value, size_t vl) {76 return __riscv_vsm(base, value, vl);77}78 79