250 lines · c
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 22// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \4// RUN: -target-feature +zvfhmin -disable-O0-optnone \5// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \6// RUN: FileCheck --check-prefix=CHECK-RV64 %s7 8#include <riscv_vector.h>9 10// CHECK-RV64-LABEL: define dso_local void @test_vsseg3e16_v_f16mf4x311// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], target("riscv.vector.tuple", <vscale x 2 x i8>, 3) [[V_TUPLE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {12// CHECK-RV64-NEXT: entry:13// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) [[V_TUPLE]], ptr [[BASE]], i64 [[VL]], i64 4)14// CHECK-RV64-NEXT: ret void15//16void test_vsseg3e16_v_f16mf4x3(_Float16 *base, vfloat16mf4x3_t v_tuple, size_t vl) {17 return __riscv_vsseg3e16(base, v_tuple, vl);18}19 20// CHECK-RV64-LABEL: define dso_local void @test_vsseg3e16_v_f16mf2x321// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[V_TUPLE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {22// CHECK-RV64-NEXT: entry:23// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[V_TUPLE]], ptr [[BASE]], i64 [[VL]], i64 4)24// CHECK-RV64-NEXT: ret void25//26void test_vsseg3e16_v_f16mf2x3(_Float16 *base, vfloat16mf2x3_t v_tuple, size_t vl) {27 return __riscv_vsseg3e16(base, v_tuple, vl);28}29 30// CHECK-RV64-LABEL: define dso_local void @test_vsseg3e16_v_f16m1x331// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], target("riscv.vector.tuple", <vscale x 8 x i8>, 3) [[V_TUPLE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {32// CHECK-RV64-NEXT: entry:33// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) [[V_TUPLE]], ptr [[BASE]], i64 [[VL]], i64 4)34// CHECK-RV64-NEXT: ret void35//36void test_vsseg3e16_v_f16m1x3(_Float16 *base, vfloat16m1x3_t v_tuple, size_t vl) {37 return __riscv_vsseg3e16(base, v_tuple, vl);38}39 40// CHECK-RV64-LABEL: define dso_local void @test_vsseg3e16_v_f16m2x341// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], target("riscv.vector.tuple", <vscale x 16 x i8>, 3) [[V_TUPLE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {42// CHECK-RV64-NEXT: entry:43// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) [[V_TUPLE]], ptr [[BASE]], i64 [[VL]], i64 4)44// CHECK-RV64-NEXT: ret void45//46void test_vsseg3e16_v_f16m2x3(_Float16 *base, vfloat16m2x3_t v_tuple, size_t vl) {47 return __riscv_vsseg3e16(base, v_tuple, vl);48}49 50// CHECK-RV64-LABEL: define dso_local void @test_vsseg3e16_v_i16mf4x351// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], target("riscv.vector.tuple", <vscale x 2 x i8>, 3) [[V_TUPLE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {52// CHECK-RV64-NEXT: entry:53// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) [[V_TUPLE]], ptr [[BASE]], i64 [[VL]], i64 4)54// CHECK-RV64-NEXT: ret void55//56void test_vsseg3e16_v_i16mf4x3(int16_t *base, vint16mf4x3_t v_tuple, size_t vl) {57 return __riscv_vsseg3e16(base, v_tuple, vl);58}59 60// CHECK-RV64-LABEL: define dso_local void @test_vsseg3e16_v_i16mf2x361// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[V_TUPLE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {62// CHECK-RV64-NEXT: entry:63// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[V_TUPLE]], ptr [[BASE]], i64 [[VL]], i64 4)64// CHECK-RV64-NEXT: ret void65//66void test_vsseg3e16_v_i16mf2x3(int16_t *base, vint16mf2x3_t v_tuple, size_t vl) {67 return __riscv_vsseg3e16(base, v_tuple, vl);68}69 70// CHECK-RV64-LABEL: define dso_local void @test_vsseg3e16_v_i16m1x371// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], target("riscv.vector.tuple", <vscale x 8 x i8>, 3) [[V_TUPLE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {72// CHECK-RV64-NEXT: entry:73// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) [[V_TUPLE]], ptr [[BASE]], i64 [[VL]], i64 4)74// CHECK-RV64-NEXT: ret void75//76void test_vsseg3e16_v_i16m1x3(int16_t *base, vint16m1x3_t v_tuple, size_t vl) {77 return __riscv_vsseg3e16(base, v_tuple, vl);78}79 80// CHECK-RV64-LABEL: define dso_local void @test_vsseg3e16_v_i16m2x381// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], target("riscv.vector.tuple", <vscale x 16 x i8>, 3) [[V_TUPLE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {82// CHECK-RV64-NEXT: entry:83// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) [[V_TUPLE]], ptr [[BASE]], i64 [[VL]], i64 4)84// CHECK-RV64-NEXT: ret void85//86void test_vsseg3e16_v_i16m2x3(int16_t *base, vint16m2x3_t v_tuple, size_t vl) {87 return __riscv_vsseg3e16(base, v_tuple, vl);88}89 90// CHECK-RV64-LABEL: define dso_local void @test_vsseg3e16_v_u16mf4x391// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], target("riscv.vector.tuple", <vscale x 2 x i8>, 3) [[V_TUPLE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {92// CHECK-RV64-NEXT: entry:93// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) [[V_TUPLE]], ptr [[BASE]], i64 [[VL]], i64 4)94// CHECK-RV64-NEXT: ret void95//96void test_vsseg3e16_v_u16mf4x3(uint16_t *base, vuint16mf4x3_t v_tuple, size_t vl) {97 return __riscv_vsseg3e16(base, v_tuple, vl);98}99 100// CHECK-RV64-LABEL: define dso_local void @test_vsseg3e16_v_u16mf2x3101// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[V_TUPLE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {102// CHECK-RV64-NEXT: entry:103// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[V_TUPLE]], ptr [[BASE]], i64 [[VL]], i64 4)104// CHECK-RV64-NEXT: ret void105//106void test_vsseg3e16_v_u16mf2x3(uint16_t *base, vuint16mf2x3_t v_tuple, size_t vl) {107 return __riscv_vsseg3e16(base, v_tuple, vl);108}109 110// CHECK-RV64-LABEL: define dso_local void @test_vsseg3e16_v_u16m1x3111// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], target("riscv.vector.tuple", <vscale x 8 x i8>, 3) [[V_TUPLE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {112// CHECK-RV64-NEXT: entry:113// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) [[V_TUPLE]], ptr [[BASE]], i64 [[VL]], i64 4)114// CHECK-RV64-NEXT: ret void115//116void test_vsseg3e16_v_u16m1x3(uint16_t *base, vuint16m1x3_t v_tuple, size_t vl) {117 return __riscv_vsseg3e16(base, v_tuple, vl);118}119 120// CHECK-RV64-LABEL: define dso_local void @test_vsseg3e16_v_u16m2x3121// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], target("riscv.vector.tuple", <vscale x 16 x i8>, 3) [[V_TUPLE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {122// CHECK-RV64-NEXT: entry:123// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) [[V_TUPLE]], ptr [[BASE]], i64 [[VL]], i64 4)124// CHECK-RV64-NEXT: ret void125//126void test_vsseg3e16_v_u16m2x3(uint16_t *base, vuint16m2x3_t v_tuple, size_t vl) {127 return __riscv_vsseg3e16(base, v_tuple, vl);128}129 130// CHECK-RV64-LABEL: define dso_local void @test_vsseg3e16_v_f16mf4x3_m131// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], target("riscv.vector.tuple", <vscale x 2 x i8>, 3) [[V_TUPLE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {132// CHECK-RV64-NEXT: entry:133// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) [[V_TUPLE]], ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 4)134// CHECK-RV64-NEXT: ret void135//136void test_vsseg3e16_v_f16mf4x3_m(vbool64_t mask, _Float16 *base, vfloat16mf4x3_t v_tuple, size_t vl) {137 return __riscv_vsseg3e16(mask, base, v_tuple, vl);138}139 140// CHECK-RV64-LABEL: define dso_local void @test_vsseg3e16_v_f16mf2x3_m141// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[V_TUPLE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {142// CHECK-RV64-NEXT: entry:143// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[V_TUPLE]], ptr [[BASE]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 4)144// CHECK-RV64-NEXT: ret void145//146void test_vsseg3e16_v_f16mf2x3_m(vbool32_t mask, _Float16 *base, vfloat16mf2x3_t v_tuple, size_t vl) {147 return __riscv_vsseg3e16(mask, base, v_tuple, vl);148}149 150// CHECK-RV64-LABEL: define dso_local void @test_vsseg3e16_v_f16m1x3_m151// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], target("riscv.vector.tuple", <vscale x 8 x i8>, 3) [[V_TUPLE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {152// CHECK-RV64-NEXT: entry:153// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) [[V_TUPLE]], ptr [[BASE]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 4)154// CHECK-RV64-NEXT: ret void155//156void test_vsseg3e16_v_f16m1x3_m(vbool16_t mask, _Float16 *base, vfloat16m1x3_t v_tuple, size_t vl) {157 return __riscv_vsseg3e16(mask, base, v_tuple, vl);158}159 160// CHECK-RV64-LABEL: define dso_local void @test_vsseg3e16_v_f16m2x3_m161// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], target("riscv.vector.tuple", <vscale x 16 x i8>, 3) [[V_TUPLE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {162// CHECK-RV64-NEXT: entry:163// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) [[V_TUPLE]], ptr [[BASE]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 4)164// CHECK-RV64-NEXT: ret void165//166void test_vsseg3e16_v_f16m2x3_m(vbool8_t mask, _Float16 *base, vfloat16m2x3_t v_tuple, size_t vl) {167 return __riscv_vsseg3e16(mask, base, v_tuple, vl);168}169 170// CHECK-RV64-LABEL: define dso_local void @test_vsseg3e16_v_i16mf4x3_m171// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], target("riscv.vector.tuple", <vscale x 2 x i8>, 3) [[V_TUPLE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {172// CHECK-RV64-NEXT: entry:173// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) [[V_TUPLE]], ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 4)174// CHECK-RV64-NEXT: ret void175//176void test_vsseg3e16_v_i16mf4x3_m(vbool64_t mask, int16_t *base, vint16mf4x3_t v_tuple, size_t vl) {177 return __riscv_vsseg3e16(mask, base, v_tuple, vl);178}179 180// CHECK-RV64-LABEL: define dso_local void @test_vsseg3e16_v_i16mf2x3_m181// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[V_TUPLE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {182// CHECK-RV64-NEXT: entry:183// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[V_TUPLE]], ptr [[BASE]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 4)184// CHECK-RV64-NEXT: ret void185//186void test_vsseg3e16_v_i16mf2x3_m(vbool32_t mask, int16_t *base, vint16mf2x3_t v_tuple, size_t vl) {187 return __riscv_vsseg3e16(mask, base, v_tuple, vl);188}189 190// CHECK-RV64-LABEL: define dso_local void @test_vsseg3e16_v_i16m1x3_m191// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], target("riscv.vector.tuple", <vscale x 8 x i8>, 3) [[V_TUPLE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {192// CHECK-RV64-NEXT: entry:193// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) [[V_TUPLE]], ptr [[BASE]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 4)194// CHECK-RV64-NEXT: ret void195//196void test_vsseg3e16_v_i16m1x3_m(vbool16_t mask, int16_t *base, vint16m1x3_t v_tuple, size_t vl) {197 return __riscv_vsseg3e16(mask, base, v_tuple, vl);198}199 200// CHECK-RV64-LABEL: define dso_local void @test_vsseg3e16_v_i16m2x3_m201// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], target("riscv.vector.tuple", <vscale x 16 x i8>, 3) [[V_TUPLE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {202// CHECK-RV64-NEXT: entry:203// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) [[V_TUPLE]], ptr [[BASE]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 4)204// CHECK-RV64-NEXT: ret void205//206void test_vsseg3e16_v_i16m2x3_m(vbool8_t mask, int16_t *base, vint16m2x3_t v_tuple, size_t vl) {207 return __riscv_vsseg3e16(mask, base, v_tuple, vl);208}209 210// CHECK-RV64-LABEL: define dso_local void @test_vsseg3e16_v_u16mf4x3_m211// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], target("riscv.vector.tuple", <vscale x 2 x i8>, 3) [[V_TUPLE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {212// CHECK-RV64-NEXT: entry:213// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) [[V_TUPLE]], ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 4)214// CHECK-RV64-NEXT: ret void215//216void test_vsseg3e16_v_u16mf4x3_m(vbool64_t mask, uint16_t *base, vuint16mf4x3_t v_tuple, size_t vl) {217 return __riscv_vsseg3e16(mask, base, v_tuple, vl);218}219 220// CHECK-RV64-LABEL: define dso_local void @test_vsseg3e16_v_u16mf2x3_m221// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[V_TUPLE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {222// CHECK-RV64-NEXT: entry:223// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[V_TUPLE]], ptr [[BASE]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 4)224// CHECK-RV64-NEXT: ret void225//226void test_vsseg3e16_v_u16mf2x3_m(vbool32_t mask, uint16_t *base, vuint16mf2x3_t v_tuple, size_t vl) {227 return __riscv_vsseg3e16(mask, base, v_tuple, vl);228}229 230// CHECK-RV64-LABEL: define dso_local void @test_vsseg3e16_v_u16m1x3_m231// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], target("riscv.vector.tuple", <vscale x 8 x i8>, 3) [[V_TUPLE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {232// CHECK-RV64-NEXT: entry:233// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) [[V_TUPLE]], ptr [[BASE]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 4)234// CHECK-RV64-NEXT: ret void235//236void test_vsseg3e16_v_u16m1x3_m(vbool16_t mask, uint16_t *base, vuint16m1x3_t v_tuple, size_t vl) {237 return __riscv_vsseg3e16(mask, base, v_tuple, vl);238}239 240// CHECK-RV64-LABEL: define dso_local void @test_vsseg3e16_v_u16m2x3_m241// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], target("riscv.vector.tuple", <vscale x 16 x i8>, 3) [[V_TUPLE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {242// CHECK-RV64-NEXT: entry:243// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) [[V_TUPLE]], ptr [[BASE]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 4)244// CHECK-RV64-NEXT: ret void245//246void test_vsseg3e16_v_u16m2x3_m(vbool8_t mask, uint16_t *base, vuint16m2x3_t v_tuple, size_t vl) {247 return __riscv_vsseg3e16(mask, base, v_tuple, vl);248}249 250