130 lines · c
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 22// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \4// RUN: -target-feature +zvfh -disable-O0-optnone \5// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \6// RUN: FileCheck --check-prefix=CHECK-RV64 %s7 8#include <riscv_vector.h>9 10// CHECK-RV64-LABEL: define dso_local void @test_vssseg6e32_v_f32mf2x611// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[V_TUPLE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {12// CHECK-RV64-NEXT: entry:13// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[V_TUPLE]], ptr [[BASE]], i64 [[BSTRIDE]], i64 [[VL]], i64 5)14// CHECK-RV64-NEXT: ret void15//16void test_vssseg6e32_v_f32mf2x6(float *base, ptrdiff_t bstride, vfloat32mf2x6_t v_tuple, size_t vl) {17 return __riscv_vssseg6e32(base, bstride, v_tuple, vl);18}19 20// CHECK-RV64-LABEL: define dso_local void @test_vssseg6e32_v_f32m1x621// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], target("riscv.vector.tuple", <vscale x 8 x i8>, 6) [[V_TUPLE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {22// CHECK-RV64-NEXT: entry:23// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) [[V_TUPLE]], ptr [[BASE]], i64 [[BSTRIDE]], i64 [[VL]], i64 5)24// CHECK-RV64-NEXT: ret void25//26void test_vssseg6e32_v_f32m1x6(float *base, ptrdiff_t bstride, vfloat32m1x6_t v_tuple, size_t vl) {27 return __riscv_vssseg6e32(base, bstride, v_tuple, vl);28}29 30// CHECK-RV64-LABEL: define dso_local void @test_vssseg6e32_v_i32mf2x631// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[V_TUPLE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {32// CHECK-RV64-NEXT: entry:33// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[V_TUPLE]], ptr [[BASE]], i64 [[BSTRIDE]], i64 [[VL]], i64 5)34// CHECK-RV64-NEXT: ret void35//36void test_vssseg6e32_v_i32mf2x6(int32_t *base, ptrdiff_t bstride, vint32mf2x6_t v_tuple, size_t vl) {37 return __riscv_vssseg6e32(base, bstride, v_tuple, vl);38}39 40// CHECK-RV64-LABEL: define dso_local void @test_vssseg6e32_v_i32m1x641// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], target("riscv.vector.tuple", <vscale x 8 x i8>, 6) [[V_TUPLE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {42// CHECK-RV64-NEXT: entry:43// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) [[V_TUPLE]], ptr [[BASE]], i64 [[BSTRIDE]], i64 [[VL]], i64 5)44// CHECK-RV64-NEXT: ret void45//46void test_vssseg6e32_v_i32m1x6(int32_t *base, ptrdiff_t bstride, vint32m1x6_t v_tuple, size_t vl) {47 return __riscv_vssseg6e32(base, bstride, v_tuple, vl);48}49 50// CHECK-RV64-LABEL: define dso_local void @test_vssseg6e32_v_u32mf2x651// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[V_TUPLE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {52// CHECK-RV64-NEXT: entry:53// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[V_TUPLE]], ptr [[BASE]], i64 [[BSTRIDE]], i64 [[VL]], i64 5)54// CHECK-RV64-NEXT: ret void55//56void test_vssseg6e32_v_u32mf2x6(uint32_t *base, ptrdiff_t bstride, vuint32mf2x6_t v_tuple, size_t vl) {57 return __riscv_vssseg6e32(base, bstride, v_tuple, vl);58}59 60// CHECK-RV64-LABEL: define dso_local void @test_vssseg6e32_v_u32m1x661// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], target("riscv.vector.tuple", <vscale x 8 x i8>, 6) [[V_TUPLE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {62// CHECK-RV64-NEXT: entry:63// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) [[V_TUPLE]], ptr [[BASE]], i64 [[BSTRIDE]], i64 [[VL]], i64 5)64// CHECK-RV64-NEXT: ret void65//66void test_vssseg6e32_v_u32m1x6(uint32_t *base, ptrdiff_t bstride, vuint32m1x6_t v_tuple, size_t vl) {67 return __riscv_vssseg6e32(base, bstride, v_tuple, vl);68}69 70// CHECK-RV64-LABEL: define dso_local void @test_vssseg6e32_v_f32mf2x6_m71// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[V_TUPLE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {72// CHECK-RV64-NEXT: entry:73// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[V_TUPLE]], ptr [[BASE]], i64 [[BSTRIDE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)74// CHECK-RV64-NEXT: ret void75//76void test_vssseg6e32_v_f32mf2x6_m(vbool64_t mask, float *base, ptrdiff_t bstride, vfloat32mf2x6_t v_tuple, size_t vl) {77 return __riscv_vssseg6e32(mask, base, bstride, v_tuple, vl);78}79 80// CHECK-RV64-LABEL: define dso_local void @test_vssseg6e32_v_f32m1x6_m81// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], target("riscv.vector.tuple", <vscale x 8 x i8>, 6) [[V_TUPLE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {82// CHECK-RV64-NEXT: entry:83// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) [[V_TUPLE]], ptr [[BASE]], i64 [[BSTRIDE]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 5)84// CHECK-RV64-NEXT: ret void85//86void test_vssseg6e32_v_f32m1x6_m(vbool32_t mask, float *base, ptrdiff_t bstride, vfloat32m1x6_t v_tuple, size_t vl) {87 return __riscv_vssseg6e32(mask, base, bstride, v_tuple, vl);88}89 90// CHECK-RV64-LABEL: define dso_local void @test_vssseg6e32_v_i32mf2x6_m91// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[V_TUPLE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {92// CHECK-RV64-NEXT: entry:93// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[V_TUPLE]], ptr [[BASE]], i64 [[BSTRIDE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)94// CHECK-RV64-NEXT: ret void95//96void test_vssseg6e32_v_i32mf2x6_m(vbool64_t mask, int32_t *base, ptrdiff_t bstride, vint32mf2x6_t v_tuple, size_t vl) {97 return __riscv_vssseg6e32(mask, base, bstride, v_tuple, vl);98}99 100// CHECK-RV64-LABEL: define dso_local void @test_vssseg6e32_v_i32m1x6_m101// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], target("riscv.vector.tuple", <vscale x 8 x i8>, 6) [[V_TUPLE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {102// CHECK-RV64-NEXT: entry:103// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) [[V_TUPLE]], ptr [[BASE]], i64 [[BSTRIDE]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 5)104// CHECK-RV64-NEXT: ret void105//106void test_vssseg6e32_v_i32m1x6_m(vbool32_t mask, int32_t *base, ptrdiff_t bstride, vint32m1x6_t v_tuple, size_t vl) {107 return __riscv_vssseg6e32(mask, base, bstride, v_tuple, vl);108}109 110// CHECK-RV64-LABEL: define dso_local void @test_vssseg6e32_v_u32mf2x6_m111// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[V_TUPLE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {112// CHECK-RV64-NEXT: entry:113// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[V_TUPLE]], ptr [[BASE]], i64 [[BSTRIDE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)114// CHECK-RV64-NEXT: ret void115//116void test_vssseg6e32_v_u32mf2x6_m(vbool64_t mask, uint32_t *base, ptrdiff_t bstride, vuint32mf2x6_t v_tuple, size_t vl) {117 return __riscv_vssseg6e32(mask, base, bstride, v_tuple, vl);118}119 120// CHECK-RV64-LABEL: define dso_local void @test_vssseg6e32_v_u32m1x6_m121// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], target("riscv.vector.tuple", <vscale x 8 x i8>, 6) [[V_TUPLE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {122// CHECK-RV64-NEXT: entry:123// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) [[V_TUPLE]], ptr [[BASE]], i64 [[BSTRIDE]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 5)124// CHECK-RV64-NEXT: ret void125//126void test_vssseg6e32_v_u32m1x6_m(vbool32_t mask, uint32_t *base, ptrdiff_t bstride, vuint32m1x6_t v_tuple, size_t vl) {127 return __riscv_vssseg6e32(mask, base, bstride, v_tuple, vl);128}129 130