610 lines · c
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 22// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \4// RUN: -target-feature +zvfh -disable-O0-optnone \5// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \6// RUN: FileCheck --check-prefix=CHECK-RV64 %s7 8#include <riscv_vector.h>9 10// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vfclass_v_u16mf4_tu11// CHECK-RV64-SAME: (<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {12// CHECK-RV64-NEXT: entry:13// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1f16.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x half> [[OP1]], i64 [[VL]])14// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]15//16vuint16mf4_t test_vfclass_v_u16mf4_tu(vuint16mf4_t maskedoff, vfloat16mf4_t op1, size_t vl) {17 return __riscv_vfclass_v_u16mf4_tu(maskedoff, op1, vl);18}19 20// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vfclass_v_u16mf2_tu21// CHECK-RV64-SAME: (<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {22// CHECK-RV64-NEXT: entry:23// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2f16.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x half> [[OP1]], i64 [[VL]])24// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]25//26vuint16mf2_t test_vfclass_v_u16mf2_tu(vuint16mf2_t maskedoff, vfloat16mf2_t op1, size_t vl) {27 return __riscv_vfclass_v_u16mf2_tu(maskedoff, op1, vl);28}29 30// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfclass_v_u16m1_tu31// CHECK-RV64-SAME: (<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {32// CHECK-RV64-NEXT: entry:33// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4f16.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x half> [[OP1]], i64 [[VL]])34// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]35//36vuint16m1_t test_vfclass_v_u16m1_tu(vuint16m1_t maskedoff, vfloat16m1_t op1, size_t vl) {37 return __riscv_vfclass_v_u16m1_tu(maskedoff, op1, vl);38}39 40// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfclass_v_u16m2_tu41// CHECK-RV64-SAME: (<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {42// CHECK-RV64-NEXT: entry:43// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8f16.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x half> [[OP1]], i64 [[VL]])44// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]45//46vuint16m2_t test_vfclass_v_u16m2_tu(vuint16m2_t maskedoff, vfloat16m2_t op1, size_t vl) {47 return __riscv_vfclass_v_u16m2_tu(maskedoff, op1, vl);48}49 50// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfclass_v_u16m4_tu51// CHECK-RV64-SAME: (<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {52// CHECK-RV64-NEXT: entry:53// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16f16.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x half> [[OP1]], i64 [[VL]])54// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]55//56vuint16m4_t test_vfclass_v_u16m4_tu(vuint16m4_t maskedoff, vfloat16m4_t op1, size_t vl) {57 return __riscv_vfclass_v_u16m4_tu(maskedoff, op1, vl);58}59 60// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vfclass_v_u16m8_tu61// CHECK-RV64-SAME: (<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {62// CHECK-RV64-NEXT: entry:63// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32f16.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x half> [[OP1]], i64 [[VL]])64// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]65//66vuint16m8_t test_vfclass_v_u16m8_tu(vuint16m8_t maskedoff, vfloat16m8_t op1, size_t vl) {67 return __riscv_vfclass_v_u16m8_tu(maskedoff, op1, vl);68}69 70// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfclass_v_u32mf2_tu71// CHECK-RV64-SAME: (<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {72// CHECK-RV64-NEXT: entry:73// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1f32.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x float> [[OP1]], i64 [[VL]])74// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]75//76vuint32mf2_t test_vfclass_v_u32mf2_tu(vuint32mf2_t maskedoff, vfloat32mf2_t op1, size_t vl) {77 return __riscv_vfclass_v_u32mf2_tu(maskedoff, op1, vl);78}79 80// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfclass_v_u32m1_tu81// CHECK-RV64-SAME: (<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {82// CHECK-RV64-NEXT: entry:83// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2f32.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x float> [[OP1]], i64 [[VL]])84// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]85//86vuint32m1_t test_vfclass_v_u32m1_tu(vuint32m1_t maskedoff, vfloat32m1_t op1, size_t vl) {87 return __riscv_vfclass_v_u32m1_tu(maskedoff, op1, vl);88}89 90// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfclass_v_u32m2_tu91// CHECK-RV64-SAME: (<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {92// CHECK-RV64-NEXT: entry:93// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4f32.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x float> [[OP1]], i64 [[VL]])94// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]95//96vuint32m2_t test_vfclass_v_u32m2_tu(vuint32m2_t maskedoff, vfloat32m2_t op1, size_t vl) {97 return __riscv_vfclass_v_u32m2_tu(maskedoff, op1, vl);98}99 100// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfclass_v_u32m4_tu101// CHECK-RV64-SAME: (<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {102// CHECK-RV64-NEXT: entry:103// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfclass.nxv8f32.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x float> [[OP1]], i64 [[VL]])104// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]105//106vuint32m4_t test_vfclass_v_u32m4_tu(vuint32m4_t maskedoff, vfloat32m4_t op1, size_t vl) {107 return __riscv_vfclass_v_u32m4_tu(maskedoff, op1, vl);108}109 110// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfclass_v_u32m8_tu111// CHECK-RV64-SAME: (<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {112// CHECK-RV64-NEXT: entry:113// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfclass.nxv16f32.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x float> [[OP1]], i64 [[VL]])114// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]115//116vuint32m8_t test_vfclass_v_u32m8_tu(vuint32m8_t maskedoff, vfloat32m8_t op1, size_t vl) {117 return __riscv_vfclass_v_u32m8_tu(maskedoff, op1, vl);118}119 120// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfclass_v_u64m1_tu121// CHECK-RV64-SAME: (<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {122// CHECK-RV64-NEXT: entry:123// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfclass.nxv1f64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x double> [[OP1]], i64 [[VL]])124// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]125//126vuint64m1_t test_vfclass_v_u64m1_tu(vuint64m1_t maskedoff, vfloat64m1_t op1, size_t vl) {127 return __riscv_vfclass_v_u64m1_tu(maskedoff, op1, vl);128}129 130// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfclass_v_u64m2_tu131// CHECK-RV64-SAME: (<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {132// CHECK-RV64-NEXT: entry:133// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfclass.nxv2f64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x double> [[OP1]], i64 [[VL]])134// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]135//136vuint64m2_t test_vfclass_v_u64m2_tu(vuint64m2_t maskedoff, vfloat64m2_t op1, size_t vl) {137 return __riscv_vfclass_v_u64m2_tu(maskedoff, op1, vl);138}139 140// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfclass_v_u64m4_tu141// CHECK-RV64-SAME: (<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {142// CHECK-RV64-NEXT: entry:143// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfclass.nxv4f64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x double> [[OP1]], i64 [[VL]])144// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]145//146vuint64m4_t test_vfclass_v_u64m4_tu(vuint64m4_t maskedoff, vfloat64m4_t op1, size_t vl) {147 return __riscv_vfclass_v_u64m4_tu(maskedoff, op1, vl);148}149 150// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfclass_v_u64m8_tu151// CHECK-RV64-SAME: (<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {152// CHECK-RV64-NEXT: entry:153// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfclass.nxv8f64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x double> [[OP1]], i64 [[VL]])154// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]155//156vuint64m8_t test_vfclass_v_u64m8_tu(vuint64m8_t maskedoff, vfloat64m8_t op1, size_t vl) {157 return __riscv_vfclass_v_u64m8_tu(maskedoff, op1, vl);158}159 160// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vfclass_v_u16mf4_tum161// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {162// CHECK-RV64-NEXT: entry:163// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1f16.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x half> [[OP1]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)164// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]165//166vuint16mf4_t test_vfclass_v_u16mf4_tum(vbool64_t mask, vuint16mf4_t maskedoff, vfloat16mf4_t op1, size_t vl) {167 return __riscv_vfclass_v_u16mf4_tum(mask, maskedoff, op1, vl);168}169 170// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vfclass_v_u16mf2_tum171// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {172// CHECK-RV64-NEXT: entry:173// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2f16.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x half> [[OP1]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)174// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]175//176vuint16mf2_t test_vfclass_v_u16mf2_tum(vbool32_t mask, vuint16mf2_t maskedoff, vfloat16mf2_t op1, size_t vl) {177 return __riscv_vfclass_v_u16mf2_tum(mask, maskedoff, op1, vl);178}179 180// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfclass_v_u16m1_tum181// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {182// CHECK-RV64-NEXT: entry:183// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4f16.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x half> [[OP1]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)184// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]185//186vuint16m1_t test_vfclass_v_u16m1_tum(vbool16_t mask, vuint16m1_t maskedoff, vfloat16m1_t op1, size_t vl) {187 return __riscv_vfclass_v_u16m1_tum(mask, maskedoff, op1, vl);188}189 190// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfclass_v_u16m2_tum191// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {192// CHECK-RV64-NEXT: entry:193// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfclass.mask.nxv8f16.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x half> [[OP1]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)194// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]195//196vuint16m2_t test_vfclass_v_u16m2_tum(vbool8_t mask, vuint16m2_t maskedoff, vfloat16m2_t op1, size_t vl) {197 return __riscv_vfclass_v_u16m2_tum(mask, maskedoff, op1, vl);198}199 200// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfclass_v_u16m4_tum201// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {202// CHECK-RV64-NEXT: entry:203// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfclass.mask.nxv16f16.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x half> [[OP1]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)204// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]205//206vuint16m4_t test_vfclass_v_u16m4_tum(vbool4_t mask, vuint16m4_t maskedoff, vfloat16m4_t op1, size_t vl) {207 return __riscv_vfclass_v_u16m4_tum(mask, maskedoff, op1, vl);208}209 210// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vfclass_v_u16m8_tum211// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {212// CHECK-RV64-NEXT: entry:213// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vfclass.mask.nxv32f16.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x half> [[OP1]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2)214// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]215//216vuint16m8_t test_vfclass_v_u16m8_tum(vbool2_t mask, vuint16m8_t maskedoff, vfloat16m8_t op1, size_t vl) {217 return __riscv_vfclass_v_u16m8_tum(mask, maskedoff, op1, vl);218}219 220// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfclass_v_u32mf2_tum221// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {222// CHECK-RV64-NEXT: entry:223// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfclass.mask.nxv1f32.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x float> [[OP1]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)224// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]225//226vuint32mf2_t test_vfclass_v_u32mf2_tum(vbool64_t mask, vuint32mf2_t maskedoff, vfloat32mf2_t op1, size_t vl) {227 return __riscv_vfclass_v_u32mf2_tum(mask, maskedoff, op1, vl);228}229 230// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfclass_v_u32m1_tum231// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {232// CHECK-RV64-NEXT: entry:233// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfclass.mask.nxv2f32.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x float> [[OP1]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)234// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]235//236vuint32m1_t test_vfclass_v_u32m1_tum(vbool32_t mask, vuint32m1_t maskedoff, vfloat32m1_t op1, size_t vl) {237 return __riscv_vfclass_v_u32m1_tum(mask, maskedoff, op1, vl);238}239 240// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfclass_v_u32m2_tum241// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {242// CHECK-RV64-NEXT: entry:243// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfclass.mask.nxv4f32.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x float> [[OP1]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)244// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]245//246vuint32m2_t test_vfclass_v_u32m2_tum(vbool16_t mask, vuint32m2_t maskedoff, vfloat32m2_t op1, size_t vl) {247 return __riscv_vfclass_v_u32m2_tum(mask, maskedoff, op1, vl);248}249 250// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfclass_v_u32m4_tum251// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {252// CHECK-RV64-NEXT: entry:253// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfclass.mask.nxv8f32.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x float> [[OP1]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)254// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]255//256vuint32m4_t test_vfclass_v_u32m4_tum(vbool8_t mask, vuint32m4_t maskedoff, vfloat32m4_t op1, size_t vl) {257 return __riscv_vfclass_v_u32m4_tum(mask, maskedoff, op1, vl);258}259 260// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfclass_v_u32m8_tum261// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {262// CHECK-RV64-NEXT: entry:263// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfclass.mask.nxv16f32.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x float> [[OP1]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)264// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]265//266vuint32m8_t test_vfclass_v_u32m8_tum(vbool4_t mask, vuint32m8_t maskedoff, vfloat32m8_t op1, size_t vl) {267 return __riscv_vfclass_v_u32m8_tum(mask, maskedoff, op1, vl);268}269 270// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfclass_v_u64m1_tum271// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {272// CHECK-RV64-NEXT: entry:273// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfclass.mask.nxv1f64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x double> [[OP1]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)274// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]275//276vuint64m1_t test_vfclass_v_u64m1_tum(vbool64_t mask, vuint64m1_t maskedoff, vfloat64m1_t op1, size_t vl) {277 return __riscv_vfclass_v_u64m1_tum(mask, maskedoff, op1, vl);278}279 280// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfclass_v_u64m2_tum281// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {282// CHECK-RV64-NEXT: entry:283// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfclass.mask.nxv2f64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x double> [[OP1]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)284// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]285//286vuint64m2_t test_vfclass_v_u64m2_tum(vbool32_t mask, vuint64m2_t maskedoff, vfloat64m2_t op1, size_t vl) {287 return __riscv_vfclass_v_u64m2_tum(mask, maskedoff, op1, vl);288}289 290// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfclass_v_u64m4_tum291// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {292// CHECK-RV64-NEXT: entry:293// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfclass.mask.nxv4f64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x double> [[OP1]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)294// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]295//296vuint64m4_t test_vfclass_v_u64m4_tum(vbool16_t mask, vuint64m4_t maskedoff, vfloat64m4_t op1, size_t vl) {297 return __riscv_vfclass_v_u64m4_tum(mask, maskedoff, op1, vl);298}299 300// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfclass_v_u64m8_tum301// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {302// CHECK-RV64-NEXT: entry:303// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfclass.mask.nxv8f64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x double> [[OP1]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)304// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]305//306vuint64m8_t test_vfclass_v_u64m8_tum(vbool8_t mask, vuint64m8_t maskedoff, vfloat64m8_t op1, size_t vl) {307 return __riscv_vfclass_v_u64m8_tum(mask, maskedoff, op1, vl);308}309 310// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vfclass_v_u16mf4_tumu311// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {312// CHECK-RV64-NEXT: entry:313// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1f16.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x half> [[OP1]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)314// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]315//316vuint16mf4_t test_vfclass_v_u16mf4_tumu(vbool64_t mask, vuint16mf4_t maskedoff, vfloat16mf4_t op1, size_t vl) {317 return __riscv_vfclass_v_u16mf4_tumu(mask, maskedoff, op1, vl);318}319 320// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vfclass_v_u16mf2_tumu321// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {322// CHECK-RV64-NEXT: entry:323// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2f16.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x half> [[OP1]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)324// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]325//326vuint16mf2_t test_vfclass_v_u16mf2_tumu(vbool32_t mask, vuint16mf2_t maskedoff, vfloat16mf2_t op1, size_t vl) {327 return __riscv_vfclass_v_u16mf2_tumu(mask, maskedoff, op1, vl);328}329 330// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfclass_v_u16m1_tumu331// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {332// CHECK-RV64-NEXT: entry:333// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4f16.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x half> [[OP1]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)334// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]335//336vuint16m1_t test_vfclass_v_u16m1_tumu(vbool16_t mask, vuint16m1_t maskedoff, vfloat16m1_t op1, size_t vl) {337 return __riscv_vfclass_v_u16m1_tumu(mask, maskedoff, op1, vl);338}339 340// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfclass_v_u16m2_tumu341// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {342// CHECK-RV64-NEXT: entry:343// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfclass.mask.nxv8f16.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x half> [[OP1]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)344// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]345//346vuint16m2_t test_vfclass_v_u16m2_tumu(vbool8_t mask, vuint16m2_t maskedoff, vfloat16m2_t op1, size_t vl) {347 return __riscv_vfclass_v_u16m2_tumu(mask, maskedoff, op1, vl);348}349 350// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfclass_v_u16m4_tumu351// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {352// CHECK-RV64-NEXT: entry:353// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfclass.mask.nxv16f16.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x half> [[OP1]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)354// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]355//356vuint16m4_t test_vfclass_v_u16m4_tumu(vbool4_t mask, vuint16m4_t maskedoff, vfloat16m4_t op1, size_t vl) {357 return __riscv_vfclass_v_u16m4_tumu(mask, maskedoff, op1, vl);358}359 360// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vfclass_v_u16m8_tumu361// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {362// CHECK-RV64-NEXT: entry:363// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vfclass.mask.nxv32f16.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x half> [[OP1]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0)364// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]365//366vuint16m8_t test_vfclass_v_u16m8_tumu(vbool2_t mask, vuint16m8_t maskedoff, vfloat16m8_t op1, size_t vl) {367 return __riscv_vfclass_v_u16m8_tumu(mask, maskedoff, op1, vl);368}369 370// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfclass_v_u32mf2_tumu371// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {372// CHECK-RV64-NEXT: entry:373// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfclass.mask.nxv1f32.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x float> [[OP1]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)374// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]375//376vuint32mf2_t test_vfclass_v_u32mf2_tumu(vbool64_t mask, vuint32mf2_t maskedoff, vfloat32mf2_t op1, size_t vl) {377 return __riscv_vfclass_v_u32mf2_tumu(mask, maskedoff, op1, vl);378}379 380// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfclass_v_u32m1_tumu381// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {382// CHECK-RV64-NEXT: entry:383// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfclass.mask.nxv2f32.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x float> [[OP1]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)384// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]385//386vuint32m1_t test_vfclass_v_u32m1_tumu(vbool32_t mask, vuint32m1_t maskedoff, vfloat32m1_t op1, size_t vl) {387 return __riscv_vfclass_v_u32m1_tumu(mask, maskedoff, op1, vl);388}389 390// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfclass_v_u32m2_tumu391// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {392// CHECK-RV64-NEXT: entry:393// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfclass.mask.nxv4f32.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x float> [[OP1]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)394// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]395//396vuint32m2_t test_vfclass_v_u32m2_tumu(vbool16_t mask, vuint32m2_t maskedoff, vfloat32m2_t op1, size_t vl) {397 return __riscv_vfclass_v_u32m2_tumu(mask, maskedoff, op1, vl);398}399 400// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfclass_v_u32m4_tumu401// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {402// CHECK-RV64-NEXT: entry:403// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfclass.mask.nxv8f32.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x float> [[OP1]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)404// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]405//406vuint32m4_t test_vfclass_v_u32m4_tumu(vbool8_t mask, vuint32m4_t maskedoff, vfloat32m4_t op1, size_t vl) {407 return __riscv_vfclass_v_u32m4_tumu(mask, maskedoff, op1, vl);408}409 410// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfclass_v_u32m8_tumu411// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {412// CHECK-RV64-NEXT: entry:413// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfclass.mask.nxv16f32.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x float> [[OP1]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)414// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]415//416vuint32m8_t test_vfclass_v_u32m8_tumu(vbool4_t mask, vuint32m8_t maskedoff, vfloat32m8_t op1, size_t vl) {417 return __riscv_vfclass_v_u32m8_tumu(mask, maskedoff, op1, vl);418}419 420// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfclass_v_u64m1_tumu421// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {422// CHECK-RV64-NEXT: entry:423// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfclass.mask.nxv1f64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x double> [[OP1]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)424// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]425//426vuint64m1_t test_vfclass_v_u64m1_tumu(vbool64_t mask, vuint64m1_t maskedoff, vfloat64m1_t op1, size_t vl) {427 return __riscv_vfclass_v_u64m1_tumu(mask, maskedoff, op1, vl);428}429 430// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfclass_v_u64m2_tumu431// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {432// CHECK-RV64-NEXT: entry:433// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfclass.mask.nxv2f64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x double> [[OP1]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)434// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]435//436vuint64m2_t test_vfclass_v_u64m2_tumu(vbool32_t mask, vuint64m2_t maskedoff, vfloat64m2_t op1, size_t vl) {437 return __riscv_vfclass_v_u64m2_tumu(mask, maskedoff, op1, vl);438}439 440// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfclass_v_u64m4_tumu441// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {442// CHECK-RV64-NEXT: entry:443// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfclass.mask.nxv4f64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x double> [[OP1]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)444// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]445//446vuint64m4_t test_vfclass_v_u64m4_tumu(vbool16_t mask, vuint64m4_t maskedoff, vfloat64m4_t op1, size_t vl) {447 return __riscv_vfclass_v_u64m4_tumu(mask, maskedoff, op1, vl);448}449 450// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfclass_v_u64m8_tumu451// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {452// CHECK-RV64-NEXT: entry:453// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfclass.mask.nxv8f64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x double> [[OP1]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)454// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]455//456vuint64m8_t test_vfclass_v_u64m8_tumu(vbool8_t mask, vuint64m8_t maskedoff, vfloat64m8_t op1, size_t vl) {457 return __riscv_vfclass_v_u64m8_tumu(mask, maskedoff, op1, vl);458}459 460// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vfclass_v_u16mf4_mu461// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {462// CHECK-RV64-NEXT: entry:463// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1f16.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x half> [[OP1]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)464// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]465//466vuint16mf4_t test_vfclass_v_u16mf4_mu(vbool64_t mask, vuint16mf4_t maskedoff, vfloat16mf4_t op1, size_t vl) {467 return __riscv_vfclass_v_u16mf4_mu(mask, maskedoff, op1, vl);468}469 470// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vfclass_v_u16mf2_mu471// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {472// CHECK-RV64-NEXT: entry:473// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2f16.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x half> [[OP1]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)474// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]475//476vuint16mf2_t test_vfclass_v_u16mf2_mu(vbool32_t mask, vuint16mf2_t maskedoff, vfloat16mf2_t op1, size_t vl) {477 return __riscv_vfclass_v_u16mf2_mu(mask, maskedoff, op1, vl);478}479 480// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfclass_v_u16m1_mu481// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {482// CHECK-RV64-NEXT: entry:483// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4f16.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x half> [[OP1]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)484// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]485//486vuint16m1_t test_vfclass_v_u16m1_mu(vbool16_t mask, vuint16m1_t maskedoff, vfloat16m1_t op1, size_t vl) {487 return __riscv_vfclass_v_u16m1_mu(mask, maskedoff, op1, vl);488}489 490// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfclass_v_u16m2_mu491// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {492// CHECK-RV64-NEXT: entry:493// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfclass.mask.nxv8f16.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x half> [[OP1]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)494// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]495//496vuint16m2_t test_vfclass_v_u16m2_mu(vbool8_t mask, vuint16m2_t maskedoff, vfloat16m2_t op1, size_t vl) {497 return __riscv_vfclass_v_u16m2_mu(mask, maskedoff, op1, vl);498}499 500// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfclass_v_u16m4_mu501// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {502// CHECK-RV64-NEXT: entry:503// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfclass.mask.nxv16f16.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x half> [[OP1]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)504// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]505//506vuint16m4_t test_vfclass_v_u16m4_mu(vbool4_t mask, vuint16m4_t maskedoff, vfloat16m4_t op1, size_t vl) {507 return __riscv_vfclass_v_u16m4_mu(mask, maskedoff, op1, vl);508}509 510// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vfclass_v_u16m8_mu511// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {512// CHECK-RV64-NEXT: entry:513// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vfclass.mask.nxv32f16.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x half> [[OP1]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1)514// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]515//516vuint16m8_t test_vfclass_v_u16m8_mu(vbool2_t mask, vuint16m8_t maskedoff, vfloat16m8_t op1, size_t vl) {517 return __riscv_vfclass_v_u16m8_mu(mask, maskedoff, op1, vl);518}519 520// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfclass_v_u32mf2_mu521// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {522// CHECK-RV64-NEXT: entry:523// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfclass.mask.nxv1f32.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x float> [[OP1]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)524// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]525//526vuint32mf2_t test_vfclass_v_u32mf2_mu(vbool64_t mask, vuint32mf2_t maskedoff, vfloat32mf2_t op1, size_t vl) {527 return __riscv_vfclass_v_u32mf2_mu(mask, maskedoff, op1, vl);528}529 530// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfclass_v_u32m1_mu531// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {532// CHECK-RV64-NEXT: entry:533// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfclass.mask.nxv2f32.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x float> [[OP1]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)534// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]535//536vuint32m1_t test_vfclass_v_u32m1_mu(vbool32_t mask, vuint32m1_t maskedoff, vfloat32m1_t op1, size_t vl) {537 return __riscv_vfclass_v_u32m1_mu(mask, maskedoff, op1, vl);538}539 540// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfclass_v_u32m2_mu541// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {542// CHECK-RV64-NEXT: entry:543// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfclass.mask.nxv4f32.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x float> [[OP1]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)544// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]545//546vuint32m2_t test_vfclass_v_u32m2_mu(vbool16_t mask, vuint32m2_t maskedoff, vfloat32m2_t op1, size_t vl) {547 return __riscv_vfclass_v_u32m2_mu(mask, maskedoff, op1, vl);548}549 550// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfclass_v_u32m4_mu551// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {552// CHECK-RV64-NEXT: entry:553// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfclass.mask.nxv8f32.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x float> [[OP1]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)554// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]555//556vuint32m4_t test_vfclass_v_u32m4_mu(vbool8_t mask, vuint32m4_t maskedoff, vfloat32m4_t op1, size_t vl) {557 return __riscv_vfclass_v_u32m4_mu(mask, maskedoff, op1, vl);558}559 560// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfclass_v_u32m8_mu561// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {562// CHECK-RV64-NEXT: entry:563// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfclass.mask.nxv16f32.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x float> [[OP1]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)564// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]565//566vuint32m8_t test_vfclass_v_u32m8_mu(vbool4_t mask, vuint32m8_t maskedoff, vfloat32m8_t op1, size_t vl) {567 return __riscv_vfclass_v_u32m8_mu(mask, maskedoff, op1, vl);568}569 570// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfclass_v_u64m1_mu571// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {572// CHECK-RV64-NEXT: entry:573// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfclass.mask.nxv1f64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x double> [[OP1]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)574// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]575//576vuint64m1_t test_vfclass_v_u64m1_mu(vbool64_t mask, vuint64m1_t maskedoff, vfloat64m1_t op1, size_t vl) {577 return __riscv_vfclass_v_u64m1_mu(mask, maskedoff, op1, vl);578}579 580// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfclass_v_u64m2_mu581// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {582// CHECK-RV64-NEXT: entry:583// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfclass.mask.nxv2f64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x double> [[OP1]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)584// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]585//586vuint64m2_t test_vfclass_v_u64m2_mu(vbool32_t mask, vuint64m2_t maskedoff, vfloat64m2_t op1, size_t vl) {587 return __riscv_vfclass_v_u64m2_mu(mask, maskedoff, op1, vl);588}589 590// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfclass_v_u64m4_mu591// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {592// CHECK-RV64-NEXT: entry:593// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfclass.mask.nxv4f64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x double> [[OP1]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)594// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]595//596vuint64m4_t test_vfclass_v_u64m4_mu(vbool16_t mask, vuint64m4_t maskedoff, vfloat64m4_t op1, size_t vl) {597 return __riscv_vfclass_v_u64m4_mu(mask, maskedoff, op1, vl);598}599 600// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfclass_v_u64m8_mu601// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {602// CHECK-RV64-NEXT: entry:603// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfclass.mask.nxv8f64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x double> [[OP1]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)604// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]605//606vuint64m8_t test_vfclass_v_u64m8_mu(vbool8_t mask, vuint64m8_t maskedoff, vfloat64m8_t op1, size_t vl) {607 return __riscv_vfclass_v_u64m8_mu(mask, maskedoff, op1, vl);608}609 610