946 lines · c
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 22// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \4// RUN: -target-feature +zvfhmin -disable-O0-optnone \5// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \6// RUN: FileCheck --check-prefix=CHECK-RV64 %s7 8#include <riscv_vector.h>9 10// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vle16ff_v_f16mf4_tu11// CHECK-RV64-SAME: (<vscale x 1 x half> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {12// CHECK-RV64-NEXT: entry:13// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 1 x half>, i64 } @llvm.riscv.vleff.nxv1f16.i64.p0(<vscale x 1 x half> [[MASKEDOFF]], ptr [[BASE]], i64 [[VL]])14// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x half>, i64 } [[TMP0]], 015// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x half>, i64 } [[TMP0]], 116// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 217// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP1]]18//19vfloat16mf4_t test_vle16ff_v_f16mf4_tu(vfloat16mf4_t maskedoff, const _Float16 *base, size_t *new_vl, size_t vl) {20 return __riscv_vle16ff_v_f16mf4_tu(maskedoff, base, new_vl, vl);21}22 23// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vle16ff_v_f16mf2_tu24// CHECK-RV64-SAME: (<vscale x 2 x half> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {25// CHECK-RV64-NEXT: entry:26// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 2 x half>, i64 } @llvm.riscv.vleff.nxv2f16.i64.p0(<vscale x 2 x half> [[MASKEDOFF]], ptr [[BASE]], i64 [[VL]])27// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 2 x half>, i64 } [[TMP0]], 028// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x half>, i64 } [[TMP0]], 129// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 230// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP1]]31//32vfloat16mf2_t test_vle16ff_v_f16mf2_tu(vfloat16mf2_t maskedoff, const _Float16 *base, size_t *new_vl, size_t vl) {33 return __riscv_vle16ff_v_f16mf2_tu(maskedoff, base, new_vl, vl);34}35 36// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vle16ff_v_f16m1_tu37// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {38// CHECK-RV64-NEXT: entry:39// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 4 x half>, i64 } @llvm.riscv.vleff.nxv4f16.i64.p0(<vscale x 4 x half> [[MASKEDOFF]], ptr [[BASE]], i64 [[VL]])40// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 4 x half>, i64 } [[TMP0]], 041// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x half>, i64 } [[TMP0]], 142// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 243// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP1]]44//45vfloat16m1_t test_vle16ff_v_f16m1_tu(vfloat16m1_t maskedoff, const _Float16 *base, size_t *new_vl, size_t vl) {46 return __riscv_vle16ff_v_f16m1_tu(maskedoff, base, new_vl, vl);47}48 49// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vle16ff_v_f16m2_tu50// CHECK-RV64-SAME: (<vscale x 8 x half> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {51// CHECK-RV64-NEXT: entry:52// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 8 x half>, i64 } @llvm.riscv.vleff.nxv8f16.i64.p0(<vscale x 8 x half> [[MASKEDOFF]], ptr [[BASE]], i64 [[VL]])53// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 8 x half>, i64 } [[TMP0]], 054// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x half>, i64 } [[TMP0]], 155// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 256// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP1]]57//58vfloat16m2_t test_vle16ff_v_f16m2_tu(vfloat16m2_t maskedoff, const _Float16 *base, size_t *new_vl, size_t vl) {59 return __riscv_vle16ff_v_f16m2_tu(maskedoff, base, new_vl, vl);60}61 62// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vle16ff_v_f16m4_tu63// CHECK-RV64-SAME: (<vscale x 16 x half> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {64// CHECK-RV64-NEXT: entry:65// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 16 x half>, i64 } @llvm.riscv.vleff.nxv16f16.i64.p0(<vscale x 16 x half> [[MASKEDOFF]], ptr [[BASE]], i64 [[VL]])66// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 16 x half>, i64 } [[TMP0]], 067// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 16 x half>, i64 } [[TMP0]], 168// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 269// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP1]]70//71vfloat16m4_t test_vle16ff_v_f16m4_tu(vfloat16m4_t maskedoff, const _Float16 *base, size_t *new_vl, size_t vl) {72 return __riscv_vle16ff_v_f16m4_tu(maskedoff, base, new_vl, vl);73}74 75// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vle16ff_v_f16m8_tu76// CHECK-RV64-SAME: (<vscale x 32 x half> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {77// CHECK-RV64-NEXT: entry:78// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 32 x half>, i64 } @llvm.riscv.vleff.nxv32f16.i64.p0(<vscale x 32 x half> [[MASKEDOFF]], ptr [[BASE]], i64 [[VL]])79// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 32 x half>, i64 } [[TMP0]], 080// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 32 x half>, i64 } [[TMP0]], 181// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 282// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP1]]83//84vfloat16m8_t test_vle16ff_v_f16m8_tu(vfloat16m8_t maskedoff, const _Float16 *base, size_t *new_vl, size_t vl) {85 return __riscv_vle16ff_v_f16m8_tu(maskedoff, base, new_vl, vl);86}87 88// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vle16ff_v_i16mf4_tu89// CHECK-RV64-SAME: (<vscale x 1 x i16> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {90// CHECK-RV64-NEXT: entry:91// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.nxv1i16.i64.p0(<vscale x 1 x i16> [[MASKEDOFF]], ptr [[BASE]], i64 [[VL]])92// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i16>, i64 } [[TMP0]], 093// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x i16>, i64 } [[TMP0]], 194// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 295// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]96//97vint16mf4_t test_vle16ff_v_i16mf4_tu(vint16mf4_t maskedoff, const int16_t *base, size_t *new_vl, size_t vl) {98 return __riscv_vle16ff_v_i16mf4_tu(maskedoff, base, new_vl, vl);99}100 101// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vle16ff_v_i16mf2_tu102// CHECK-RV64-SAME: (<vscale x 2 x i16> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {103// CHECK-RV64-NEXT: entry:104// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.nxv2i16.i64.p0(<vscale x 2 x i16> [[MASKEDOFF]], ptr [[BASE]], i64 [[VL]])105// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 2 x i16>, i64 } [[TMP0]], 0106// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x i16>, i64 } [[TMP0]], 1107// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 2108// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]109//110vint16mf2_t test_vle16ff_v_i16mf2_tu(vint16mf2_t maskedoff, const int16_t *base, size_t *new_vl, size_t vl) {111 return __riscv_vle16ff_v_i16mf2_tu(maskedoff, base, new_vl, vl);112}113 114// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vle16ff_v_i16m1_tu115// CHECK-RV64-SAME: (<vscale x 4 x i16> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {116// CHECK-RV64-NEXT: entry:117// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 4 x i16>, i64 } @llvm.riscv.vleff.nxv4i16.i64.p0(<vscale x 4 x i16> [[MASKEDOFF]], ptr [[BASE]], i64 [[VL]])118// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 4 x i16>, i64 } [[TMP0]], 0119// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x i16>, i64 } [[TMP0]], 1120// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 2121// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]122//123vint16m1_t test_vle16ff_v_i16m1_tu(vint16m1_t maskedoff, const int16_t *base, size_t *new_vl, size_t vl) {124 return __riscv_vle16ff_v_i16m1_tu(maskedoff, base, new_vl, vl);125}126 127// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vle16ff_v_i16m2_tu128// CHECK-RV64-SAME: (<vscale x 8 x i16> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {129// CHECK-RV64-NEXT: entry:130// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 8 x i16>, i64 } @llvm.riscv.vleff.nxv8i16.i64.p0(<vscale x 8 x i16> [[MASKEDOFF]], ptr [[BASE]], i64 [[VL]])131// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 8 x i16>, i64 } [[TMP0]], 0132// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x i16>, i64 } [[TMP0]], 1133// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 2134// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]135//136vint16m2_t test_vle16ff_v_i16m2_tu(vint16m2_t maskedoff, const int16_t *base, size_t *new_vl, size_t vl) {137 return __riscv_vle16ff_v_i16m2_tu(maskedoff, base, new_vl, vl);138}139 140// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vle16ff_v_i16m4_tu141// CHECK-RV64-SAME: (<vscale x 16 x i16> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {142// CHECK-RV64-NEXT: entry:143// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 16 x i16>, i64 } @llvm.riscv.vleff.nxv16i16.i64.p0(<vscale x 16 x i16> [[MASKEDOFF]], ptr [[BASE]], i64 [[VL]])144// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 16 x i16>, i64 } [[TMP0]], 0145// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 16 x i16>, i64 } [[TMP0]], 1146// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 2147// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]148//149vint16m4_t test_vle16ff_v_i16m4_tu(vint16m4_t maskedoff, const int16_t *base, size_t *new_vl, size_t vl) {150 return __riscv_vle16ff_v_i16m4_tu(maskedoff, base, new_vl, vl);151}152 153// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vle16ff_v_i16m8_tu154// CHECK-RV64-SAME: (<vscale x 32 x i16> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {155// CHECK-RV64-NEXT: entry:156// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 32 x i16>, i64 } @llvm.riscv.vleff.nxv32i16.i64.p0(<vscale x 32 x i16> [[MASKEDOFF]], ptr [[BASE]], i64 [[VL]])157// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 32 x i16>, i64 } [[TMP0]], 0158// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 32 x i16>, i64 } [[TMP0]], 1159// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 2160// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]]161//162vint16m8_t test_vle16ff_v_i16m8_tu(vint16m8_t maskedoff, const int16_t *base, size_t *new_vl, size_t vl) {163 return __riscv_vle16ff_v_i16m8_tu(maskedoff, base, new_vl, vl);164}165 166// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vle16ff_v_u16mf4_tu167// CHECK-RV64-SAME: (<vscale x 1 x i16> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {168// CHECK-RV64-NEXT: entry:169// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.nxv1i16.i64.p0(<vscale x 1 x i16> [[MASKEDOFF]], ptr [[BASE]], i64 [[VL]])170// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i16>, i64 } [[TMP0]], 0171// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x i16>, i64 } [[TMP0]], 1172// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 2173// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]174//175vuint16mf4_t test_vle16ff_v_u16mf4_tu(vuint16mf4_t maskedoff, const uint16_t *base, size_t *new_vl, size_t vl) {176 return __riscv_vle16ff_v_u16mf4_tu(maskedoff, base, new_vl, vl);177}178 179// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vle16ff_v_u16mf2_tu180// CHECK-RV64-SAME: (<vscale x 2 x i16> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {181// CHECK-RV64-NEXT: entry:182// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.nxv2i16.i64.p0(<vscale x 2 x i16> [[MASKEDOFF]], ptr [[BASE]], i64 [[VL]])183// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 2 x i16>, i64 } [[TMP0]], 0184// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x i16>, i64 } [[TMP0]], 1185// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 2186// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]187//188vuint16mf2_t test_vle16ff_v_u16mf2_tu(vuint16mf2_t maskedoff, const uint16_t *base, size_t *new_vl, size_t vl) {189 return __riscv_vle16ff_v_u16mf2_tu(maskedoff, base, new_vl, vl);190}191 192// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vle16ff_v_u16m1_tu193// CHECK-RV64-SAME: (<vscale x 4 x i16> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {194// CHECK-RV64-NEXT: entry:195// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 4 x i16>, i64 } @llvm.riscv.vleff.nxv4i16.i64.p0(<vscale x 4 x i16> [[MASKEDOFF]], ptr [[BASE]], i64 [[VL]])196// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 4 x i16>, i64 } [[TMP0]], 0197// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x i16>, i64 } [[TMP0]], 1198// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 2199// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]200//201vuint16m1_t test_vle16ff_v_u16m1_tu(vuint16m1_t maskedoff, const uint16_t *base, size_t *new_vl, size_t vl) {202 return __riscv_vle16ff_v_u16m1_tu(maskedoff, base, new_vl, vl);203}204 205// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vle16ff_v_u16m2_tu206// CHECK-RV64-SAME: (<vscale x 8 x i16> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {207// CHECK-RV64-NEXT: entry:208// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 8 x i16>, i64 } @llvm.riscv.vleff.nxv8i16.i64.p0(<vscale x 8 x i16> [[MASKEDOFF]], ptr [[BASE]], i64 [[VL]])209// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 8 x i16>, i64 } [[TMP0]], 0210// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x i16>, i64 } [[TMP0]], 1211// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 2212// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]213//214vuint16m2_t test_vle16ff_v_u16m2_tu(vuint16m2_t maskedoff, const uint16_t *base, size_t *new_vl, size_t vl) {215 return __riscv_vle16ff_v_u16m2_tu(maskedoff, base, new_vl, vl);216}217 218// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vle16ff_v_u16m4_tu219// CHECK-RV64-SAME: (<vscale x 16 x i16> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {220// CHECK-RV64-NEXT: entry:221// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 16 x i16>, i64 } @llvm.riscv.vleff.nxv16i16.i64.p0(<vscale x 16 x i16> [[MASKEDOFF]], ptr [[BASE]], i64 [[VL]])222// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 16 x i16>, i64 } [[TMP0]], 0223// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 16 x i16>, i64 } [[TMP0]], 1224// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 2225// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]226//227vuint16m4_t test_vle16ff_v_u16m4_tu(vuint16m4_t maskedoff, const uint16_t *base, size_t *new_vl, size_t vl) {228 return __riscv_vle16ff_v_u16m4_tu(maskedoff, base, new_vl, vl);229}230 231// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vle16ff_v_u16m8_tu232// CHECK-RV64-SAME: (<vscale x 32 x i16> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {233// CHECK-RV64-NEXT: entry:234// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 32 x i16>, i64 } @llvm.riscv.vleff.nxv32i16.i64.p0(<vscale x 32 x i16> [[MASKEDOFF]], ptr [[BASE]], i64 [[VL]])235// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 32 x i16>, i64 } [[TMP0]], 0236// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 32 x i16>, i64 } [[TMP0]], 1237// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 2238// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]]239//240vuint16m8_t test_vle16ff_v_u16m8_tu(vuint16m8_t maskedoff, const uint16_t *base, size_t *new_vl, size_t vl) {241 return __riscv_vle16ff_v_u16m8_tu(maskedoff, base, new_vl, vl);242}243 244// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vle16ff_v_f16mf4_tum245// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {246// CHECK-RV64-NEXT: entry:247// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 1 x half>, i64 } @llvm.riscv.vleff.mask.nxv1f16.i64.p0(<vscale x 1 x half> [[MASKEDOFF]], ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)248// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x half>, i64 } [[TMP0]], 0249// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x half>, i64 } [[TMP0]], 1250// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8251// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP1]]252//253vfloat16mf4_t test_vle16ff_v_f16mf4_tum(vbool64_t mask, vfloat16mf4_t maskedoff, const _Float16 *base, size_t *new_vl, size_t vl) {254 return __riscv_vle16ff_v_f16mf4_tum(mask, maskedoff, base, new_vl, vl);255}256 257// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vle16ff_v_f16mf2_tum258// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {259// CHECK-RV64-NEXT: entry:260// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 2 x half>, i64 } @llvm.riscv.vleff.mask.nxv2f16.i64.p0(<vscale x 2 x half> [[MASKEDOFF]], ptr [[BASE]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)261// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 2 x half>, i64 } [[TMP0]], 0262// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x half>, i64 } [[TMP0]], 1263// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8264// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP1]]265//266vfloat16mf2_t test_vle16ff_v_f16mf2_tum(vbool32_t mask, vfloat16mf2_t maskedoff, const _Float16 *base, size_t *new_vl, size_t vl) {267 return __riscv_vle16ff_v_f16mf2_tum(mask, maskedoff, base, new_vl, vl);268}269 270// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vle16ff_v_f16m1_tum271// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {272// CHECK-RV64-NEXT: entry:273// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 4 x half>, i64 } @llvm.riscv.vleff.mask.nxv4f16.i64.p0(<vscale x 4 x half> [[MASKEDOFF]], ptr [[BASE]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)274// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 4 x half>, i64 } [[TMP0]], 0275// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x half>, i64 } [[TMP0]], 1276// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8277// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP1]]278//279vfloat16m1_t test_vle16ff_v_f16m1_tum(vbool16_t mask, vfloat16m1_t maskedoff, const _Float16 *base, size_t *new_vl, size_t vl) {280 return __riscv_vle16ff_v_f16m1_tum(mask, maskedoff, base, new_vl, vl);281}282 283// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vle16ff_v_f16m2_tum284// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {285// CHECK-RV64-NEXT: entry:286// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 8 x half>, i64 } @llvm.riscv.vleff.mask.nxv8f16.i64.p0(<vscale x 8 x half> [[MASKEDOFF]], ptr [[BASE]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)287// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 8 x half>, i64 } [[TMP0]], 0288// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x half>, i64 } [[TMP0]], 1289// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8290// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP1]]291//292vfloat16m2_t test_vle16ff_v_f16m2_tum(vbool8_t mask, vfloat16m2_t maskedoff, const _Float16 *base, size_t *new_vl, size_t vl) {293 return __riscv_vle16ff_v_f16m2_tum(mask, maskedoff, base, new_vl, vl);294}295 296// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vle16ff_v_f16m4_tum297// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {298// CHECK-RV64-NEXT: entry:299// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 16 x half>, i64 } @llvm.riscv.vleff.mask.nxv16f16.i64.p0(<vscale x 16 x half> [[MASKEDOFF]], ptr [[BASE]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)300// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 16 x half>, i64 } [[TMP0]], 0301// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 16 x half>, i64 } [[TMP0]], 1302// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8303// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP1]]304//305vfloat16m4_t test_vle16ff_v_f16m4_tum(vbool4_t mask, vfloat16m4_t maskedoff, const _Float16 *base, size_t *new_vl, size_t vl) {306 return __riscv_vle16ff_v_f16m4_tum(mask, maskedoff, base, new_vl, vl);307}308 309// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vle16ff_v_f16m8_tum310// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {311// CHECK-RV64-NEXT: entry:312// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 32 x half>, i64 } @llvm.riscv.vleff.mask.nxv32f16.i64.p0(<vscale x 32 x half> [[MASKEDOFF]], ptr [[BASE]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2)313// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 32 x half>, i64 } [[TMP0]], 0314// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 32 x half>, i64 } [[TMP0]], 1315// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8316// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP1]]317//318vfloat16m8_t test_vle16ff_v_f16m8_tum(vbool2_t mask, vfloat16m8_t maskedoff, const _Float16 *base, size_t *new_vl, size_t vl) {319 return __riscv_vle16ff_v_f16m8_tum(mask, maskedoff, base, new_vl, vl);320}321 322// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vle16ff_v_i16mf4_tum323// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {324// CHECK-RV64-NEXT: entry:325// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.mask.nxv1i16.i64.p0(<vscale x 1 x i16> [[MASKEDOFF]], ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)326// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i16>, i64 } [[TMP0]], 0327// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x i16>, i64 } [[TMP0]], 1328// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8329// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]330//331vint16mf4_t test_vle16ff_v_i16mf4_tum(vbool64_t mask, vint16mf4_t maskedoff, const int16_t *base, size_t *new_vl, size_t vl) {332 return __riscv_vle16ff_v_i16mf4_tum(mask, maskedoff, base, new_vl, vl);333}334 335// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vle16ff_v_i16mf2_tum336// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {337// CHECK-RV64-NEXT: entry:338// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.mask.nxv2i16.i64.p0(<vscale x 2 x i16> [[MASKEDOFF]], ptr [[BASE]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)339// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 2 x i16>, i64 } [[TMP0]], 0340// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x i16>, i64 } [[TMP0]], 1341// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8342// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]343//344vint16mf2_t test_vle16ff_v_i16mf2_tum(vbool32_t mask, vint16mf2_t maskedoff, const int16_t *base, size_t *new_vl, size_t vl) {345 return __riscv_vle16ff_v_i16mf2_tum(mask, maskedoff, base, new_vl, vl);346}347 348// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vle16ff_v_i16m1_tum349// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {350// CHECK-RV64-NEXT: entry:351// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 4 x i16>, i64 } @llvm.riscv.vleff.mask.nxv4i16.i64.p0(<vscale x 4 x i16> [[MASKEDOFF]], ptr [[BASE]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)352// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 4 x i16>, i64 } [[TMP0]], 0353// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x i16>, i64 } [[TMP0]], 1354// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8355// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]356//357vint16m1_t test_vle16ff_v_i16m1_tum(vbool16_t mask, vint16m1_t maskedoff, const int16_t *base, size_t *new_vl, size_t vl) {358 return __riscv_vle16ff_v_i16m1_tum(mask, maskedoff, base, new_vl, vl);359}360 361// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vle16ff_v_i16m2_tum362// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {363// CHECK-RV64-NEXT: entry:364// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 8 x i16>, i64 } @llvm.riscv.vleff.mask.nxv8i16.i64.p0(<vscale x 8 x i16> [[MASKEDOFF]], ptr [[BASE]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)365// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 8 x i16>, i64 } [[TMP0]], 0366// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x i16>, i64 } [[TMP0]], 1367// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8368// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]369//370vint16m2_t test_vle16ff_v_i16m2_tum(vbool8_t mask, vint16m2_t maskedoff, const int16_t *base, size_t *new_vl, size_t vl) {371 return __riscv_vle16ff_v_i16m2_tum(mask, maskedoff, base, new_vl, vl);372}373 374// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vle16ff_v_i16m4_tum375// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {376// CHECK-RV64-NEXT: entry:377// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 16 x i16>, i64 } @llvm.riscv.vleff.mask.nxv16i16.i64.p0(<vscale x 16 x i16> [[MASKEDOFF]], ptr [[BASE]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)378// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 16 x i16>, i64 } [[TMP0]], 0379// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 16 x i16>, i64 } [[TMP0]], 1380// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8381// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]382//383vint16m4_t test_vle16ff_v_i16m4_tum(vbool4_t mask, vint16m4_t maskedoff, const int16_t *base, size_t *new_vl, size_t vl) {384 return __riscv_vle16ff_v_i16m4_tum(mask, maskedoff, base, new_vl, vl);385}386 387// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vle16ff_v_i16m8_tum388// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {389// CHECK-RV64-NEXT: entry:390// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 32 x i16>, i64 } @llvm.riscv.vleff.mask.nxv32i16.i64.p0(<vscale x 32 x i16> [[MASKEDOFF]], ptr [[BASE]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2)391// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 32 x i16>, i64 } [[TMP0]], 0392// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 32 x i16>, i64 } [[TMP0]], 1393// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8394// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]]395//396vint16m8_t test_vle16ff_v_i16m8_tum(vbool2_t mask, vint16m8_t maskedoff, const int16_t *base, size_t *new_vl, size_t vl) {397 return __riscv_vle16ff_v_i16m8_tum(mask, maskedoff, base, new_vl, vl);398}399 400// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vle16ff_v_u16mf4_tum401// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {402// CHECK-RV64-NEXT: entry:403// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.mask.nxv1i16.i64.p0(<vscale x 1 x i16> [[MASKEDOFF]], ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)404// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i16>, i64 } [[TMP0]], 0405// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x i16>, i64 } [[TMP0]], 1406// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8407// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]408//409vuint16mf4_t test_vle16ff_v_u16mf4_tum(vbool64_t mask, vuint16mf4_t maskedoff, const uint16_t *base, size_t *new_vl, size_t vl) {410 return __riscv_vle16ff_v_u16mf4_tum(mask, maskedoff, base, new_vl, vl);411}412 413// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vle16ff_v_u16mf2_tum414// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {415// CHECK-RV64-NEXT: entry:416// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.mask.nxv2i16.i64.p0(<vscale x 2 x i16> [[MASKEDOFF]], ptr [[BASE]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)417// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 2 x i16>, i64 } [[TMP0]], 0418// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x i16>, i64 } [[TMP0]], 1419// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8420// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]421//422vuint16mf2_t test_vle16ff_v_u16mf2_tum(vbool32_t mask, vuint16mf2_t maskedoff, const uint16_t *base, size_t *new_vl, size_t vl) {423 return __riscv_vle16ff_v_u16mf2_tum(mask, maskedoff, base, new_vl, vl);424}425 426// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vle16ff_v_u16m1_tum427// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {428// CHECK-RV64-NEXT: entry:429// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 4 x i16>, i64 } @llvm.riscv.vleff.mask.nxv4i16.i64.p0(<vscale x 4 x i16> [[MASKEDOFF]], ptr [[BASE]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)430// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 4 x i16>, i64 } [[TMP0]], 0431// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x i16>, i64 } [[TMP0]], 1432// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8433// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]434//435vuint16m1_t test_vle16ff_v_u16m1_tum(vbool16_t mask, vuint16m1_t maskedoff, const uint16_t *base, size_t *new_vl, size_t vl) {436 return __riscv_vle16ff_v_u16m1_tum(mask, maskedoff, base, new_vl, vl);437}438 439// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vle16ff_v_u16m2_tum440// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {441// CHECK-RV64-NEXT: entry:442// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 8 x i16>, i64 } @llvm.riscv.vleff.mask.nxv8i16.i64.p0(<vscale x 8 x i16> [[MASKEDOFF]], ptr [[BASE]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)443// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 8 x i16>, i64 } [[TMP0]], 0444// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x i16>, i64 } [[TMP0]], 1445// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8446// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]447//448vuint16m2_t test_vle16ff_v_u16m2_tum(vbool8_t mask, vuint16m2_t maskedoff, const uint16_t *base, size_t *new_vl, size_t vl) {449 return __riscv_vle16ff_v_u16m2_tum(mask, maskedoff, base, new_vl, vl);450}451 452// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vle16ff_v_u16m4_tum453// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {454// CHECK-RV64-NEXT: entry:455// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 16 x i16>, i64 } @llvm.riscv.vleff.mask.nxv16i16.i64.p0(<vscale x 16 x i16> [[MASKEDOFF]], ptr [[BASE]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)456// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 16 x i16>, i64 } [[TMP0]], 0457// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 16 x i16>, i64 } [[TMP0]], 1458// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8459// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]460//461vuint16m4_t test_vle16ff_v_u16m4_tum(vbool4_t mask, vuint16m4_t maskedoff, const uint16_t *base, size_t *new_vl, size_t vl) {462 return __riscv_vle16ff_v_u16m4_tum(mask, maskedoff, base, new_vl, vl);463}464 465// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vle16ff_v_u16m8_tum466// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {467// CHECK-RV64-NEXT: entry:468// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 32 x i16>, i64 } @llvm.riscv.vleff.mask.nxv32i16.i64.p0(<vscale x 32 x i16> [[MASKEDOFF]], ptr [[BASE]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2)469// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 32 x i16>, i64 } [[TMP0]], 0470// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 32 x i16>, i64 } [[TMP0]], 1471// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8472// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]]473//474vuint16m8_t test_vle16ff_v_u16m8_tum(vbool2_t mask, vuint16m8_t maskedoff, const uint16_t *base, size_t *new_vl, size_t vl) {475 return __riscv_vle16ff_v_u16m8_tum(mask, maskedoff, base, new_vl, vl);476}477 478// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vle16ff_v_f16mf4_tumu479// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {480// CHECK-RV64-NEXT: entry:481// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 1 x half>, i64 } @llvm.riscv.vleff.mask.nxv1f16.i64.p0(<vscale x 1 x half> [[MASKEDOFF]], ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)482// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x half>, i64 } [[TMP0]], 0483// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x half>, i64 } [[TMP0]], 1484// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8485// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP1]]486//487vfloat16mf4_t test_vle16ff_v_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t maskedoff, const _Float16 *base, size_t *new_vl, size_t vl) {488 return __riscv_vle16ff_v_f16mf4_tumu(mask, maskedoff, base, new_vl, vl);489}490 491// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vle16ff_v_f16mf2_tumu492// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {493// CHECK-RV64-NEXT: entry:494// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 2 x half>, i64 } @llvm.riscv.vleff.mask.nxv2f16.i64.p0(<vscale x 2 x half> [[MASKEDOFF]], ptr [[BASE]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)495// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 2 x half>, i64 } [[TMP0]], 0496// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x half>, i64 } [[TMP0]], 1497// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8498// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP1]]499//500vfloat16mf2_t test_vle16ff_v_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t maskedoff, const _Float16 *base, size_t *new_vl, size_t vl) {501 return __riscv_vle16ff_v_f16mf2_tumu(mask, maskedoff, base, new_vl, vl);502}503 504// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vle16ff_v_f16m1_tumu505// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {506// CHECK-RV64-NEXT: entry:507// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 4 x half>, i64 } @llvm.riscv.vleff.mask.nxv4f16.i64.p0(<vscale x 4 x half> [[MASKEDOFF]], ptr [[BASE]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)508// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 4 x half>, i64 } [[TMP0]], 0509// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x half>, i64 } [[TMP0]], 1510// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8511// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP1]]512//513vfloat16m1_t test_vle16ff_v_f16m1_tumu(vbool16_t mask, vfloat16m1_t maskedoff, const _Float16 *base, size_t *new_vl, size_t vl) {514 return __riscv_vle16ff_v_f16m1_tumu(mask, maskedoff, base, new_vl, vl);515}516 517// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vle16ff_v_f16m2_tumu518// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {519// CHECK-RV64-NEXT: entry:520// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 8 x half>, i64 } @llvm.riscv.vleff.mask.nxv8f16.i64.p0(<vscale x 8 x half> [[MASKEDOFF]], ptr [[BASE]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)521// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 8 x half>, i64 } [[TMP0]], 0522// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x half>, i64 } [[TMP0]], 1523// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8524// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP1]]525//526vfloat16m2_t test_vle16ff_v_f16m2_tumu(vbool8_t mask, vfloat16m2_t maskedoff, const _Float16 *base, size_t *new_vl, size_t vl) {527 return __riscv_vle16ff_v_f16m2_tumu(mask, maskedoff, base, new_vl, vl);528}529 530// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vle16ff_v_f16m4_tumu531// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {532// CHECK-RV64-NEXT: entry:533// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 16 x half>, i64 } @llvm.riscv.vleff.mask.nxv16f16.i64.p0(<vscale x 16 x half> [[MASKEDOFF]], ptr [[BASE]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)534// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 16 x half>, i64 } [[TMP0]], 0535// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 16 x half>, i64 } [[TMP0]], 1536// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8537// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP1]]538//539vfloat16m4_t test_vle16ff_v_f16m4_tumu(vbool4_t mask, vfloat16m4_t maskedoff, const _Float16 *base, size_t *new_vl, size_t vl) {540 return __riscv_vle16ff_v_f16m4_tumu(mask, maskedoff, base, new_vl, vl);541}542 543// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vle16ff_v_f16m8_tumu544// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {545// CHECK-RV64-NEXT: entry:546// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 32 x half>, i64 } @llvm.riscv.vleff.mask.nxv32f16.i64.p0(<vscale x 32 x half> [[MASKEDOFF]], ptr [[BASE]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0)547// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 32 x half>, i64 } [[TMP0]], 0548// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 32 x half>, i64 } [[TMP0]], 1549// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8550// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP1]]551//552vfloat16m8_t test_vle16ff_v_f16m8_tumu(vbool2_t mask, vfloat16m8_t maskedoff, const _Float16 *base, size_t *new_vl, size_t vl) {553 return __riscv_vle16ff_v_f16m8_tumu(mask, maskedoff, base, new_vl, vl);554}555 556// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vle16ff_v_i16mf4_tumu557// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {558// CHECK-RV64-NEXT: entry:559// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.mask.nxv1i16.i64.p0(<vscale x 1 x i16> [[MASKEDOFF]], ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)560// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i16>, i64 } [[TMP0]], 0561// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x i16>, i64 } [[TMP0]], 1562// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8563// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]564//565vint16mf4_t test_vle16ff_v_i16mf4_tumu(vbool64_t mask, vint16mf4_t maskedoff, const int16_t *base, size_t *new_vl, size_t vl) {566 return __riscv_vle16ff_v_i16mf4_tumu(mask, maskedoff, base, new_vl, vl);567}568 569// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vle16ff_v_i16mf2_tumu570// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {571// CHECK-RV64-NEXT: entry:572// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.mask.nxv2i16.i64.p0(<vscale x 2 x i16> [[MASKEDOFF]], ptr [[BASE]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)573// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 2 x i16>, i64 } [[TMP0]], 0574// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x i16>, i64 } [[TMP0]], 1575// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8576// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]577//578vint16mf2_t test_vle16ff_v_i16mf2_tumu(vbool32_t mask, vint16mf2_t maskedoff, const int16_t *base, size_t *new_vl, size_t vl) {579 return __riscv_vle16ff_v_i16mf2_tumu(mask, maskedoff, base, new_vl, vl);580}581 582// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vle16ff_v_i16m1_tumu583// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {584// CHECK-RV64-NEXT: entry:585// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 4 x i16>, i64 } @llvm.riscv.vleff.mask.nxv4i16.i64.p0(<vscale x 4 x i16> [[MASKEDOFF]], ptr [[BASE]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)586// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 4 x i16>, i64 } [[TMP0]], 0587// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x i16>, i64 } [[TMP0]], 1588// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8589// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]590//591vint16m1_t test_vle16ff_v_i16m1_tumu(vbool16_t mask, vint16m1_t maskedoff, const int16_t *base, size_t *new_vl, size_t vl) {592 return __riscv_vle16ff_v_i16m1_tumu(mask, maskedoff, base, new_vl, vl);593}594 595// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vle16ff_v_i16m2_tumu596// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {597// CHECK-RV64-NEXT: entry:598// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 8 x i16>, i64 } @llvm.riscv.vleff.mask.nxv8i16.i64.p0(<vscale x 8 x i16> [[MASKEDOFF]], ptr [[BASE]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)599// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 8 x i16>, i64 } [[TMP0]], 0600// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x i16>, i64 } [[TMP0]], 1601// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8602// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]603//604vint16m2_t test_vle16ff_v_i16m2_tumu(vbool8_t mask, vint16m2_t maskedoff, const int16_t *base, size_t *new_vl, size_t vl) {605 return __riscv_vle16ff_v_i16m2_tumu(mask, maskedoff, base, new_vl, vl);606}607 608// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vle16ff_v_i16m4_tumu609// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {610// CHECK-RV64-NEXT: entry:611// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 16 x i16>, i64 } @llvm.riscv.vleff.mask.nxv16i16.i64.p0(<vscale x 16 x i16> [[MASKEDOFF]], ptr [[BASE]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)612// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 16 x i16>, i64 } [[TMP0]], 0613// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 16 x i16>, i64 } [[TMP0]], 1614// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8615// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]616//617vint16m4_t test_vle16ff_v_i16m4_tumu(vbool4_t mask, vint16m4_t maskedoff, const int16_t *base, size_t *new_vl, size_t vl) {618 return __riscv_vle16ff_v_i16m4_tumu(mask, maskedoff, base, new_vl, vl);619}620 621// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vle16ff_v_i16m8_tumu622// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {623// CHECK-RV64-NEXT: entry:624// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 32 x i16>, i64 } @llvm.riscv.vleff.mask.nxv32i16.i64.p0(<vscale x 32 x i16> [[MASKEDOFF]], ptr [[BASE]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0)625// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 32 x i16>, i64 } [[TMP0]], 0626// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 32 x i16>, i64 } [[TMP0]], 1627// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8628// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]]629//630vint16m8_t test_vle16ff_v_i16m8_tumu(vbool2_t mask, vint16m8_t maskedoff, const int16_t *base, size_t *new_vl, size_t vl) {631 return __riscv_vle16ff_v_i16m8_tumu(mask, maskedoff, base, new_vl, vl);632}633 634// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vle16ff_v_u16mf4_tumu635// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {636// CHECK-RV64-NEXT: entry:637// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.mask.nxv1i16.i64.p0(<vscale x 1 x i16> [[MASKEDOFF]], ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)638// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i16>, i64 } [[TMP0]], 0639// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x i16>, i64 } [[TMP0]], 1640// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8641// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]642//643vuint16mf4_t test_vle16ff_v_u16mf4_tumu(vbool64_t mask, vuint16mf4_t maskedoff, const uint16_t *base, size_t *new_vl, size_t vl) {644 return __riscv_vle16ff_v_u16mf4_tumu(mask, maskedoff, base, new_vl, vl);645}646 647// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vle16ff_v_u16mf2_tumu648// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {649// CHECK-RV64-NEXT: entry:650// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.mask.nxv2i16.i64.p0(<vscale x 2 x i16> [[MASKEDOFF]], ptr [[BASE]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)651// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 2 x i16>, i64 } [[TMP0]], 0652// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x i16>, i64 } [[TMP0]], 1653// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8654// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]655//656vuint16mf2_t test_vle16ff_v_u16mf2_tumu(vbool32_t mask, vuint16mf2_t maskedoff, const uint16_t *base, size_t *new_vl, size_t vl) {657 return __riscv_vle16ff_v_u16mf2_tumu(mask, maskedoff, base, new_vl, vl);658}659 660// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vle16ff_v_u16m1_tumu661// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {662// CHECK-RV64-NEXT: entry:663// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 4 x i16>, i64 } @llvm.riscv.vleff.mask.nxv4i16.i64.p0(<vscale x 4 x i16> [[MASKEDOFF]], ptr [[BASE]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)664// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 4 x i16>, i64 } [[TMP0]], 0665// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x i16>, i64 } [[TMP0]], 1666// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8667// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]668//669vuint16m1_t test_vle16ff_v_u16m1_tumu(vbool16_t mask, vuint16m1_t maskedoff, const uint16_t *base, size_t *new_vl, size_t vl) {670 return __riscv_vle16ff_v_u16m1_tumu(mask, maskedoff, base, new_vl, vl);671}672 673// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vle16ff_v_u16m2_tumu674// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {675// CHECK-RV64-NEXT: entry:676// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 8 x i16>, i64 } @llvm.riscv.vleff.mask.nxv8i16.i64.p0(<vscale x 8 x i16> [[MASKEDOFF]], ptr [[BASE]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)677// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 8 x i16>, i64 } [[TMP0]], 0678// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x i16>, i64 } [[TMP0]], 1679// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8680// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]681//682vuint16m2_t test_vle16ff_v_u16m2_tumu(vbool8_t mask, vuint16m2_t maskedoff, const uint16_t *base, size_t *new_vl, size_t vl) {683 return __riscv_vle16ff_v_u16m2_tumu(mask, maskedoff, base, new_vl, vl);684}685 686// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vle16ff_v_u16m4_tumu687// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {688// CHECK-RV64-NEXT: entry:689// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 16 x i16>, i64 } @llvm.riscv.vleff.mask.nxv16i16.i64.p0(<vscale x 16 x i16> [[MASKEDOFF]], ptr [[BASE]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)690// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 16 x i16>, i64 } [[TMP0]], 0691// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 16 x i16>, i64 } [[TMP0]], 1692// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8693// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]694//695vuint16m4_t test_vle16ff_v_u16m4_tumu(vbool4_t mask, vuint16m4_t maskedoff, const uint16_t *base, size_t *new_vl, size_t vl) {696 return __riscv_vle16ff_v_u16m4_tumu(mask, maskedoff, base, new_vl, vl);697}698 699// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vle16ff_v_u16m8_tumu700// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {701// CHECK-RV64-NEXT: entry:702// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 32 x i16>, i64 } @llvm.riscv.vleff.mask.nxv32i16.i64.p0(<vscale x 32 x i16> [[MASKEDOFF]], ptr [[BASE]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0)703// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 32 x i16>, i64 } [[TMP0]], 0704// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 32 x i16>, i64 } [[TMP0]], 1705// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8706// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]]707//708vuint16m8_t test_vle16ff_v_u16m8_tumu(vbool2_t mask, vuint16m8_t maskedoff, const uint16_t *base, size_t *new_vl, size_t vl) {709 return __riscv_vle16ff_v_u16m8_tumu(mask, maskedoff, base, new_vl, vl);710}711 712// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vle16ff_v_f16mf4_mu713// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {714// CHECK-RV64-NEXT: entry:715// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 1 x half>, i64 } @llvm.riscv.vleff.mask.nxv1f16.i64.p0(<vscale x 1 x half> [[MASKEDOFF]], ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)716// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x half>, i64 } [[TMP0]], 0717// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x half>, i64 } [[TMP0]], 1718// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8719// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP1]]720//721vfloat16mf4_t test_vle16ff_v_f16mf4_mu(vbool64_t mask, vfloat16mf4_t maskedoff, const _Float16 *base, size_t *new_vl, size_t vl) {722 return __riscv_vle16ff_v_f16mf4_mu(mask, maskedoff, base, new_vl, vl);723}724 725// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vle16ff_v_f16mf2_mu726// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {727// CHECK-RV64-NEXT: entry:728// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 2 x half>, i64 } @llvm.riscv.vleff.mask.nxv2f16.i64.p0(<vscale x 2 x half> [[MASKEDOFF]], ptr [[BASE]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)729// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 2 x half>, i64 } [[TMP0]], 0730// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x half>, i64 } [[TMP0]], 1731// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8732// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP1]]733//734vfloat16mf2_t test_vle16ff_v_f16mf2_mu(vbool32_t mask, vfloat16mf2_t maskedoff, const _Float16 *base, size_t *new_vl, size_t vl) {735 return __riscv_vle16ff_v_f16mf2_mu(mask, maskedoff, base, new_vl, vl);736}737 738// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vle16ff_v_f16m1_mu739// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {740// CHECK-RV64-NEXT: entry:741// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 4 x half>, i64 } @llvm.riscv.vleff.mask.nxv4f16.i64.p0(<vscale x 4 x half> [[MASKEDOFF]], ptr [[BASE]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)742// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 4 x half>, i64 } [[TMP0]], 0743// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x half>, i64 } [[TMP0]], 1744// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8745// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP1]]746//747vfloat16m1_t test_vle16ff_v_f16m1_mu(vbool16_t mask, vfloat16m1_t maskedoff, const _Float16 *base, size_t *new_vl, size_t vl) {748 return __riscv_vle16ff_v_f16m1_mu(mask, maskedoff, base, new_vl, vl);749}750 751// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vle16ff_v_f16m2_mu752// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {753// CHECK-RV64-NEXT: entry:754// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 8 x half>, i64 } @llvm.riscv.vleff.mask.nxv8f16.i64.p0(<vscale x 8 x half> [[MASKEDOFF]], ptr [[BASE]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)755// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 8 x half>, i64 } [[TMP0]], 0756// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x half>, i64 } [[TMP0]], 1757// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8758// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP1]]759//760vfloat16m2_t test_vle16ff_v_f16m2_mu(vbool8_t mask, vfloat16m2_t maskedoff, const _Float16 *base, size_t *new_vl, size_t vl) {761 return __riscv_vle16ff_v_f16m2_mu(mask, maskedoff, base, new_vl, vl);762}763 764// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vle16ff_v_f16m4_mu765// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {766// CHECK-RV64-NEXT: entry:767// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 16 x half>, i64 } @llvm.riscv.vleff.mask.nxv16f16.i64.p0(<vscale x 16 x half> [[MASKEDOFF]], ptr [[BASE]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)768// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 16 x half>, i64 } [[TMP0]], 0769// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 16 x half>, i64 } [[TMP0]], 1770// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8771// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP1]]772//773vfloat16m4_t test_vle16ff_v_f16m4_mu(vbool4_t mask, vfloat16m4_t maskedoff, const _Float16 *base, size_t *new_vl, size_t vl) {774 return __riscv_vle16ff_v_f16m4_mu(mask, maskedoff, base, new_vl, vl);775}776 777// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vle16ff_v_f16m8_mu778// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {779// CHECK-RV64-NEXT: entry:780// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 32 x half>, i64 } @llvm.riscv.vleff.mask.nxv32f16.i64.p0(<vscale x 32 x half> [[MASKEDOFF]], ptr [[BASE]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1)781// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 32 x half>, i64 } [[TMP0]], 0782// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 32 x half>, i64 } [[TMP0]], 1783// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8784// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP1]]785//786vfloat16m8_t test_vle16ff_v_f16m8_mu(vbool2_t mask, vfloat16m8_t maskedoff, const _Float16 *base, size_t *new_vl, size_t vl) {787 return __riscv_vle16ff_v_f16m8_mu(mask, maskedoff, base, new_vl, vl);788}789 790// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vle16ff_v_i16mf4_mu791// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {792// CHECK-RV64-NEXT: entry:793// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.mask.nxv1i16.i64.p0(<vscale x 1 x i16> [[MASKEDOFF]], ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)794// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i16>, i64 } [[TMP0]], 0795// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x i16>, i64 } [[TMP0]], 1796// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8797// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]798//799vint16mf4_t test_vle16ff_v_i16mf4_mu(vbool64_t mask, vint16mf4_t maskedoff, const int16_t *base, size_t *new_vl, size_t vl) {800 return __riscv_vle16ff_v_i16mf4_mu(mask, maskedoff, base, new_vl, vl);801}802 803// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vle16ff_v_i16mf2_mu804// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {805// CHECK-RV64-NEXT: entry:806// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.mask.nxv2i16.i64.p0(<vscale x 2 x i16> [[MASKEDOFF]], ptr [[BASE]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)807// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 2 x i16>, i64 } [[TMP0]], 0808// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x i16>, i64 } [[TMP0]], 1809// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8810// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]811//812vint16mf2_t test_vle16ff_v_i16mf2_mu(vbool32_t mask, vint16mf2_t maskedoff, const int16_t *base, size_t *new_vl, size_t vl) {813 return __riscv_vle16ff_v_i16mf2_mu(mask, maskedoff, base, new_vl, vl);814}815 816// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vle16ff_v_i16m1_mu817// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {818// CHECK-RV64-NEXT: entry:819// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 4 x i16>, i64 } @llvm.riscv.vleff.mask.nxv4i16.i64.p0(<vscale x 4 x i16> [[MASKEDOFF]], ptr [[BASE]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)820// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 4 x i16>, i64 } [[TMP0]], 0821// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x i16>, i64 } [[TMP0]], 1822// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8823// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]824//825vint16m1_t test_vle16ff_v_i16m1_mu(vbool16_t mask, vint16m1_t maskedoff, const int16_t *base, size_t *new_vl, size_t vl) {826 return __riscv_vle16ff_v_i16m1_mu(mask, maskedoff, base, new_vl, vl);827}828 829// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vle16ff_v_i16m2_mu830// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {831// CHECK-RV64-NEXT: entry:832// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 8 x i16>, i64 } @llvm.riscv.vleff.mask.nxv8i16.i64.p0(<vscale x 8 x i16> [[MASKEDOFF]], ptr [[BASE]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)833// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 8 x i16>, i64 } [[TMP0]], 0834// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x i16>, i64 } [[TMP0]], 1835// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8836// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]837//838vint16m2_t test_vle16ff_v_i16m2_mu(vbool8_t mask, vint16m2_t maskedoff, const int16_t *base, size_t *new_vl, size_t vl) {839 return __riscv_vle16ff_v_i16m2_mu(mask, maskedoff, base, new_vl, vl);840}841 842// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vle16ff_v_i16m4_mu843// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {844// CHECK-RV64-NEXT: entry:845// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 16 x i16>, i64 } @llvm.riscv.vleff.mask.nxv16i16.i64.p0(<vscale x 16 x i16> [[MASKEDOFF]], ptr [[BASE]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)846// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 16 x i16>, i64 } [[TMP0]], 0847// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 16 x i16>, i64 } [[TMP0]], 1848// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8849// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]850//851vint16m4_t test_vle16ff_v_i16m4_mu(vbool4_t mask, vint16m4_t maskedoff, const int16_t *base, size_t *new_vl, size_t vl) {852 return __riscv_vle16ff_v_i16m4_mu(mask, maskedoff, base, new_vl, vl);853}854 855// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vle16ff_v_i16m8_mu856// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {857// CHECK-RV64-NEXT: entry:858// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 32 x i16>, i64 } @llvm.riscv.vleff.mask.nxv32i16.i64.p0(<vscale x 32 x i16> [[MASKEDOFF]], ptr [[BASE]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1)859// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 32 x i16>, i64 } [[TMP0]], 0860// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 32 x i16>, i64 } [[TMP0]], 1861// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8862// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]]863//864vint16m8_t test_vle16ff_v_i16m8_mu(vbool2_t mask, vint16m8_t maskedoff, const int16_t *base, size_t *new_vl, size_t vl) {865 return __riscv_vle16ff_v_i16m8_mu(mask, maskedoff, base, new_vl, vl);866}867 868// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vle16ff_v_u16mf4_mu869// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {870// CHECK-RV64-NEXT: entry:871// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.mask.nxv1i16.i64.p0(<vscale x 1 x i16> [[MASKEDOFF]], ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)872// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i16>, i64 } [[TMP0]], 0873// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x i16>, i64 } [[TMP0]], 1874// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8875// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]876//877vuint16mf4_t test_vle16ff_v_u16mf4_mu(vbool64_t mask, vuint16mf4_t maskedoff, const uint16_t *base, size_t *new_vl, size_t vl) {878 return __riscv_vle16ff_v_u16mf4_mu(mask, maskedoff, base, new_vl, vl);879}880 881// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vle16ff_v_u16mf2_mu882// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {883// CHECK-RV64-NEXT: entry:884// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.mask.nxv2i16.i64.p0(<vscale x 2 x i16> [[MASKEDOFF]], ptr [[BASE]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)885// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 2 x i16>, i64 } [[TMP0]], 0886// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x i16>, i64 } [[TMP0]], 1887// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8888// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]889//890vuint16mf2_t test_vle16ff_v_u16mf2_mu(vbool32_t mask, vuint16mf2_t maskedoff, const uint16_t *base, size_t *new_vl, size_t vl) {891 return __riscv_vle16ff_v_u16mf2_mu(mask, maskedoff, base, new_vl, vl);892}893 894// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vle16ff_v_u16m1_mu895// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {896// CHECK-RV64-NEXT: entry:897// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 4 x i16>, i64 } @llvm.riscv.vleff.mask.nxv4i16.i64.p0(<vscale x 4 x i16> [[MASKEDOFF]], ptr [[BASE]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)898// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 4 x i16>, i64 } [[TMP0]], 0899// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x i16>, i64 } [[TMP0]], 1900// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8901// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]902//903vuint16m1_t test_vle16ff_v_u16m1_mu(vbool16_t mask, vuint16m1_t maskedoff, const uint16_t *base, size_t *new_vl, size_t vl) {904 return __riscv_vle16ff_v_u16m1_mu(mask, maskedoff, base, new_vl, vl);905}906 907// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vle16ff_v_u16m2_mu908// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {909// CHECK-RV64-NEXT: entry:910// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 8 x i16>, i64 } @llvm.riscv.vleff.mask.nxv8i16.i64.p0(<vscale x 8 x i16> [[MASKEDOFF]], ptr [[BASE]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)911// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 8 x i16>, i64 } [[TMP0]], 0912// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x i16>, i64 } [[TMP0]], 1913// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8914// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]915//916vuint16m2_t test_vle16ff_v_u16m2_mu(vbool8_t mask, vuint16m2_t maskedoff, const uint16_t *base, size_t *new_vl, size_t vl) {917 return __riscv_vle16ff_v_u16m2_mu(mask, maskedoff, base, new_vl, vl);918}919 920// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vle16ff_v_u16m4_mu921// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {922// CHECK-RV64-NEXT: entry:923// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 16 x i16>, i64 } @llvm.riscv.vleff.mask.nxv16i16.i64.p0(<vscale x 16 x i16> [[MASKEDOFF]], ptr [[BASE]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)924// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 16 x i16>, i64 } [[TMP0]], 0925// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 16 x i16>, i64 } [[TMP0]], 1926// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8927// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]928//929vuint16m4_t test_vle16ff_v_u16m4_mu(vbool4_t mask, vuint16m4_t maskedoff, const uint16_t *base, size_t *new_vl, size_t vl) {930 return __riscv_vle16ff_v_u16m4_mu(mask, maskedoff, base, new_vl, vl);931}932 933// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vle16ff_v_u16m8_mu934// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {935// CHECK-RV64-NEXT: entry:936// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 32 x i16>, i64 } @llvm.riscv.vleff.mask.nxv32i16.i64.p0(<vscale x 32 x i16> [[MASKEDOFF]], ptr [[BASE]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1)937// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 32 x i16>, i64 } [[TMP0]], 0938// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 32 x i16>, i64 } [[TMP0]], 1939// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8940// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]]941//942vuint16m8_t test_vle16ff_v_u16m8_mu(vbool2_t mask, vuint16m8_t maskedoff, const uint16_t *base, size_t *new_vl, size_t vl) {943 return __riscv_vle16ff_v_u16m8_mu(mask, maskedoff, base, new_vl, vl);944}945 946