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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 22// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \4// RUN:   -target-feature +zvfh -disable-O0-optnone  \5// RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \6// RUN:   FileCheck --check-prefix=CHECK-RV64 %s7 8#include <riscv_vector.h>9 10// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vmadd_vv_i8mf8_tu11// CHECK-RV64-SAME: (<vscale x 1 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS1:%.*]], <vscale x 1 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {12// CHECK-RV64-NEXT:  entry:13// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[VD]], <vscale x 1 x i8> [[VS1]], <vscale x 1 x i8> [[VS2]], i64 [[VL]], i64 2)14// CHECK-RV64-NEXT:    ret <vscale x 1 x i8> [[TMP0]]15//16vint8mf8_t test_vmadd_vv_i8mf8_tu(vint8mf8_t vd, vint8mf8_t vs1, vint8mf8_t vs2, size_t vl) {17  return __riscv_vmadd_vv_i8mf8_tu(vd, vs1, vs2, vl);18}19 20// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vmadd_vx_i8mf8_tu21// CHECK-RV64-SAME: (<vscale x 1 x i8> [[VD:%.*]], i8 noundef signext [[RS1:%.*]], <vscale x 1 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {22// CHECK-RV64-NEXT:  entry:23// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.i8.i64(<vscale x 1 x i8> [[VD]], i8 [[RS1]], <vscale x 1 x i8> [[VS2]], i64 [[VL]], i64 2)24// CHECK-RV64-NEXT:    ret <vscale x 1 x i8> [[TMP0]]25//26vint8mf8_t test_vmadd_vx_i8mf8_tu(vint8mf8_t vd, int8_t rs1, vint8mf8_t vs2, size_t vl) {27  return __riscv_vmadd_vx_i8mf8_tu(vd, rs1, vs2, vl);28}29 30// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vmadd_vv_i8mf4_tu31// CHECK-RV64-SAME: (<vscale x 2 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS1:%.*]], <vscale x 2 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {32// CHECK-RV64-NEXT:  entry:33// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 2 x i8> [[VS1]], <vscale x 2 x i8> [[VS2]], i64 [[VL]], i64 2)34// CHECK-RV64-NEXT:    ret <vscale x 2 x i8> [[TMP0]]35//36vint8mf4_t test_vmadd_vv_i8mf4_tu(vint8mf4_t vd, vint8mf4_t vs1, vint8mf4_t vs2, size_t vl) {37  return __riscv_vmadd_vv_i8mf4_tu(vd, vs1, vs2, vl);38}39 40// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vmadd_vx_i8mf4_tu41// CHECK-RV64-SAME: (<vscale x 2 x i8> [[VD:%.*]], i8 noundef signext [[RS1:%.*]], <vscale x 2 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {42// CHECK-RV64-NEXT:  entry:43// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.i8.i64(<vscale x 2 x i8> [[VD]], i8 [[RS1]], <vscale x 2 x i8> [[VS2]], i64 [[VL]], i64 2)44// CHECK-RV64-NEXT:    ret <vscale x 2 x i8> [[TMP0]]45//46vint8mf4_t test_vmadd_vx_i8mf4_tu(vint8mf4_t vd, int8_t rs1, vint8mf4_t vs2, size_t vl) {47  return __riscv_vmadd_vx_i8mf4_tu(vd, rs1, vs2, vl);48}49 50// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vmadd_vv_i8mf2_tu51// CHECK-RV64-SAME: (<vscale x 4 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS1:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {52// CHECK-RV64-NEXT:  entry:53// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 4 x i8> [[VS1]], <vscale x 4 x i8> [[VS2]], i64 [[VL]], i64 2)54// CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[TMP0]]55//56vint8mf2_t test_vmadd_vv_i8mf2_tu(vint8mf2_t vd, vint8mf2_t vs1, vint8mf2_t vs2, size_t vl) {57  return __riscv_vmadd_vv_i8mf2_tu(vd, vs1, vs2, vl);58}59 60// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vmadd_vx_i8mf2_tu61// CHECK-RV64-SAME: (<vscale x 4 x i8> [[VD:%.*]], i8 noundef signext [[RS1:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {62// CHECK-RV64-NEXT:  entry:63// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.i8.i64(<vscale x 4 x i8> [[VD]], i8 [[RS1]], <vscale x 4 x i8> [[VS2]], i64 [[VL]], i64 2)64// CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[TMP0]]65//66vint8mf2_t test_vmadd_vx_i8mf2_tu(vint8mf2_t vd, int8_t rs1, vint8mf2_t vs2, size_t vl) {67  return __riscv_vmadd_vx_i8mf2_tu(vd, rs1, vs2, vl);68}69 70// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vmadd_vv_i8m1_tu71// CHECK-RV64-SAME: (<vscale x 8 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {72// CHECK-RV64-NEXT:  entry:73// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 2)74// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]75//76vint8m1_t test_vmadd_vv_i8m1_tu(vint8m1_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) {77  return __riscv_vmadd_vv_i8m1_tu(vd, vs1, vs2, vl);78}79 80// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vmadd_vx_i8m1_tu81// CHECK-RV64-SAME: (<vscale x 8 x i8> [[VD:%.*]], i8 noundef signext [[RS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {82// CHECK-RV64-NEXT:  entry:83// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.i8.i64(<vscale x 8 x i8> [[VD]], i8 [[RS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 2)84// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]85//86vint8m1_t test_vmadd_vx_i8m1_tu(vint8m1_t vd, int8_t rs1, vint8m1_t vs2, size_t vl) {87  return __riscv_vmadd_vx_i8m1_tu(vd, rs1, vs2, vl);88}89 90// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vmadd_vv_i8m2_tu91// CHECK-RV64-SAME: (<vscale x 16 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {92// CHECK-RV64-NEXT:  entry:93// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 16 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 2)94// CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]95//96vint8m2_t test_vmadd_vv_i8m2_tu(vint8m2_t vd, vint8m2_t vs1, vint8m2_t vs2, size_t vl) {97  return __riscv_vmadd_vv_i8m2_tu(vd, vs1, vs2, vl);98}99 100// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vmadd_vx_i8m2_tu101// CHECK-RV64-SAME: (<vscale x 16 x i8> [[VD:%.*]], i8 noundef signext [[RS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {102// CHECK-RV64-NEXT:  entry:103// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmadd.nxv16i8.i8.i64(<vscale x 16 x i8> [[VD]], i8 [[RS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 2)104// CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]105//106vint8m2_t test_vmadd_vx_i8m2_tu(vint8m2_t vd, int8_t rs1, vint8m2_t vs2, size_t vl) {107  return __riscv_vmadd_vx_i8m2_tu(vd, rs1, vs2, vl);108}109 110// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vmadd_vv_i8m4_tu111// CHECK-RV64-SAME: (<vscale x 32 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {112// CHECK-RV64-NEXT:  entry:113// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmadd.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 32 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 2)114// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]115//116vint8m4_t test_vmadd_vv_i8m4_tu(vint8m4_t vd, vint8m4_t vs1, vint8m4_t vs2, size_t vl) {117  return __riscv_vmadd_vv_i8m4_tu(vd, vs1, vs2, vl);118}119 120// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vmadd_vx_i8m4_tu121// CHECK-RV64-SAME: (<vscale x 32 x i8> [[VD:%.*]], i8 noundef signext [[RS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {122// CHECK-RV64-NEXT:  entry:123// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmadd.nxv32i8.i8.i64(<vscale x 32 x i8> [[VD]], i8 [[RS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 2)124// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]125//126vint8m4_t test_vmadd_vx_i8m4_tu(vint8m4_t vd, int8_t rs1, vint8m4_t vs2, size_t vl) {127  return __riscv_vmadd_vx_i8m4_tu(vd, rs1, vs2, vl);128}129 130// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vmadd_vv_i8m8_tu131// CHECK-RV64-SAME: (<vscale x 64 x i8> [[VD:%.*]], <vscale x 64 x i8> [[VS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {132// CHECK-RV64-NEXT:  entry:133// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmadd.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[VD]], <vscale x 64 x i8> [[VS1]], <vscale x 64 x i8> [[VS2]], i64 [[VL]], i64 2)134// CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP0]]135//136vint8m8_t test_vmadd_vv_i8m8_tu(vint8m8_t vd, vint8m8_t vs1, vint8m8_t vs2, size_t vl) {137  return __riscv_vmadd_vv_i8m8_tu(vd, vs1, vs2, vl);138}139 140// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vmadd_vx_i8m8_tu141// CHECK-RV64-SAME: (<vscale x 64 x i8> [[VD:%.*]], i8 noundef signext [[RS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {142// CHECK-RV64-NEXT:  entry:143// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmadd.nxv64i8.i8.i64(<vscale x 64 x i8> [[VD]], i8 [[RS1]], <vscale x 64 x i8> [[VS2]], i64 [[VL]], i64 2)144// CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP0]]145//146vint8m8_t test_vmadd_vx_i8m8_tu(vint8m8_t vd, int8_t rs1, vint8m8_t vs2, size_t vl) {147  return __riscv_vmadd_vx_i8m8_tu(vd, rs1, vs2, vl);148}149 150// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vmadd_vv_i16mf4_tu151// CHECK-RV64-SAME: (<vscale x 1 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS1:%.*]], <vscale x 1 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {152// CHECK-RV64-NEXT:  entry:153// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmadd.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[VD]], <vscale x 1 x i16> [[VS1]], <vscale x 1 x i16> [[VS2]], i64 [[VL]], i64 2)154// CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]155//156vint16mf4_t test_vmadd_vv_i16mf4_tu(vint16mf4_t vd, vint16mf4_t vs1, vint16mf4_t vs2, size_t vl) {157  return __riscv_vmadd_vv_i16mf4_tu(vd, vs1, vs2, vl);158}159 160// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vmadd_vx_i16mf4_tu161// CHECK-RV64-SAME: (<vscale x 1 x i16> [[VD:%.*]], i16 noundef signext [[RS1:%.*]], <vscale x 1 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {162// CHECK-RV64-NEXT:  entry:163// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmadd.nxv1i16.i16.i64(<vscale x 1 x i16> [[VD]], i16 [[RS1]], <vscale x 1 x i16> [[VS2]], i64 [[VL]], i64 2)164// CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]165//166vint16mf4_t test_vmadd_vx_i16mf4_tu(vint16mf4_t vd, int16_t rs1, vint16mf4_t vs2, size_t vl) {167  return __riscv_vmadd_vx_i16mf4_tu(vd, rs1, vs2, vl);168}169 170// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vmadd_vv_i16mf2_tu171// CHECK-RV64-SAME: (<vscale x 2 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS1:%.*]], <vscale x 2 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {172// CHECK-RV64-NEXT:  entry:173// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmadd.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 2 x i16> [[VS1]], <vscale x 2 x i16> [[VS2]], i64 [[VL]], i64 2)174// CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]175//176vint16mf2_t test_vmadd_vv_i16mf2_tu(vint16mf2_t vd, vint16mf2_t vs1, vint16mf2_t vs2, size_t vl) {177  return __riscv_vmadd_vv_i16mf2_tu(vd, vs1, vs2, vl);178}179 180// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vmadd_vx_i16mf2_tu181// CHECK-RV64-SAME: (<vscale x 2 x i16> [[VD:%.*]], i16 noundef signext [[RS1:%.*]], <vscale x 2 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {182// CHECK-RV64-NEXT:  entry:183// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmadd.nxv2i16.i16.i64(<vscale x 2 x i16> [[VD]], i16 [[RS1]], <vscale x 2 x i16> [[VS2]], i64 [[VL]], i64 2)184// CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]185//186vint16mf2_t test_vmadd_vx_i16mf2_tu(vint16mf2_t vd, int16_t rs1, vint16mf2_t vs2, size_t vl) {187  return __riscv_vmadd_vx_i16mf2_tu(vd, rs1, vs2, vl);188}189 190// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vmadd_vv_i16m1_tu191// CHECK-RV64-SAME: (<vscale x 4 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS1:%.*]], <vscale x 4 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {192// CHECK-RV64-NEXT:  entry:193// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmadd.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 4 x i16> [[VS1]], <vscale x 4 x i16> [[VS2]], i64 [[VL]], i64 2)194// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]195//196vint16m1_t test_vmadd_vv_i16m1_tu(vint16m1_t vd, vint16m1_t vs1, vint16m1_t vs2, size_t vl) {197  return __riscv_vmadd_vv_i16m1_tu(vd, vs1, vs2, vl);198}199 200// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vmadd_vx_i16m1_tu201// CHECK-RV64-SAME: (<vscale x 4 x i16> [[VD:%.*]], i16 noundef signext [[RS1:%.*]], <vscale x 4 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {202// CHECK-RV64-NEXT:  entry:203// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmadd.nxv4i16.i16.i64(<vscale x 4 x i16> [[VD]], i16 [[RS1]], <vscale x 4 x i16> [[VS2]], i64 [[VL]], i64 2)204// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]205//206vint16m1_t test_vmadd_vx_i16m1_tu(vint16m1_t vd, int16_t rs1, vint16m1_t vs2, size_t vl) {207  return __riscv_vmadd_vx_i16m1_tu(vd, rs1, vs2, vl);208}209 210// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vmadd_vv_i16m2_tu211// CHECK-RV64-SAME: (<vscale x 8 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS1:%.*]], <vscale x 8 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {212// CHECK-RV64-NEXT:  entry:213// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmadd.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 8 x i16> [[VS1]], <vscale x 8 x i16> [[VS2]], i64 [[VL]], i64 2)214// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]215//216vint16m2_t test_vmadd_vv_i16m2_tu(vint16m2_t vd, vint16m2_t vs1, vint16m2_t vs2, size_t vl) {217  return __riscv_vmadd_vv_i16m2_tu(vd, vs1, vs2, vl);218}219 220// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vmadd_vx_i16m2_tu221// CHECK-RV64-SAME: (<vscale x 8 x i16> [[VD:%.*]], i16 noundef signext [[RS1:%.*]], <vscale x 8 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {222// CHECK-RV64-NEXT:  entry:223// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmadd.nxv8i16.i16.i64(<vscale x 8 x i16> [[VD]], i16 [[RS1]], <vscale x 8 x i16> [[VS2]], i64 [[VL]], i64 2)224// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]225//226vint16m2_t test_vmadd_vx_i16m2_tu(vint16m2_t vd, int16_t rs1, vint16m2_t vs2, size_t vl) {227  return __riscv_vmadd_vx_i16m2_tu(vd, rs1, vs2, vl);228}229 230// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vmadd_vv_i16m4_tu231// CHECK-RV64-SAME: (<vscale x 16 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS1:%.*]], <vscale x 16 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {232// CHECK-RV64-NEXT:  entry:233// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmadd.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 16 x i16> [[VS1]], <vscale x 16 x i16> [[VS2]], i64 [[VL]], i64 2)234// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]235//236vint16m4_t test_vmadd_vv_i16m4_tu(vint16m4_t vd, vint16m4_t vs1, vint16m4_t vs2, size_t vl) {237  return __riscv_vmadd_vv_i16m4_tu(vd, vs1, vs2, vl);238}239 240// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vmadd_vx_i16m4_tu241// CHECK-RV64-SAME: (<vscale x 16 x i16> [[VD:%.*]], i16 noundef signext [[RS1:%.*]], <vscale x 16 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {242// CHECK-RV64-NEXT:  entry:243// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmadd.nxv16i16.i16.i64(<vscale x 16 x i16> [[VD]], i16 [[RS1]], <vscale x 16 x i16> [[VS2]], i64 [[VL]], i64 2)244// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]245//246vint16m4_t test_vmadd_vx_i16m4_tu(vint16m4_t vd, int16_t rs1, vint16m4_t vs2, size_t vl) {247  return __riscv_vmadd_vx_i16m4_tu(vd, rs1, vs2, vl);248}249 250// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vmadd_vv_i16m8_tu251// CHECK-RV64-SAME: (<vscale x 32 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS1:%.*]], <vscale x 32 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {252// CHECK-RV64-NEXT:  entry:253// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmadd.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[VD]], <vscale x 32 x i16> [[VS1]], <vscale x 32 x i16> [[VS2]], i64 [[VL]], i64 2)254// CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]255//256vint16m8_t test_vmadd_vv_i16m8_tu(vint16m8_t vd, vint16m8_t vs1, vint16m8_t vs2, size_t vl) {257  return __riscv_vmadd_vv_i16m8_tu(vd, vs1, vs2, vl);258}259 260// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vmadd_vx_i16m8_tu261// CHECK-RV64-SAME: (<vscale x 32 x i16> [[VD:%.*]], i16 noundef signext [[RS1:%.*]], <vscale x 32 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {262// CHECK-RV64-NEXT:  entry:263// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmadd.nxv32i16.i16.i64(<vscale x 32 x i16> [[VD]], i16 [[RS1]], <vscale x 32 x i16> [[VS2]], i64 [[VL]], i64 2)264// CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]265//266vint16m8_t test_vmadd_vx_i16m8_tu(vint16m8_t vd, int16_t rs1, vint16m8_t vs2, size_t vl) {267  return __riscv_vmadd_vx_i16m8_tu(vd, rs1, vs2, vl);268}269 270// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vmadd_vv_i32mf2_tu271// CHECK-RV64-SAME: (<vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS1:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {272// CHECK-RV64-NEXT:  entry:273// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmadd.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i32> [[VS2]], i64 [[VL]], i64 2)274// CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]275//276vint32mf2_t test_vmadd_vv_i32mf2_tu(vint32mf2_t vd, vint32mf2_t vs1, vint32mf2_t vs2, size_t vl) {277  return __riscv_vmadd_vv_i32mf2_tu(vd, vs1, vs2, vl);278}279 280// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vmadd_vx_i32mf2_tu281// CHECK-RV64-SAME: (<vscale x 1 x i32> [[VD:%.*]], i32 noundef signext [[RS1:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {282// CHECK-RV64-NEXT:  entry:283// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmadd.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], i32 [[RS1]], <vscale x 1 x i32> [[VS2]], i64 [[VL]], i64 2)284// CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]285//286vint32mf2_t test_vmadd_vx_i32mf2_tu(vint32mf2_t vd, int32_t rs1, vint32mf2_t vs2, size_t vl) {287  return __riscv_vmadd_vx_i32mf2_tu(vd, rs1, vs2, vl);288}289 290// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vmadd_vv_i32m1_tu291// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS1:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {292// CHECK-RV64-NEXT:  entry:293// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmadd.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i32> [[VS2]], i64 [[VL]], i64 2)294// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]295//296vint32m1_t test_vmadd_vv_i32m1_tu(vint32m1_t vd, vint32m1_t vs1, vint32m1_t vs2, size_t vl) {297  return __riscv_vmadd_vv_i32m1_tu(vd, vs1, vs2, vl);298}299 300// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vmadd_vx_i32m1_tu301// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], i32 noundef signext [[RS1:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {302// CHECK-RV64-NEXT:  entry:303// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmadd.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], i32 [[RS1]], <vscale x 2 x i32> [[VS2]], i64 [[VL]], i64 2)304// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]305//306vint32m1_t test_vmadd_vx_i32m1_tu(vint32m1_t vd, int32_t rs1, vint32m1_t vs2, size_t vl) {307  return __riscv_vmadd_vx_i32m1_tu(vd, rs1, vs2, vl);308}309 310// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vmadd_vv_i32m2_tu311// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS1:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {312// CHECK-RV64-NEXT:  entry:313// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmadd.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i32> [[VS2]], i64 [[VL]], i64 2)314// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]315//316vint32m2_t test_vmadd_vv_i32m2_tu(vint32m2_t vd, vint32m2_t vs1, vint32m2_t vs2, size_t vl) {317  return __riscv_vmadd_vv_i32m2_tu(vd, vs1, vs2, vl);318}319 320// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vmadd_vx_i32m2_tu321// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], i32 noundef signext [[RS1:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {322// CHECK-RV64-NEXT:  entry:323// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmadd.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], i32 [[RS1]], <vscale x 4 x i32> [[VS2]], i64 [[VL]], i64 2)324// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]325//326vint32m2_t test_vmadd_vx_i32m2_tu(vint32m2_t vd, int32_t rs1, vint32m2_t vs2, size_t vl) {327  return __riscv_vmadd_vx_i32m2_tu(vd, rs1, vs2, vl);328}329 330// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vmadd_vv_i32m4_tu331// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS1:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {332// CHECK-RV64-NEXT:  entry:333// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmadd.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i32> [[VS2]], i64 [[VL]], i64 2)334// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]335//336vint32m4_t test_vmadd_vv_i32m4_tu(vint32m4_t vd, vint32m4_t vs1, vint32m4_t vs2, size_t vl) {337  return __riscv_vmadd_vv_i32m4_tu(vd, vs1, vs2, vl);338}339 340// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vmadd_vx_i32m4_tu341// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], i32 noundef signext [[RS1:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {342// CHECK-RV64-NEXT:  entry:343// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmadd.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], i32 [[RS1]], <vscale x 8 x i32> [[VS2]], i64 [[VL]], i64 2)344// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]345//346vint32m4_t test_vmadd_vx_i32m4_tu(vint32m4_t vd, int32_t rs1, vint32m4_t vs2, size_t vl) {347  return __riscv_vmadd_vx_i32m4_tu(vd, rs1, vs2, vl);348}349 350// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vmadd_vv_i32m8_tu351// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS1:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {352// CHECK-RV64-NEXT:  entry:353// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmadd.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i32> [[VS2]], i64 [[VL]], i64 2)354// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]355//356vint32m8_t test_vmadd_vv_i32m8_tu(vint32m8_t vd, vint32m8_t vs1, vint32m8_t vs2, size_t vl) {357  return __riscv_vmadd_vv_i32m8_tu(vd, vs1, vs2, vl);358}359 360// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vmadd_vx_i32m8_tu361// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], i32 noundef signext [[RS1:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {362// CHECK-RV64-NEXT:  entry:363// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmadd.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], i32 [[RS1]], <vscale x 16 x i32> [[VS2]], i64 [[VL]], i64 2)364// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]365//366vint32m8_t test_vmadd_vx_i32m8_tu(vint32m8_t vd, int32_t rs1, vint32m8_t vs2, size_t vl) {367  return __riscv_vmadd_vx_i32m8_tu(vd, rs1, vs2, vl);368}369 370// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vmadd_vv_i64m1_tu371// CHECK-RV64-SAME: (<vscale x 1 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS1:%.*]], <vscale x 1 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {372// CHECK-RV64-NEXT:  entry:373// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[VD]], <vscale x 1 x i64> [[VS1]], <vscale x 1 x i64> [[VS2]], i64 [[VL]], i64 2)374// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]375//376vint64m1_t test_vmadd_vv_i64m1_tu(vint64m1_t vd, vint64m1_t vs1, vint64m1_t vs2, size_t vl) {377  return __riscv_vmadd_vv_i64m1_tu(vd, vs1, vs2, vl);378}379 380// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vmadd_vx_i64m1_tu381// CHECK-RV64-SAME: (<vscale x 1 x i64> [[VD:%.*]], i64 noundef [[RS1:%.*]], <vscale x 1 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {382// CHECK-RV64-NEXT:  entry:383// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmadd.nxv1i64.i64.i64(<vscale x 1 x i64> [[VD]], i64 [[RS1]], <vscale x 1 x i64> [[VS2]], i64 [[VL]], i64 2)384// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]385//386vint64m1_t test_vmadd_vx_i64m1_tu(vint64m1_t vd, int64_t rs1, vint64m1_t vs2, size_t vl) {387  return __riscv_vmadd_vx_i64m1_tu(vd, rs1, vs2, vl);388}389 390// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vmadd_vv_i64m2_tu391// CHECK-RV64-SAME: (<vscale x 2 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS1:%.*]], <vscale x 2 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {392// CHECK-RV64-NEXT:  entry:393// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmadd.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 2 x i64> [[VS1]], <vscale x 2 x i64> [[VS2]], i64 [[VL]], i64 2)394// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]395//396vint64m2_t test_vmadd_vv_i64m2_tu(vint64m2_t vd, vint64m2_t vs1, vint64m2_t vs2, size_t vl) {397  return __riscv_vmadd_vv_i64m2_tu(vd, vs1, vs2, vl);398}399 400// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vmadd_vx_i64m2_tu401// CHECK-RV64-SAME: (<vscale x 2 x i64> [[VD:%.*]], i64 noundef [[RS1:%.*]], <vscale x 2 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {402// CHECK-RV64-NEXT:  entry:403// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmadd.nxv2i64.i64.i64(<vscale x 2 x i64> [[VD]], i64 [[RS1]], <vscale x 2 x i64> [[VS2]], i64 [[VL]], i64 2)404// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]405//406vint64m2_t test_vmadd_vx_i64m2_tu(vint64m2_t vd, int64_t rs1, vint64m2_t vs2, size_t vl) {407  return __riscv_vmadd_vx_i64m2_tu(vd, rs1, vs2, vl);408}409 410// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vmadd_vv_i64m4_tu411// CHECK-RV64-SAME: (<vscale x 4 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS1:%.*]], <vscale x 4 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {412// CHECK-RV64-NEXT:  entry:413// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmadd.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 4 x i64> [[VS1]], <vscale x 4 x i64> [[VS2]], i64 [[VL]], i64 2)414// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]415//416vint64m4_t test_vmadd_vv_i64m4_tu(vint64m4_t vd, vint64m4_t vs1, vint64m4_t vs2, size_t vl) {417  return __riscv_vmadd_vv_i64m4_tu(vd, vs1, vs2, vl);418}419 420// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vmadd_vx_i64m4_tu421// CHECK-RV64-SAME: (<vscale x 4 x i64> [[VD:%.*]], i64 noundef [[RS1:%.*]], <vscale x 4 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {422// CHECK-RV64-NEXT:  entry:423// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmadd.nxv4i64.i64.i64(<vscale x 4 x i64> [[VD]], i64 [[RS1]], <vscale x 4 x i64> [[VS2]], i64 [[VL]], i64 2)424// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]425//426vint64m4_t test_vmadd_vx_i64m4_tu(vint64m4_t vd, int64_t rs1, vint64m4_t vs2, size_t vl) {427  return __riscv_vmadd_vx_i64m4_tu(vd, rs1, vs2, vl);428}429 430// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vmadd_vv_i64m8_tu431// CHECK-RV64-SAME: (<vscale x 8 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS1:%.*]], <vscale x 8 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {432// CHECK-RV64-NEXT:  entry:433// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmadd.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[VD]], <vscale x 8 x i64> [[VS1]], <vscale x 8 x i64> [[VS2]], i64 [[VL]], i64 2)434// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]435//436vint64m8_t test_vmadd_vv_i64m8_tu(vint64m8_t vd, vint64m8_t vs1, vint64m8_t vs2, size_t vl) {437  return __riscv_vmadd_vv_i64m8_tu(vd, vs1, vs2, vl);438}439 440// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vmadd_vx_i64m8_tu441// CHECK-RV64-SAME: (<vscale x 8 x i64> [[VD:%.*]], i64 noundef [[RS1:%.*]], <vscale x 8 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {442// CHECK-RV64-NEXT:  entry:443// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmadd.nxv8i64.i64.i64(<vscale x 8 x i64> [[VD]], i64 [[RS1]], <vscale x 8 x i64> [[VS2]], i64 [[VL]], i64 2)444// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]445//446vint64m8_t test_vmadd_vx_i64m8_tu(vint64m8_t vd, int64_t rs1, vint64m8_t vs2, size_t vl) {447  return __riscv_vmadd_vx_i64m8_tu(vd, rs1, vs2, vl);448}449 450// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vmadd_vv_u8mf8_tu451// CHECK-RV64-SAME: (<vscale x 1 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS1:%.*]], <vscale x 1 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {452// CHECK-RV64-NEXT:  entry:453// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[VD]], <vscale x 1 x i8> [[VS1]], <vscale x 1 x i8> [[VS2]], i64 [[VL]], i64 2)454// CHECK-RV64-NEXT:    ret <vscale x 1 x i8> [[TMP0]]455//456vuint8mf8_t test_vmadd_vv_u8mf8_tu(vuint8mf8_t vd, vuint8mf8_t vs1, vuint8mf8_t vs2, size_t vl) {457  return __riscv_vmadd_vv_u8mf8_tu(vd, vs1, vs2, vl);458}459 460// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vmadd_vx_u8mf8_tu461// CHECK-RV64-SAME: (<vscale x 1 x i8> [[VD:%.*]], i8 noundef zeroext [[RS1:%.*]], <vscale x 1 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {462// CHECK-RV64-NEXT:  entry:463// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.i8.i64(<vscale x 1 x i8> [[VD]], i8 [[RS1]], <vscale x 1 x i8> [[VS2]], i64 [[VL]], i64 2)464// CHECK-RV64-NEXT:    ret <vscale x 1 x i8> [[TMP0]]465//466vuint8mf8_t test_vmadd_vx_u8mf8_tu(vuint8mf8_t vd, uint8_t rs1, vuint8mf8_t vs2, size_t vl) {467  return __riscv_vmadd_vx_u8mf8_tu(vd, rs1, vs2, vl);468}469 470// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vmadd_vv_u8mf4_tu471// CHECK-RV64-SAME: (<vscale x 2 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS1:%.*]], <vscale x 2 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {472// CHECK-RV64-NEXT:  entry:473// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 2 x i8> [[VS1]], <vscale x 2 x i8> [[VS2]], i64 [[VL]], i64 2)474// CHECK-RV64-NEXT:    ret <vscale x 2 x i8> [[TMP0]]475//476vuint8mf4_t test_vmadd_vv_u8mf4_tu(vuint8mf4_t vd, vuint8mf4_t vs1, vuint8mf4_t vs2, size_t vl) {477  return __riscv_vmadd_vv_u8mf4_tu(vd, vs1, vs2, vl);478}479 480// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vmadd_vx_u8mf4_tu481// CHECK-RV64-SAME: (<vscale x 2 x i8> [[VD:%.*]], i8 noundef zeroext [[RS1:%.*]], <vscale x 2 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {482// CHECK-RV64-NEXT:  entry:483// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.i8.i64(<vscale x 2 x i8> [[VD]], i8 [[RS1]], <vscale x 2 x i8> [[VS2]], i64 [[VL]], i64 2)484// CHECK-RV64-NEXT:    ret <vscale x 2 x i8> [[TMP0]]485//486vuint8mf4_t test_vmadd_vx_u8mf4_tu(vuint8mf4_t vd, uint8_t rs1, vuint8mf4_t vs2, size_t vl) {487  return __riscv_vmadd_vx_u8mf4_tu(vd, rs1, vs2, vl);488}489 490// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vmadd_vv_u8mf2_tu491// CHECK-RV64-SAME: (<vscale x 4 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS1:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {492// CHECK-RV64-NEXT:  entry:493// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 4 x i8> [[VS1]], <vscale x 4 x i8> [[VS2]], i64 [[VL]], i64 2)494// CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[TMP0]]495//496vuint8mf2_t test_vmadd_vv_u8mf2_tu(vuint8mf2_t vd, vuint8mf2_t vs1, vuint8mf2_t vs2, size_t vl) {497  return __riscv_vmadd_vv_u8mf2_tu(vd, vs1, vs2, vl);498}499 500// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vmadd_vx_u8mf2_tu501// CHECK-RV64-SAME: (<vscale x 4 x i8> [[VD:%.*]], i8 noundef zeroext [[RS1:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {502// CHECK-RV64-NEXT:  entry:503// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.i8.i64(<vscale x 4 x i8> [[VD]], i8 [[RS1]], <vscale x 4 x i8> [[VS2]], i64 [[VL]], i64 2)504// CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[TMP0]]505//506vuint8mf2_t test_vmadd_vx_u8mf2_tu(vuint8mf2_t vd, uint8_t rs1, vuint8mf2_t vs2, size_t vl) {507  return __riscv_vmadd_vx_u8mf2_tu(vd, rs1, vs2, vl);508}509 510// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vmadd_vv_u8m1_tu511// CHECK-RV64-SAME: (<vscale x 8 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {512// CHECK-RV64-NEXT:  entry:513// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 2)514// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]515//516vuint8m1_t test_vmadd_vv_u8m1_tu(vuint8m1_t vd, vuint8m1_t vs1, vuint8m1_t vs2, size_t vl) {517  return __riscv_vmadd_vv_u8m1_tu(vd, vs1, vs2, vl);518}519 520// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vmadd_vx_u8m1_tu521// CHECK-RV64-SAME: (<vscale x 8 x i8> [[VD:%.*]], i8 noundef zeroext [[RS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {522// CHECK-RV64-NEXT:  entry:523// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.i8.i64(<vscale x 8 x i8> [[VD]], i8 [[RS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 2)524// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]525//526vuint8m1_t test_vmadd_vx_u8m1_tu(vuint8m1_t vd, uint8_t rs1, vuint8m1_t vs2, size_t vl) {527  return __riscv_vmadd_vx_u8m1_tu(vd, rs1, vs2, vl);528}529 530// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vmadd_vv_u8m2_tu531// CHECK-RV64-SAME: (<vscale x 16 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {532// CHECK-RV64-NEXT:  entry:533// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 16 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 2)534// CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]535//536vuint8m2_t test_vmadd_vv_u8m2_tu(vuint8m2_t vd, vuint8m2_t vs1, vuint8m2_t vs2, size_t vl) {537  return __riscv_vmadd_vv_u8m2_tu(vd, vs1, vs2, vl);538}539 540// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vmadd_vx_u8m2_tu541// CHECK-RV64-SAME: (<vscale x 16 x i8> [[VD:%.*]], i8 noundef zeroext [[RS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {542// CHECK-RV64-NEXT:  entry:543// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmadd.nxv16i8.i8.i64(<vscale x 16 x i8> [[VD]], i8 [[RS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 2)544// CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]545//546vuint8m2_t test_vmadd_vx_u8m2_tu(vuint8m2_t vd, uint8_t rs1, vuint8m2_t vs2, size_t vl) {547  return __riscv_vmadd_vx_u8m2_tu(vd, rs1, vs2, vl);548}549 550// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vmadd_vv_u8m4_tu551// CHECK-RV64-SAME: (<vscale x 32 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {552// CHECK-RV64-NEXT:  entry:553// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmadd.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 32 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 2)554// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]555//556vuint8m4_t test_vmadd_vv_u8m4_tu(vuint8m4_t vd, vuint8m4_t vs1, vuint8m4_t vs2, size_t vl) {557  return __riscv_vmadd_vv_u8m4_tu(vd, vs1, vs2, vl);558}559 560// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vmadd_vx_u8m4_tu561// CHECK-RV64-SAME: (<vscale x 32 x i8> [[VD:%.*]], i8 noundef zeroext [[RS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {562// CHECK-RV64-NEXT:  entry:563// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmadd.nxv32i8.i8.i64(<vscale x 32 x i8> [[VD]], i8 [[RS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 2)564// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]565//566vuint8m4_t test_vmadd_vx_u8m4_tu(vuint8m4_t vd, uint8_t rs1, vuint8m4_t vs2, size_t vl) {567  return __riscv_vmadd_vx_u8m4_tu(vd, rs1, vs2, vl);568}569 570// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vmadd_vv_u8m8_tu571// CHECK-RV64-SAME: (<vscale x 64 x i8> [[VD:%.*]], <vscale x 64 x i8> [[VS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {572// CHECK-RV64-NEXT:  entry:573// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmadd.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[VD]], <vscale x 64 x i8> [[VS1]], <vscale x 64 x i8> [[VS2]], i64 [[VL]], i64 2)574// CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP0]]575//576vuint8m8_t test_vmadd_vv_u8m8_tu(vuint8m8_t vd, vuint8m8_t vs1, vuint8m8_t vs2, size_t vl) {577  return __riscv_vmadd_vv_u8m8_tu(vd, vs1, vs2, vl);578}579 580// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vmadd_vx_u8m8_tu581// CHECK-RV64-SAME: (<vscale x 64 x i8> [[VD:%.*]], i8 noundef zeroext [[RS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {582// CHECK-RV64-NEXT:  entry:583// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmadd.nxv64i8.i8.i64(<vscale x 64 x i8> [[VD]], i8 [[RS1]], <vscale x 64 x i8> [[VS2]], i64 [[VL]], i64 2)584// CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP0]]585//586vuint8m8_t test_vmadd_vx_u8m8_tu(vuint8m8_t vd, uint8_t rs1, vuint8m8_t vs2, size_t vl) {587  return __riscv_vmadd_vx_u8m8_tu(vd, rs1, vs2, vl);588}589 590// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vmadd_vv_u16mf4_tu591// CHECK-RV64-SAME: (<vscale x 1 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS1:%.*]], <vscale x 1 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {592// CHECK-RV64-NEXT:  entry:593// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmadd.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[VD]], <vscale x 1 x i16> [[VS1]], <vscale x 1 x i16> [[VS2]], i64 [[VL]], i64 2)594// CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]595//596vuint16mf4_t test_vmadd_vv_u16mf4_tu(vuint16mf4_t vd, vuint16mf4_t vs1, vuint16mf4_t vs2, size_t vl) {597  return __riscv_vmadd_vv_u16mf4_tu(vd, vs1, vs2, vl);598}599 600// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vmadd_vx_u16mf4_tu601// CHECK-RV64-SAME: (<vscale x 1 x i16> [[VD:%.*]], i16 noundef zeroext [[RS1:%.*]], <vscale x 1 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {602// CHECK-RV64-NEXT:  entry:603// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmadd.nxv1i16.i16.i64(<vscale x 1 x i16> [[VD]], i16 [[RS1]], <vscale x 1 x i16> [[VS2]], i64 [[VL]], i64 2)604// CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]605//606vuint16mf4_t test_vmadd_vx_u16mf4_tu(vuint16mf4_t vd, uint16_t rs1, vuint16mf4_t vs2, size_t vl) {607  return __riscv_vmadd_vx_u16mf4_tu(vd, rs1, vs2, vl);608}609 610// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vmadd_vv_u16mf2_tu611// CHECK-RV64-SAME: (<vscale x 2 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS1:%.*]], <vscale x 2 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {612// CHECK-RV64-NEXT:  entry:613// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmadd.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 2 x i16> [[VS1]], <vscale x 2 x i16> [[VS2]], i64 [[VL]], i64 2)614// CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]615//616vuint16mf2_t test_vmadd_vv_u16mf2_tu(vuint16mf2_t vd, vuint16mf2_t vs1, vuint16mf2_t vs2, size_t vl) {617  return __riscv_vmadd_vv_u16mf2_tu(vd, vs1, vs2, vl);618}619 620// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vmadd_vx_u16mf2_tu621// CHECK-RV64-SAME: (<vscale x 2 x i16> [[VD:%.*]], i16 noundef zeroext [[RS1:%.*]], <vscale x 2 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {622// CHECK-RV64-NEXT:  entry:623// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmadd.nxv2i16.i16.i64(<vscale x 2 x i16> [[VD]], i16 [[RS1]], <vscale x 2 x i16> [[VS2]], i64 [[VL]], i64 2)624// CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]625//626vuint16mf2_t test_vmadd_vx_u16mf2_tu(vuint16mf2_t vd, uint16_t rs1, vuint16mf2_t vs2, size_t vl) {627  return __riscv_vmadd_vx_u16mf2_tu(vd, rs1, vs2, vl);628}629 630// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vmadd_vv_u16m1_tu631// CHECK-RV64-SAME: (<vscale x 4 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS1:%.*]], <vscale x 4 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {632// CHECK-RV64-NEXT:  entry:633// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmadd.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 4 x i16> [[VS1]], <vscale x 4 x i16> [[VS2]], i64 [[VL]], i64 2)634// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]635//636vuint16m1_t test_vmadd_vv_u16m1_tu(vuint16m1_t vd, vuint16m1_t vs1, vuint16m1_t vs2, size_t vl) {637  return __riscv_vmadd_vv_u16m1_tu(vd, vs1, vs2, vl);638}639 640// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vmadd_vx_u16m1_tu641// CHECK-RV64-SAME: (<vscale x 4 x i16> [[VD:%.*]], i16 noundef zeroext [[RS1:%.*]], <vscale x 4 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {642// CHECK-RV64-NEXT:  entry:643// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmadd.nxv4i16.i16.i64(<vscale x 4 x i16> [[VD]], i16 [[RS1]], <vscale x 4 x i16> [[VS2]], i64 [[VL]], i64 2)644// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]645//646vuint16m1_t test_vmadd_vx_u16m1_tu(vuint16m1_t vd, uint16_t rs1, vuint16m1_t vs2, size_t vl) {647  return __riscv_vmadd_vx_u16m1_tu(vd, rs1, vs2, vl);648}649 650// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vmadd_vv_u16m2_tu651// CHECK-RV64-SAME: (<vscale x 8 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS1:%.*]], <vscale x 8 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {652// CHECK-RV64-NEXT:  entry:653// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmadd.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 8 x i16> [[VS1]], <vscale x 8 x i16> [[VS2]], i64 [[VL]], i64 2)654// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]655//656vuint16m2_t test_vmadd_vv_u16m2_tu(vuint16m2_t vd, vuint16m2_t vs1, vuint16m2_t vs2, size_t vl) {657  return __riscv_vmadd_vv_u16m2_tu(vd, vs1, vs2, vl);658}659 660// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vmadd_vx_u16m2_tu661// CHECK-RV64-SAME: (<vscale x 8 x i16> [[VD:%.*]], i16 noundef zeroext [[RS1:%.*]], <vscale x 8 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {662// CHECK-RV64-NEXT:  entry:663// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmadd.nxv8i16.i16.i64(<vscale x 8 x i16> [[VD]], i16 [[RS1]], <vscale x 8 x i16> [[VS2]], i64 [[VL]], i64 2)664// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]665//666vuint16m2_t test_vmadd_vx_u16m2_tu(vuint16m2_t vd, uint16_t rs1, vuint16m2_t vs2, size_t vl) {667  return __riscv_vmadd_vx_u16m2_tu(vd, rs1, vs2, vl);668}669 670// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vmadd_vv_u16m4_tu671// CHECK-RV64-SAME: (<vscale x 16 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS1:%.*]], <vscale x 16 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {672// CHECK-RV64-NEXT:  entry:673// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmadd.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 16 x i16> [[VS1]], <vscale x 16 x i16> [[VS2]], i64 [[VL]], i64 2)674// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]675//676vuint16m4_t test_vmadd_vv_u16m4_tu(vuint16m4_t vd, vuint16m4_t vs1, vuint16m4_t vs2, size_t vl) {677  return __riscv_vmadd_vv_u16m4_tu(vd, vs1, vs2, vl);678}679 680// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vmadd_vx_u16m4_tu681// CHECK-RV64-SAME: (<vscale x 16 x i16> [[VD:%.*]], i16 noundef zeroext [[RS1:%.*]], <vscale x 16 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {682// CHECK-RV64-NEXT:  entry:683// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmadd.nxv16i16.i16.i64(<vscale x 16 x i16> [[VD]], i16 [[RS1]], <vscale x 16 x i16> [[VS2]], i64 [[VL]], i64 2)684// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]685//686vuint16m4_t test_vmadd_vx_u16m4_tu(vuint16m4_t vd, uint16_t rs1, vuint16m4_t vs2, size_t vl) {687  return __riscv_vmadd_vx_u16m4_tu(vd, rs1, vs2, vl);688}689 690// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vmadd_vv_u16m8_tu691// CHECK-RV64-SAME: (<vscale x 32 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS1:%.*]], <vscale x 32 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {692// CHECK-RV64-NEXT:  entry:693// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmadd.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[VD]], <vscale x 32 x i16> [[VS1]], <vscale x 32 x i16> [[VS2]], i64 [[VL]], i64 2)694// CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]695//696vuint16m8_t test_vmadd_vv_u16m8_tu(vuint16m8_t vd, vuint16m8_t vs1, vuint16m8_t vs2, size_t vl) {697  return __riscv_vmadd_vv_u16m8_tu(vd, vs1, vs2, vl);698}699 700// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vmadd_vx_u16m8_tu701// CHECK-RV64-SAME: (<vscale x 32 x i16> [[VD:%.*]], i16 noundef zeroext [[RS1:%.*]], <vscale x 32 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {702// CHECK-RV64-NEXT:  entry:703// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmadd.nxv32i16.i16.i64(<vscale x 32 x i16> [[VD]], i16 [[RS1]], <vscale x 32 x i16> [[VS2]], i64 [[VL]], i64 2)704// CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]705//706vuint16m8_t test_vmadd_vx_u16m8_tu(vuint16m8_t vd, uint16_t rs1, vuint16m8_t vs2, size_t vl) {707  return __riscv_vmadd_vx_u16m8_tu(vd, rs1, vs2, vl);708}709 710// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vmadd_vv_u32mf2_tu711// CHECK-RV64-SAME: (<vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS1:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {712// CHECK-RV64-NEXT:  entry:713// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmadd.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i32> [[VS2]], i64 [[VL]], i64 2)714// CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]715//716vuint32mf2_t test_vmadd_vv_u32mf2_tu(vuint32mf2_t vd, vuint32mf2_t vs1, vuint32mf2_t vs2, size_t vl) {717  return __riscv_vmadd_vv_u32mf2_tu(vd, vs1, vs2, vl);718}719 720// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vmadd_vx_u32mf2_tu721// CHECK-RV64-SAME: (<vscale x 1 x i32> [[VD:%.*]], i32 noundef signext [[RS1:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {722// CHECK-RV64-NEXT:  entry:723// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmadd.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], i32 [[RS1]], <vscale x 1 x i32> [[VS2]], i64 [[VL]], i64 2)724// CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]725//726vuint32mf2_t test_vmadd_vx_u32mf2_tu(vuint32mf2_t vd, uint32_t rs1, vuint32mf2_t vs2, size_t vl) {727  return __riscv_vmadd_vx_u32mf2_tu(vd, rs1, vs2, vl);728}729 730// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vmadd_vv_u32m1_tu731// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS1:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {732// CHECK-RV64-NEXT:  entry:733// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmadd.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i32> [[VS2]], i64 [[VL]], i64 2)734// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]735//736vuint32m1_t test_vmadd_vv_u32m1_tu(vuint32m1_t vd, vuint32m1_t vs1, vuint32m1_t vs2, size_t vl) {737  return __riscv_vmadd_vv_u32m1_tu(vd, vs1, vs2, vl);738}739 740// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vmadd_vx_u32m1_tu741// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], i32 noundef signext [[RS1:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {742// CHECK-RV64-NEXT:  entry:743// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmadd.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], i32 [[RS1]], <vscale x 2 x i32> [[VS2]], i64 [[VL]], i64 2)744// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]745//746vuint32m1_t test_vmadd_vx_u32m1_tu(vuint32m1_t vd, uint32_t rs1, vuint32m1_t vs2, size_t vl) {747  return __riscv_vmadd_vx_u32m1_tu(vd, rs1, vs2, vl);748}749 750// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vmadd_vv_u32m2_tu751// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS1:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {752// CHECK-RV64-NEXT:  entry:753// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmadd.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i32> [[VS2]], i64 [[VL]], i64 2)754// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]755//756vuint32m2_t test_vmadd_vv_u32m2_tu(vuint32m2_t vd, vuint32m2_t vs1, vuint32m2_t vs2, size_t vl) {757  return __riscv_vmadd_vv_u32m2_tu(vd, vs1, vs2, vl);758}759 760// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vmadd_vx_u32m2_tu761// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], i32 noundef signext [[RS1:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {762// CHECK-RV64-NEXT:  entry:763// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmadd.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], i32 [[RS1]], <vscale x 4 x i32> [[VS2]], i64 [[VL]], i64 2)764// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]765//766vuint32m2_t test_vmadd_vx_u32m2_tu(vuint32m2_t vd, uint32_t rs1, vuint32m2_t vs2, size_t vl) {767  return __riscv_vmadd_vx_u32m2_tu(vd, rs1, vs2, vl);768}769 770// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vmadd_vv_u32m4_tu771// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS1:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {772// CHECK-RV64-NEXT:  entry:773// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmadd.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i32> [[VS2]], i64 [[VL]], i64 2)774// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]775//776vuint32m4_t test_vmadd_vv_u32m4_tu(vuint32m4_t vd, vuint32m4_t vs1, vuint32m4_t vs2, size_t vl) {777  return __riscv_vmadd_vv_u32m4_tu(vd, vs1, vs2, vl);778}779 780// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vmadd_vx_u32m4_tu781// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], i32 noundef signext [[RS1:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {782// CHECK-RV64-NEXT:  entry:783// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmadd.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], i32 [[RS1]], <vscale x 8 x i32> [[VS2]], i64 [[VL]], i64 2)784// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]785//786vuint32m4_t test_vmadd_vx_u32m4_tu(vuint32m4_t vd, uint32_t rs1, vuint32m4_t vs2, size_t vl) {787  return __riscv_vmadd_vx_u32m4_tu(vd, rs1, vs2, vl);788}789 790// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vmadd_vv_u32m8_tu791// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS1:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {792// CHECK-RV64-NEXT:  entry:793// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmadd.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i32> [[VS2]], i64 [[VL]], i64 2)794// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]795//796vuint32m8_t test_vmadd_vv_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs1, vuint32m8_t vs2, size_t vl) {797  return __riscv_vmadd_vv_u32m8_tu(vd, vs1, vs2, vl);798}799 800// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vmadd_vx_u32m8_tu801// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], i32 noundef signext [[RS1:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {802// CHECK-RV64-NEXT:  entry:803// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmadd.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], i32 [[RS1]], <vscale x 16 x i32> [[VS2]], i64 [[VL]], i64 2)804// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]805//806vuint32m8_t test_vmadd_vx_u32m8_tu(vuint32m8_t vd, uint32_t rs1, vuint32m8_t vs2, size_t vl) {807  return __riscv_vmadd_vx_u32m8_tu(vd, rs1, vs2, vl);808}809 810// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vmadd_vv_u64m1_tu811// CHECK-RV64-SAME: (<vscale x 1 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS1:%.*]], <vscale x 1 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {812// CHECK-RV64-NEXT:  entry:813// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[VD]], <vscale x 1 x i64> [[VS1]], <vscale x 1 x i64> [[VS2]], i64 [[VL]], i64 2)814// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]815//816vuint64m1_t test_vmadd_vv_u64m1_tu(vuint64m1_t vd, vuint64m1_t vs1, vuint64m1_t vs2, size_t vl) {817  return __riscv_vmadd_vv_u64m1_tu(vd, vs1, vs2, vl);818}819 820// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vmadd_vx_u64m1_tu821// CHECK-RV64-SAME: (<vscale x 1 x i64> [[VD:%.*]], i64 noundef [[RS1:%.*]], <vscale x 1 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {822// CHECK-RV64-NEXT:  entry:823// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmadd.nxv1i64.i64.i64(<vscale x 1 x i64> [[VD]], i64 [[RS1]], <vscale x 1 x i64> [[VS2]], i64 [[VL]], i64 2)824// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]825//826vuint64m1_t test_vmadd_vx_u64m1_tu(vuint64m1_t vd, uint64_t rs1, vuint64m1_t vs2, size_t vl) {827  return __riscv_vmadd_vx_u64m1_tu(vd, rs1, vs2, vl);828}829 830// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vmadd_vv_u64m2_tu831// CHECK-RV64-SAME: (<vscale x 2 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS1:%.*]], <vscale x 2 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {832// CHECK-RV64-NEXT:  entry:833// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmadd.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 2 x i64> [[VS1]], <vscale x 2 x i64> [[VS2]], i64 [[VL]], i64 2)834// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]835//836vuint64m2_t test_vmadd_vv_u64m2_tu(vuint64m2_t vd, vuint64m2_t vs1, vuint64m2_t vs2, size_t vl) {837  return __riscv_vmadd_vv_u64m2_tu(vd, vs1, vs2, vl);838}839 840// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vmadd_vx_u64m2_tu841// CHECK-RV64-SAME: (<vscale x 2 x i64> [[VD:%.*]], i64 noundef [[RS1:%.*]], <vscale x 2 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {842// CHECK-RV64-NEXT:  entry:843// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmadd.nxv2i64.i64.i64(<vscale x 2 x i64> [[VD]], i64 [[RS1]], <vscale x 2 x i64> [[VS2]], i64 [[VL]], i64 2)844// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]845//846vuint64m2_t test_vmadd_vx_u64m2_tu(vuint64m2_t vd, uint64_t rs1, vuint64m2_t vs2, size_t vl) {847  return __riscv_vmadd_vx_u64m2_tu(vd, rs1, vs2, vl);848}849 850// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vmadd_vv_u64m4_tu851// CHECK-RV64-SAME: (<vscale x 4 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS1:%.*]], <vscale x 4 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {852// CHECK-RV64-NEXT:  entry:853// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmadd.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 4 x i64> [[VS1]], <vscale x 4 x i64> [[VS2]], i64 [[VL]], i64 2)854// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]855//856vuint64m4_t test_vmadd_vv_u64m4_tu(vuint64m4_t vd, vuint64m4_t vs1, vuint64m4_t vs2, size_t vl) {857  return __riscv_vmadd_vv_u64m4_tu(vd, vs1, vs2, vl);858}859 860// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vmadd_vx_u64m4_tu861// CHECK-RV64-SAME: (<vscale x 4 x i64> [[VD:%.*]], i64 noundef [[RS1:%.*]], <vscale x 4 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {862// CHECK-RV64-NEXT:  entry:863// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmadd.nxv4i64.i64.i64(<vscale x 4 x i64> [[VD]], i64 [[RS1]], <vscale x 4 x i64> [[VS2]], i64 [[VL]], i64 2)864// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]865//866vuint64m4_t test_vmadd_vx_u64m4_tu(vuint64m4_t vd, uint64_t rs1, vuint64m4_t vs2, size_t vl) {867  return __riscv_vmadd_vx_u64m4_tu(vd, rs1, vs2, vl);868}869 870// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vmadd_vv_u64m8_tu871// CHECK-RV64-SAME: (<vscale x 8 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS1:%.*]], <vscale x 8 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {872// CHECK-RV64-NEXT:  entry:873// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmadd.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[VD]], <vscale x 8 x i64> [[VS1]], <vscale x 8 x i64> [[VS2]], i64 [[VL]], i64 2)874// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]875//876vuint64m8_t test_vmadd_vv_u64m8_tu(vuint64m8_t vd, vuint64m8_t vs1, vuint64m8_t vs2, size_t vl) {877  return __riscv_vmadd_vv_u64m8_tu(vd, vs1, vs2, vl);878}879 880// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vmadd_vx_u64m8_tu881// CHECK-RV64-SAME: (<vscale x 8 x i64> [[VD:%.*]], i64 noundef [[RS1:%.*]], <vscale x 8 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {882// CHECK-RV64-NEXT:  entry:883// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmadd.nxv8i64.i64.i64(<vscale x 8 x i64> [[VD]], i64 [[RS1]], <vscale x 8 x i64> [[VS2]], i64 [[VL]], i64 2)884// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]885//886vuint64m8_t test_vmadd_vx_u64m8_tu(vuint64m8_t vd, uint64_t rs1, vuint64m8_t vs2, size_t vl) {887  return __riscv_vmadd_vx_u64m8_tu(vd, rs1, vs2, vl);888}889 890// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vmadd_vv_i8mf8_tum891// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS1:%.*]], <vscale x 1 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {892// CHECK-RV64-NEXT:  entry:893// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmadd.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[VD]], <vscale x 1 x i8> [[VS1]], <vscale x 1 x i8> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)894// CHECK-RV64-NEXT:    ret <vscale x 1 x i8> [[TMP0]]895//896vint8mf8_t test_vmadd_vv_i8mf8_tum(vbool64_t mask, vint8mf8_t vd, vint8mf8_t vs1, vint8mf8_t vs2, size_t vl) {897  return __riscv_vmadd_vv_i8mf8_tum(mask, vd, vs1, vs2, vl);898}899 900// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vmadd_vx_i8mf8_tum901// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[VD:%.*]], i8 noundef signext [[RS1:%.*]], <vscale x 1 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {902// CHECK-RV64-NEXT:  entry:903// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmadd.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[VD]], i8 [[RS1]], <vscale x 1 x i8> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)904// CHECK-RV64-NEXT:    ret <vscale x 1 x i8> [[TMP0]]905//906vint8mf8_t test_vmadd_vx_i8mf8_tum(vbool64_t mask, vint8mf8_t vd, int8_t rs1, vint8mf8_t vs2, size_t vl) {907  return __riscv_vmadd_vx_i8mf8_tum(mask, vd, rs1, vs2, vl);908}909 910// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vmadd_vv_i8mf4_tum911// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS1:%.*]], <vscale x 2 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {912// CHECK-RV64-NEXT:  entry:913// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmadd.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 2 x i8> [[VS1]], <vscale x 2 x i8> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)914// CHECK-RV64-NEXT:    ret <vscale x 2 x i8> [[TMP0]]915//916vint8mf4_t test_vmadd_vv_i8mf4_tum(vbool32_t mask, vint8mf4_t vd, vint8mf4_t vs1, vint8mf4_t vs2, size_t vl) {917  return __riscv_vmadd_vv_i8mf4_tum(mask, vd, vs1, vs2, vl);918}919 920// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vmadd_vx_i8mf4_tum921// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[VD:%.*]], i8 noundef signext [[RS1:%.*]], <vscale x 2 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {922// CHECK-RV64-NEXT:  entry:923// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmadd.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[VD]], i8 [[RS1]], <vscale x 2 x i8> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)924// CHECK-RV64-NEXT:    ret <vscale x 2 x i8> [[TMP0]]925//926vint8mf4_t test_vmadd_vx_i8mf4_tum(vbool32_t mask, vint8mf4_t vd, int8_t rs1, vint8mf4_t vs2, size_t vl) {927  return __riscv_vmadd_vx_i8mf4_tum(mask, vd, rs1, vs2, vl);928}929 930// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vmadd_vv_i8mf2_tum931// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS1:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {932// CHECK-RV64-NEXT:  entry:933// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmadd.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 4 x i8> [[VS1]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)934// CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[TMP0]]935//936vint8mf2_t test_vmadd_vv_i8mf2_tum(vbool16_t mask, vint8mf2_t vd, vint8mf2_t vs1, vint8mf2_t vs2, size_t vl) {937  return __riscv_vmadd_vv_i8mf2_tum(mask, vd, vs1, vs2, vl);938}939 940// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vmadd_vx_i8mf2_tum941// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[VD:%.*]], i8 noundef signext [[RS1:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {942// CHECK-RV64-NEXT:  entry:943// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmadd.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[VD]], i8 [[RS1]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)944// CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[TMP0]]945//946vint8mf2_t test_vmadd_vx_i8mf2_tum(vbool16_t mask, vint8mf2_t vd, int8_t rs1, vint8mf2_t vs2, size_t vl) {947  return __riscv_vmadd_vx_i8mf2_tum(mask, vd, rs1, vs2, vl);948}949 950// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vmadd_vv_i8m1_tum951// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {952// CHECK-RV64-NEXT:  entry:953// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmadd.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)954// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]955//956vint8m1_t test_vmadd_vv_i8m1_tum(vbool8_t mask, vint8m1_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) {957  return __riscv_vmadd_vv_i8m1_tum(mask, vd, vs1, vs2, vl);958}959 960// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vmadd_vx_i8m1_tum961// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[VD:%.*]], i8 noundef signext [[RS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {962// CHECK-RV64-NEXT:  entry:963// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmadd.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[VD]], i8 [[RS1]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)964// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]965//966vint8m1_t test_vmadd_vx_i8m1_tum(vbool8_t mask, vint8m1_t vd, int8_t rs1, vint8m1_t vs2, size_t vl) {967  return __riscv_vmadd_vx_i8m1_tum(mask, vd, rs1, vs2, vl);968}969 970// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vmadd_vv_i8m2_tum971// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {972// CHECK-RV64-NEXT:  entry:973// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmadd.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 16 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)974// CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]975//976vint8m2_t test_vmadd_vv_i8m2_tum(vbool4_t mask, vint8m2_t vd, vint8m2_t vs1, vint8m2_t vs2, size_t vl) {977  return __riscv_vmadd_vv_i8m2_tum(mask, vd, vs1, vs2, vl);978}979 980// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vmadd_vx_i8m2_tum981// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[VD:%.*]], i8 noundef signext [[RS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {982// CHECK-RV64-NEXT:  entry:983// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmadd.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[VD]], i8 [[RS1]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)984// CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]985//986vint8m2_t test_vmadd_vx_i8m2_tum(vbool4_t mask, vint8m2_t vd, int8_t rs1, vint8m2_t vs2, size_t vl) {987  return __riscv_vmadd_vx_i8m2_tum(mask, vd, rs1, vs2, vl);988}989 990// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vmadd_vv_i8m4_tum991// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {992// CHECK-RV64-NEXT:  entry:993// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmadd.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 32 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2)994// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]995//996vint8m4_t test_vmadd_vv_i8m4_tum(vbool2_t mask, vint8m4_t vd, vint8m4_t vs1, vint8m4_t vs2, size_t vl) {997  return __riscv_vmadd_vv_i8m4_tum(mask, vd, vs1, vs2, vl);998}999 1000// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vmadd_vx_i8m4_tum1001// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[VD:%.*]], i8 noundef signext [[RS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1002// CHECK-RV64-NEXT:  entry:1003// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmadd.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[VD]], i8 [[RS1]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2)1004// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]1005//1006vint8m4_t test_vmadd_vx_i8m4_tum(vbool2_t mask, vint8m4_t vd, int8_t rs1, vint8m4_t vs2, size_t vl) {1007  return __riscv_vmadd_vx_i8m4_tum(mask, vd, rs1, vs2, vl);1008}1009 1010// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vmadd_vv_i8m8_tum1011// CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[VD:%.*]], <vscale x 64 x i8> [[VS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1012// CHECK-RV64-NEXT:  entry:1013// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmadd.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[VD]], <vscale x 64 x i8> [[VS1]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 2)1014// CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP0]]1015//1016vint8m8_t test_vmadd_vv_i8m8_tum(vbool1_t mask, vint8m8_t vd, vint8m8_t vs1, vint8m8_t vs2, size_t vl) {1017  return __riscv_vmadd_vv_i8m8_tum(mask, vd, vs1, vs2, vl);1018}1019 1020// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vmadd_vx_i8m8_tum1021// CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[VD:%.*]], i8 noundef signext [[RS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1022// CHECK-RV64-NEXT:  entry:1023// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmadd.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[VD]], i8 [[RS1]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 2)1024// CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP0]]1025//1026vint8m8_t test_vmadd_vx_i8m8_tum(vbool1_t mask, vint8m8_t vd, int8_t rs1, vint8m8_t vs2, size_t vl) {1027  return __riscv_vmadd_vx_i8m8_tum(mask, vd, rs1, vs2, vl);1028}1029 1030// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vmadd_vv_i16mf4_tum1031// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS1:%.*]], <vscale x 1 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1032// CHECK-RV64-NEXT:  entry:1033// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmadd.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[VD]], <vscale x 1 x i16> [[VS1]], <vscale x 1 x i16> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)1034// CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]1035//1036vint16mf4_t test_vmadd_vv_i16mf4_tum(vbool64_t mask, vint16mf4_t vd, vint16mf4_t vs1, vint16mf4_t vs2, size_t vl) {1037  return __riscv_vmadd_vv_i16mf4_tum(mask, vd, vs1, vs2, vl);1038}1039 1040// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vmadd_vx_i16mf4_tum1041// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[VD:%.*]], i16 noundef signext [[RS1:%.*]], <vscale x 1 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1042// CHECK-RV64-NEXT:  entry:1043// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmadd.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[VD]], i16 [[RS1]], <vscale x 1 x i16> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)1044// CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]1045//1046vint16mf4_t test_vmadd_vx_i16mf4_tum(vbool64_t mask, vint16mf4_t vd, int16_t rs1, vint16mf4_t vs2, size_t vl) {1047  return __riscv_vmadd_vx_i16mf4_tum(mask, vd, rs1, vs2, vl);1048}1049 1050// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vmadd_vv_i16mf2_tum1051// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS1:%.*]], <vscale x 2 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1052// CHECK-RV64-NEXT:  entry:1053// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmadd.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 2 x i16> [[VS1]], <vscale x 2 x i16> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)1054// CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]1055//1056vint16mf2_t test_vmadd_vv_i16mf2_tum(vbool32_t mask, vint16mf2_t vd, vint16mf2_t vs1, vint16mf2_t vs2, size_t vl) {1057  return __riscv_vmadd_vv_i16mf2_tum(mask, vd, vs1, vs2, vl);1058}1059 1060// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vmadd_vx_i16mf2_tum1061// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[VD:%.*]], i16 noundef signext [[RS1:%.*]], <vscale x 2 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1062// CHECK-RV64-NEXT:  entry:1063// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmadd.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[VD]], i16 [[RS1]], <vscale x 2 x i16> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)1064// CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]1065//1066vint16mf2_t test_vmadd_vx_i16mf2_tum(vbool32_t mask, vint16mf2_t vd, int16_t rs1, vint16mf2_t vs2, size_t vl) {1067  return __riscv_vmadd_vx_i16mf2_tum(mask, vd, rs1, vs2, vl);1068}1069 1070// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vmadd_vv_i16m1_tum1071// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS1:%.*]], <vscale x 4 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1072// CHECK-RV64-NEXT:  entry:1073// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmadd.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 4 x i16> [[VS1]], <vscale x 4 x i16> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)1074// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]1075//1076vint16m1_t test_vmadd_vv_i16m1_tum(vbool16_t mask, vint16m1_t vd, vint16m1_t vs1, vint16m1_t vs2, size_t vl) {1077  return __riscv_vmadd_vv_i16m1_tum(mask, vd, vs1, vs2, vl);1078}1079 1080// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vmadd_vx_i16m1_tum1081// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[VD:%.*]], i16 noundef signext [[RS1:%.*]], <vscale x 4 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1082// CHECK-RV64-NEXT:  entry:1083// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmadd.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[VD]], i16 [[RS1]], <vscale x 4 x i16> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)1084// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]1085//1086vint16m1_t test_vmadd_vx_i16m1_tum(vbool16_t mask, vint16m1_t vd, int16_t rs1, vint16m1_t vs2, size_t vl) {1087  return __riscv_vmadd_vx_i16m1_tum(mask, vd, rs1, vs2, vl);1088}1089 1090// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vmadd_vv_i16m2_tum1091// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS1:%.*]], <vscale x 8 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1092// CHECK-RV64-NEXT:  entry:1093// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmadd.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 8 x i16> [[VS1]], <vscale x 8 x i16> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)1094// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]1095//1096vint16m2_t test_vmadd_vv_i16m2_tum(vbool8_t mask, vint16m2_t vd, vint16m2_t vs1, vint16m2_t vs2, size_t vl) {1097  return __riscv_vmadd_vv_i16m2_tum(mask, vd, vs1, vs2, vl);1098}1099 1100// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vmadd_vx_i16m2_tum1101// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[VD:%.*]], i16 noundef signext [[RS1:%.*]], <vscale x 8 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1102// CHECK-RV64-NEXT:  entry:1103// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmadd.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[VD]], i16 [[RS1]], <vscale x 8 x i16> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)1104// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]1105//1106vint16m2_t test_vmadd_vx_i16m2_tum(vbool8_t mask, vint16m2_t vd, int16_t rs1, vint16m2_t vs2, size_t vl) {1107  return __riscv_vmadd_vx_i16m2_tum(mask, vd, rs1, vs2, vl);1108}1109 1110// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vmadd_vv_i16m4_tum1111// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS1:%.*]], <vscale x 16 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1112// CHECK-RV64-NEXT:  entry:1113// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmadd.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 16 x i16> [[VS1]], <vscale x 16 x i16> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)1114// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]1115//1116vint16m4_t test_vmadd_vv_i16m4_tum(vbool4_t mask, vint16m4_t vd, vint16m4_t vs1, vint16m4_t vs2, size_t vl) {1117  return __riscv_vmadd_vv_i16m4_tum(mask, vd, vs1, vs2, vl);1118}1119 1120// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vmadd_vx_i16m4_tum1121// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[VD:%.*]], i16 noundef signext [[RS1:%.*]], <vscale x 16 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1122// CHECK-RV64-NEXT:  entry:1123// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmadd.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[VD]], i16 [[RS1]], <vscale x 16 x i16> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)1124// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]1125//1126vint16m4_t test_vmadd_vx_i16m4_tum(vbool4_t mask, vint16m4_t vd, int16_t rs1, vint16m4_t vs2, size_t vl) {1127  return __riscv_vmadd_vx_i16m4_tum(mask, vd, rs1, vs2, vl);1128}1129 1130// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vmadd_vv_i16m8_tum1131// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS1:%.*]], <vscale x 32 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1132// CHECK-RV64-NEXT:  entry:1133// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmadd.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[VD]], <vscale x 32 x i16> [[VS1]], <vscale x 32 x i16> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2)1134// CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]1135//1136vint16m8_t test_vmadd_vv_i16m8_tum(vbool2_t mask, vint16m8_t vd, vint16m8_t vs1, vint16m8_t vs2, size_t vl) {1137  return __riscv_vmadd_vv_i16m8_tum(mask, vd, vs1, vs2, vl);1138}1139 1140// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vmadd_vx_i16m8_tum1141// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[VD:%.*]], i16 noundef signext [[RS1:%.*]], <vscale x 32 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1142// CHECK-RV64-NEXT:  entry:1143// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmadd.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[VD]], i16 [[RS1]], <vscale x 32 x i16> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2)1144// CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]1145//1146vint16m8_t test_vmadd_vx_i16m8_tum(vbool2_t mask, vint16m8_t vd, int16_t rs1, vint16m8_t vs2, size_t vl) {1147  return __riscv_vmadd_vx_i16m8_tum(mask, vd, rs1, vs2, vl);1148}1149 1150// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vmadd_vv_i32mf2_tum1151// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS1:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1152// CHECK-RV64-NEXT:  entry:1153// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmadd.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)1154// CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]1155//1156vint32mf2_t test_vmadd_vv_i32mf2_tum(vbool64_t mask, vint32mf2_t vd, vint32mf2_t vs1, vint32mf2_t vs2, size_t vl) {1157  return __riscv_vmadd_vv_i32mf2_tum(mask, vd, vs1, vs2, vl);1158}1159 1160// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vmadd_vx_i32mf2_tum1161// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[VD:%.*]], i32 noundef signext [[RS1:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1162// CHECK-RV64-NEXT:  entry:1163// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmadd.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], i32 [[RS1]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)1164// CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]1165//1166vint32mf2_t test_vmadd_vx_i32mf2_tum(vbool64_t mask, vint32mf2_t vd, int32_t rs1, vint32mf2_t vs2, size_t vl) {1167  return __riscv_vmadd_vx_i32mf2_tum(mask, vd, rs1, vs2, vl);1168}1169 1170// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vmadd_vv_i32m1_tum1171// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS1:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1172// CHECK-RV64-NEXT:  entry:1173// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmadd.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)1174// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]1175//1176vint32m1_t test_vmadd_vv_i32m1_tum(vbool32_t mask, vint32m1_t vd, vint32m1_t vs1, vint32m1_t vs2, size_t vl) {1177  return __riscv_vmadd_vv_i32m1_tum(mask, vd, vs1, vs2, vl);1178}1179 1180// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vmadd_vx_i32m1_tum1181// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[VD:%.*]], i32 noundef signext [[RS1:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1182// CHECK-RV64-NEXT:  entry:1183// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmadd.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], i32 [[RS1]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)1184// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]1185//1186vint32m1_t test_vmadd_vx_i32m1_tum(vbool32_t mask, vint32m1_t vd, int32_t rs1, vint32m1_t vs2, size_t vl) {1187  return __riscv_vmadd_vx_i32m1_tum(mask, vd, rs1, vs2, vl);1188}1189 1190// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vmadd_vv_i32m2_tum1191// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS1:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1192// CHECK-RV64-NEXT:  entry:1193// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmadd.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)1194// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]1195//1196vint32m2_t test_vmadd_vv_i32m2_tum(vbool16_t mask, vint32m2_t vd, vint32m2_t vs1, vint32m2_t vs2, size_t vl) {1197  return __riscv_vmadd_vv_i32m2_tum(mask, vd, vs1, vs2, vl);1198}1199 1200// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vmadd_vx_i32m2_tum1201// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[VD:%.*]], i32 noundef signext [[RS1:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1202// CHECK-RV64-NEXT:  entry:1203// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmadd.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], i32 [[RS1]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)1204// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]1205//1206vint32m2_t test_vmadd_vx_i32m2_tum(vbool16_t mask, vint32m2_t vd, int32_t rs1, vint32m2_t vs2, size_t vl) {1207  return __riscv_vmadd_vx_i32m2_tum(mask, vd, rs1, vs2, vl);1208}1209 1210// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vmadd_vv_i32m4_tum1211// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS1:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1212// CHECK-RV64-NEXT:  entry:1213// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmadd.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)1214// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]1215//1216vint32m4_t test_vmadd_vv_i32m4_tum(vbool8_t mask, vint32m4_t vd, vint32m4_t vs1, vint32m4_t vs2, size_t vl) {1217  return __riscv_vmadd_vv_i32m4_tum(mask, vd, vs1, vs2, vl);1218}1219 1220// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vmadd_vx_i32m4_tum1221// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[VD:%.*]], i32 noundef signext [[RS1:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1222// CHECK-RV64-NEXT:  entry:1223// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmadd.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], i32 [[RS1]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)1224// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]1225//1226vint32m4_t test_vmadd_vx_i32m4_tum(vbool8_t mask, vint32m4_t vd, int32_t rs1, vint32m4_t vs2, size_t vl) {1227  return __riscv_vmadd_vx_i32m4_tum(mask, vd, rs1, vs2, vl);1228}1229 1230// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vmadd_vv_i32m8_tum1231// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS1:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1232// CHECK-RV64-NEXT:  entry:1233// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmadd.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)1234// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]1235//1236vint32m8_t test_vmadd_vv_i32m8_tum(vbool4_t mask, vint32m8_t vd, vint32m8_t vs1, vint32m8_t vs2, size_t vl) {1237  return __riscv_vmadd_vv_i32m8_tum(mask, vd, vs1, vs2, vl);1238}1239 1240// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vmadd_vx_i32m8_tum1241// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[VD:%.*]], i32 noundef signext [[RS1:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1242// CHECK-RV64-NEXT:  entry:1243// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmadd.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], i32 [[RS1]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)1244// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]1245//1246vint32m8_t test_vmadd_vx_i32m8_tum(vbool4_t mask, vint32m8_t vd, int32_t rs1, vint32m8_t vs2, size_t vl) {1247  return __riscv_vmadd_vx_i32m8_tum(mask, vd, rs1, vs2, vl);1248}1249 1250// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vmadd_vv_i64m1_tum1251// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS1:%.*]], <vscale x 1 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1252// CHECK-RV64-NEXT:  entry:1253// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmadd.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[VD]], <vscale x 1 x i64> [[VS1]], <vscale x 1 x i64> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)1254// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]1255//1256vint64m1_t test_vmadd_vv_i64m1_tum(vbool64_t mask, vint64m1_t vd, vint64m1_t vs1, vint64m1_t vs2, size_t vl) {1257  return __riscv_vmadd_vv_i64m1_tum(mask, vd, vs1, vs2, vl);1258}1259 1260// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vmadd_vx_i64m1_tum1261// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[VD:%.*]], i64 noundef [[RS1:%.*]], <vscale x 1 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1262// CHECK-RV64-NEXT:  entry:1263// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmadd.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[VD]], i64 [[RS1]], <vscale x 1 x i64> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)1264// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]1265//1266vint64m1_t test_vmadd_vx_i64m1_tum(vbool64_t mask, vint64m1_t vd, int64_t rs1, vint64m1_t vs2, size_t vl) {1267  return __riscv_vmadd_vx_i64m1_tum(mask, vd, rs1, vs2, vl);1268}1269 1270// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vmadd_vv_i64m2_tum1271// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS1:%.*]], <vscale x 2 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1272// CHECK-RV64-NEXT:  entry:1273// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmadd.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 2 x i64> [[VS1]], <vscale x 2 x i64> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)1274// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]1275//1276vint64m2_t test_vmadd_vv_i64m2_tum(vbool32_t mask, vint64m2_t vd, vint64m2_t vs1, vint64m2_t vs2, size_t vl) {1277  return __riscv_vmadd_vv_i64m2_tum(mask, vd, vs1, vs2, vl);1278}1279 1280// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vmadd_vx_i64m2_tum1281// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[VD:%.*]], i64 noundef [[RS1:%.*]], <vscale x 2 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1282// CHECK-RV64-NEXT:  entry:1283// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmadd.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[VD]], i64 [[RS1]], <vscale x 2 x i64> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)1284// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]1285//1286vint64m2_t test_vmadd_vx_i64m2_tum(vbool32_t mask, vint64m2_t vd, int64_t rs1, vint64m2_t vs2, size_t vl) {1287  return __riscv_vmadd_vx_i64m2_tum(mask, vd, rs1, vs2, vl);1288}1289 1290// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vmadd_vv_i64m4_tum1291// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS1:%.*]], <vscale x 4 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1292// CHECK-RV64-NEXT:  entry:1293// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmadd.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 4 x i64> [[VS1]], <vscale x 4 x i64> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)1294// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]1295//1296vint64m4_t test_vmadd_vv_i64m4_tum(vbool16_t mask, vint64m4_t vd, vint64m4_t vs1, vint64m4_t vs2, size_t vl) {1297  return __riscv_vmadd_vv_i64m4_tum(mask, vd, vs1, vs2, vl);1298}1299 1300// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vmadd_vx_i64m4_tum1301// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[VD:%.*]], i64 noundef [[RS1:%.*]], <vscale x 4 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1302// CHECK-RV64-NEXT:  entry:1303// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmadd.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[VD]], i64 [[RS1]], <vscale x 4 x i64> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)1304// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]1305//1306vint64m4_t test_vmadd_vx_i64m4_tum(vbool16_t mask, vint64m4_t vd, int64_t rs1, vint64m4_t vs2, size_t vl) {1307  return __riscv_vmadd_vx_i64m4_tum(mask, vd, rs1, vs2, vl);1308}1309 1310// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vmadd_vv_i64m8_tum1311// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS1:%.*]], <vscale x 8 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1312// CHECK-RV64-NEXT:  entry:1313// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmadd.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[VD]], <vscale x 8 x i64> [[VS1]], <vscale x 8 x i64> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)1314// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]1315//1316vint64m8_t test_vmadd_vv_i64m8_tum(vbool8_t mask, vint64m8_t vd, vint64m8_t vs1, vint64m8_t vs2, size_t vl) {1317  return __riscv_vmadd_vv_i64m8_tum(mask, vd, vs1, vs2, vl);1318}1319 1320// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vmadd_vx_i64m8_tum1321// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[VD:%.*]], i64 noundef [[RS1:%.*]], <vscale x 8 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1322// CHECK-RV64-NEXT:  entry:1323// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmadd.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[VD]], i64 [[RS1]], <vscale x 8 x i64> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)1324// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]1325//1326vint64m8_t test_vmadd_vx_i64m8_tum(vbool8_t mask, vint64m8_t vd, int64_t rs1, vint64m8_t vs2, size_t vl) {1327  return __riscv_vmadd_vx_i64m8_tum(mask, vd, rs1, vs2, vl);1328}1329 1330// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vmadd_vv_u8mf8_tum1331// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS1:%.*]], <vscale x 1 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1332// CHECK-RV64-NEXT:  entry:1333// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmadd.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[VD]], <vscale x 1 x i8> [[VS1]], <vscale x 1 x i8> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)1334// CHECK-RV64-NEXT:    ret <vscale x 1 x i8> [[TMP0]]1335//1336vuint8mf8_t test_vmadd_vv_u8mf8_tum(vbool64_t mask, vuint8mf8_t vd, vuint8mf8_t vs1, vuint8mf8_t vs2, size_t vl) {1337  return __riscv_vmadd_vv_u8mf8_tum(mask, vd, vs1, vs2, vl);1338}1339 1340// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vmadd_vx_u8mf8_tum1341// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[VD:%.*]], i8 noundef zeroext [[RS1:%.*]], <vscale x 1 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1342// CHECK-RV64-NEXT:  entry:1343// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmadd.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[VD]], i8 [[RS1]], <vscale x 1 x i8> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)1344// CHECK-RV64-NEXT:    ret <vscale x 1 x i8> [[TMP0]]1345//1346vuint8mf8_t test_vmadd_vx_u8mf8_tum(vbool64_t mask, vuint8mf8_t vd, uint8_t rs1, vuint8mf8_t vs2, size_t vl) {1347  return __riscv_vmadd_vx_u8mf8_tum(mask, vd, rs1, vs2, vl);1348}1349 1350// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vmadd_vv_u8mf4_tum1351// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS1:%.*]], <vscale x 2 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1352// CHECK-RV64-NEXT:  entry:1353// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmadd.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 2 x i8> [[VS1]], <vscale x 2 x i8> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)1354// CHECK-RV64-NEXT:    ret <vscale x 2 x i8> [[TMP0]]1355//1356vuint8mf4_t test_vmadd_vv_u8mf4_tum(vbool32_t mask, vuint8mf4_t vd, vuint8mf4_t vs1, vuint8mf4_t vs2, size_t vl) {1357  return __riscv_vmadd_vv_u8mf4_tum(mask, vd, vs1, vs2, vl);1358}1359 1360// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vmadd_vx_u8mf4_tum1361// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[VD:%.*]], i8 noundef zeroext [[RS1:%.*]], <vscale x 2 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1362// CHECK-RV64-NEXT:  entry:1363// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmadd.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[VD]], i8 [[RS1]], <vscale x 2 x i8> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)1364// CHECK-RV64-NEXT:    ret <vscale x 2 x i8> [[TMP0]]1365//1366vuint8mf4_t test_vmadd_vx_u8mf4_tum(vbool32_t mask, vuint8mf4_t vd, uint8_t rs1, vuint8mf4_t vs2, size_t vl) {1367  return __riscv_vmadd_vx_u8mf4_tum(mask, vd, rs1, vs2, vl);1368}1369 1370// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vmadd_vv_u8mf2_tum1371// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS1:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1372// CHECK-RV64-NEXT:  entry:1373// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmadd.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 4 x i8> [[VS1]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)1374// CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[TMP0]]1375//1376vuint8mf2_t test_vmadd_vv_u8mf2_tum(vbool16_t mask, vuint8mf2_t vd, vuint8mf2_t vs1, vuint8mf2_t vs2, size_t vl) {1377  return __riscv_vmadd_vv_u8mf2_tum(mask, vd, vs1, vs2, vl);1378}1379 1380// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vmadd_vx_u8mf2_tum1381// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[VD:%.*]], i8 noundef zeroext [[RS1:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1382// CHECK-RV64-NEXT:  entry:1383// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmadd.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[VD]], i8 [[RS1]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)1384// CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[TMP0]]1385//1386vuint8mf2_t test_vmadd_vx_u8mf2_tum(vbool16_t mask, vuint8mf2_t vd, uint8_t rs1, vuint8mf2_t vs2, size_t vl) {1387  return __riscv_vmadd_vx_u8mf2_tum(mask, vd, rs1, vs2, vl);1388}1389 1390// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vmadd_vv_u8m1_tum1391// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1392// CHECK-RV64-NEXT:  entry:1393// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmadd.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)1394// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]1395//1396vuint8m1_t test_vmadd_vv_u8m1_tum(vbool8_t mask, vuint8m1_t vd, vuint8m1_t vs1, vuint8m1_t vs2, size_t vl) {1397  return __riscv_vmadd_vv_u8m1_tum(mask, vd, vs1, vs2, vl);1398}1399 1400// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vmadd_vx_u8m1_tum1401// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[VD:%.*]], i8 noundef zeroext [[RS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1402// CHECK-RV64-NEXT:  entry:1403// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmadd.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[VD]], i8 [[RS1]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)1404// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]1405//1406vuint8m1_t test_vmadd_vx_u8m1_tum(vbool8_t mask, vuint8m1_t vd, uint8_t rs1, vuint8m1_t vs2, size_t vl) {1407  return __riscv_vmadd_vx_u8m1_tum(mask, vd, rs1, vs2, vl);1408}1409 1410// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vmadd_vv_u8m2_tum1411// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1412// CHECK-RV64-NEXT:  entry:1413// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmadd.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 16 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)1414// CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]1415//1416vuint8m2_t test_vmadd_vv_u8m2_tum(vbool4_t mask, vuint8m2_t vd, vuint8m2_t vs1, vuint8m2_t vs2, size_t vl) {1417  return __riscv_vmadd_vv_u8m2_tum(mask, vd, vs1, vs2, vl);1418}1419 1420// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vmadd_vx_u8m2_tum1421// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[VD:%.*]], i8 noundef zeroext [[RS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1422// CHECK-RV64-NEXT:  entry:1423// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmadd.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[VD]], i8 [[RS1]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)1424// CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]1425//1426vuint8m2_t test_vmadd_vx_u8m2_tum(vbool4_t mask, vuint8m2_t vd, uint8_t rs1, vuint8m2_t vs2, size_t vl) {1427  return __riscv_vmadd_vx_u8m2_tum(mask, vd, rs1, vs2, vl);1428}1429 1430// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vmadd_vv_u8m4_tum1431// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1432// CHECK-RV64-NEXT:  entry:1433// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmadd.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 32 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2)1434// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]1435//1436vuint8m4_t test_vmadd_vv_u8m4_tum(vbool2_t mask, vuint8m4_t vd, vuint8m4_t vs1, vuint8m4_t vs2, size_t vl) {1437  return __riscv_vmadd_vv_u8m4_tum(mask, vd, vs1, vs2, vl);1438}1439 1440// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vmadd_vx_u8m4_tum1441// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[VD:%.*]], i8 noundef zeroext [[RS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1442// CHECK-RV64-NEXT:  entry:1443// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmadd.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[VD]], i8 [[RS1]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2)1444// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]1445//1446vuint8m4_t test_vmadd_vx_u8m4_tum(vbool2_t mask, vuint8m4_t vd, uint8_t rs1, vuint8m4_t vs2, size_t vl) {1447  return __riscv_vmadd_vx_u8m4_tum(mask, vd, rs1, vs2, vl);1448}1449 1450// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vmadd_vv_u8m8_tum1451// CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[VD:%.*]], <vscale x 64 x i8> [[VS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1452// CHECK-RV64-NEXT:  entry:1453// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmadd.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[VD]], <vscale x 64 x i8> [[VS1]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 2)1454// CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP0]]1455//1456vuint8m8_t test_vmadd_vv_u8m8_tum(vbool1_t mask, vuint8m8_t vd, vuint8m8_t vs1, vuint8m8_t vs2, size_t vl) {1457  return __riscv_vmadd_vv_u8m8_tum(mask, vd, vs1, vs2, vl);1458}1459 1460// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vmadd_vx_u8m8_tum1461// CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[VD:%.*]], i8 noundef zeroext [[RS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1462// CHECK-RV64-NEXT:  entry:1463// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmadd.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[VD]], i8 [[RS1]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 2)1464// CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP0]]1465//1466vuint8m8_t test_vmadd_vx_u8m8_tum(vbool1_t mask, vuint8m8_t vd, uint8_t rs1, vuint8m8_t vs2, size_t vl) {1467  return __riscv_vmadd_vx_u8m8_tum(mask, vd, rs1, vs2, vl);1468}1469 1470// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vmadd_vv_u16mf4_tum1471// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS1:%.*]], <vscale x 1 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1472// CHECK-RV64-NEXT:  entry:1473// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmadd.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[VD]], <vscale x 1 x i16> [[VS1]], <vscale x 1 x i16> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)1474// CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]1475//1476vuint16mf4_t test_vmadd_vv_u16mf4_tum(vbool64_t mask, vuint16mf4_t vd, vuint16mf4_t vs1, vuint16mf4_t vs2, size_t vl) {1477  return __riscv_vmadd_vv_u16mf4_tum(mask, vd, vs1, vs2, vl);1478}1479 1480// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vmadd_vx_u16mf4_tum1481// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[VD:%.*]], i16 noundef zeroext [[RS1:%.*]], <vscale x 1 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1482// CHECK-RV64-NEXT:  entry:1483// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmadd.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[VD]], i16 [[RS1]], <vscale x 1 x i16> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)1484// CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]1485//1486vuint16mf4_t test_vmadd_vx_u16mf4_tum(vbool64_t mask, vuint16mf4_t vd, uint16_t rs1, vuint16mf4_t vs2, size_t vl) {1487  return __riscv_vmadd_vx_u16mf4_tum(mask, vd, rs1, vs2, vl);1488}1489 1490// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vmadd_vv_u16mf2_tum1491// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS1:%.*]], <vscale x 2 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1492// CHECK-RV64-NEXT:  entry:1493// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmadd.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 2 x i16> [[VS1]], <vscale x 2 x i16> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)1494// CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]1495//1496vuint16mf2_t test_vmadd_vv_u16mf2_tum(vbool32_t mask, vuint16mf2_t vd, vuint16mf2_t vs1, vuint16mf2_t vs2, size_t vl) {1497  return __riscv_vmadd_vv_u16mf2_tum(mask, vd, vs1, vs2, vl);1498}1499 1500// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vmadd_vx_u16mf2_tum1501// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[VD:%.*]], i16 noundef zeroext [[RS1:%.*]], <vscale x 2 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1502// CHECK-RV64-NEXT:  entry:1503// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmadd.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[VD]], i16 [[RS1]], <vscale x 2 x i16> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)1504// CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]1505//1506vuint16mf2_t test_vmadd_vx_u16mf2_tum(vbool32_t mask, vuint16mf2_t vd, uint16_t rs1, vuint16mf2_t vs2, size_t vl) {1507  return __riscv_vmadd_vx_u16mf2_tum(mask, vd, rs1, vs2, vl);1508}1509 1510// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vmadd_vv_u16m1_tum1511// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS1:%.*]], <vscale x 4 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1512// CHECK-RV64-NEXT:  entry:1513// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmadd.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 4 x i16> [[VS1]], <vscale x 4 x i16> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)1514// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]1515//1516vuint16m1_t test_vmadd_vv_u16m1_tum(vbool16_t mask, vuint16m1_t vd, vuint16m1_t vs1, vuint16m1_t vs2, size_t vl) {1517  return __riscv_vmadd_vv_u16m1_tum(mask, vd, vs1, vs2, vl);1518}1519 1520// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vmadd_vx_u16m1_tum1521// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[VD:%.*]], i16 noundef zeroext [[RS1:%.*]], <vscale x 4 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1522// CHECK-RV64-NEXT:  entry:1523// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmadd.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[VD]], i16 [[RS1]], <vscale x 4 x i16> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)1524// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]1525//1526vuint16m1_t test_vmadd_vx_u16m1_tum(vbool16_t mask, vuint16m1_t vd, uint16_t rs1, vuint16m1_t vs2, size_t vl) {1527  return __riscv_vmadd_vx_u16m1_tum(mask, vd, rs1, vs2, vl);1528}1529 1530// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vmadd_vv_u16m2_tum1531// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS1:%.*]], <vscale x 8 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1532// CHECK-RV64-NEXT:  entry:1533// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmadd.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 8 x i16> [[VS1]], <vscale x 8 x i16> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)1534// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]1535//1536vuint16m2_t test_vmadd_vv_u16m2_tum(vbool8_t mask, vuint16m2_t vd, vuint16m2_t vs1, vuint16m2_t vs2, size_t vl) {1537  return __riscv_vmadd_vv_u16m2_tum(mask, vd, vs1, vs2, vl);1538}1539 1540// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vmadd_vx_u16m2_tum1541// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[VD:%.*]], i16 noundef zeroext [[RS1:%.*]], <vscale x 8 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1542// CHECK-RV64-NEXT:  entry:1543// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmadd.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[VD]], i16 [[RS1]], <vscale x 8 x i16> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)1544// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]1545//1546vuint16m2_t test_vmadd_vx_u16m2_tum(vbool8_t mask, vuint16m2_t vd, uint16_t rs1, vuint16m2_t vs2, size_t vl) {1547  return __riscv_vmadd_vx_u16m2_tum(mask, vd, rs1, vs2, vl);1548}1549 1550// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vmadd_vv_u16m4_tum1551// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS1:%.*]], <vscale x 16 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1552// CHECK-RV64-NEXT:  entry:1553// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmadd.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 16 x i16> [[VS1]], <vscale x 16 x i16> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)1554// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]1555//1556vuint16m4_t test_vmadd_vv_u16m4_tum(vbool4_t mask, vuint16m4_t vd, vuint16m4_t vs1, vuint16m4_t vs2, size_t vl) {1557  return __riscv_vmadd_vv_u16m4_tum(mask, vd, vs1, vs2, vl);1558}1559 1560// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vmadd_vx_u16m4_tum1561// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[VD:%.*]], i16 noundef zeroext [[RS1:%.*]], <vscale x 16 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1562// CHECK-RV64-NEXT:  entry:1563// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmadd.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[VD]], i16 [[RS1]], <vscale x 16 x i16> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)1564// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]1565//1566vuint16m4_t test_vmadd_vx_u16m4_tum(vbool4_t mask, vuint16m4_t vd, uint16_t rs1, vuint16m4_t vs2, size_t vl) {1567  return __riscv_vmadd_vx_u16m4_tum(mask, vd, rs1, vs2, vl);1568}1569 1570// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vmadd_vv_u16m8_tum1571// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS1:%.*]], <vscale x 32 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1572// CHECK-RV64-NEXT:  entry:1573// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmadd.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[VD]], <vscale x 32 x i16> [[VS1]], <vscale x 32 x i16> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2)1574// CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]1575//1576vuint16m8_t test_vmadd_vv_u16m8_tum(vbool2_t mask, vuint16m8_t vd, vuint16m8_t vs1, vuint16m8_t vs2, size_t vl) {1577  return __riscv_vmadd_vv_u16m8_tum(mask, vd, vs1, vs2, vl);1578}1579 1580// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vmadd_vx_u16m8_tum1581// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[VD:%.*]], i16 noundef zeroext [[RS1:%.*]], <vscale x 32 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1582// CHECK-RV64-NEXT:  entry:1583// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmadd.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[VD]], i16 [[RS1]], <vscale x 32 x i16> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2)1584// CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]1585//1586vuint16m8_t test_vmadd_vx_u16m8_tum(vbool2_t mask, vuint16m8_t vd, uint16_t rs1, vuint16m8_t vs2, size_t vl) {1587  return __riscv_vmadd_vx_u16m8_tum(mask, vd, rs1, vs2, vl);1588}1589 1590// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vmadd_vv_u32mf2_tum1591// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS1:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1592// CHECK-RV64-NEXT:  entry:1593// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmadd.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)1594// CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]1595//1596vuint32mf2_t test_vmadd_vv_u32mf2_tum(vbool64_t mask, vuint32mf2_t vd, vuint32mf2_t vs1, vuint32mf2_t vs2, size_t vl) {1597  return __riscv_vmadd_vv_u32mf2_tum(mask, vd, vs1, vs2, vl);1598}1599 1600// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vmadd_vx_u32mf2_tum1601// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[VD:%.*]], i32 noundef signext [[RS1:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1602// CHECK-RV64-NEXT:  entry:1603// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmadd.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], i32 [[RS1]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)1604// CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]1605//1606vuint32mf2_t test_vmadd_vx_u32mf2_tum(vbool64_t mask, vuint32mf2_t vd, uint32_t rs1, vuint32mf2_t vs2, size_t vl) {1607  return __riscv_vmadd_vx_u32mf2_tum(mask, vd, rs1, vs2, vl);1608}1609 1610// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vmadd_vv_u32m1_tum1611// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS1:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1612// CHECK-RV64-NEXT:  entry:1613// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmadd.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)1614// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]1615//1616vuint32m1_t test_vmadd_vv_u32m1_tum(vbool32_t mask, vuint32m1_t vd, vuint32m1_t vs1, vuint32m1_t vs2, size_t vl) {1617  return __riscv_vmadd_vv_u32m1_tum(mask, vd, vs1, vs2, vl);1618}1619 1620// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vmadd_vx_u32m1_tum1621// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[VD:%.*]], i32 noundef signext [[RS1:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1622// CHECK-RV64-NEXT:  entry:1623// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmadd.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], i32 [[RS1]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)1624// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]1625//1626vuint32m1_t test_vmadd_vx_u32m1_tum(vbool32_t mask, vuint32m1_t vd, uint32_t rs1, vuint32m1_t vs2, size_t vl) {1627  return __riscv_vmadd_vx_u32m1_tum(mask, vd, rs1, vs2, vl);1628}1629 1630// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vmadd_vv_u32m2_tum1631// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS1:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1632// CHECK-RV64-NEXT:  entry:1633// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmadd.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)1634// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]1635//1636vuint32m2_t test_vmadd_vv_u32m2_tum(vbool16_t mask, vuint32m2_t vd, vuint32m2_t vs1, vuint32m2_t vs2, size_t vl) {1637  return __riscv_vmadd_vv_u32m2_tum(mask, vd, vs1, vs2, vl);1638}1639 1640// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vmadd_vx_u32m2_tum1641// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[VD:%.*]], i32 noundef signext [[RS1:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1642// CHECK-RV64-NEXT:  entry:1643// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmadd.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], i32 [[RS1]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)1644// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]1645//1646vuint32m2_t test_vmadd_vx_u32m2_tum(vbool16_t mask, vuint32m2_t vd, uint32_t rs1, vuint32m2_t vs2, size_t vl) {1647  return __riscv_vmadd_vx_u32m2_tum(mask, vd, rs1, vs2, vl);1648}1649 1650// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vmadd_vv_u32m4_tum1651// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS1:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1652// CHECK-RV64-NEXT:  entry:1653// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmadd.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)1654// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]1655//1656vuint32m4_t test_vmadd_vv_u32m4_tum(vbool8_t mask, vuint32m4_t vd, vuint32m4_t vs1, vuint32m4_t vs2, size_t vl) {1657  return __riscv_vmadd_vv_u32m4_tum(mask, vd, vs1, vs2, vl);1658}1659 1660// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vmadd_vx_u32m4_tum1661// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[VD:%.*]], i32 noundef signext [[RS1:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1662// CHECK-RV64-NEXT:  entry:1663// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmadd.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], i32 [[RS1]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)1664// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]1665//1666vuint32m4_t test_vmadd_vx_u32m4_tum(vbool8_t mask, vuint32m4_t vd, uint32_t rs1, vuint32m4_t vs2, size_t vl) {1667  return __riscv_vmadd_vx_u32m4_tum(mask, vd, rs1, vs2, vl);1668}1669 1670// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vmadd_vv_u32m8_tum1671// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS1:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1672// CHECK-RV64-NEXT:  entry:1673// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmadd.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)1674// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]1675//1676vuint32m8_t test_vmadd_vv_u32m8_tum(vbool4_t mask, vuint32m8_t vd, vuint32m8_t vs1, vuint32m8_t vs2, size_t vl) {1677  return __riscv_vmadd_vv_u32m8_tum(mask, vd, vs1, vs2, vl);1678}1679 1680// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vmadd_vx_u32m8_tum1681// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[VD:%.*]], i32 noundef signext [[RS1:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1682// CHECK-RV64-NEXT:  entry:1683// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmadd.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], i32 [[RS1]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)1684// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]1685//1686vuint32m8_t test_vmadd_vx_u32m8_tum(vbool4_t mask, vuint32m8_t vd, uint32_t rs1, vuint32m8_t vs2, size_t vl) {1687  return __riscv_vmadd_vx_u32m8_tum(mask, vd, rs1, vs2, vl);1688}1689 1690// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vmadd_vv_u64m1_tum1691// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS1:%.*]], <vscale x 1 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1692// CHECK-RV64-NEXT:  entry:1693// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmadd.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[VD]], <vscale x 1 x i64> [[VS1]], <vscale x 1 x i64> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)1694// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]1695//1696vuint64m1_t test_vmadd_vv_u64m1_tum(vbool64_t mask, vuint64m1_t vd, vuint64m1_t vs1, vuint64m1_t vs2, size_t vl) {1697  return __riscv_vmadd_vv_u64m1_tum(mask, vd, vs1, vs2, vl);1698}1699 1700// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vmadd_vx_u64m1_tum1701// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[VD:%.*]], i64 noundef [[RS1:%.*]], <vscale x 1 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1702// CHECK-RV64-NEXT:  entry:1703// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmadd.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[VD]], i64 [[RS1]], <vscale x 1 x i64> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)1704// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]1705//1706vuint64m1_t test_vmadd_vx_u64m1_tum(vbool64_t mask, vuint64m1_t vd, uint64_t rs1, vuint64m1_t vs2, size_t vl) {1707  return __riscv_vmadd_vx_u64m1_tum(mask, vd, rs1, vs2, vl);1708}1709 1710// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vmadd_vv_u64m2_tum1711// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS1:%.*]], <vscale x 2 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1712// CHECK-RV64-NEXT:  entry:1713// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmadd.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 2 x i64> [[VS1]], <vscale x 2 x i64> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)1714// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]1715//1716vuint64m2_t test_vmadd_vv_u64m2_tum(vbool32_t mask, vuint64m2_t vd, vuint64m2_t vs1, vuint64m2_t vs2, size_t vl) {1717  return __riscv_vmadd_vv_u64m2_tum(mask, vd, vs1, vs2, vl);1718}1719 1720// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vmadd_vx_u64m2_tum1721// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[VD:%.*]], i64 noundef [[RS1:%.*]], <vscale x 2 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1722// CHECK-RV64-NEXT:  entry:1723// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmadd.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[VD]], i64 [[RS1]], <vscale x 2 x i64> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)1724// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]1725//1726vuint64m2_t test_vmadd_vx_u64m2_tum(vbool32_t mask, vuint64m2_t vd, uint64_t rs1, vuint64m2_t vs2, size_t vl) {1727  return __riscv_vmadd_vx_u64m2_tum(mask, vd, rs1, vs2, vl);1728}1729 1730// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vmadd_vv_u64m4_tum1731// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS1:%.*]], <vscale x 4 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1732// CHECK-RV64-NEXT:  entry:1733// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmadd.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 4 x i64> [[VS1]], <vscale x 4 x i64> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)1734// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]1735//1736vuint64m4_t test_vmadd_vv_u64m4_tum(vbool16_t mask, vuint64m4_t vd, vuint64m4_t vs1, vuint64m4_t vs2, size_t vl) {1737  return __riscv_vmadd_vv_u64m4_tum(mask, vd, vs1, vs2, vl);1738}1739 1740// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vmadd_vx_u64m4_tum1741// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[VD:%.*]], i64 noundef [[RS1:%.*]], <vscale x 4 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1742// CHECK-RV64-NEXT:  entry:1743// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmadd.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[VD]], i64 [[RS1]], <vscale x 4 x i64> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)1744// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]1745//1746vuint64m4_t test_vmadd_vx_u64m4_tum(vbool16_t mask, vuint64m4_t vd, uint64_t rs1, vuint64m4_t vs2, size_t vl) {1747  return __riscv_vmadd_vx_u64m4_tum(mask, vd, rs1, vs2, vl);1748}1749 1750// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vmadd_vv_u64m8_tum1751// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS1:%.*]], <vscale x 8 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1752// CHECK-RV64-NEXT:  entry:1753// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmadd.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[VD]], <vscale x 8 x i64> [[VS1]], <vscale x 8 x i64> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)1754// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]1755//1756vuint64m8_t test_vmadd_vv_u64m8_tum(vbool8_t mask, vuint64m8_t vd, vuint64m8_t vs1, vuint64m8_t vs2, size_t vl) {1757  return __riscv_vmadd_vv_u64m8_tum(mask, vd, vs1, vs2, vl);1758}1759 1760// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vmadd_vx_u64m8_tum1761// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[VD:%.*]], i64 noundef [[RS1:%.*]], <vscale x 8 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1762// CHECK-RV64-NEXT:  entry:1763// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmadd.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[VD]], i64 [[RS1]], <vscale x 8 x i64> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)1764// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]1765//1766vuint64m8_t test_vmadd_vx_u64m8_tum(vbool8_t mask, vuint64m8_t vd, uint64_t rs1, vuint64m8_t vs2, size_t vl) {1767  return __riscv_vmadd_vx_u64m8_tum(mask, vd, rs1, vs2, vl);1768}1769 1770// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vmadd_vv_i8mf8_tumu1771// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS1:%.*]], <vscale x 1 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1772// CHECK-RV64-NEXT:  entry:1773// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmadd.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[VD]], <vscale x 1 x i8> [[VS1]], <vscale x 1 x i8> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)1774// CHECK-RV64-NEXT:    ret <vscale x 1 x i8> [[TMP0]]1775//1776vint8mf8_t test_vmadd_vv_i8mf8_tumu(vbool64_t mask, vint8mf8_t vd, vint8mf8_t vs1, vint8mf8_t vs2, size_t vl) {1777  return __riscv_vmadd_vv_i8mf8_tumu(mask, vd, vs1, vs2, vl);1778}1779 1780// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vmadd_vx_i8mf8_tumu1781// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[VD:%.*]], i8 noundef signext [[RS1:%.*]], <vscale x 1 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1782// CHECK-RV64-NEXT:  entry:1783// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmadd.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[VD]], i8 [[RS1]], <vscale x 1 x i8> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)1784// CHECK-RV64-NEXT:    ret <vscale x 1 x i8> [[TMP0]]1785//1786vint8mf8_t test_vmadd_vx_i8mf8_tumu(vbool64_t mask, vint8mf8_t vd, int8_t rs1, vint8mf8_t vs2, size_t vl) {1787  return __riscv_vmadd_vx_i8mf8_tumu(mask, vd, rs1, vs2, vl);1788}1789 1790// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vmadd_vv_i8mf4_tumu1791// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS1:%.*]], <vscale x 2 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1792// CHECK-RV64-NEXT:  entry:1793// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmadd.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 2 x i8> [[VS1]], <vscale x 2 x i8> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)1794// CHECK-RV64-NEXT:    ret <vscale x 2 x i8> [[TMP0]]1795//1796vint8mf4_t test_vmadd_vv_i8mf4_tumu(vbool32_t mask, vint8mf4_t vd, vint8mf4_t vs1, vint8mf4_t vs2, size_t vl) {1797  return __riscv_vmadd_vv_i8mf4_tumu(mask, vd, vs1, vs2, vl);1798}1799 1800// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vmadd_vx_i8mf4_tumu1801// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[VD:%.*]], i8 noundef signext [[RS1:%.*]], <vscale x 2 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1802// CHECK-RV64-NEXT:  entry:1803// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmadd.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[VD]], i8 [[RS1]], <vscale x 2 x i8> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)1804// CHECK-RV64-NEXT:    ret <vscale x 2 x i8> [[TMP0]]1805//1806vint8mf4_t test_vmadd_vx_i8mf4_tumu(vbool32_t mask, vint8mf4_t vd, int8_t rs1, vint8mf4_t vs2, size_t vl) {1807  return __riscv_vmadd_vx_i8mf4_tumu(mask, vd, rs1, vs2, vl);1808}1809 1810// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vmadd_vv_i8mf2_tumu1811// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS1:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1812// CHECK-RV64-NEXT:  entry:1813// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmadd.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 4 x i8> [[VS1]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)1814// CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[TMP0]]1815//1816vint8mf2_t test_vmadd_vv_i8mf2_tumu(vbool16_t mask, vint8mf2_t vd, vint8mf2_t vs1, vint8mf2_t vs2, size_t vl) {1817  return __riscv_vmadd_vv_i8mf2_tumu(mask, vd, vs1, vs2, vl);1818}1819 1820// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vmadd_vx_i8mf2_tumu1821// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[VD:%.*]], i8 noundef signext [[RS1:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1822// CHECK-RV64-NEXT:  entry:1823// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmadd.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[VD]], i8 [[RS1]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)1824// CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[TMP0]]1825//1826vint8mf2_t test_vmadd_vx_i8mf2_tumu(vbool16_t mask, vint8mf2_t vd, int8_t rs1, vint8mf2_t vs2, size_t vl) {1827  return __riscv_vmadd_vx_i8mf2_tumu(mask, vd, rs1, vs2, vl);1828}1829 1830// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vmadd_vv_i8m1_tumu1831// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1832// CHECK-RV64-NEXT:  entry:1833// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmadd.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)1834// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]1835//1836vint8m1_t test_vmadd_vv_i8m1_tumu(vbool8_t mask, vint8m1_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) {1837  return __riscv_vmadd_vv_i8m1_tumu(mask, vd, vs1, vs2, vl);1838}1839 1840// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vmadd_vx_i8m1_tumu1841// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[VD:%.*]], i8 noundef signext [[RS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1842// CHECK-RV64-NEXT:  entry:1843// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmadd.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[VD]], i8 [[RS1]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)1844// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]1845//1846vint8m1_t test_vmadd_vx_i8m1_tumu(vbool8_t mask, vint8m1_t vd, int8_t rs1, vint8m1_t vs2, size_t vl) {1847  return __riscv_vmadd_vx_i8m1_tumu(mask, vd, rs1, vs2, vl);1848}1849 1850// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vmadd_vv_i8m2_tumu1851// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1852// CHECK-RV64-NEXT:  entry:1853// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmadd.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 16 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)1854// CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]1855//1856vint8m2_t test_vmadd_vv_i8m2_tumu(vbool4_t mask, vint8m2_t vd, vint8m2_t vs1, vint8m2_t vs2, size_t vl) {1857  return __riscv_vmadd_vv_i8m2_tumu(mask, vd, vs1, vs2, vl);1858}1859 1860// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vmadd_vx_i8m2_tumu1861// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[VD:%.*]], i8 noundef signext [[RS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1862// CHECK-RV64-NEXT:  entry:1863// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmadd.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[VD]], i8 [[RS1]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)1864// CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]1865//1866vint8m2_t test_vmadd_vx_i8m2_tumu(vbool4_t mask, vint8m2_t vd, int8_t rs1, vint8m2_t vs2, size_t vl) {1867  return __riscv_vmadd_vx_i8m2_tumu(mask, vd, rs1, vs2, vl);1868}1869 1870// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vmadd_vv_i8m4_tumu1871// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1872// CHECK-RV64-NEXT:  entry:1873// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmadd.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 32 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0)1874// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]1875//1876vint8m4_t test_vmadd_vv_i8m4_tumu(vbool2_t mask, vint8m4_t vd, vint8m4_t vs1, vint8m4_t vs2, size_t vl) {1877  return __riscv_vmadd_vv_i8m4_tumu(mask, vd, vs1, vs2, vl);1878}1879 1880// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vmadd_vx_i8m4_tumu1881// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[VD:%.*]], i8 noundef signext [[RS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1882// CHECK-RV64-NEXT:  entry:1883// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmadd.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[VD]], i8 [[RS1]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0)1884// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]1885//1886vint8m4_t test_vmadd_vx_i8m4_tumu(vbool2_t mask, vint8m4_t vd, int8_t rs1, vint8m4_t vs2, size_t vl) {1887  return __riscv_vmadd_vx_i8m4_tumu(mask, vd, rs1, vs2, vl);1888}1889 1890// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vmadd_vv_i8m8_tumu1891// CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[VD:%.*]], <vscale x 64 x i8> [[VS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1892// CHECK-RV64-NEXT:  entry:1893// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmadd.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[VD]], <vscale x 64 x i8> [[VS1]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 0)1894// CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP0]]1895//1896vint8m8_t test_vmadd_vv_i8m8_tumu(vbool1_t mask, vint8m8_t vd, vint8m8_t vs1, vint8m8_t vs2, size_t vl) {1897  return __riscv_vmadd_vv_i8m8_tumu(mask, vd, vs1, vs2, vl);1898}1899 1900// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vmadd_vx_i8m8_tumu1901// CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[VD:%.*]], i8 noundef signext [[RS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1902// CHECK-RV64-NEXT:  entry:1903// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmadd.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[VD]], i8 [[RS1]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 0)1904// CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP0]]1905//1906vint8m8_t test_vmadd_vx_i8m8_tumu(vbool1_t mask, vint8m8_t vd, int8_t rs1, vint8m8_t vs2, size_t vl) {1907  return __riscv_vmadd_vx_i8m8_tumu(mask, vd, rs1, vs2, vl);1908}1909 1910// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vmadd_vv_i16mf4_tumu1911// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS1:%.*]], <vscale x 1 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1912// CHECK-RV64-NEXT:  entry:1913// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmadd.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[VD]], <vscale x 1 x i16> [[VS1]], <vscale x 1 x i16> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)1914// CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]1915//1916vint16mf4_t test_vmadd_vv_i16mf4_tumu(vbool64_t mask, vint16mf4_t vd, vint16mf4_t vs1, vint16mf4_t vs2, size_t vl) {1917  return __riscv_vmadd_vv_i16mf4_tumu(mask, vd, vs1, vs2, vl);1918}1919 1920// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vmadd_vx_i16mf4_tumu1921// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[VD:%.*]], i16 noundef signext [[RS1:%.*]], <vscale x 1 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1922// CHECK-RV64-NEXT:  entry:1923// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmadd.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[VD]], i16 [[RS1]], <vscale x 1 x i16> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)1924// CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]1925//1926vint16mf4_t test_vmadd_vx_i16mf4_tumu(vbool64_t mask, vint16mf4_t vd, int16_t rs1, vint16mf4_t vs2, size_t vl) {1927  return __riscv_vmadd_vx_i16mf4_tumu(mask, vd, rs1, vs2, vl);1928}1929 1930// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vmadd_vv_i16mf2_tumu1931// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS1:%.*]], <vscale x 2 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1932// CHECK-RV64-NEXT:  entry:1933// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmadd.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 2 x i16> [[VS1]], <vscale x 2 x i16> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)1934// CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]1935//1936vint16mf2_t test_vmadd_vv_i16mf2_tumu(vbool32_t mask, vint16mf2_t vd, vint16mf2_t vs1, vint16mf2_t vs2, size_t vl) {1937  return __riscv_vmadd_vv_i16mf2_tumu(mask, vd, vs1, vs2, vl);1938}1939 1940// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vmadd_vx_i16mf2_tumu1941// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[VD:%.*]], i16 noundef signext [[RS1:%.*]], <vscale x 2 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1942// CHECK-RV64-NEXT:  entry:1943// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmadd.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[VD]], i16 [[RS1]], <vscale x 2 x i16> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)1944// CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]1945//1946vint16mf2_t test_vmadd_vx_i16mf2_tumu(vbool32_t mask, vint16mf2_t vd, int16_t rs1, vint16mf2_t vs2, size_t vl) {1947  return __riscv_vmadd_vx_i16mf2_tumu(mask, vd, rs1, vs2, vl);1948}1949 1950// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vmadd_vv_i16m1_tumu1951// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS1:%.*]], <vscale x 4 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1952// CHECK-RV64-NEXT:  entry:1953// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmadd.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 4 x i16> [[VS1]], <vscale x 4 x i16> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)1954// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]1955//1956vint16m1_t test_vmadd_vv_i16m1_tumu(vbool16_t mask, vint16m1_t vd, vint16m1_t vs1, vint16m1_t vs2, size_t vl) {1957  return __riscv_vmadd_vv_i16m1_tumu(mask, vd, vs1, vs2, vl);1958}1959 1960// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vmadd_vx_i16m1_tumu1961// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[VD:%.*]], i16 noundef signext [[RS1:%.*]], <vscale x 4 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1962// CHECK-RV64-NEXT:  entry:1963// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmadd.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[VD]], i16 [[RS1]], <vscale x 4 x i16> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)1964// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]1965//1966vint16m1_t test_vmadd_vx_i16m1_tumu(vbool16_t mask, vint16m1_t vd, int16_t rs1, vint16m1_t vs2, size_t vl) {1967  return __riscv_vmadd_vx_i16m1_tumu(mask, vd, rs1, vs2, vl);1968}1969 1970// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vmadd_vv_i16m2_tumu1971// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS1:%.*]], <vscale x 8 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1972// CHECK-RV64-NEXT:  entry:1973// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmadd.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 8 x i16> [[VS1]], <vscale x 8 x i16> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)1974// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]1975//1976vint16m2_t test_vmadd_vv_i16m2_tumu(vbool8_t mask, vint16m2_t vd, vint16m2_t vs1, vint16m2_t vs2, size_t vl) {1977  return __riscv_vmadd_vv_i16m2_tumu(mask, vd, vs1, vs2, vl);1978}1979 1980// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vmadd_vx_i16m2_tumu1981// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[VD:%.*]], i16 noundef signext [[RS1:%.*]], <vscale x 8 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1982// CHECK-RV64-NEXT:  entry:1983// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmadd.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[VD]], i16 [[RS1]], <vscale x 8 x i16> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)1984// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]1985//1986vint16m2_t test_vmadd_vx_i16m2_tumu(vbool8_t mask, vint16m2_t vd, int16_t rs1, vint16m2_t vs2, size_t vl) {1987  return __riscv_vmadd_vx_i16m2_tumu(mask, vd, rs1, vs2, vl);1988}1989 1990// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vmadd_vv_i16m4_tumu1991// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS1:%.*]], <vscale x 16 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1992// CHECK-RV64-NEXT:  entry:1993// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmadd.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 16 x i16> [[VS1]], <vscale x 16 x i16> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)1994// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]1995//1996vint16m4_t test_vmadd_vv_i16m4_tumu(vbool4_t mask, vint16m4_t vd, vint16m4_t vs1, vint16m4_t vs2, size_t vl) {1997  return __riscv_vmadd_vv_i16m4_tumu(mask, vd, vs1, vs2, vl);1998}1999 2000// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vmadd_vx_i16m4_tumu2001// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[VD:%.*]], i16 noundef signext [[RS1:%.*]], <vscale x 16 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2002// CHECK-RV64-NEXT:  entry:2003// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmadd.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[VD]], i16 [[RS1]], <vscale x 16 x i16> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)2004// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]2005//2006vint16m4_t test_vmadd_vx_i16m4_tumu(vbool4_t mask, vint16m4_t vd, int16_t rs1, vint16m4_t vs2, size_t vl) {2007  return __riscv_vmadd_vx_i16m4_tumu(mask, vd, rs1, vs2, vl);2008}2009 2010// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vmadd_vv_i16m8_tumu2011// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS1:%.*]], <vscale x 32 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2012// CHECK-RV64-NEXT:  entry:2013// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmadd.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[VD]], <vscale x 32 x i16> [[VS1]], <vscale x 32 x i16> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0)2014// CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]2015//2016vint16m8_t test_vmadd_vv_i16m8_tumu(vbool2_t mask, vint16m8_t vd, vint16m8_t vs1, vint16m8_t vs2, size_t vl) {2017  return __riscv_vmadd_vv_i16m8_tumu(mask, vd, vs1, vs2, vl);2018}2019 2020// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vmadd_vx_i16m8_tumu2021// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[VD:%.*]], i16 noundef signext [[RS1:%.*]], <vscale x 32 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2022// CHECK-RV64-NEXT:  entry:2023// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmadd.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[VD]], i16 [[RS1]], <vscale x 32 x i16> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0)2024// CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]2025//2026vint16m8_t test_vmadd_vx_i16m8_tumu(vbool2_t mask, vint16m8_t vd, int16_t rs1, vint16m8_t vs2, size_t vl) {2027  return __riscv_vmadd_vx_i16m8_tumu(mask, vd, rs1, vs2, vl);2028}2029 2030// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vmadd_vv_i32mf2_tumu2031// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS1:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2032// CHECK-RV64-NEXT:  entry:2033// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmadd.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)2034// CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]2035//2036vint32mf2_t test_vmadd_vv_i32mf2_tumu(vbool64_t mask, vint32mf2_t vd, vint32mf2_t vs1, vint32mf2_t vs2, size_t vl) {2037  return __riscv_vmadd_vv_i32mf2_tumu(mask, vd, vs1, vs2, vl);2038}2039 2040// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vmadd_vx_i32mf2_tumu2041// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[VD:%.*]], i32 noundef signext [[RS1:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2042// CHECK-RV64-NEXT:  entry:2043// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmadd.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], i32 [[RS1]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)2044// CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]2045//2046vint32mf2_t test_vmadd_vx_i32mf2_tumu(vbool64_t mask, vint32mf2_t vd, int32_t rs1, vint32mf2_t vs2, size_t vl) {2047  return __riscv_vmadd_vx_i32mf2_tumu(mask, vd, rs1, vs2, vl);2048}2049 2050// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vmadd_vv_i32m1_tumu2051// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS1:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2052// CHECK-RV64-NEXT:  entry:2053// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmadd.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)2054// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]2055//2056vint32m1_t test_vmadd_vv_i32m1_tumu(vbool32_t mask, vint32m1_t vd, vint32m1_t vs1, vint32m1_t vs2, size_t vl) {2057  return __riscv_vmadd_vv_i32m1_tumu(mask, vd, vs1, vs2, vl);2058}2059 2060// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vmadd_vx_i32m1_tumu2061// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[VD:%.*]], i32 noundef signext [[RS1:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2062// CHECK-RV64-NEXT:  entry:2063// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmadd.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], i32 [[RS1]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)2064// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]2065//2066vint32m1_t test_vmadd_vx_i32m1_tumu(vbool32_t mask, vint32m1_t vd, int32_t rs1, vint32m1_t vs2, size_t vl) {2067  return __riscv_vmadd_vx_i32m1_tumu(mask, vd, rs1, vs2, vl);2068}2069 2070// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vmadd_vv_i32m2_tumu2071// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS1:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2072// CHECK-RV64-NEXT:  entry:2073// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmadd.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)2074// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]2075//2076vint32m2_t test_vmadd_vv_i32m2_tumu(vbool16_t mask, vint32m2_t vd, vint32m2_t vs1, vint32m2_t vs2, size_t vl) {2077  return __riscv_vmadd_vv_i32m2_tumu(mask, vd, vs1, vs2, vl);2078}2079 2080// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vmadd_vx_i32m2_tumu2081// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[VD:%.*]], i32 noundef signext [[RS1:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2082// CHECK-RV64-NEXT:  entry:2083// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmadd.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], i32 [[RS1]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)2084// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]2085//2086vint32m2_t test_vmadd_vx_i32m2_tumu(vbool16_t mask, vint32m2_t vd, int32_t rs1, vint32m2_t vs2, size_t vl) {2087  return __riscv_vmadd_vx_i32m2_tumu(mask, vd, rs1, vs2, vl);2088}2089 2090// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vmadd_vv_i32m4_tumu2091// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS1:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2092// CHECK-RV64-NEXT:  entry:2093// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmadd.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)2094// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]2095//2096vint32m4_t test_vmadd_vv_i32m4_tumu(vbool8_t mask, vint32m4_t vd, vint32m4_t vs1, vint32m4_t vs2, size_t vl) {2097  return __riscv_vmadd_vv_i32m4_tumu(mask, vd, vs1, vs2, vl);2098}2099 2100// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vmadd_vx_i32m4_tumu2101// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[VD:%.*]], i32 noundef signext [[RS1:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2102// CHECK-RV64-NEXT:  entry:2103// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmadd.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], i32 [[RS1]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)2104// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]2105//2106vint32m4_t test_vmadd_vx_i32m4_tumu(vbool8_t mask, vint32m4_t vd, int32_t rs1, vint32m4_t vs2, size_t vl) {2107  return __riscv_vmadd_vx_i32m4_tumu(mask, vd, rs1, vs2, vl);2108}2109 2110// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vmadd_vv_i32m8_tumu2111// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS1:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2112// CHECK-RV64-NEXT:  entry:2113// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmadd.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)2114// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]2115//2116vint32m8_t test_vmadd_vv_i32m8_tumu(vbool4_t mask, vint32m8_t vd, vint32m8_t vs1, vint32m8_t vs2, size_t vl) {2117  return __riscv_vmadd_vv_i32m8_tumu(mask, vd, vs1, vs2, vl);2118}2119 2120// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vmadd_vx_i32m8_tumu2121// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[VD:%.*]], i32 noundef signext [[RS1:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2122// CHECK-RV64-NEXT:  entry:2123// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmadd.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], i32 [[RS1]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)2124// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]2125//2126vint32m8_t test_vmadd_vx_i32m8_tumu(vbool4_t mask, vint32m8_t vd, int32_t rs1, vint32m8_t vs2, size_t vl) {2127  return __riscv_vmadd_vx_i32m8_tumu(mask, vd, rs1, vs2, vl);2128}2129 2130// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vmadd_vv_i64m1_tumu2131// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS1:%.*]], <vscale x 1 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2132// CHECK-RV64-NEXT:  entry:2133// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmadd.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[VD]], <vscale x 1 x i64> [[VS1]], <vscale x 1 x i64> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)2134// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]2135//2136vint64m1_t test_vmadd_vv_i64m1_tumu(vbool64_t mask, vint64m1_t vd, vint64m1_t vs1, vint64m1_t vs2, size_t vl) {2137  return __riscv_vmadd_vv_i64m1_tumu(mask, vd, vs1, vs2, vl);2138}2139 2140// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vmadd_vx_i64m1_tumu2141// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[VD:%.*]], i64 noundef [[RS1:%.*]], <vscale x 1 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2142// CHECK-RV64-NEXT:  entry:2143// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmadd.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[VD]], i64 [[RS1]], <vscale x 1 x i64> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)2144// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]2145//2146vint64m1_t test_vmadd_vx_i64m1_tumu(vbool64_t mask, vint64m1_t vd, int64_t rs1, vint64m1_t vs2, size_t vl) {2147  return __riscv_vmadd_vx_i64m1_tumu(mask, vd, rs1, vs2, vl);2148}2149 2150// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vmadd_vv_i64m2_tumu2151// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS1:%.*]], <vscale x 2 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2152// CHECK-RV64-NEXT:  entry:2153// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmadd.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 2 x i64> [[VS1]], <vscale x 2 x i64> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)2154// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]2155//2156vint64m2_t test_vmadd_vv_i64m2_tumu(vbool32_t mask, vint64m2_t vd, vint64m2_t vs1, vint64m2_t vs2, size_t vl) {2157  return __riscv_vmadd_vv_i64m2_tumu(mask, vd, vs1, vs2, vl);2158}2159 2160// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vmadd_vx_i64m2_tumu2161// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[VD:%.*]], i64 noundef [[RS1:%.*]], <vscale x 2 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2162// CHECK-RV64-NEXT:  entry:2163// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmadd.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[VD]], i64 [[RS1]], <vscale x 2 x i64> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)2164// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]2165//2166vint64m2_t test_vmadd_vx_i64m2_tumu(vbool32_t mask, vint64m2_t vd, int64_t rs1, vint64m2_t vs2, size_t vl) {2167  return __riscv_vmadd_vx_i64m2_tumu(mask, vd, rs1, vs2, vl);2168}2169 2170// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vmadd_vv_i64m4_tumu2171// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS1:%.*]], <vscale x 4 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2172// CHECK-RV64-NEXT:  entry:2173// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmadd.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 4 x i64> [[VS1]], <vscale x 4 x i64> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)2174// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]2175//2176vint64m4_t test_vmadd_vv_i64m4_tumu(vbool16_t mask, vint64m4_t vd, vint64m4_t vs1, vint64m4_t vs2, size_t vl) {2177  return __riscv_vmadd_vv_i64m4_tumu(mask, vd, vs1, vs2, vl);2178}2179 2180// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vmadd_vx_i64m4_tumu2181// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[VD:%.*]], i64 noundef [[RS1:%.*]], <vscale x 4 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2182// CHECK-RV64-NEXT:  entry:2183// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmadd.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[VD]], i64 [[RS1]], <vscale x 4 x i64> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)2184// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]2185//2186vint64m4_t test_vmadd_vx_i64m4_tumu(vbool16_t mask, vint64m4_t vd, int64_t rs1, vint64m4_t vs2, size_t vl) {2187  return __riscv_vmadd_vx_i64m4_tumu(mask, vd, rs1, vs2, vl);2188}2189 2190// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vmadd_vv_i64m8_tumu2191// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS1:%.*]], <vscale x 8 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2192// CHECK-RV64-NEXT:  entry:2193// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmadd.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[VD]], <vscale x 8 x i64> [[VS1]], <vscale x 8 x i64> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)2194// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]2195//2196vint64m8_t test_vmadd_vv_i64m8_tumu(vbool8_t mask, vint64m8_t vd, vint64m8_t vs1, vint64m8_t vs2, size_t vl) {2197  return __riscv_vmadd_vv_i64m8_tumu(mask, vd, vs1, vs2, vl);2198}2199 2200// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vmadd_vx_i64m8_tumu2201// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[VD:%.*]], i64 noundef [[RS1:%.*]], <vscale x 8 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2202// CHECK-RV64-NEXT:  entry:2203// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmadd.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[VD]], i64 [[RS1]], <vscale x 8 x i64> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)2204// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]2205//2206vint64m8_t test_vmadd_vx_i64m8_tumu(vbool8_t mask, vint64m8_t vd, int64_t rs1, vint64m8_t vs2, size_t vl) {2207  return __riscv_vmadd_vx_i64m8_tumu(mask, vd, rs1, vs2, vl);2208}2209 2210// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vmadd_vv_u8mf8_tumu2211// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS1:%.*]], <vscale x 1 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2212// CHECK-RV64-NEXT:  entry:2213// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmadd.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[VD]], <vscale x 1 x i8> [[VS1]], <vscale x 1 x i8> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)2214// CHECK-RV64-NEXT:    ret <vscale x 1 x i8> [[TMP0]]2215//2216vuint8mf8_t test_vmadd_vv_u8mf8_tumu(vbool64_t mask, vuint8mf8_t vd, vuint8mf8_t vs1, vuint8mf8_t vs2, size_t vl) {2217  return __riscv_vmadd_vv_u8mf8_tumu(mask, vd, vs1, vs2, vl);2218}2219 2220// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vmadd_vx_u8mf8_tumu2221// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[VD:%.*]], i8 noundef zeroext [[RS1:%.*]], <vscale x 1 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2222// CHECK-RV64-NEXT:  entry:2223// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmadd.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[VD]], i8 [[RS1]], <vscale x 1 x i8> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)2224// CHECK-RV64-NEXT:    ret <vscale x 1 x i8> [[TMP0]]2225//2226vuint8mf8_t test_vmadd_vx_u8mf8_tumu(vbool64_t mask, vuint8mf8_t vd, uint8_t rs1, vuint8mf8_t vs2, size_t vl) {2227  return __riscv_vmadd_vx_u8mf8_tumu(mask, vd, rs1, vs2, vl);2228}2229 2230// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vmadd_vv_u8mf4_tumu2231// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS1:%.*]], <vscale x 2 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2232// CHECK-RV64-NEXT:  entry:2233// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmadd.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 2 x i8> [[VS1]], <vscale x 2 x i8> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)2234// CHECK-RV64-NEXT:    ret <vscale x 2 x i8> [[TMP0]]2235//2236vuint8mf4_t test_vmadd_vv_u8mf4_tumu(vbool32_t mask, vuint8mf4_t vd, vuint8mf4_t vs1, vuint8mf4_t vs2, size_t vl) {2237  return __riscv_vmadd_vv_u8mf4_tumu(mask, vd, vs1, vs2, vl);2238}2239 2240// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vmadd_vx_u8mf4_tumu2241// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[VD:%.*]], i8 noundef zeroext [[RS1:%.*]], <vscale x 2 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2242// CHECK-RV64-NEXT:  entry:2243// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmadd.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[VD]], i8 [[RS1]], <vscale x 2 x i8> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)2244// CHECK-RV64-NEXT:    ret <vscale x 2 x i8> [[TMP0]]2245//2246vuint8mf4_t test_vmadd_vx_u8mf4_tumu(vbool32_t mask, vuint8mf4_t vd, uint8_t rs1, vuint8mf4_t vs2, size_t vl) {2247  return __riscv_vmadd_vx_u8mf4_tumu(mask, vd, rs1, vs2, vl);2248}2249 2250// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vmadd_vv_u8mf2_tumu2251// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS1:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2252// CHECK-RV64-NEXT:  entry:2253// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmadd.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 4 x i8> [[VS1]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)2254// CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[TMP0]]2255//2256vuint8mf2_t test_vmadd_vv_u8mf2_tumu(vbool16_t mask, vuint8mf2_t vd, vuint8mf2_t vs1, vuint8mf2_t vs2, size_t vl) {2257  return __riscv_vmadd_vv_u8mf2_tumu(mask, vd, vs1, vs2, vl);2258}2259 2260// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vmadd_vx_u8mf2_tumu2261// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[VD:%.*]], i8 noundef zeroext [[RS1:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2262// CHECK-RV64-NEXT:  entry:2263// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmadd.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[VD]], i8 [[RS1]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)2264// CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[TMP0]]2265//2266vuint8mf2_t test_vmadd_vx_u8mf2_tumu(vbool16_t mask, vuint8mf2_t vd, uint8_t rs1, vuint8mf2_t vs2, size_t vl) {2267  return __riscv_vmadd_vx_u8mf2_tumu(mask, vd, rs1, vs2, vl);2268}2269 2270// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vmadd_vv_u8m1_tumu2271// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2272// CHECK-RV64-NEXT:  entry:2273// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmadd.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)2274// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]2275//2276vuint8m1_t test_vmadd_vv_u8m1_tumu(vbool8_t mask, vuint8m1_t vd, vuint8m1_t vs1, vuint8m1_t vs2, size_t vl) {2277  return __riscv_vmadd_vv_u8m1_tumu(mask, vd, vs1, vs2, vl);2278}2279 2280// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vmadd_vx_u8m1_tumu2281// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[VD:%.*]], i8 noundef zeroext [[RS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2282// CHECK-RV64-NEXT:  entry:2283// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmadd.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[VD]], i8 [[RS1]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)2284// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]2285//2286vuint8m1_t test_vmadd_vx_u8m1_tumu(vbool8_t mask, vuint8m1_t vd, uint8_t rs1, vuint8m1_t vs2, size_t vl) {2287  return __riscv_vmadd_vx_u8m1_tumu(mask, vd, rs1, vs2, vl);2288}2289 2290// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vmadd_vv_u8m2_tumu2291// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2292// CHECK-RV64-NEXT:  entry:2293// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmadd.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 16 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)2294// CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]2295//2296vuint8m2_t test_vmadd_vv_u8m2_tumu(vbool4_t mask, vuint8m2_t vd, vuint8m2_t vs1, vuint8m2_t vs2, size_t vl) {2297  return __riscv_vmadd_vv_u8m2_tumu(mask, vd, vs1, vs2, vl);2298}2299 2300// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vmadd_vx_u8m2_tumu2301// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[VD:%.*]], i8 noundef zeroext [[RS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2302// CHECK-RV64-NEXT:  entry:2303// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmadd.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[VD]], i8 [[RS1]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)2304// CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]2305//2306vuint8m2_t test_vmadd_vx_u8m2_tumu(vbool4_t mask, vuint8m2_t vd, uint8_t rs1, vuint8m2_t vs2, size_t vl) {2307  return __riscv_vmadd_vx_u8m2_tumu(mask, vd, rs1, vs2, vl);2308}2309 2310// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vmadd_vv_u8m4_tumu2311// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2312// CHECK-RV64-NEXT:  entry:2313// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmadd.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 32 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0)2314// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]2315//2316vuint8m4_t test_vmadd_vv_u8m4_tumu(vbool2_t mask, vuint8m4_t vd, vuint8m4_t vs1, vuint8m4_t vs2, size_t vl) {2317  return __riscv_vmadd_vv_u8m4_tumu(mask, vd, vs1, vs2, vl);2318}2319 2320// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vmadd_vx_u8m4_tumu2321// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[VD:%.*]], i8 noundef zeroext [[RS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2322// CHECK-RV64-NEXT:  entry:2323// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmadd.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[VD]], i8 [[RS1]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0)2324// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]2325//2326vuint8m4_t test_vmadd_vx_u8m4_tumu(vbool2_t mask, vuint8m4_t vd, uint8_t rs1, vuint8m4_t vs2, size_t vl) {2327  return __riscv_vmadd_vx_u8m4_tumu(mask, vd, rs1, vs2, vl);2328}2329 2330// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vmadd_vv_u8m8_tumu2331// CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[VD:%.*]], <vscale x 64 x i8> [[VS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2332// CHECK-RV64-NEXT:  entry:2333// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmadd.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[VD]], <vscale x 64 x i8> [[VS1]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 0)2334// CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP0]]2335//2336vuint8m8_t test_vmadd_vv_u8m8_tumu(vbool1_t mask, vuint8m8_t vd, vuint8m8_t vs1, vuint8m8_t vs2, size_t vl) {2337  return __riscv_vmadd_vv_u8m8_tumu(mask, vd, vs1, vs2, vl);2338}2339 2340// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vmadd_vx_u8m8_tumu2341// CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[VD:%.*]], i8 noundef zeroext [[RS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2342// CHECK-RV64-NEXT:  entry:2343// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmadd.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[VD]], i8 [[RS1]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 0)2344// CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP0]]2345//2346vuint8m8_t test_vmadd_vx_u8m8_tumu(vbool1_t mask, vuint8m8_t vd, uint8_t rs1, vuint8m8_t vs2, size_t vl) {2347  return __riscv_vmadd_vx_u8m8_tumu(mask, vd, rs1, vs2, vl);2348}2349 2350// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vmadd_vv_u16mf4_tumu2351// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS1:%.*]], <vscale x 1 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2352// CHECK-RV64-NEXT:  entry:2353// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmadd.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[VD]], <vscale x 1 x i16> [[VS1]], <vscale x 1 x i16> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)2354// CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]2355//2356vuint16mf4_t test_vmadd_vv_u16mf4_tumu(vbool64_t mask, vuint16mf4_t vd, vuint16mf4_t vs1, vuint16mf4_t vs2, size_t vl) {2357  return __riscv_vmadd_vv_u16mf4_tumu(mask, vd, vs1, vs2, vl);2358}2359 2360// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vmadd_vx_u16mf4_tumu2361// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[VD:%.*]], i16 noundef zeroext [[RS1:%.*]], <vscale x 1 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2362// CHECK-RV64-NEXT:  entry:2363// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmadd.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[VD]], i16 [[RS1]], <vscale x 1 x i16> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)2364// CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]2365//2366vuint16mf4_t test_vmadd_vx_u16mf4_tumu(vbool64_t mask, vuint16mf4_t vd, uint16_t rs1, vuint16mf4_t vs2, size_t vl) {2367  return __riscv_vmadd_vx_u16mf4_tumu(mask, vd, rs1, vs2, vl);2368}2369 2370// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vmadd_vv_u16mf2_tumu2371// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS1:%.*]], <vscale x 2 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2372// CHECK-RV64-NEXT:  entry:2373// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmadd.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 2 x i16> [[VS1]], <vscale x 2 x i16> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)2374// CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]2375//2376vuint16mf2_t test_vmadd_vv_u16mf2_tumu(vbool32_t mask, vuint16mf2_t vd, vuint16mf2_t vs1, vuint16mf2_t vs2, size_t vl) {2377  return __riscv_vmadd_vv_u16mf2_tumu(mask, vd, vs1, vs2, vl);2378}2379 2380// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vmadd_vx_u16mf2_tumu2381// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[VD:%.*]], i16 noundef zeroext [[RS1:%.*]], <vscale x 2 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2382// CHECK-RV64-NEXT:  entry:2383// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmadd.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[VD]], i16 [[RS1]], <vscale x 2 x i16> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)2384// CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]2385//2386vuint16mf2_t test_vmadd_vx_u16mf2_tumu(vbool32_t mask, vuint16mf2_t vd, uint16_t rs1, vuint16mf2_t vs2, size_t vl) {2387  return __riscv_vmadd_vx_u16mf2_tumu(mask, vd, rs1, vs2, vl);2388}2389 2390// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vmadd_vv_u16m1_tumu2391// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS1:%.*]], <vscale x 4 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2392// CHECK-RV64-NEXT:  entry:2393// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmadd.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 4 x i16> [[VS1]], <vscale x 4 x i16> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)2394// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]2395//2396vuint16m1_t test_vmadd_vv_u16m1_tumu(vbool16_t mask, vuint16m1_t vd, vuint16m1_t vs1, vuint16m1_t vs2, size_t vl) {2397  return __riscv_vmadd_vv_u16m1_tumu(mask, vd, vs1, vs2, vl);2398}2399 2400// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vmadd_vx_u16m1_tumu2401// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[VD:%.*]], i16 noundef zeroext [[RS1:%.*]], <vscale x 4 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2402// CHECK-RV64-NEXT:  entry:2403// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmadd.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[VD]], i16 [[RS1]], <vscale x 4 x i16> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)2404// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]2405//2406vuint16m1_t test_vmadd_vx_u16m1_tumu(vbool16_t mask, vuint16m1_t vd, uint16_t rs1, vuint16m1_t vs2, size_t vl) {2407  return __riscv_vmadd_vx_u16m1_tumu(mask, vd, rs1, vs2, vl);2408}2409 2410// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vmadd_vv_u16m2_tumu2411// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS1:%.*]], <vscale x 8 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2412// CHECK-RV64-NEXT:  entry:2413// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmadd.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 8 x i16> [[VS1]], <vscale x 8 x i16> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)2414// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]2415//2416vuint16m2_t test_vmadd_vv_u16m2_tumu(vbool8_t mask, vuint16m2_t vd, vuint16m2_t vs1, vuint16m2_t vs2, size_t vl) {2417  return __riscv_vmadd_vv_u16m2_tumu(mask, vd, vs1, vs2, vl);2418}2419 2420// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vmadd_vx_u16m2_tumu2421// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[VD:%.*]], i16 noundef zeroext [[RS1:%.*]], <vscale x 8 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2422// CHECK-RV64-NEXT:  entry:2423// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmadd.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[VD]], i16 [[RS1]], <vscale x 8 x i16> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)2424// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]2425//2426vuint16m2_t test_vmadd_vx_u16m2_tumu(vbool8_t mask, vuint16m2_t vd, uint16_t rs1, vuint16m2_t vs2, size_t vl) {2427  return __riscv_vmadd_vx_u16m2_tumu(mask, vd, rs1, vs2, vl);2428}2429 2430// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vmadd_vv_u16m4_tumu2431// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS1:%.*]], <vscale x 16 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2432// CHECK-RV64-NEXT:  entry:2433// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmadd.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 16 x i16> [[VS1]], <vscale x 16 x i16> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)2434// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]2435//2436vuint16m4_t test_vmadd_vv_u16m4_tumu(vbool4_t mask, vuint16m4_t vd, vuint16m4_t vs1, vuint16m4_t vs2, size_t vl) {2437  return __riscv_vmadd_vv_u16m4_tumu(mask, vd, vs1, vs2, vl);2438}2439 2440// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vmadd_vx_u16m4_tumu2441// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[VD:%.*]], i16 noundef zeroext [[RS1:%.*]], <vscale x 16 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2442// CHECK-RV64-NEXT:  entry:2443// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmadd.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[VD]], i16 [[RS1]], <vscale x 16 x i16> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)2444// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]2445//2446vuint16m4_t test_vmadd_vx_u16m4_tumu(vbool4_t mask, vuint16m4_t vd, uint16_t rs1, vuint16m4_t vs2, size_t vl) {2447  return __riscv_vmadd_vx_u16m4_tumu(mask, vd, rs1, vs2, vl);2448}2449 2450// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vmadd_vv_u16m8_tumu2451// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS1:%.*]], <vscale x 32 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2452// CHECK-RV64-NEXT:  entry:2453// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmadd.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[VD]], <vscale x 32 x i16> [[VS1]], <vscale x 32 x i16> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0)2454// CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]2455//2456vuint16m8_t test_vmadd_vv_u16m8_tumu(vbool2_t mask, vuint16m8_t vd, vuint16m8_t vs1, vuint16m8_t vs2, size_t vl) {2457  return __riscv_vmadd_vv_u16m8_tumu(mask, vd, vs1, vs2, vl);2458}2459 2460// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vmadd_vx_u16m8_tumu2461// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[VD:%.*]], i16 noundef zeroext [[RS1:%.*]], <vscale x 32 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2462// CHECK-RV64-NEXT:  entry:2463// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmadd.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[VD]], i16 [[RS1]], <vscale x 32 x i16> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0)2464// CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]2465//2466vuint16m8_t test_vmadd_vx_u16m8_tumu(vbool2_t mask, vuint16m8_t vd, uint16_t rs1, vuint16m8_t vs2, size_t vl) {2467  return __riscv_vmadd_vx_u16m8_tumu(mask, vd, rs1, vs2, vl);2468}2469 2470// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vmadd_vv_u32mf2_tumu2471// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS1:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2472// CHECK-RV64-NEXT:  entry:2473// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmadd.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)2474// CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]2475//2476vuint32mf2_t test_vmadd_vv_u32mf2_tumu(vbool64_t mask, vuint32mf2_t vd, vuint32mf2_t vs1, vuint32mf2_t vs2, size_t vl) {2477  return __riscv_vmadd_vv_u32mf2_tumu(mask, vd, vs1, vs2, vl);2478}2479 2480// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vmadd_vx_u32mf2_tumu2481// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[VD:%.*]], i32 noundef signext [[RS1:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2482// CHECK-RV64-NEXT:  entry:2483// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmadd.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], i32 [[RS1]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)2484// CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]2485//2486vuint32mf2_t test_vmadd_vx_u32mf2_tumu(vbool64_t mask, vuint32mf2_t vd, uint32_t rs1, vuint32mf2_t vs2, size_t vl) {2487  return __riscv_vmadd_vx_u32mf2_tumu(mask, vd, rs1, vs2, vl);2488}2489 2490// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vmadd_vv_u32m1_tumu2491// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS1:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2492// CHECK-RV64-NEXT:  entry:2493// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmadd.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)2494// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]2495//2496vuint32m1_t test_vmadd_vv_u32m1_tumu(vbool32_t mask, vuint32m1_t vd, vuint32m1_t vs1, vuint32m1_t vs2, size_t vl) {2497  return __riscv_vmadd_vv_u32m1_tumu(mask, vd, vs1, vs2, vl);2498}2499 2500// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vmadd_vx_u32m1_tumu2501// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[VD:%.*]], i32 noundef signext [[RS1:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2502// CHECK-RV64-NEXT:  entry:2503// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmadd.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], i32 [[RS1]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)2504// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]2505//2506vuint32m1_t test_vmadd_vx_u32m1_tumu(vbool32_t mask, vuint32m1_t vd, uint32_t rs1, vuint32m1_t vs2, size_t vl) {2507  return __riscv_vmadd_vx_u32m1_tumu(mask, vd, rs1, vs2, vl);2508}2509 2510// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vmadd_vv_u32m2_tumu2511// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS1:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2512// CHECK-RV64-NEXT:  entry:2513// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmadd.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)2514// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]2515//2516vuint32m2_t test_vmadd_vv_u32m2_tumu(vbool16_t mask, vuint32m2_t vd, vuint32m2_t vs1, vuint32m2_t vs2, size_t vl) {2517  return __riscv_vmadd_vv_u32m2_tumu(mask, vd, vs1, vs2, vl);2518}2519 2520// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vmadd_vx_u32m2_tumu2521// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[VD:%.*]], i32 noundef signext [[RS1:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2522// CHECK-RV64-NEXT:  entry:2523// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmadd.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], i32 [[RS1]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)2524// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]2525//2526vuint32m2_t test_vmadd_vx_u32m2_tumu(vbool16_t mask, vuint32m2_t vd, uint32_t rs1, vuint32m2_t vs2, size_t vl) {2527  return __riscv_vmadd_vx_u32m2_tumu(mask, vd, rs1, vs2, vl);2528}2529 2530// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vmadd_vv_u32m4_tumu2531// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS1:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2532// CHECK-RV64-NEXT:  entry:2533// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmadd.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)2534// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]2535//2536vuint32m4_t test_vmadd_vv_u32m4_tumu(vbool8_t mask, vuint32m4_t vd, vuint32m4_t vs1, vuint32m4_t vs2, size_t vl) {2537  return __riscv_vmadd_vv_u32m4_tumu(mask, vd, vs1, vs2, vl);2538}2539 2540// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vmadd_vx_u32m4_tumu2541// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[VD:%.*]], i32 noundef signext [[RS1:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2542// CHECK-RV64-NEXT:  entry:2543// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmadd.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], i32 [[RS1]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)2544// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]2545//2546vuint32m4_t test_vmadd_vx_u32m4_tumu(vbool8_t mask, vuint32m4_t vd, uint32_t rs1, vuint32m4_t vs2, size_t vl) {2547  return __riscv_vmadd_vx_u32m4_tumu(mask, vd, rs1, vs2, vl);2548}2549 2550// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vmadd_vv_u32m8_tumu2551// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS1:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2552// CHECK-RV64-NEXT:  entry:2553// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmadd.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)2554// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]2555//2556vuint32m8_t test_vmadd_vv_u32m8_tumu(vbool4_t mask, vuint32m8_t vd, vuint32m8_t vs1, vuint32m8_t vs2, size_t vl) {2557  return __riscv_vmadd_vv_u32m8_tumu(mask, vd, vs1, vs2, vl);2558}2559 2560// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vmadd_vx_u32m8_tumu2561// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[VD:%.*]], i32 noundef signext [[RS1:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2562// CHECK-RV64-NEXT:  entry:2563// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmadd.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], i32 [[RS1]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)2564// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]2565//2566vuint32m8_t test_vmadd_vx_u32m8_tumu(vbool4_t mask, vuint32m8_t vd, uint32_t rs1, vuint32m8_t vs2, size_t vl) {2567  return __riscv_vmadd_vx_u32m8_tumu(mask, vd, rs1, vs2, vl);2568}2569 2570// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vmadd_vv_u64m1_tumu2571// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS1:%.*]], <vscale x 1 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2572// CHECK-RV64-NEXT:  entry:2573// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmadd.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[VD]], <vscale x 1 x i64> [[VS1]], <vscale x 1 x i64> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)2574// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]2575//2576vuint64m1_t test_vmadd_vv_u64m1_tumu(vbool64_t mask, vuint64m1_t vd, vuint64m1_t vs1, vuint64m1_t vs2, size_t vl) {2577  return __riscv_vmadd_vv_u64m1_tumu(mask, vd, vs1, vs2, vl);2578}2579 2580// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vmadd_vx_u64m1_tumu2581// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[VD:%.*]], i64 noundef [[RS1:%.*]], <vscale x 1 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2582// CHECK-RV64-NEXT:  entry:2583// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmadd.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[VD]], i64 [[RS1]], <vscale x 1 x i64> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)2584// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]2585//2586vuint64m1_t test_vmadd_vx_u64m1_tumu(vbool64_t mask, vuint64m1_t vd, uint64_t rs1, vuint64m1_t vs2, size_t vl) {2587  return __riscv_vmadd_vx_u64m1_tumu(mask, vd, rs1, vs2, vl);2588}2589 2590// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vmadd_vv_u64m2_tumu2591// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS1:%.*]], <vscale x 2 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2592// CHECK-RV64-NEXT:  entry:2593// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmadd.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 2 x i64> [[VS1]], <vscale x 2 x i64> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)2594// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]2595//2596vuint64m2_t test_vmadd_vv_u64m2_tumu(vbool32_t mask, vuint64m2_t vd, vuint64m2_t vs1, vuint64m2_t vs2, size_t vl) {2597  return __riscv_vmadd_vv_u64m2_tumu(mask, vd, vs1, vs2, vl);2598}2599 2600// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vmadd_vx_u64m2_tumu2601// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[VD:%.*]], i64 noundef [[RS1:%.*]], <vscale x 2 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2602// CHECK-RV64-NEXT:  entry:2603// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmadd.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[VD]], i64 [[RS1]], <vscale x 2 x i64> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)2604// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]2605//2606vuint64m2_t test_vmadd_vx_u64m2_tumu(vbool32_t mask, vuint64m2_t vd, uint64_t rs1, vuint64m2_t vs2, size_t vl) {2607  return __riscv_vmadd_vx_u64m2_tumu(mask, vd, rs1, vs2, vl);2608}2609 2610// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vmadd_vv_u64m4_tumu2611// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS1:%.*]], <vscale x 4 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2612// CHECK-RV64-NEXT:  entry:2613// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmadd.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 4 x i64> [[VS1]], <vscale x 4 x i64> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)2614// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]2615//2616vuint64m4_t test_vmadd_vv_u64m4_tumu(vbool16_t mask, vuint64m4_t vd, vuint64m4_t vs1, vuint64m4_t vs2, size_t vl) {2617  return __riscv_vmadd_vv_u64m4_tumu(mask, vd, vs1, vs2, vl);2618}2619 2620// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vmadd_vx_u64m4_tumu2621// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[VD:%.*]], i64 noundef [[RS1:%.*]], <vscale x 4 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2622// CHECK-RV64-NEXT:  entry:2623// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmadd.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[VD]], i64 [[RS1]], <vscale x 4 x i64> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)2624// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]2625//2626vuint64m4_t test_vmadd_vx_u64m4_tumu(vbool16_t mask, vuint64m4_t vd, uint64_t rs1, vuint64m4_t vs2, size_t vl) {2627  return __riscv_vmadd_vx_u64m4_tumu(mask, vd, rs1, vs2, vl);2628}2629 2630// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vmadd_vv_u64m8_tumu2631// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS1:%.*]], <vscale x 8 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2632// CHECK-RV64-NEXT:  entry:2633// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmadd.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[VD]], <vscale x 8 x i64> [[VS1]], <vscale x 8 x i64> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)2634// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]2635//2636vuint64m8_t test_vmadd_vv_u64m8_tumu(vbool8_t mask, vuint64m8_t vd, vuint64m8_t vs1, vuint64m8_t vs2, size_t vl) {2637  return __riscv_vmadd_vv_u64m8_tumu(mask, vd, vs1, vs2, vl);2638}2639 2640// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vmadd_vx_u64m8_tumu2641// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[VD:%.*]], i64 noundef [[RS1:%.*]], <vscale x 8 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2642// CHECK-RV64-NEXT:  entry:2643// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmadd.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[VD]], i64 [[RS1]], <vscale x 8 x i64> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)2644// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]2645//2646vuint64m8_t test_vmadd_vx_u64m8_tumu(vbool8_t mask, vuint64m8_t vd, uint64_t rs1, vuint64m8_t vs2, size_t vl) {2647  return __riscv_vmadd_vx_u64m8_tumu(mask, vd, rs1, vs2, vl);2648}2649 2650// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vmadd_vv_i8mf8_mu2651// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS1:%.*]], <vscale x 1 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2652// CHECK-RV64-NEXT:  entry:2653// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmadd.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[VD]], <vscale x 1 x i8> [[VS1]], <vscale x 1 x i8> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)2654// CHECK-RV64-NEXT:    ret <vscale x 1 x i8> [[TMP0]]2655//2656vint8mf8_t test_vmadd_vv_i8mf8_mu(vbool64_t mask, vint8mf8_t vd, vint8mf8_t vs1, vint8mf8_t vs2, size_t vl) {2657  return __riscv_vmadd_vv_i8mf8_mu(mask, vd, vs1, vs2, vl);2658}2659 2660// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vmadd_vx_i8mf8_mu2661// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[VD:%.*]], i8 noundef signext [[RS1:%.*]], <vscale x 1 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2662// CHECK-RV64-NEXT:  entry:2663// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmadd.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[VD]], i8 [[RS1]], <vscale x 1 x i8> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)2664// CHECK-RV64-NEXT:    ret <vscale x 1 x i8> [[TMP0]]2665//2666vint8mf8_t test_vmadd_vx_i8mf8_mu(vbool64_t mask, vint8mf8_t vd, int8_t rs1, vint8mf8_t vs2, size_t vl) {2667  return __riscv_vmadd_vx_i8mf8_mu(mask, vd, rs1, vs2, vl);2668}2669 2670// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vmadd_vv_i8mf4_mu2671// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS1:%.*]], <vscale x 2 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2672// CHECK-RV64-NEXT:  entry:2673// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmadd.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 2 x i8> [[VS1]], <vscale x 2 x i8> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)2674// CHECK-RV64-NEXT:    ret <vscale x 2 x i8> [[TMP0]]2675//2676vint8mf4_t test_vmadd_vv_i8mf4_mu(vbool32_t mask, vint8mf4_t vd, vint8mf4_t vs1, vint8mf4_t vs2, size_t vl) {2677  return __riscv_vmadd_vv_i8mf4_mu(mask, vd, vs1, vs2, vl);2678}2679 2680// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vmadd_vx_i8mf4_mu2681// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[VD:%.*]], i8 noundef signext [[RS1:%.*]], <vscale x 2 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2682// CHECK-RV64-NEXT:  entry:2683// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmadd.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[VD]], i8 [[RS1]], <vscale x 2 x i8> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)2684// CHECK-RV64-NEXT:    ret <vscale x 2 x i8> [[TMP0]]2685//2686vint8mf4_t test_vmadd_vx_i8mf4_mu(vbool32_t mask, vint8mf4_t vd, int8_t rs1, vint8mf4_t vs2, size_t vl) {2687  return __riscv_vmadd_vx_i8mf4_mu(mask, vd, rs1, vs2, vl);2688}2689 2690// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vmadd_vv_i8mf2_mu2691// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS1:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2692// CHECK-RV64-NEXT:  entry:2693// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmadd.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 4 x i8> [[VS1]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)2694// CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[TMP0]]2695//2696vint8mf2_t test_vmadd_vv_i8mf2_mu(vbool16_t mask, vint8mf2_t vd, vint8mf2_t vs1, vint8mf2_t vs2, size_t vl) {2697  return __riscv_vmadd_vv_i8mf2_mu(mask, vd, vs1, vs2, vl);2698}2699 2700// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vmadd_vx_i8mf2_mu2701// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[VD:%.*]], i8 noundef signext [[RS1:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2702// CHECK-RV64-NEXT:  entry:2703// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmadd.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[VD]], i8 [[RS1]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)2704// CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[TMP0]]2705//2706vint8mf2_t test_vmadd_vx_i8mf2_mu(vbool16_t mask, vint8mf2_t vd, int8_t rs1, vint8mf2_t vs2, size_t vl) {2707  return __riscv_vmadd_vx_i8mf2_mu(mask, vd, rs1, vs2, vl);2708}2709 2710// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vmadd_vv_i8m1_mu2711// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2712// CHECK-RV64-NEXT:  entry:2713// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmadd.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)2714// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]2715//2716vint8m1_t test_vmadd_vv_i8m1_mu(vbool8_t mask, vint8m1_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) {2717  return __riscv_vmadd_vv_i8m1_mu(mask, vd, vs1, vs2, vl);2718}2719 2720// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vmadd_vx_i8m1_mu2721// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[VD:%.*]], i8 noundef signext [[RS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2722// CHECK-RV64-NEXT:  entry:2723// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmadd.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[VD]], i8 [[RS1]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)2724// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]2725//2726vint8m1_t test_vmadd_vx_i8m1_mu(vbool8_t mask, vint8m1_t vd, int8_t rs1, vint8m1_t vs2, size_t vl) {2727  return __riscv_vmadd_vx_i8m1_mu(mask, vd, rs1, vs2, vl);2728}2729 2730// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vmadd_vv_i8m2_mu2731// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2732// CHECK-RV64-NEXT:  entry:2733// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmadd.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 16 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)2734// CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]2735//2736vint8m2_t test_vmadd_vv_i8m2_mu(vbool4_t mask, vint8m2_t vd, vint8m2_t vs1, vint8m2_t vs2, size_t vl) {2737  return __riscv_vmadd_vv_i8m2_mu(mask, vd, vs1, vs2, vl);2738}2739 2740// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vmadd_vx_i8m2_mu2741// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[VD:%.*]], i8 noundef signext [[RS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2742// CHECK-RV64-NEXT:  entry:2743// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmadd.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[VD]], i8 [[RS1]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)2744// CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]2745//2746vint8m2_t test_vmadd_vx_i8m2_mu(vbool4_t mask, vint8m2_t vd, int8_t rs1, vint8m2_t vs2, size_t vl) {2747  return __riscv_vmadd_vx_i8m2_mu(mask, vd, rs1, vs2, vl);2748}2749 2750// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vmadd_vv_i8m4_mu2751// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2752// CHECK-RV64-NEXT:  entry:2753// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmadd.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 32 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1)2754// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]2755//2756vint8m4_t test_vmadd_vv_i8m4_mu(vbool2_t mask, vint8m4_t vd, vint8m4_t vs1, vint8m4_t vs2, size_t vl) {2757  return __riscv_vmadd_vv_i8m4_mu(mask, vd, vs1, vs2, vl);2758}2759 2760// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vmadd_vx_i8m4_mu2761// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[VD:%.*]], i8 noundef signext [[RS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2762// CHECK-RV64-NEXT:  entry:2763// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmadd.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[VD]], i8 [[RS1]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1)2764// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]2765//2766vint8m4_t test_vmadd_vx_i8m4_mu(vbool2_t mask, vint8m4_t vd, int8_t rs1, vint8m4_t vs2, size_t vl) {2767  return __riscv_vmadd_vx_i8m4_mu(mask, vd, rs1, vs2, vl);2768}2769 2770// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vmadd_vv_i8m8_mu2771// CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[VD:%.*]], <vscale x 64 x i8> [[VS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2772// CHECK-RV64-NEXT:  entry:2773// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmadd.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[VD]], <vscale x 64 x i8> [[VS1]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 1)2774// CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP0]]2775//2776vint8m8_t test_vmadd_vv_i8m8_mu(vbool1_t mask, vint8m8_t vd, vint8m8_t vs1, vint8m8_t vs2, size_t vl) {2777  return __riscv_vmadd_vv_i8m8_mu(mask, vd, vs1, vs2, vl);2778}2779 2780// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vmadd_vx_i8m8_mu2781// CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[VD:%.*]], i8 noundef signext [[RS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2782// CHECK-RV64-NEXT:  entry:2783// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmadd.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[VD]], i8 [[RS1]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 1)2784// CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP0]]2785//2786vint8m8_t test_vmadd_vx_i8m8_mu(vbool1_t mask, vint8m8_t vd, int8_t rs1, vint8m8_t vs2, size_t vl) {2787  return __riscv_vmadd_vx_i8m8_mu(mask, vd, rs1, vs2, vl);2788}2789 2790// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vmadd_vv_i16mf4_mu2791// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS1:%.*]], <vscale x 1 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2792// CHECK-RV64-NEXT:  entry:2793// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmadd.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[VD]], <vscale x 1 x i16> [[VS1]], <vscale x 1 x i16> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)2794// CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]2795//2796vint16mf4_t test_vmadd_vv_i16mf4_mu(vbool64_t mask, vint16mf4_t vd, vint16mf4_t vs1, vint16mf4_t vs2, size_t vl) {2797  return __riscv_vmadd_vv_i16mf4_mu(mask, vd, vs1, vs2, vl);2798}2799 2800// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vmadd_vx_i16mf4_mu2801// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[VD:%.*]], i16 noundef signext [[RS1:%.*]], <vscale x 1 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2802// CHECK-RV64-NEXT:  entry:2803// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmadd.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[VD]], i16 [[RS1]], <vscale x 1 x i16> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)2804// CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]2805//2806vint16mf4_t test_vmadd_vx_i16mf4_mu(vbool64_t mask, vint16mf4_t vd, int16_t rs1, vint16mf4_t vs2, size_t vl) {2807  return __riscv_vmadd_vx_i16mf4_mu(mask, vd, rs1, vs2, vl);2808}2809 2810// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vmadd_vv_i16mf2_mu2811// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS1:%.*]], <vscale x 2 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2812// CHECK-RV64-NEXT:  entry:2813// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmadd.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 2 x i16> [[VS1]], <vscale x 2 x i16> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)2814// CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]2815//2816vint16mf2_t test_vmadd_vv_i16mf2_mu(vbool32_t mask, vint16mf2_t vd, vint16mf2_t vs1, vint16mf2_t vs2, size_t vl) {2817  return __riscv_vmadd_vv_i16mf2_mu(mask, vd, vs1, vs2, vl);2818}2819 2820// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vmadd_vx_i16mf2_mu2821// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[VD:%.*]], i16 noundef signext [[RS1:%.*]], <vscale x 2 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2822// CHECK-RV64-NEXT:  entry:2823// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmadd.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[VD]], i16 [[RS1]], <vscale x 2 x i16> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)2824// CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]2825//2826vint16mf2_t test_vmadd_vx_i16mf2_mu(vbool32_t mask, vint16mf2_t vd, int16_t rs1, vint16mf2_t vs2, size_t vl) {2827  return __riscv_vmadd_vx_i16mf2_mu(mask, vd, rs1, vs2, vl);2828}2829 2830// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vmadd_vv_i16m1_mu2831// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS1:%.*]], <vscale x 4 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2832// CHECK-RV64-NEXT:  entry:2833// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmadd.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 4 x i16> [[VS1]], <vscale x 4 x i16> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)2834// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]2835//2836vint16m1_t test_vmadd_vv_i16m1_mu(vbool16_t mask, vint16m1_t vd, vint16m1_t vs1, vint16m1_t vs2, size_t vl) {2837  return __riscv_vmadd_vv_i16m1_mu(mask, vd, vs1, vs2, vl);2838}2839 2840// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vmadd_vx_i16m1_mu2841// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[VD:%.*]], i16 noundef signext [[RS1:%.*]], <vscale x 4 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2842// CHECK-RV64-NEXT:  entry:2843// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmadd.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[VD]], i16 [[RS1]], <vscale x 4 x i16> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)2844// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]2845//2846vint16m1_t test_vmadd_vx_i16m1_mu(vbool16_t mask, vint16m1_t vd, int16_t rs1, vint16m1_t vs2, size_t vl) {2847  return __riscv_vmadd_vx_i16m1_mu(mask, vd, rs1, vs2, vl);2848}2849 2850// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vmadd_vv_i16m2_mu2851// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS1:%.*]], <vscale x 8 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2852// CHECK-RV64-NEXT:  entry:2853// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmadd.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 8 x i16> [[VS1]], <vscale x 8 x i16> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)2854// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]2855//2856vint16m2_t test_vmadd_vv_i16m2_mu(vbool8_t mask, vint16m2_t vd, vint16m2_t vs1, vint16m2_t vs2, size_t vl) {2857  return __riscv_vmadd_vv_i16m2_mu(mask, vd, vs1, vs2, vl);2858}2859 2860// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vmadd_vx_i16m2_mu2861// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[VD:%.*]], i16 noundef signext [[RS1:%.*]], <vscale x 8 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2862// CHECK-RV64-NEXT:  entry:2863// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmadd.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[VD]], i16 [[RS1]], <vscale x 8 x i16> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)2864// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]2865//2866vint16m2_t test_vmadd_vx_i16m2_mu(vbool8_t mask, vint16m2_t vd, int16_t rs1, vint16m2_t vs2, size_t vl) {2867  return __riscv_vmadd_vx_i16m2_mu(mask, vd, rs1, vs2, vl);2868}2869 2870// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vmadd_vv_i16m4_mu2871// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS1:%.*]], <vscale x 16 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2872// CHECK-RV64-NEXT:  entry:2873// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmadd.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 16 x i16> [[VS1]], <vscale x 16 x i16> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)2874// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]2875//2876vint16m4_t test_vmadd_vv_i16m4_mu(vbool4_t mask, vint16m4_t vd, vint16m4_t vs1, vint16m4_t vs2, size_t vl) {2877  return __riscv_vmadd_vv_i16m4_mu(mask, vd, vs1, vs2, vl);2878}2879 2880// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vmadd_vx_i16m4_mu2881// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[VD:%.*]], i16 noundef signext [[RS1:%.*]], <vscale x 16 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2882// CHECK-RV64-NEXT:  entry:2883// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmadd.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[VD]], i16 [[RS1]], <vscale x 16 x i16> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)2884// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]2885//2886vint16m4_t test_vmadd_vx_i16m4_mu(vbool4_t mask, vint16m4_t vd, int16_t rs1, vint16m4_t vs2, size_t vl) {2887  return __riscv_vmadd_vx_i16m4_mu(mask, vd, rs1, vs2, vl);2888}2889 2890// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vmadd_vv_i16m8_mu2891// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS1:%.*]], <vscale x 32 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2892// CHECK-RV64-NEXT:  entry:2893// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmadd.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[VD]], <vscale x 32 x i16> [[VS1]], <vscale x 32 x i16> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1)2894// CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]2895//2896vint16m8_t test_vmadd_vv_i16m8_mu(vbool2_t mask, vint16m8_t vd, vint16m8_t vs1, vint16m8_t vs2, size_t vl) {2897  return __riscv_vmadd_vv_i16m8_mu(mask, vd, vs1, vs2, vl);2898}2899 2900// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vmadd_vx_i16m8_mu2901// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[VD:%.*]], i16 noundef signext [[RS1:%.*]], <vscale x 32 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2902// CHECK-RV64-NEXT:  entry:2903// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmadd.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[VD]], i16 [[RS1]], <vscale x 32 x i16> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1)2904// CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]2905//2906vint16m8_t test_vmadd_vx_i16m8_mu(vbool2_t mask, vint16m8_t vd, int16_t rs1, vint16m8_t vs2, size_t vl) {2907  return __riscv_vmadd_vx_i16m8_mu(mask, vd, rs1, vs2, vl);2908}2909 2910// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vmadd_vv_i32mf2_mu2911// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS1:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2912// CHECK-RV64-NEXT:  entry:2913// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmadd.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)2914// CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]2915//2916vint32mf2_t test_vmadd_vv_i32mf2_mu(vbool64_t mask, vint32mf2_t vd, vint32mf2_t vs1, vint32mf2_t vs2, size_t vl) {2917  return __riscv_vmadd_vv_i32mf2_mu(mask, vd, vs1, vs2, vl);2918}2919 2920// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vmadd_vx_i32mf2_mu2921// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[VD:%.*]], i32 noundef signext [[RS1:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2922// CHECK-RV64-NEXT:  entry:2923// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmadd.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], i32 [[RS1]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)2924// CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]2925//2926vint32mf2_t test_vmadd_vx_i32mf2_mu(vbool64_t mask, vint32mf2_t vd, int32_t rs1, vint32mf2_t vs2, size_t vl) {2927  return __riscv_vmadd_vx_i32mf2_mu(mask, vd, rs1, vs2, vl);2928}2929 2930// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vmadd_vv_i32m1_mu2931// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS1:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2932// CHECK-RV64-NEXT:  entry:2933// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmadd.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)2934// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]2935//2936vint32m1_t test_vmadd_vv_i32m1_mu(vbool32_t mask, vint32m1_t vd, vint32m1_t vs1, vint32m1_t vs2, size_t vl) {2937  return __riscv_vmadd_vv_i32m1_mu(mask, vd, vs1, vs2, vl);2938}2939 2940// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vmadd_vx_i32m1_mu2941// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[VD:%.*]], i32 noundef signext [[RS1:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2942// CHECK-RV64-NEXT:  entry:2943// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmadd.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], i32 [[RS1]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)2944// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]2945//2946vint32m1_t test_vmadd_vx_i32m1_mu(vbool32_t mask, vint32m1_t vd, int32_t rs1, vint32m1_t vs2, size_t vl) {2947  return __riscv_vmadd_vx_i32m1_mu(mask, vd, rs1, vs2, vl);2948}2949 2950// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vmadd_vv_i32m2_mu2951// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS1:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2952// CHECK-RV64-NEXT:  entry:2953// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmadd.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)2954// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]2955//2956vint32m2_t test_vmadd_vv_i32m2_mu(vbool16_t mask, vint32m2_t vd, vint32m2_t vs1, vint32m2_t vs2, size_t vl) {2957  return __riscv_vmadd_vv_i32m2_mu(mask, vd, vs1, vs2, vl);2958}2959 2960// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vmadd_vx_i32m2_mu2961// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[VD:%.*]], i32 noundef signext [[RS1:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2962// CHECK-RV64-NEXT:  entry:2963// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmadd.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], i32 [[RS1]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)2964// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]2965//2966vint32m2_t test_vmadd_vx_i32m2_mu(vbool16_t mask, vint32m2_t vd, int32_t rs1, vint32m2_t vs2, size_t vl) {2967  return __riscv_vmadd_vx_i32m2_mu(mask, vd, rs1, vs2, vl);2968}2969 2970// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vmadd_vv_i32m4_mu2971// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS1:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2972// CHECK-RV64-NEXT:  entry:2973// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmadd.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)2974// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]2975//2976vint32m4_t test_vmadd_vv_i32m4_mu(vbool8_t mask, vint32m4_t vd, vint32m4_t vs1, vint32m4_t vs2, size_t vl) {2977  return __riscv_vmadd_vv_i32m4_mu(mask, vd, vs1, vs2, vl);2978}2979 2980// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vmadd_vx_i32m4_mu2981// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[VD:%.*]], i32 noundef signext [[RS1:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2982// CHECK-RV64-NEXT:  entry:2983// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmadd.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], i32 [[RS1]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)2984// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]2985//2986vint32m4_t test_vmadd_vx_i32m4_mu(vbool8_t mask, vint32m4_t vd, int32_t rs1, vint32m4_t vs2, size_t vl) {2987  return __riscv_vmadd_vx_i32m4_mu(mask, vd, rs1, vs2, vl);2988}2989 2990// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vmadd_vv_i32m8_mu2991// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS1:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2992// CHECK-RV64-NEXT:  entry:2993// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmadd.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)2994// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]2995//2996vint32m8_t test_vmadd_vv_i32m8_mu(vbool4_t mask, vint32m8_t vd, vint32m8_t vs1, vint32m8_t vs2, size_t vl) {2997  return __riscv_vmadd_vv_i32m8_mu(mask, vd, vs1, vs2, vl);2998}2999 3000// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vmadd_vx_i32m8_mu3001// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[VD:%.*]], i32 noundef signext [[RS1:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3002// CHECK-RV64-NEXT:  entry:3003// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmadd.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], i32 [[RS1]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)3004// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]3005//3006vint32m8_t test_vmadd_vx_i32m8_mu(vbool4_t mask, vint32m8_t vd, int32_t rs1, vint32m8_t vs2, size_t vl) {3007  return __riscv_vmadd_vx_i32m8_mu(mask, vd, rs1, vs2, vl);3008}3009 3010// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vmadd_vv_i64m1_mu3011// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS1:%.*]], <vscale x 1 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3012// CHECK-RV64-NEXT:  entry:3013// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmadd.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[VD]], <vscale x 1 x i64> [[VS1]], <vscale x 1 x i64> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)3014// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]3015//3016vint64m1_t test_vmadd_vv_i64m1_mu(vbool64_t mask, vint64m1_t vd, vint64m1_t vs1, vint64m1_t vs2, size_t vl) {3017  return __riscv_vmadd_vv_i64m1_mu(mask, vd, vs1, vs2, vl);3018}3019 3020// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vmadd_vx_i64m1_mu3021// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[VD:%.*]], i64 noundef [[RS1:%.*]], <vscale x 1 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3022// CHECK-RV64-NEXT:  entry:3023// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmadd.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[VD]], i64 [[RS1]], <vscale x 1 x i64> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)3024// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]3025//3026vint64m1_t test_vmadd_vx_i64m1_mu(vbool64_t mask, vint64m1_t vd, int64_t rs1, vint64m1_t vs2, size_t vl) {3027  return __riscv_vmadd_vx_i64m1_mu(mask, vd, rs1, vs2, vl);3028}3029 3030// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vmadd_vv_i64m2_mu3031// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS1:%.*]], <vscale x 2 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3032// CHECK-RV64-NEXT:  entry:3033// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmadd.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 2 x i64> [[VS1]], <vscale x 2 x i64> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)3034// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]3035//3036vint64m2_t test_vmadd_vv_i64m2_mu(vbool32_t mask, vint64m2_t vd, vint64m2_t vs1, vint64m2_t vs2, size_t vl) {3037  return __riscv_vmadd_vv_i64m2_mu(mask, vd, vs1, vs2, vl);3038}3039 3040// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vmadd_vx_i64m2_mu3041// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[VD:%.*]], i64 noundef [[RS1:%.*]], <vscale x 2 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3042// CHECK-RV64-NEXT:  entry:3043// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmadd.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[VD]], i64 [[RS1]], <vscale x 2 x i64> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)3044// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]3045//3046vint64m2_t test_vmadd_vx_i64m2_mu(vbool32_t mask, vint64m2_t vd, int64_t rs1, vint64m2_t vs2, size_t vl) {3047  return __riscv_vmadd_vx_i64m2_mu(mask, vd, rs1, vs2, vl);3048}3049 3050// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vmadd_vv_i64m4_mu3051// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS1:%.*]], <vscale x 4 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3052// CHECK-RV64-NEXT:  entry:3053// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmadd.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 4 x i64> [[VS1]], <vscale x 4 x i64> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)3054// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]3055//3056vint64m4_t test_vmadd_vv_i64m4_mu(vbool16_t mask, vint64m4_t vd, vint64m4_t vs1, vint64m4_t vs2, size_t vl) {3057  return __riscv_vmadd_vv_i64m4_mu(mask, vd, vs1, vs2, vl);3058}3059 3060// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vmadd_vx_i64m4_mu3061// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[VD:%.*]], i64 noundef [[RS1:%.*]], <vscale x 4 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3062// CHECK-RV64-NEXT:  entry:3063// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmadd.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[VD]], i64 [[RS1]], <vscale x 4 x i64> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)3064// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]3065//3066vint64m4_t test_vmadd_vx_i64m4_mu(vbool16_t mask, vint64m4_t vd, int64_t rs1, vint64m4_t vs2, size_t vl) {3067  return __riscv_vmadd_vx_i64m4_mu(mask, vd, rs1, vs2, vl);3068}3069 3070// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vmadd_vv_i64m8_mu3071// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS1:%.*]], <vscale x 8 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3072// CHECK-RV64-NEXT:  entry:3073// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmadd.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[VD]], <vscale x 8 x i64> [[VS1]], <vscale x 8 x i64> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)3074// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]3075//3076vint64m8_t test_vmadd_vv_i64m8_mu(vbool8_t mask, vint64m8_t vd, vint64m8_t vs1, vint64m8_t vs2, size_t vl) {3077  return __riscv_vmadd_vv_i64m8_mu(mask, vd, vs1, vs2, vl);3078}3079 3080// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vmadd_vx_i64m8_mu3081// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[VD:%.*]], i64 noundef [[RS1:%.*]], <vscale x 8 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3082// CHECK-RV64-NEXT:  entry:3083// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmadd.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[VD]], i64 [[RS1]], <vscale x 8 x i64> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)3084// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]3085//3086vint64m8_t test_vmadd_vx_i64m8_mu(vbool8_t mask, vint64m8_t vd, int64_t rs1, vint64m8_t vs2, size_t vl) {3087  return __riscv_vmadd_vx_i64m8_mu(mask, vd, rs1, vs2, vl);3088}3089 3090// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vmadd_vv_u8mf8_mu3091// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS1:%.*]], <vscale x 1 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3092// CHECK-RV64-NEXT:  entry:3093// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmadd.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[VD]], <vscale x 1 x i8> [[VS1]], <vscale x 1 x i8> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)3094// CHECK-RV64-NEXT:    ret <vscale x 1 x i8> [[TMP0]]3095//3096vuint8mf8_t test_vmadd_vv_u8mf8_mu(vbool64_t mask, vuint8mf8_t vd, vuint8mf8_t vs1, vuint8mf8_t vs2, size_t vl) {3097  return __riscv_vmadd_vv_u8mf8_mu(mask, vd, vs1, vs2, vl);3098}3099 3100// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vmadd_vx_u8mf8_mu3101// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[VD:%.*]], i8 noundef zeroext [[RS1:%.*]], <vscale x 1 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3102// CHECK-RV64-NEXT:  entry:3103// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmadd.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[VD]], i8 [[RS1]], <vscale x 1 x i8> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)3104// CHECK-RV64-NEXT:    ret <vscale x 1 x i8> [[TMP0]]3105//3106vuint8mf8_t test_vmadd_vx_u8mf8_mu(vbool64_t mask, vuint8mf8_t vd, uint8_t rs1, vuint8mf8_t vs2, size_t vl) {3107  return __riscv_vmadd_vx_u8mf8_mu(mask, vd, rs1, vs2, vl);3108}3109 3110// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vmadd_vv_u8mf4_mu3111// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS1:%.*]], <vscale x 2 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3112// CHECK-RV64-NEXT:  entry:3113// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmadd.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 2 x i8> [[VS1]], <vscale x 2 x i8> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)3114// CHECK-RV64-NEXT:    ret <vscale x 2 x i8> [[TMP0]]3115//3116vuint8mf4_t test_vmadd_vv_u8mf4_mu(vbool32_t mask, vuint8mf4_t vd, vuint8mf4_t vs1, vuint8mf4_t vs2, size_t vl) {3117  return __riscv_vmadd_vv_u8mf4_mu(mask, vd, vs1, vs2, vl);3118}3119 3120// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vmadd_vx_u8mf4_mu3121// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[VD:%.*]], i8 noundef zeroext [[RS1:%.*]], <vscale x 2 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3122// CHECK-RV64-NEXT:  entry:3123// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmadd.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[VD]], i8 [[RS1]], <vscale x 2 x i8> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)3124// CHECK-RV64-NEXT:    ret <vscale x 2 x i8> [[TMP0]]3125//3126vuint8mf4_t test_vmadd_vx_u8mf4_mu(vbool32_t mask, vuint8mf4_t vd, uint8_t rs1, vuint8mf4_t vs2, size_t vl) {3127  return __riscv_vmadd_vx_u8mf4_mu(mask, vd, rs1, vs2, vl);3128}3129 3130// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vmadd_vv_u8mf2_mu3131// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS1:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3132// CHECK-RV64-NEXT:  entry:3133// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmadd.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 4 x i8> [[VS1]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)3134// CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[TMP0]]3135//3136vuint8mf2_t test_vmadd_vv_u8mf2_mu(vbool16_t mask, vuint8mf2_t vd, vuint8mf2_t vs1, vuint8mf2_t vs2, size_t vl) {3137  return __riscv_vmadd_vv_u8mf2_mu(mask, vd, vs1, vs2, vl);3138}3139 3140// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vmadd_vx_u8mf2_mu3141// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[VD:%.*]], i8 noundef zeroext [[RS1:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3142// CHECK-RV64-NEXT:  entry:3143// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmadd.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[VD]], i8 [[RS1]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)3144// CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[TMP0]]3145//3146vuint8mf2_t test_vmadd_vx_u8mf2_mu(vbool16_t mask, vuint8mf2_t vd, uint8_t rs1, vuint8mf2_t vs2, size_t vl) {3147  return __riscv_vmadd_vx_u8mf2_mu(mask, vd, rs1, vs2, vl);3148}3149 3150// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vmadd_vv_u8m1_mu3151// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3152// CHECK-RV64-NEXT:  entry:3153// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmadd.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)3154// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]3155//3156vuint8m1_t test_vmadd_vv_u8m1_mu(vbool8_t mask, vuint8m1_t vd, vuint8m1_t vs1, vuint8m1_t vs2, size_t vl) {3157  return __riscv_vmadd_vv_u8m1_mu(mask, vd, vs1, vs2, vl);3158}3159 3160// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vmadd_vx_u8m1_mu3161// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[VD:%.*]], i8 noundef zeroext [[RS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3162// CHECK-RV64-NEXT:  entry:3163// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmadd.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[VD]], i8 [[RS1]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)3164// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]3165//3166vuint8m1_t test_vmadd_vx_u8m1_mu(vbool8_t mask, vuint8m1_t vd, uint8_t rs1, vuint8m1_t vs2, size_t vl) {3167  return __riscv_vmadd_vx_u8m1_mu(mask, vd, rs1, vs2, vl);3168}3169 3170// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vmadd_vv_u8m2_mu3171// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3172// CHECK-RV64-NEXT:  entry:3173// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmadd.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 16 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)3174// CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]3175//3176vuint8m2_t test_vmadd_vv_u8m2_mu(vbool4_t mask, vuint8m2_t vd, vuint8m2_t vs1, vuint8m2_t vs2, size_t vl) {3177  return __riscv_vmadd_vv_u8m2_mu(mask, vd, vs1, vs2, vl);3178}3179 3180// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vmadd_vx_u8m2_mu3181// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[VD:%.*]], i8 noundef zeroext [[RS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3182// CHECK-RV64-NEXT:  entry:3183// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmadd.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[VD]], i8 [[RS1]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)3184// CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]3185//3186vuint8m2_t test_vmadd_vx_u8m2_mu(vbool4_t mask, vuint8m2_t vd, uint8_t rs1, vuint8m2_t vs2, size_t vl) {3187  return __riscv_vmadd_vx_u8m2_mu(mask, vd, rs1, vs2, vl);3188}3189 3190// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vmadd_vv_u8m4_mu3191// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3192// CHECK-RV64-NEXT:  entry:3193// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmadd.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 32 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1)3194// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]3195//3196vuint8m4_t test_vmadd_vv_u8m4_mu(vbool2_t mask, vuint8m4_t vd, vuint8m4_t vs1, vuint8m4_t vs2, size_t vl) {3197  return __riscv_vmadd_vv_u8m4_mu(mask, vd, vs1, vs2, vl);3198}3199 3200// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vmadd_vx_u8m4_mu3201// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[VD:%.*]], i8 noundef zeroext [[RS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3202// CHECK-RV64-NEXT:  entry:3203// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmadd.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[VD]], i8 [[RS1]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1)3204// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]3205//3206vuint8m4_t test_vmadd_vx_u8m4_mu(vbool2_t mask, vuint8m4_t vd, uint8_t rs1, vuint8m4_t vs2, size_t vl) {3207  return __riscv_vmadd_vx_u8m4_mu(mask, vd, rs1, vs2, vl);3208}3209 3210// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vmadd_vv_u8m8_mu3211// CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[VD:%.*]], <vscale x 64 x i8> [[VS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3212// CHECK-RV64-NEXT:  entry:3213// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmadd.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[VD]], <vscale x 64 x i8> [[VS1]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 1)3214// CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP0]]3215//3216vuint8m8_t test_vmadd_vv_u8m8_mu(vbool1_t mask, vuint8m8_t vd, vuint8m8_t vs1, vuint8m8_t vs2, size_t vl) {3217  return __riscv_vmadd_vv_u8m8_mu(mask, vd, vs1, vs2, vl);3218}3219 3220// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vmadd_vx_u8m8_mu3221// CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[VD:%.*]], i8 noundef zeroext [[RS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3222// CHECK-RV64-NEXT:  entry:3223// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmadd.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[VD]], i8 [[RS1]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 1)3224// CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP0]]3225//3226vuint8m8_t test_vmadd_vx_u8m8_mu(vbool1_t mask, vuint8m8_t vd, uint8_t rs1, vuint8m8_t vs2, size_t vl) {3227  return __riscv_vmadd_vx_u8m8_mu(mask, vd, rs1, vs2, vl);3228}3229 3230// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vmadd_vv_u16mf4_mu3231// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS1:%.*]], <vscale x 1 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3232// CHECK-RV64-NEXT:  entry:3233// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmadd.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[VD]], <vscale x 1 x i16> [[VS1]], <vscale x 1 x i16> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)3234// CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]3235//3236vuint16mf4_t test_vmadd_vv_u16mf4_mu(vbool64_t mask, vuint16mf4_t vd, vuint16mf4_t vs1, vuint16mf4_t vs2, size_t vl) {3237  return __riscv_vmadd_vv_u16mf4_mu(mask, vd, vs1, vs2, vl);3238}3239 3240// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vmadd_vx_u16mf4_mu3241// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[VD:%.*]], i16 noundef zeroext [[RS1:%.*]], <vscale x 1 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3242// CHECK-RV64-NEXT:  entry:3243// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmadd.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[VD]], i16 [[RS1]], <vscale x 1 x i16> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)3244// CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]3245//3246vuint16mf4_t test_vmadd_vx_u16mf4_mu(vbool64_t mask, vuint16mf4_t vd, uint16_t rs1, vuint16mf4_t vs2, size_t vl) {3247  return __riscv_vmadd_vx_u16mf4_mu(mask, vd, rs1, vs2, vl);3248}3249 3250// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vmadd_vv_u16mf2_mu3251// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS1:%.*]], <vscale x 2 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3252// CHECK-RV64-NEXT:  entry:3253// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmadd.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 2 x i16> [[VS1]], <vscale x 2 x i16> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)3254// CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]3255//3256vuint16mf2_t test_vmadd_vv_u16mf2_mu(vbool32_t mask, vuint16mf2_t vd, vuint16mf2_t vs1, vuint16mf2_t vs2, size_t vl) {3257  return __riscv_vmadd_vv_u16mf2_mu(mask, vd, vs1, vs2, vl);3258}3259 3260// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vmadd_vx_u16mf2_mu3261// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[VD:%.*]], i16 noundef zeroext [[RS1:%.*]], <vscale x 2 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3262// CHECK-RV64-NEXT:  entry:3263// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmadd.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[VD]], i16 [[RS1]], <vscale x 2 x i16> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)3264// CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]3265//3266vuint16mf2_t test_vmadd_vx_u16mf2_mu(vbool32_t mask, vuint16mf2_t vd, uint16_t rs1, vuint16mf2_t vs2, size_t vl) {3267  return __riscv_vmadd_vx_u16mf2_mu(mask, vd, rs1, vs2, vl);3268}3269 3270// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vmadd_vv_u16m1_mu3271// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS1:%.*]], <vscale x 4 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3272// CHECK-RV64-NEXT:  entry:3273// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmadd.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 4 x i16> [[VS1]], <vscale x 4 x i16> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)3274// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]3275//3276vuint16m1_t test_vmadd_vv_u16m1_mu(vbool16_t mask, vuint16m1_t vd, vuint16m1_t vs1, vuint16m1_t vs2, size_t vl) {3277  return __riscv_vmadd_vv_u16m1_mu(mask, vd, vs1, vs2, vl);3278}3279 3280// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vmadd_vx_u16m1_mu3281// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[VD:%.*]], i16 noundef zeroext [[RS1:%.*]], <vscale x 4 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3282// CHECK-RV64-NEXT:  entry:3283// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmadd.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[VD]], i16 [[RS1]], <vscale x 4 x i16> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)3284// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]3285//3286vuint16m1_t test_vmadd_vx_u16m1_mu(vbool16_t mask, vuint16m1_t vd, uint16_t rs1, vuint16m1_t vs2, size_t vl) {3287  return __riscv_vmadd_vx_u16m1_mu(mask, vd, rs1, vs2, vl);3288}3289 3290// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vmadd_vv_u16m2_mu3291// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS1:%.*]], <vscale x 8 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3292// CHECK-RV64-NEXT:  entry:3293// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmadd.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 8 x i16> [[VS1]], <vscale x 8 x i16> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)3294// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]3295//3296vuint16m2_t test_vmadd_vv_u16m2_mu(vbool8_t mask, vuint16m2_t vd, vuint16m2_t vs1, vuint16m2_t vs2, size_t vl) {3297  return __riscv_vmadd_vv_u16m2_mu(mask, vd, vs1, vs2, vl);3298}3299 3300// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vmadd_vx_u16m2_mu3301// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[VD:%.*]], i16 noundef zeroext [[RS1:%.*]], <vscale x 8 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3302// CHECK-RV64-NEXT:  entry:3303// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmadd.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[VD]], i16 [[RS1]], <vscale x 8 x i16> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)3304// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]3305//3306vuint16m2_t test_vmadd_vx_u16m2_mu(vbool8_t mask, vuint16m2_t vd, uint16_t rs1, vuint16m2_t vs2, size_t vl) {3307  return __riscv_vmadd_vx_u16m2_mu(mask, vd, rs1, vs2, vl);3308}3309 3310// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vmadd_vv_u16m4_mu3311// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS1:%.*]], <vscale x 16 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3312// CHECK-RV64-NEXT:  entry:3313// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmadd.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 16 x i16> [[VS1]], <vscale x 16 x i16> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)3314// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]3315//3316vuint16m4_t test_vmadd_vv_u16m4_mu(vbool4_t mask, vuint16m4_t vd, vuint16m4_t vs1, vuint16m4_t vs2, size_t vl) {3317  return __riscv_vmadd_vv_u16m4_mu(mask, vd, vs1, vs2, vl);3318}3319 3320// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vmadd_vx_u16m4_mu3321// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[VD:%.*]], i16 noundef zeroext [[RS1:%.*]], <vscale x 16 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3322// CHECK-RV64-NEXT:  entry:3323// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmadd.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[VD]], i16 [[RS1]], <vscale x 16 x i16> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)3324// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]3325//3326vuint16m4_t test_vmadd_vx_u16m4_mu(vbool4_t mask, vuint16m4_t vd, uint16_t rs1, vuint16m4_t vs2, size_t vl) {3327  return __riscv_vmadd_vx_u16m4_mu(mask, vd, rs1, vs2, vl);3328}3329 3330// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vmadd_vv_u16m8_mu3331// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS1:%.*]], <vscale x 32 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3332// CHECK-RV64-NEXT:  entry:3333// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmadd.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[VD]], <vscale x 32 x i16> [[VS1]], <vscale x 32 x i16> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1)3334// CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]3335//3336vuint16m8_t test_vmadd_vv_u16m8_mu(vbool2_t mask, vuint16m8_t vd, vuint16m8_t vs1, vuint16m8_t vs2, size_t vl) {3337  return __riscv_vmadd_vv_u16m8_mu(mask, vd, vs1, vs2, vl);3338}3339 3340// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vmadd_vx_u16m8_mu3341// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[VD:%.*]], i16 noundef zeroext [[RS1:%.*]], <vscale x 32 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3342// CHECK-RV64-NEXT:  entry:3343// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmadd.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[VD]], i16 [[RS1]], <vscale x 32 x i16> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1)3344// CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]3345//3346vuint16m8_t test_vmadd_vx_u16m8_mu(vbool2_t mask, vuint16m8_t vd, uint16_t rs1, vuint16m8_t vs2, size_t vl) {3347  return __riscv_vmadd_vx_u16m8_mu(mask, vd, rs1, vs2, vl);3348}3349 3350// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vmadd_vv_u32mf2_mu3351// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS1:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3352// CHECK-RV64-NEXT:  entry:3353// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmadd.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)3354// CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]3355//3356vuint32mf2_t test_vmadd_vv_u32mf2_mu(vbool64_t mask, vuint32mf2_t vd, vuint32mf2_t vs1, vuint32mf2_t vs2, size_t vl) {3357  return __riscv_vmadd_vv_u32mf2_mu(mask, vd, vs1, vs2, vl);3358}3359 3360// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vmadd_vx_u32mf2_mu3361// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[VD:%.*]], i32 noundef signext [[RS1:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3362// CHECK-RV64-NEXT:  entry:3363// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmadd.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], i32 [[RS1]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)3364// CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]3365//3366vuint32mf2_t test_vmadd_vx_u32mf2_mu(vbool64_t mask, vuint32mf2_t vd, uint32_t rs1, vuint32mf2_t vs2, size_t vl) {3367  return __riscv_vmadd_vx_u32mf2_mu(mask, vd, rs1, vs2, vl);3368}3369 3370// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vmadd_vv_u32m1_mu3371// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS1:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3372// CHECK-RV64-NEXT:  entry:3373// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmadd.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)3374// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]3375//3376vuint32m1_t test_vmadd_vv_u32m1_mu(vbool32_t mask, vuint32m1_t vd, vuint32m1_t vs1, vuint32m1_t vs2, size_t vl) {3377  return __riscv_vmadd_vv_u32m1_mu(mask, vd, vs1, vs2, vl);3378}3379 3380// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vmadd_vx_u32m1_mu3381// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[VD:%.*]], i32 noundef signext [[RS1:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3382// CHECK-RV64-NEXT:  entry:3383// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmadd.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], i32 [[RS1]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)3384// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]3385//3386vuint32m1_t test_vmadd_vx_u32m1_mu(vbool32_t mask, vuint32m1_t vd, uint32_t rs1, vuint32m1_t vs2, size_t vl) {3387  return __riscv_vmadd_vx_u32m1_mu(mask, vd, rs1, vs2, vl);3388}3389 3390// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vmadd_vv_u32m2_mu3391// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS1:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3392// CHECK-RV64-NEXT:  entry:3393// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmadd.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)3394// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]3395//3396vuint32m2_t test_vmadd_vv_u32m2_mu(vbool16_t mask, vuint32m2_t vd, vuint32m2_t vs1, vuint32m2_t vs2, size_t vl) {3397  return __riscv_vmadd_vv_u32m2_mu(mask, vd, vs1, vs2, vl);3398}3399 3400// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vmadd_vx_u32m2_mu3401// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[VD:%.*]], i32 noundef signext [[RS1:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3402// CHECK-RV64-NEXT:  entry:3403// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmadd.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], i32 [[RS1]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)3404// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]3405//3406vuint32m2_t test_vmadd_vx_u32m2_mu(vbool16_t mask, vuint32m2_t vd, uint32_t rs1, vuint32m2_t vs2, size_t vl) {3407  return __riscv_vmadd_vx_u32m2_mu(mask, vd, rs1, vs2, vl);3408}3409 3410// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vmadd_vv_u32m4_mu3411// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS1:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3412// CHECK-RV64-NEXT:  entry:3413// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmadd.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)3414// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]3415//3416vuint32m4_t test_vmadd_vv_u32m4_mu(vbool8_t mask, vuint32m4_t vd, vuint32m4_t vs1, vuint32m4_t vs2, size_t vl) {3417  return __riscv_vmadd_vv_u32m4_mu(mask, vd, vs1, vs2, vl);3418}3419 3420// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vmadd_vx_u32m4_mu3421// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[VD:%.*]], i32 noundef signext [[RS1:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3422// CHECK-RV64-NEXT:  entry:3423// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmadd.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], i32 [[RS1]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)3424// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]3425//3426vuint32m4_t test_vmadd_vx_u32m4_mu(vbool8_t mask, vuint32m4_t vd, uint32_t rs1, vuint32m4_t vs2, size_t vl) {3427  return __riscv_vmadd_vx_u32m4_mu(mask, vd, rs1, vs2, vl);3428}3429 3430// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vmadd_vv_u32m8_mu3431// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS1:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3432// CHECK-RV64-NEXT:  entry:3433// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmadd.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)3434// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]3435//3436vuint32m8_t test_vmadd_vv_u32m8_mu(vbool4_t mask, vuint32m8_t vd, vuint32m8_t vs1, vuint32m8_t vs2, size_t vl) {3437  return __riscv_vmadd_vv_u32m8_mu(mask, vd, vs1, vs2, vl);3438}3439 3440// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vmadd_vx_u32m8_mu3441// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[VD:%.*]], i32 noundef signext [[RS1:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3442// CHECK-RV64-NEXT:  entry:3443// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmadd.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], i32 [[RS1]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)3444// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]3445//3446vuint32m8_t test_vmadd_vx_u32m8_mu(vbool4_t mask, vuint32m8_t vd, uint32_t rs1, vuint32m8_t vs2, size_t vl) {3447  return __riscv_vmadd_vx_u32m8_mu(mask, vd, rs1, vs2, vl);3448}3449 3450// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vmadd_vv_u64m1_mu3451// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS1:%.*]], <vscale x 1 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3452// CHECK-RV64-NEXT:  entry:3453// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmadd.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[VD]], <vscale x 1 x i64> [[VS1]], <vscale x 1 x i64> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)3454// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]3455//3456vuint64m1_t test_vmadd_vv_u64m1_mu(vbool64_t mask, vuint64m1_t vd, vuint64m1_t vs1, vuint64m1_t vs2, size_t vl) {3457  return __riscv_vmadd_vv_u64m1_mu(mask, vd, vs1, vs2, vl);3458}3459 3460// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vmadd_vx_u64m1_mu3461// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[VD:%.*]], i64 noundef [[RS1:%.*]], <vscale x 1 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3462// CHECK-RV64-NEXT:  entry:3463// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmadd.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[VD]], i64 [[RS1]], <vscale x 1 x i64> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)3464// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]3465//3466vuint64m1_t test_vmadd_vx_u64m1_mu(vbool64_t mask, vuint64m1_t vd, uint64_t rs1, vuint64m1_t vs2, size_t vl) {3467  return __riscv_vmadd_vx_u64m1_mu(mask, vd, rs1, vs2, vl);3468}3469 3470// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vmadd_vv_u64m2_mu3471// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS1:%.*]], <vscale x 2 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3472// CHECK-RV64-NEXT:  entry:3473// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmadd.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 2 x i64> [[VS1]], <vscale x 2 x i64> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)3474// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]3475//3476vuint64m2_t test_vmadd_vv_u64m2_mu(vbool32_t mask, vuint64m2_t vd, vuint64m2_t vs1, vuint64m2_t vs2, size_t vl) {3477  return __riscv_vmadd_vv_u64m2_mu(mask, vd, vs1, vs2, vl);3478}3479 3480// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vmadd_vx_u64m2_mu3481// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[VD:%.*]], i64 noundef [[RS1:%.*]], <vscale x 2 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3482// CHECK-RV64-NEXT:  entry:3483// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmadd.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[VD]], i64 [[RS1]], <vscale x 2 x i64> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)3484// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]3485//3486vuint64m2_t test_vmadd_vx_u64m2_mu(vbool32_t mask, vuint64m2_t vd, uint64_t rs1, vuint64m2_t vs2, size_t vl) {3487  return __riscv_vmadd_vx_u64m2_mu(mask, vd, rs1, vs2, vl);3488}3489 3490// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vmadd_vv_u64m4_mu3491// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS1:%.*]], <vscale x 4 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3492// CHECK-RV64-NEXT:  entry:3493// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmadd.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 4 x i64> [[VS1]], <vscale x 4 x i64> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)3494// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]3495//3496vuint64m4_t test_vmadd_vv_u64m4_mu(vbool16_t mask, vuint64m4_t vd, vuint64m4_t vs1, vuint64m4_t vs2, size_t vl) {3497  return __riscv_vmadd_vv_u64m4_mu(mask, vd, vs1, vs2, vl);3498}3499 3500// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vmadd_vx_u64m4_mu3501// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[VD:%.*]], i64 noundef [[RS1:%.*]], <vscale x 4 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3502// CHECK-RV64-NEXT:  entry:3503// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmadd.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[VD]], i64 [[RS1]], <vscale x 4 x i64> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)3504// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]3505//3506vuint64m4_t test_vmadd_vx_u64m4_mu(vbool16_t mask, vuint64m4_t vd, uint64_t rs1, vuint64m4_t vs2, size_t vl) {3507  return __riscv_vmadd_vx_u64m4_mu(mask, vd, rs1, vs2, vl);3508}3509 3510// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vmadd_vv_u64m8_mu3511// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS1:%.*]], <vscale x 8 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3512// CHECK-RV64-NEXT:  entry:3513// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmadd.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[VD]], <vscale x 8 x i64> [[VS1]], <vscale x 8 x i64> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)3514// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]3515//3516vuint64m8_t test_vmadd_vv_u64m8_mu(vbool8_t mask, vuint64m8_t vd, vuint64m8_t vs1, vuint64m8_t vs2, size_t vl) {3517  return __riscv_vmadd_vv_u64m8_mu(mask, vd, vs1, vs2, vl);3518}3519 3520// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vmadd_vx_u64m8_mu3521// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[VD:%.*]], i64 noundef [[RS1:%.*]], <vscale x 8 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3522// CHECK-RV64-NEXT:  entry:3523// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmadd.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[VD]], i64 [[RS1]], <vscale x 8 x i64> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)3524// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]3525//3526vuint64m8_t test_vmadd_vx_u64m8_mu(vbool8_t mask, vuint64m8_t vd, uint64_t rs1, vuint64m8_t vs2, size_t vl) {3527  return __riscv_vmadd_vx_u64m8_mu(mask, vd, rs1, vs2, vl);3528}3529 3530