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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 22// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone \4// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \5// RUN: FileCheck --check-prefix=CHECK-RV64 %s6 7#include <riscv_vector.h>8 9// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vsext_vf4_i32mf2_tu10// CHECK-RV64-SAME: (<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {11// CHECK-RV64-NEXT: entry:12// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], i64 [[VL]])13// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]14//15vint32mf2_t test_vsext_vf4_i32mf2_tu(vint32mf2_t maskedoff, vint8mf8_t op1, size_t vl) {16 return __riscv_vsext_vf4_i32mf2_tu(maskedoff, op1, vl);17}18 19// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vsext_vf4_i32m1_tu20// CHECK-RV64-SAME: (<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {21// CHECK-RV64-NEXT: entry:22// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], i64 [[VL]])23// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]24//25vint32m1_t test_vsext_vf4_i32m1_tu(vint32m1_t maskedoff, vint8mf4_t op1, size_t vl) {26 return __riscv_vsext_vf4_i32m1_tu(maskedoff, op1, vl);27}28 29// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vsext_vf4_i32m2_tu30// CHECK-RV64-SAME: (<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {31// CHECK-RV64-NEXT: entry:32// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x i8> [[OP1]], i64 [[VL]])33// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]34//35vint32m2_t test_vsext_vf4_i32m2_tu(vint32m2_t maskedoff, vint8mf2_t op1, size_t vl) {36 return __riscv_vsext_vf4_i32m2_tu(maskedoff, op1, vl);37}38 39// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vsext_vf4_i32m4_tu40// CHECK-RV64-SAME: (<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {41// CHECK-RV64-NEXT: entry:42// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x i8> [[OP1]], i64 [[VL]])43// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]44//45vint32m4_t test_vsext_vf4_i32m4_tu(vint32m4_t maskedoff, vint8m1_t op1, size_t vl) {46 return __riscv_vsext_vf4_i32m4_tu(maskedoff, op1, vl);47}48 49// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vsext_vf4_i32m8_tu50// CHECK-RV64-SAME: (<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {51// CHECK-RV64-NEXT: entry:52// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x i8> [[OP1]], i64 [[VL]])53// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]54//55vint32m8_t test_vsext_vf4_i32m8_tu(vint32m8_t maskedoff, vint8m2_t op1, size_t vl) {56 return __riscv_vsext_vf4_i32m8_tu(maskedoff, op1, vl);57}58 59// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vsext_vf4_i64m1_tu60// CHECK-RV64-SAME: (<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {61// CHECK-RV64-NEXT: entry:62// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]], i64 [[VL]])63// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]64//65vint64m1_t test_vsext_vf4_i64m1_tu(vint64m1_t maskedoff, vint16mf4_t op1, size_t vl) {66 return __riscv_vsext_vf4_i64m1_tu(maskedoff, op1, vl);67}68 69// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vsext_vf4_i64m2_tu70// CHECK-RV64-SAME: (<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {71// CHECK-RV64-NEXT: entry:72// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]], i64 [[VL]])73// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]74//75vint64m2_t test_vsext_vf4_i64m2_tu(vint64m2_t maskedoff, vint16mf2_t op1, size_t vl) {76 return __riscv_vsext_vf4_i64m2_tu(maskedoff, op1, vl);77}78 79// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vsext_vf4_i64m4_tu80// CHECK-RV64-SAME: (<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {81// CHECK-RV64-NEXT: entry:82// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]], i64 [[VL]])83// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]84//85vint64m4_t test_vsext_vf4_i64m4_tu(vint64m4_t maskedoff, vint16m1_t op1, size_t vl) {86 return __riscv_vsext_vf4_i64m4_tu(maskedoff, op1, vl);87}88 89// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vsext_vf4_i64m8_tu90// CHECK-RV64-SAME: (<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {91// CHECK-RV64-NEXT: entry:92// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]], i64 [[VL]])93// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]94//95vint64m8_t test_vsext_vf4_i64m8_tu(vint64m8_t maskedoff, vint16m2_t op1, size_t vl) {96 return __riscv_vsext_vf4_i64m8_tu(maskedoff, op1, vl);97}98 99// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vsext_vf4_i32mf2_tum100// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {101// CHECK-RV64-NEXT: entry:102// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vsext.mask.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)103// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]104//105vint32mf2_t test_vsext_vf4_i32mf2_tum(vbool64_t mask, vint32mf2_t maskedoff, vint8mf8_t op1, size_t vl) {106 return __riscv_vsext_vf4_i32mf2_tum(mask, maskedoff, op1, vl);107}108 109// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vsext_vf4_i32m1_tum110// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {111// CHECK-RV64-NEXT: entry:112// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vsext.mask.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)113// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]114//115vint32m1_t test_vsext_vf4_i32m1_tum(vbool32_t mask, vint32m1_t maskedoff, vint8mf4_t op1, size_t vl) {116 return __riscv_vsext_vf4_i32m1_tum(mask, maskedoff, op1, vl);117}118 119// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vsext_vf4_i32m2_tum120// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {121// CHECK-RV64-NEXT: entry:122// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vsext.mask.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x i8> [[OP1]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)123// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]124//125vint32m2_t test_vsext_vf4_i32m2_tum(vbool16_t mask, vint32m2_t maskedoff, vint8mf2_t op1, size_t vl) {126 return __riscv_vsext_vf4_i32m2_tum(mask, maskedoff, op1, vl);127}128 129// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vsext_vf4_i32m4_tum130// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {131// CHECK-RV64-NEXT: entry:132// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vsext.mask.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x i8> [[OP1]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)133// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]134//135vint32m4_t test_vsext_vf4_i32m4_tum(vbool8_t mask, vint32m4_t maskedoff, vint8m1_t op1, size_t vl) {136 return __riscv_vsext_vf4_i32m4_tum(mask, maskedoff, op1, vl);137}138 139// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vsext_vf4_i32m8_tum140// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {141// CHECK-RV64-NEXT: entry:142// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vsext.mask.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x i8> [[OP1]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)143// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]144//145vint32m8_t test_vsext_vf4_i32m8_tum(vbool4_t mask, vint32m8_t maskedoff, vint8m2_t op1, size_t vl) {146 return __riscv_vsext_vf4_i32m8_tum(mask, maskedoff, op1, vl);147}148 149// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vsext_vf4_i64m1_tum150// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {151// CHECK-RV64-NEXT: entry:152// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)153// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]154//155vint64m1_t test_vsext_vf4_i64m1_tum(vbool64_t mask, vint64m1_t maskedoff, vint16mf4_t op1, size_t vl) {156 return __riscv_vsext_vf4_i64m1_tum(mask, maskedoff, op1, vl);157}158 159// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vsext_vf4_i64m2_tum160// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {161// CHECK-RV64-NEXT: entry:162// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)163// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]164//165vint64m2_t test_vsext_vf4_i64m2_tum(vbool32_t mask, vint64m2_t maskedoff, vint16mf2_t op1, size_t vl) {166 return __riscv_vsext_vf4_i64m2_tum(mask, maskedoff, op1, vl);167}168 169// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vsext_vf4_i64m4_tum170// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {171// CHECK-RV64-NEXT: entry:172// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)173// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]174//175vint64m4_t test_vsext_vf4_i64m4_tum(vbool16_t mask, vint64m4_t maskedoff, vint16m1_t op1, size_t vl) {176 return __riscv_vsext_vf4_i64m4_tum(mask, maskedoff, op1, vl);177}178 179// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vsext_vf4_i64m8_tum180// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {181// CHECK-RV64-NEXT: entry:182// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)183// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]184//185vint64m8_t test_vsext_vf4_i64m8_tum(vbool8_t mask, vint64m8_t maskedoff, vint16m2_t op1, size_t vl) {186 return __riscv_vsext_vf4_i64m8_tum(mask, maskedoff, op1, vl);187}188 189// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vsext_vf4_i32mf2_tumu190// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {191// CHECK-RV64-NEXT: entry:192// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vsext.mask.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)193// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]194//195vint32mf2_t test_vsext_vf4_i32mf2_tumu(vbool64_t mask, vint32mf2_t maskedoff, vint8mf8_t op1, size_t vl) {196 return __riscv_vsext_vf4_i32mf2_tumu(mask, maskedoff, op1, vl);197}198 199// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vsext_vf4_i32m1_tumu200// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {201// CHECK-RV64-NEXT: entry:202// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vsext.mask.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)203// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]204//205vint32m1_t test_vsext_vf4_i32m1_tumu(vbool32_t mask, vint32m1_t maskedoff, vint8mf4_t op1, size_t vl) {206 return __riscv_vsext_vf4_i32m1_tumu(mask, maskedoff, op1, vl);207}208 209// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vsext_vf4_i32m2_tumu210// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {211// CHECK-RV64-NEXT: entry:212// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vsext.mask.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x i8> [[OP1]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)213// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]214//215vint32m2_t test_vsext_vf4_i32m2_tumu(vbool16_t mask, vint32m2_t maskedoff, vint8mf2_t op1, size_t vl) {216 return __riscv_vsext_vf4_i32m2_tumu(mask, maskedoff, op1, vl);217}218 219// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vsext_vf4_i32m4_tumu220// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {221// CHECK-RV64-NEXT: entry:222// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vsext.mask.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x i8> [[OP1]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)223// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]224//225vint32m4_t test_vsext_vf4_i32m4_tumu(vbool8_t mask, vint32m4_t maskedoff, vint8m1_t op1, size_t vl) {226 return __riscv_vsext_vf4_i32m4_tumu(mask, maskedoff, op1, vl);227}228 229// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vsext_vf4_i32m8_tumu230// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {231// CHECK-RV64-NEXT: entry:232// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vsext.mask.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x i8> [[OP1]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)233// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]234//235vint32m8_t test_vsext_vf4_i32m8_tumu(vbool4_t mask, vint32m8_t maskedoff, vint8m2_t op1, size_t vl) {236 return __riscv_vsext_vf4_i32m8_tumu(mask, maskedoff, op1, vl);237}238 239// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vsext_vf4_i64m1_tumu240// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {241// CHECK-RV64-NEXT: entry:242// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)243// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]244//245vint64m1_t test_vsext_vf4_i64m1_tumu(vbool64_t mask, vint64m1_t maskedoff, vint16mf4_t op1, size_t vl) {246 return __riscv_vsext_vf4_i64m1_tumu(mask, maskedoff, op1, vl);247}248 249// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vsext_vf4_i64m2_tumu250// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {251// CHECK-RV64-NEXT: entry:252// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)253// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]254//255vint64m2_t test_vsext_vf4_i64m2_tumu(vbool32_t mask, vint64m2_t maskedoff, vint16mf2_t op1, size_t vl) {256 return __riscv_vsext_vf4_i64m2_tumu(mask, maskedoff, op1, vl);257}258 259// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vsext_vf4_i64m4_tumu260// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {261// CHECK-RV64-NEXT: entry:262// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)263// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]264//265vint64m4_t test_vsext_vf4_i64m4_tumu(vbool16_t mask, vint64m4_t maskedoff, vint16m1_t op1, size_t vl) {266 return __riscv_vsext_vf4_i64m4_tumu(mask, maskedoff, op1, vl);267}268 269// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vsext_vf4_i64m8_tumu270// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {271// CHECK-RV64-NEXT: entry:272// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)273// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]274//275vint64m8_t test_vsext_vf4_i64m8_tumu(vbool8_t mask, vint64m8_t maskedoff, vint16m2_t op1, size_t vl) {276 return __riscv_vsext_vf4_i64m8_tumu(mask, maskedoff, op1, vl);277}278 279// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vsext_vf4_i32mf2_mu280// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {281// CHECK-RV64-NEXT: entry:282// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vsext.mask.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)283// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]284//285vint32mf2_t test_vsext_vf4_i32mf2_mu(vbool64_t mask, vint32mf2_t maskedoff, vint8mf8_t op1, size_t vl) {286 return __riscv_vsext_vf4_i32mf2_mu(mask, maskedoff, op1, vl);287}288 289// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vsext_vf4_i32m1_mu290// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {291// CHECK-RV64-NEXT: entry:292// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vsext.mask.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)293// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]294//295vint32m1_t test_vsext_vf4_i32m1_mu(vbool32_t mask, vint32m1_t maskedoff, vint8mf4_t op1, size_t vl) {296 return __riscv_vsext_vf4_i32m1_mu(mask, maskedoff, op1, vl);297}298 299// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vsext_vf4_i32m2_mu300// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {301// CHECK-RV64-NEXT: entry:302// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vsext.mask.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x i8> [[OP1]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)303// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]304//305vint32m2_t test_vsext_vf4_i32m2_mu(vbool16_t mask, vint32m2_t maskedoff, vint8mf2_t op1, size_t vl) {306 return __riscv_vsext_vf4_i32m2_mu(mask, maskedoff, op1, vl);307}308 309// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vsext_vf4_i32m4_mu310// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {311// CHECK-RV64-NEXT: entry:312// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vsext.mask.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x i8> [[OP1]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)313// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]314//315vint32m4_t test_vsext_vf4_i32m4_mu(vbool8_t mask, vint32m4_t maskedoff, vint8m1_t op1, size_t vl) {316 return __riscv_vsext_vf4_i32m4_mu(mask, maskedoff, op1, vl);317}318 319// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vsext_vf4_i32m8_mu320// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {321// CHECK-RV64-NEXT: entry:322// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vsext.mask.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x i8> [[OP1]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)323// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]324//325vint32m8_t test_vsext_vf4_i32m8_mu(vbool4_t mask, vint32m8_t maskedoff, vint8m2_t op1, size_t vl) {326 return __riscv_vsext_vf4_i32m8_mu(mask, maskedoff, op1, vl);327}328 329// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vsext_vf4_i64m1_mu330// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {331// CHECK-RV64-NEXT: entry:332// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)333// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]334//335vint64m1_t test_vsext_vf4_i64m1_mu(vbool64_t mask, vint64m1_t maskedoff, vint16mf4_t op1, size_t vl) {336 return __riscv_vsext_vf4_i64m1_mu(mask, maskedoff, op1, vl);337}338 339// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vsext_vf4_i64m2_mu340// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {341// CHECK-RV64-NEXT: entry:342// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)343// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]344//345vint64m2_t test_vsext_vf4_i64m2_mu(vbool32_t mask, vint64m2_t maskedoff, vint16mf2_t op1, size_t vl) {346 return __riscv_vsext_vf4_i64m2_mu(mask, maskedoff, op1, vl);347}348 349// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vsext_vf4_i64m4_mu350// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {351// CHECK-RV64-NEXT: entry:352// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)353// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]354//355vint64m4_t test_vsext_vf4_i64m4_mu(vbool16_t mask, vint64m4_t maskedoff, vint16m1_t op1, size_t vl) {356 return __riscv_vsext_vf4_i64m4_mu(mask, maskedoff, op1, vl);357}358 359// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vsext_vf4_i64m8_mu360// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {361// CHECK-RV64-NEXT: entry:362// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)363// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]364//365vint64m8_t test_vsext_vf4_i64m8_mu(vbool8_t mask, vint64m8_t maskedoff, vint16m2_t op1, size_t vl) {366 return __riscv_vsext_vf4_i64m8_mu(mask, maskedoff, op1, vl);367}368 369