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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 22// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \4// RUN: -target-feature +zvfh -disable-O0-optnone \5// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \6// RUN: FileCheck --check-prefix=CHECK-RV64 %s7 8#include <riscv_vector.h>9 10// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_i8mf8_tu11// CHECK-RV64-SAME: (<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {12// CHECK-RV64-NEXT: entry:13// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> [[MASKEDOFF]], <vscale x 1 x half> [[SRC]], i64 7, i64 [[VL]])14// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]15//16vint8mf8_t test_vfncvt_x_f_w_i8mf8_tu(vint8mf8_t maskedoff, vfloat16mf4_t src, size_t vl) {17 return __riscv_vfncvt_x_tu(maskedoff, src, vl);18}19 20// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vfncvt_x_f_w_i8mf4_tu21// CHECK-RV64-SAME: (<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {22// CHECK-RV64-NEXT: entry:23// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> [[MASKEDOFF]], <vscale x 2 x half> [[SRC]], i64 7, i64 [[VL]])24// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]25//26vint8mf4_t test_vfncvt_x_f_w_i8mf4_tu(vint8mf4_t maskedoff, vfloat16mf2_t src, size_t vl) {27 return __riscv_vfncvt_x_tu(maskedoff, src, vl);28}29 30// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vfncvt_x_f_w_i8mf2_tu31// CHECK-RV64-SAME: (<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {32// CHECK-RV64-NEXT: entry:33// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> [[MASKEDOFF]], <vscale x 4 x half> [[SRC]], i64 7, i64 [[VL]])34// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]35//36vint8mf2_t test_vfncvt_x_f_w_i8mf2_tu(vint8mf2_t maskedoff, vfloat16m1_t src, size_t vl) {37 return __riscv_vfncvt_x_tu(maskedoff, src, vl);38}39 40// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vfncvt_x_f_w_i8m1_tu41// CHECK-RV64-SAME: (<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {42// CHECK-RV64-NEXT: entry:43// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> [[MASKEDOFF]], <vscale x 8 x half> [[SRC]], i64 7, i64 [[VL]])44// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]45//46vint8m1_t test_vfncvt_x_f_w_i8m1_tu(vint8m1_t maskedoff, vfloat16m2_t src, size_t vl) {47 return __riscv_vfncvt_x_tu(maskedoff, src, vl);48}49 50// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vfncvt_x_f_w_i8m2_tu51// CHECK-RV64-SAME: (<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {52// CHECK-RV64-NEXT: entry:53// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> [[MASKEDOFF]], <vscale x 16 x half> [[SRC]], i64 7, i64 [[VL]])54// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]55//56vint8m2_t test_vfncvt_x_f_w_i8m2_tu(vint8m2_t maskedoff, vfloat16m4_t src, size_t vl) {57 return __riscv_vfncvt_x_tu(maskedoff, src, vl);58}59 60// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vfncvt_x_f_w_i8m4_tu61// CHECK-RV64-SAME: (<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {62// CHECK-RV64-NEXT: entry:63// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> [[MASKEDOFF]], <vscale x 32 x half> [[SRC]], i64 7, i64 [[VL]])64// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]65//66vint8m4_t test_vfncvt_x_f_w_i8m4_tu(vint8m4_t maskedoff, vfloat16m8_t src, size_t vl) {67 return __riscv_vfncvt_x_tu(maskedoff, src, vl);68}69 70// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vfncvt_xu_f_w_u8mf8_tu71// CHECK-RV64-SAME: (<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {72// CHECK-RV64-NEXT: entry:73// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> [[MASKEDOFF]], <vscale x 1 x half> [[SRC]], i64 7, i64 [[VL]])74// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]75//76vuint8mf8_t test_vfncvt_xu_f_w_u8mf8_tu(vuint8mf8_t maskedoff, vfloat16mf4_t src, size_t vl) {77 return __riscv_vfncvt_xu_tu(maskedoff, src, vl);78}79 80// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vfncvt_xu_f_w_u8mf4_tu81// CHECK-RV64-SAME: (<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {82// CHECK-RV64-NEXT: entry:83// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> [[MASKEDOFF]], <vscale x 2 x half> [[SRC]], i64 7, i64 [[VL]])84// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]85//86vuint8mf4_t test_vfncvt_xu_f_w_u8mf4_tu(vuint8mf4_t maskedoff, vfloat16mf2_t src, size_t vl) {87 return __riscv_vfncvt_xu_tu(maskedoff, src, vl);88}89 90// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vfncvt_xu_f_w_u8mf2_tu91// CHECK-RV64-SAME: (<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {92// CHECK-RV64-NEXT: entry:93// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> [[MASKEDOFF]], <vscale x 4 x half> [[SRC]], i64 7, i64 [[VL]])94// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]95//96vuint8mf2_t test_vfncvt_xu_f_w_u8mf2_tu(vuint8mf2_t maskedoff, vfloat16m1_t src, size_t vl) {97 return __riscv_vfncvt_xu_tu(maskedoff, src, vl);98}99 100// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vfncvt_xu_f_w_u8m1_tu101// CHECK-RV64-SAME: (<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {102// CHECK-RV64-NEXT: entry:103// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> [[MASKEDOFF]], <vscale x 8 x half> [[SRC]], i64 7, i64 [[VL]])104// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]105//106vuint8m1_t test_vfncvt_xu_f_w_u8m1_tu(vuint8m1_t maskedoff, vfloat16m2_t src, size_t vl) {107 return __riscv_vfncvt_xu_tu(maskedoff, src, vl);108}109 110// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vfncvt_xu_f_w_u8m2_tu111// CHECK-RV64-SAME: (<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {112// CHECK-RV64-NEXT: entry:113// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> [[MASKEDOFF]], <vscale x 16 x half> [[SRC]], i64 7, i64 [[VL]])114// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]115//116vuint8m2_t test_vfncvt_xu_f_w_u8m2_tu(vuint8m2_t maskedoff, vfloat16m4_t src, size_t vl) {117 return __riscv_vfncvt_xu_tu(maskedoff, src, vl);118}119 120// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vfncvt_xu_f_w_u8m4_tu121// CHECK-RV64-SAME: (<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {122// CHECK-RV64-NEXT: entry:123// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> [[MASKEDOFF]], <vscale x 32 x half> [[SRC]], i64 7, i64 [[VL]])124// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]125//126vuint8m4_t test_vfncvt_xu_f_w_u8m4_tu(vuint8m4_t maskedoff, vfloat16m8_t src, size_t vl) {127 return __riscv_vfncvt_xu_tu(maskedoff, src, vl);128}129 130// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vfncvt_x_f_w_i16mf4_tu131// CHECK-RV64-SAME: (<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {132// CHECK-RV64-NEXT: entry:133// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfncvt.x.f.w.nxv1i16.nxv1f32.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x float> [[SRC]], i64 7, i64 [[VL]])134// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]135//136vint16mf4_t test_vfncvt_x_f_w_i16mf4_tu(vint16mf4_t maskedoff, vfloat32mf2_t src, size_t vl) {137 return __riscv_vfncvt_x_tu(maskedoff, src, vl);138}139 140// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vfncvt_x_f_w_i16mf2_tu141// CHECK-RV64-SAME: (<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {142// CHECK-RV64-NEXT: entry:143// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfncvt.x.f.w.nxv2i16.nxv2f32.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x float> [[SRC]], i64 7, i64 [[VL]])144// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]145//146vint16mf2_t test_vfncvt_x_f_w_i16mf2_tu(vint16mf2_t maskedoff, vfloat32m1_t src, size_t vl) {147 return __riscv_vfncvt_x_tu(maskedoff, src, vl);148}149 150// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfncvt_x_f_w_i16m1_tu151// CHECK-RV64-SAME: (<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {152// CHECK-RV64-NEXT: entry:153// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfncvt.x.f.w.nxv4i16.nxv4f32.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x float> [[SRC]], i64 7, i64 [[VL]])154// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]155//156vint16m1_t test_vfncvt_x_f_w_i16m1_tu(vint16m1_t maskedoff, vfloat32m2_t src, size_t vl) {157 return __riscv_vfncvt_x_tu(maskedoff, src, vl);158}159 160// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfncvt_x_f_w_i16m2_tu161// CHECK-RV64-SAME: (<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {162// CHECK-RV64-NEXT: entry:163// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfncvt.x.f.w.nxv8i16.nxv8f32.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x float> [[SRC]], i64 7, i64 [[VL]])164// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]165//166vint16m2_t test_vfncvt_x_f_w_i16m2_tu(vint16m2_t maskedoff, vfloat32m4_t src, size_t vl) {167 return __riscv_vfncvt_x_tu(maskedoff, src, vl);168}169 170// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfncvt_x_f_w_i16m4_tu171// CHECK-RV64-SAME: (<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {172// CHECK-RV64-NEXT: entry:173// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfncvt.x.f.w.nxv16i16.nxv16f32.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x float> [[SRC]], i64 7, i64 [[VL]])174// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]175//176vint16m4_t test_vfncvt_x_f_w_i16m4_tu(vint16m4_t maskedoff, vfloat32m8_t src, size_t vl) {177 return __riscv_vfncvt_x_tu(maskedoff, src, vl);178}179 180// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vfncvt_xu_f_w_u16mf4_tu181// CHECK-RV64-SAME: (<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {182// CHECK-RV64-NEXT: entry:183// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv1i16.nxv1f32.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x float> [[SRC]], i64 7, i64 [[VL]])184// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]185//186vuint16mf4_t test_vfncvt_xu_f_w_u16mf4_tu(vuint16mf4_t maskedoff, vfloat32mf2_t src, size_t vl) {187 return __riscv_vfncvt_xu_tu(maskedoff, src, vl);188}189 190// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vfncvt_xu_f_w_u16mf2_tu191// CHECK-RV64-SAME: (<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {192// CHECK-RV64-NEXT: entry:193// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv2i16.nxv2f32.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x float> [[SRC]], i64 7, i64 [[VL]])194// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]195//196vuint16mf2_t test_vfncvt_xu_f_w_u16mf2_tu(vuint16mf2_t maskedoff, vfloat32m1_t src, size_t vl) {197 return __riscv_vfncvt_xu_tu(maskedoff, src, vl);198}199 200// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfncvt_xu_f_w_u16m1_tu201// CHECK-RV64-SAME: (<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {202// CHECK-RV64-NEXT: entry:203// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv4i16.nxv4f32.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x float> [[SRC]], i64 7, i64 [[VL]])204// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]205//206vuint16m1_t test_vfncvt_xu_f_w_u16m1_tu(vuint16m1_t maskedoff, vfloat32m2_t src, size_t vl) {207 return __riscv_vfncvt_xu_tu(maskedoff, src, vl);208}209 210// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfncvt_xu_f_w_u16m2_tu211// CHECK-RV64-SAME: (<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {212// CHECK-RV64-NEXT: entry:213// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv8i16.nxv8f32.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x float> [[SRC]], i64 7, i64 [[VL]])214// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]215//216vuint16m2_t test_vfncvt_xu_f_w_u16m2_tu(vuint16m2_t maskedoff, vfloat32m4_t src, size_t vl) {217 return __riscv_vfncvt_xu_tu(maskedoff, src, vl);218}219 220// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfncvt_xu_f_w_u16m4_tu221// CHECK-RV64-SAME: (<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {222// CHECK-RV64-NEXT: entry:223// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv16i16.nxv16f32.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x float> [[SRC]], i64 7, i64 [[VL]])224// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]225//226vuint16m4_t test_vfncvt_xu_f_w_u16m4_tu(vuint16m4_t maskedoff, vfloat32m8_t src, size_t vl) {227 return __riscv_vfncvt_xu_tu(maskedoff, src, vl);228}229 230// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfncvt_f_x_w_f16mf4_tu231// CHECK-RV64-SAME: (<vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {232// CHECK-RV64-NEXT: entry:233// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.x.w.nxv1f16.nxv1i32.i64(<vscale x 1 x half> [[MASKEDOFF]], <vscale x 1 x i32> [[SRC]], i64 7, i64 [[VL]])234// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]235//236vfloat16mf4_t test_vfncvt_f_x_w_f16mf4_tu(vfloat16mf4_t maskedoff, vint32mf2_t src, size_t vl) {237 return __riscv_vfncvt_f_tu(maskedoff, src, vl);238}239 240// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfncvt_f_x_w_f16mf2_tu241// CHECK-RV64-SAME: (<vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {242// CHECK-RV64-NEXT: entry:243// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.x.w.nxv2f16.nxv2i32.i64(<vscale x 2 x half> [[MASKEDOFF]], <vscale x 2 x i32> [[SRC]], i64 7, i64 [[VL]])244// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]245//246vfloat16mf2_t test_vfncvt_f_x_w_f16mf2_tu(vfloat16mf2_t maskedoff, vint32m1_t src, size_t vl) {247 return __riscv_vfncvt_f_tu(maskedoff, src, vl);248}249 250// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfncvt_f_x_w_f16m1_tu251// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {252// CHECK-RV64-NEXT: entry:253// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.x.w.nxv4f16.nxv4i32.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x i32> [[SRC]], i64 7, i64 [[VL]])254// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]255//256vfloat16m1_t test_vfncvt_f_x_w_f16m1_tu(vfloat16m1_t maskedoff, vint32m2_t src, size_t vl) {257 return __riscv_vfncvt_f_tu(maskedoff, src, vl);258}259 260// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfncvt_f_x_w_f16m2_tu261// CHECK-RV64-SAME: (<vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {262// CHECK-RV64-NEXT: entry:263// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.x.w.nxv8f16.nxv8i32.i64(<vscale x 8 x half> [[MASKEDOFF]], <vscale x 8 x i32> [[SRC]], i64 7, i64 [[VL]])264// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]265//266vfloat16m2_t test_vfncvt_f_x_w_f16m2_tu(vfloat16m2_t maskedoff, vint32m4_t src, size_t vl) {267 return __riscv_vfncvt_f_tu(maskedoff, src, vl);268}269 270// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfncvt_f_x_w_f16m4_tu271// CHECK-RV64-SAME: (<vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {272// CHECK-RV64-NEXT: entry:273// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.x.w.nxv16f16.nxv16i32.i64(<vscale x 16 x half> [[MASKEDOFF]], <vscale x 16 x i32> [[SRC]], i64 7, i64 [[VL]])274// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]275//276vfloat16m4_t test_vfncvt_f_x_w_f16m4_tu(vfloat16m4_t maskedoff, vint32m8_t src, size_t vl) {277 return __riscv_vfncvt_f_tu(maskedoff, src, vl);278}279 280// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfncvt_f_xu_w_f16mf4_tu281// CHECK-RV64-SAME: (<vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {282// CHECK-RV64-NEXT: entry:283// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.xu.w.nxv1f16.nxv1i32.i64(<vscale x 1 x half> [[MASKEDOFF]], <vscale x 1 x i32> [[SRC]], i64 7, i64 [[VL]])284// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]285//286vfloat16mf4_t test_vfncvt_f_xu_w_f16mf4_tu(vfloat16mf4_t maskedoff, vuint32mf2_t src, size_t vl) {287 return __riscv_vfncvt_f_tu(maskedoff, src, vl);288}289 290// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfncvt_f_xu_w_f16mf2_tu291// CHECK-RV64-SAME: (<vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {292// CHECK-RV64-NEXT: entry:293// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.xu.w.nxv2f16.nxv2i32.i64(<vscale x 2 x half> [[MASKEDOFF]], <vscale x 2 x i32> [[SRC]], i64 7, i64 [[VL]])294// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]295//296vfloat16mf2_t test_vfncvt_f_xu_w_f16mf2_tu(vfloat16mf2_t maskedoff, vuint32m1_t src, size_t vl) {297 return __riscv_vfncvt_f_tu(maskedoff, src, vl);298}299 300// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfncvt_f_xu_w_f16m1_tu301// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {302// CHECK-RV64-NEXT: entry:303// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.xu.w.nxv4f16.nxv4i32.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x i32> [[SRC]], i64 7, i64 [[VL]])304// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]305//306vfloat16m1_t test_vfncvt_f_xu_w_f16m1_tu(vfloat16m1_t maskedoff, vuint32m2_t src, size_t vl) {307 return __riscv_vfncvt_f_tu(maskedoff, src, vl);308}309 310// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfncvt_f_xu_w_f16m2_tu311// CHECK-RV64-SAME: (<vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {312// CHECK-RV64-NEXT: entry:313// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.xu.w.nxv8f16.nxv8i32.i64(<vscale x 8 x half> [[MASKEDOFF]], <vscale x 8 x i32> [[SRC]], i64 7, i64 [[VL]])314// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]315//316vfloat16m2_t test_vfncvt_f_xu_w_f16m2_tu(vfloat16m2_t maskedoff, vuint32m4_t src, size_t vl) {317 return __riscv_vfncvt_f_tu(maskedoff, src, vl);318}319 320// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfncvt_f_xu_w_f16m4_tu321// CHECK-RV64-SAME: (<vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {322// CHECK-RV64-NEXT: entry:323// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.xu.w.nxv16f16.nxv16i32.i64(<vscale x 16 x half> [[MASKEDOFF]], <vscale x 16 x i32> [[SRC]], i64 7, i64 [[VL]])324// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]325//326vfloat16m4_t test_vfncvt_f_xu_w_f16m4_tu(vfloat16m4_t maskedoff, vuint32m8_t src, size_t vl) {327 return __riscv_vfncvt_f_tu(maskedoff, src, vl);328}329 330// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfncvt_x_f_w_i32mf2_tu331// CHECK-RV64-SAME: (<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {332// CHECK-RV64-NEXT: entry:333// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfncvt.x.f.w.nxv1i32.nxv1f64.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x double> [[SRC]], i64 7, i64 [[VL]])334// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]335//336vint32mf2_t test_vfncvt_x_f_w_i32mf2_tu(vint32mf2_t maskedoff, vfloat64m1_t src, size_t vl) {337 return __riscv_vfncvt_x_tu(maskedoff, src, vl);338}339 340// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfncvt_x_f_w_i32m1_tu341// CHECK-RV64-SAME: (<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {342// CHECK-RV64-NEXT: entry:343// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfncvt.x.f.w.nxv2i32.nxv2f64.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x double> [[SRC]], i64 7, i64 [[VL]])344// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]345//346vint32m1_t test_vfncvt_x_f_w_i32m1_tu(vint32m1_t maskedoff, vfloat64m2_t src, size_t vl) {347 return __riscv_vfncvt_x_tu(maskedoff, src, vl);348}349 350// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfncvt_x_f_w_i32m2_tu351// CHECK-RV64-SAME: (<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {352// CHECK-RV64-NEXT: entry:353// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfncvt.x.f.w.nxv4i32.nxv4f64.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x double> [[SRC]], i64 7, i64 [[VL]])354// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]355//356vint32m2_t test_vfncvt_x_f_w_i32m2_tu(vint32m2_t maskedoff, vfloat64m4_t src, size_t vl) {357 return __riscv_vfncvt_x_tu(maskedoff, src, vl);358}359 360// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfncvt_x_f_w_i32m4_tu361// CHECK-RV64-SAME: (<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {362// CHECK-RV64-NEXT: entry:363// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfncvt.x.f.w.nxv8i32.nxv8f64.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x double> [[SRC]], i64 7, i64 [[VL]])364// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]365//366vint32m4_t test_vfncvt_x_f_w_i32m4_tu(vint32m4_t maskedoff, vfloat64m8_t src, size_t vl) {367 return __riscv_vfncvt_x_tu(maskedoff, src, vl);368}369 370// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfncvt_xu_f_w_u32mf2_tu371// CHECK-RV64-SAME: (<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {372// CHECK-RV64-NEXT: entry:373// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv1i32.nxv1f64.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x double> [[SRC]], i64 7, i64 [[VL]])374// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]375//376vuint32mf2_t test_vfncvt_xu_f_w_u32mf2_tu(vuint32mf2_t maskedoff, vfloat64m1_t src, size_t vl) {377 return __riscv_vfncvt_xu_tu(maskedoff, src, vl);378}379 380// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfncvt_xu_f_w_u32m1_tu381// CHECK-RV64-SAME: (<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {382// CHECK-RV64-NEXT: entry:383// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv2i32.nxv2f64.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x double> [[SRC]], i64 7, i64 [[VL]])384// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]385//386vuint32m1_t test_vfncvt_xu_f_w_u32m1_tu(vuint32m1_t maskedoff, vfloat64m2_t src, size_t vl) {387 return __riscv_vfncvt_xu_tu(maskedoff, src, vl);388}389 390// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfncvt_xu_f_w_u32m2_tu391// CHECK-RV64-SAME: (<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {392// CHECK-RV64-NEXT: entry:393// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv4i32.nxv4f64.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x double> [[SRC]], i64 7, i64 [[VL]])394// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]395//396vuint32m2_t test_vfncvt_xu_f_w_u32m2_tu(vuint32m2_t maskedoff, vfloat64m4_t src, size_t vl) {397 return __riscv_vfncvt_xu_tu(maskedoff, src, vl);398}399 400// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfncvt_xu_f_w_u32m4_tu401// CHECK-RV64-SAME: (<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {402// CHECK-RV64-NEXT: entry:403// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv8i32.nxv8f64.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x double> [[SRC]], i64 7, i64 [[VL]])404// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]405//406vuint32m4_t test_vfncvt_xu_f_w_u32m4_tu(vuint32m4_t maskedoff, vfloat64m8_t src, size_t vl) {407 return __riscv_vfncvt_xu_tu(maskedoff, src, vl);408}409 410// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfncvt_f_x_w_f32mf2_tu411// CHECK-RV64-SAME: (<vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {412// CHECK-RV64-NEXT: entry:413// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.x.w.nxv1f32.nxv1i64.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x i64> [[SRC]], i64 7, i64 [[VL]])414// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]415//416vfloat32mf2_t test_vfncvt_f_x_w_f32mf2_tu(vfloat32mf2_t maskedoff, vint64m1_t src, size_t vl) {417 return __riscv_vfncvt_f_tu(maskedoff, src, vl);418}419 420// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfncvt_f_x_w_f32m1_tu421// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {422// CHECK-RV64-NEXT: entry:423// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.x.w.nxv2f32.nxv2i64.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x i64> [[SRC]], i64 7, i64 [[VL]])424// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]425//426vfloat32m1_t test_vfncvt_f_x_w_f32m1_tu(vfloat32m1_t maskedoff, vint64m2_t src, size_t vl) {427 return __riscv_vfncvt_f_tu(maskedoff, src, vl);428}429 430// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfncvt_f_x_w_f32m2_tu431// CHECK-RV64-SAME: (<vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {432// CHECK-RV64-NEXT: entry:433// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.x.w.nxv4f32.nxv4i64.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x i64> [[SRC]], i64 7, i64 [[VL]])434// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]435//436vfloat32m2_t test_vfncvt_f_x_w_f32m2_tu(vfloat32m2_t maskedoff, vint64m4_t src, size_t vl) {437 return __riscv_vfncvt_f_tu(maskedoff, src, vl);438}439 440// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfncvt_f_x_w_f32m4_tu441// CHECK-RV64-SAME: (<vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {442// CHECK-RV64-NEXT: entry:443// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.x.w.nxv8f32.nxv8i64.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x i64> [[SRC]], i64 7, i64 [[VL]])444// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]445//446vfloat32m4_t test_vfncvt_f_x_w_f32m4_tu(vfloat32m4_t maskedoff, vint64m8_t src, size_t vl) {447 return __riscv_vfncvt_f_tu(maskedoff, src, vl);448}449 450// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfncvt_f_xu_w_f32mf2_tu451// CHECK-RV64-SAME: (<vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {452// CHECK-RV64-NEXT: entry:453// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.xu.w.nxv1f32.nxv1i64.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x i64> [[SRC]], i64 7, i64 [[VL]])454// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]455//456vfloat32mf2_t test_vfncvt_f_xu_w_f32mf2_tu(vfloat32mf2_t maskedoff, vuint64m1_t src, size_t vl) {457 return __riscv_vfncvt_f_tu(maskedoff, src, vl);458}459 460// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfncvt_f_xu_w_f32m1_tu461// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {462// CHECK-RV64-NEXT: entry:463// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.xu.w.nxv2f32.nxv2i64.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x i64> [[SRC]], i64 7, i64 [[VL]])464// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]465//466vfloat32m1_t test_vfncvt_f_xu_w_f32m1_tu(vfloat32m1_t maskedoff, vuint64m2_t src, size_t vl) {467 return __riscv_vfncvt_f_tu(maskedoff, src, vl);468}469 470// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfncvt_f_xu_w_f32m2_tu471// CHECK-RV64-SAME: (<vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {472// CHECK-RV64-NEXT: entry:473// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.xu.w.nxv4f32.nxv4i64.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x i64> [[SRC]], i64 7, i64 [[VL]])474// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]475//476vfloat32m2_t test_vfncvt_f_xu_w_f32m2_tu(vfloat32m2_t maskedoff, vuint64m4_t src, size_t vl) {477 return __riscv_vfncvt_f_tu(maskedoff, src, vl);478}479 480// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfncvt_f_xu_w_f32m4_tu481// CHECK-RV64-SAME: (<vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {482// CHECK-RV64-NEXT: entry:483// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.xu.w.nxv8f32.nxv8i64.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x i64> [[SRC]], i64 7, i64 [[VL]])484// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]485//486vfloat32m4_t test_vfncvt_f_xu_w_f32m4_tu(vfloat32m4_t maskedoff, vuint64m8_t src, size_t vl) {487 return __riscv_vfncvt_f_tu(maskedoff, src, vl);488}489 490// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_i8mf8_tum491// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {492// CHECK-RV64-NEXT: entry:493// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> [[MASKEDOFF]], <vscale x 1 x half> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)494// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]495//496vint8mf8_t test_vfncvt_x_f_w_i8mf8_tum(vbool64_t mask, vint8mf8_t maskedoff, vfloat16mf4_t src, size_t vl) {497 return __riscv_vfncvt_x_tum(mask, maskedoff, src, vl);498}499 500// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vfncvt_x_f_w_i8mf4_tum501// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {502// CHECK-RV64-NEXT: entry:503// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> [[MASKEDOFF]], <vscale x 2 x half> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)504// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]505//506vint8mf4_t test_vfncvt_x_f_w_i8mf4_tum(vbool32_t mask, vint8mf4_t maskedoff, vfloat16mf2_t src, size_t vl) {507 return __riscv_vfncvt_x_tum(mask, maskedoff, src, vl);508}509 510// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vfncvt_x_f_w_i8mf2_tum511// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {512// CHECK-RV64-NEXT: entry:513// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> [[MASKEDOFF]], <vscale x 4 x half> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)514// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]515//516vint8mf2_t test_vfncvt_x_f_w_i8mf2_tum(vbool16_t mask, vint8mf2_t maskedoff, vfloat16m1_t src, size_t vl) {517 return __riscv_vfncvt_x_tum(mask, maskedoff, src, vl);518}519 520// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vfncvt_x_f_w_i8m1_tum521// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {522// CHECK-RV64-NEXT: entry:523// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> [[MASKEDOFF]], <vscale x 8 x half> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)524// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]525//526vint8m1_t test_vfncvt_x_f_w_i8m1_tum(vbool8_t mask, vint8m1_t maskedoff, vfloat16m2_t src, size_t vl) {527 return __riscv_vfncvt_x_tum(mask, maskedoff, src, vl);528}529 530// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vfncvt_x_f_w_i8m2_tum531// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {532// CHECK-RV64-NEXT: entry:533// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> [[MASKEDOFF]], <vscale x 16 x half> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)534// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]535//536vint8m2_t test_vfncvt_x_f_w_i8m2_tum(vbool4_t mask, vint8m2_t maskedoff, vfloat16m4_t src, size_t vl) {537 return __riscv_vfncvt_x_tum(mask, maskedoff, src, vl);538}539 540// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vfncvt_x_f_w_i8m4_tum541// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {542// CHECK-RV64-NEXT: entry:543// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> [[MASKEDOFF]], <vscale x 32 x half> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)544// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]545//546vint8m4_t test_vfncvt_x_f_w_i8m4_tum(vbool2_t mask, vint8m4_t maskedoff, vfloat16m8_t src, size_t vl) {547 return __riscv_vfncvt_x_tum(mask, maskedoff, src, vl);548}549 550// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vfncvt_xu_f_w_u8mf8_tum551// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {552// CHECK-RV64-NEXT: entry:553// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> [[MASKEDOFF]], <vscale x 1 x half> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)554// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]555//556vuint8mf8_t test_vfncvt_xu_f_w_u8mf8_tum(vbool64_t mask, vuint8mf8_t maskedoff, vfloat16mf4_t src, size_t vl) {557 return __riscv_vfncvt_xu_tum(mask, maskedoff, src, vl);558}559 560// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vfncvt_xu_f_w_u8mf4_tum561// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {562// CHECK-RV64-NEXT: entry:563// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> [[MASKEDOFF]], <vscale x 2 x half> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)564// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]565//566vuint8mf4_t test_vfncvt_xu_f_w_u8mf4_tum(vbool32_t mask, vuint8mf4_t maskedoff, vfloat16mf2_t src, size_t vl) {567 return __riscv_vfncvt_xu_tum(mask, maskedoff, src, vl);568}569 570// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vfncvt_xu_f_w_u8mf2_tum571// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {572// CHECK-RV64-NEXT: entry:573// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> [[MASKEDOFF]], <vscale x 4 x half> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)574// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]575//576vuint8mf2_t test_vfncvt_xu_f_w_u8mf2_tum(vbool16_t mask, vuint8mf2_t maskedoff, vfloat16m1_t src, size_t vl) {577 return __riscv_vfncvt_xu_tum(mask, maskedoff, src, vl);578}579 580// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vfncvt_xu_f_w_u8m1_tum581// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {582// CHECK-RV64-NEXT: entry:583// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> [[MASKEDOFF]], <vscale x 8 x half> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)584// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]585//586vuint8m1_t test_vfncvt_xu_f_w_u8m1_tum(vbool8_t mask, vuint8m1_t maskedoff, vfloat16m2_t src, size_t vl) {587 return __riscv_vfncvt_xu_tum(mask, maskedoff, src, vl);588}589 590// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vfncvt_xu_f_w_u8m2_tum591// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {592// CHECK-RV64-NEXT: entry:593// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> [[MASKEDOFF]], <vscale x 16 x half> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)594// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]595//596vuint8m2_t test_vfncvt_xu_f_w_u8m2_tum(vbool4_t mask, vuint8m2_t maskedoff, vfloat16m4_t src, size_t vl) {597 return __riscv_vfncvt_xu_tum(mask, maskedoff, src, vl);598}599 600// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vfncvt_xu_f_w_u8m4_tum601// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {602// CHECK-RV64-NEXT: entry:603// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> [[MASKEDOFF]], <vscale x 32 x half> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)604// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]605//606vuint8m4_t test_vfncvt_xu_f_w_u8m4_tum(vbool2_t mask, vuint8m4_t maskedoff, vfloat16m8_t src, size_t vl) {607 return __riscv_vfncvt_xu_tum(mask, maskedoff, src, vl);608}609 610// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vfncvt_x_f_w_i16mf4_tum611// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {612// CHECK-RV64-NEXT: entry:613// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv1i16.nxv1f32.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x float> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)614// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]615//616vint16mf4_t test_vfncvt_x_f_w_i16mf4_tum(vbool64_t mask, vint16mf4_t maskedoff, vfloat32mf2_t src, size_t vl) {617 return __riscv_vfncvt_x_tum(mask, maskedoff, src, vl);618}619 620// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vfncvt_x_f_w_i16mf2_tum621// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {622// CHECK-RV64-NEXT: entry:623// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv2i16.nxv2f32.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x float> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)624// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]625//626vint16mf2_t test_vfncvt_x_f_w_i16mf2_tum(vbool32_t mask, vint16mf2_t maskedoff, vfloat32m1_t src, size_t vl) {627 return __riscv_vfncvt_x_tum(mask, maskedoff, src, vl);628}629 630// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfncvt_x_f_w_i16m1_tum631// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {632// CHECK-RV64-NEXT: entry:633// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv4i16.nxv4f32.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x float> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)634// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]635//636vint16m1_t test_vfncvt_x_f_w_i16m1_tum(vbool16_t mask, vint16m1_t maskedoff, vfloat32m2_t src, size_t vl) {637 return __riscv_vfncvt_x_tum(mask, maskedoff, src, vl);638}639 640// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfncvt_x_f_w_i16m2_tum641// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {642// CHECK-RV64-NEXT: entry:643// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv8i16.nxv8f32.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x float> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)644// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]645//646vint16m2_t test_vfncvt_x_f_w_i16m2_tum(vbool8_t mask, vint16m2_t maskedoff, vfloat32m4_t src, size_t vl) {647 return __riscv_vfncvt_x_tum(mask, maskedoff, src, vl);648}649 650// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfncvt_x_f_w_i16m4_tum651// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {652// CHECK-RV64-NEXT: entry:653// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv16i16.nxv16f32.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x float> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)654// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]655//656vint16m4_t test_vfncvt_x_f_w_i16m4_tum(vbool4_t mask, vint16m4_t maskedoff, vfloat32m8_t src, size_t vl) {657 return __riscv_vfncvt_x_tum(mask, maskedoff, src, vl);658}659 660// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vfncvt_xu_f_w_u16mf4_tum661// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {662// CHECK-RV64-NEXT: entry:663// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i16.nxv1f32.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x float> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)664// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]665//666vuint16mf4_t test_vfncvt_xu_f_w_u16mf4_tum(vbool64_t mask, vuint16mf4_t maskedoff, vfloat32mf2_t src, size_t vl) {667 return __riscv_vfncvt_xu_tum(mask, maskedoff, src, vl);668}669 670// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vfncvt_xu_f_w_u16mf2_tum671// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {672// CHECK-RV64-NEXT: entry:673// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv2i16.nxv2f32.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x float> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)674// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]675//676vuint16mf2_t test_vfncvt_xu_f_w_u16mf2_tum(vbool32_t mask, vuint16mf2_t maskedoff, vfloat32m1_t src, size_t vl) {677 return __riscv_vfncvt_xu_tum(mask, maskedoff, src, vl);678}679 680// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfncvt_xu_f_w_u16m1_tum681// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {682// CHECK-RV64-NEXT: entry:683// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv4i16.nxv4f32.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x float> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)684// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]685//686vuint16m1_t test_vfncvt_xu_f_w_u16m1_tum(vbool16_t mask, vuint16m1_t maskedoff, vfloat32m2_t src, size_t vl) {687 return __riscv_vfncvt_xu_tum(mask, maskedoff, src, vl);688}689 690// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfncvt_xu_f_w_u16m2_tum691// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {692// CHECK-RV64-NEXT: entry:693// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv8i16.nxv8f32.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x float> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)694// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]695//696vuint16m2_t test_vfncvt_xu_f_w_u16m2_tum(vbool8_t mask, vuint16m2_t maskedoff, vfloat32m4_t src, size_t vl) {697 return __riscv_vfncvt_xu_tum(mask, maskedoff, src, vl);698}699 700// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfncvt_xu_f_w_u16m4_tum701// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {702// CHECK-RV64-NEXT: entry:703// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv16i16.nxv16f32.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x float> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)704// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]705//706vuint16m4_t test_vfncvt_xu_f_w_u16m4_tum(vbool4_t mask, vuint16m4_t maskedoff, vfloat32m8_t src, size_t vl) {707 return __riscv_vfncvt_xu_tum(mask, maskedoff, src, vl);708}709 710// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfncvt_f_x_w_f16mf4_tum711// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {712// CHECK-RV64-NEXT: entry:713// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv1f16.nxv1i32.i64(<vscale x 1 x half> [[MASKEDOFF]], <vscale x 1 x i32> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)714// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]715//716vfloat16mf4_t test_vfncvt_f_x_w_f16mf4_tum(vbool64_t mask, vfloat16mf4_t maskedoff, vint32mf2_t src, size_t vl) {717 return __riscv_vfncvt_f_tum(mask, maskedoff, src, vl);718}719 720// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfncvt_f_x_w_f16mf2_tum721// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {722// CHECK-RV64-NEXT: entry:723// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv2f16.nxv2i32.i64(<vscale x 2 x half> [[MASKEDOFF]], <vscale x 2 x i32> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)724// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]725//726vfloat16mf2_t test_vfncvt_f_x_w_f16mf2_tum(vbool32_t mask, vfloat16mf2_t maskedoff, vint32m1_t src, size_t vl) {727 return __riscv_vfncvt_f_tum(mask, maskedoff, src, vl);728}729 730// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfncvt_f_x_w_f16m1_tum731// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {732// CHECK-RV64-NEXT: entry:733// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv4f16.nxv4i32.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x i32> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)734// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]735//736vfloat16m1_t test_vfncvt_f_x_w_f16m1_tum(vbool16_t mask, vfloat16m1_t maskedoff, vint32m2_t src, size_t vl) {737 return __riscv_vfncvt_f_tum(mask, maskedoff, src, vl);738}739 740// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfncvt_f_x_w_f16m2_tum741// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {742// CHECK-RV64-NEXT: entry:743// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv8f16.nxv8i32.i64(<vscale x 8 x half> [[MASKEDOFF]], <vscale x 8 x i32> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)744// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]745//746vfloat16m2_t test_vfncvt_f_x_w_f16m2_tum(vbool8_t mask, vfloat16m2_t maskedoff, vint32m4_t src, size_t vl) {747 return __riscv_vfncvt_f_tum(mask, maskedoff, src, vl);748}749 750// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfncvt_f_x_w_f16m4_tum751// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {752// CHECK-RV64-NEXT: entry:753// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv16f16.nxv16i32.i64(<vscale x 16 x half> [[MASKEDOFF]], <vscale x 16 x i32> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)754// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]755//756vfloat16m4_t test_vfncvt_f_x_w_f16m4_tum(vbool4_t mask, vfloat16m4_t maskedoff, vint32m8_t src, size_t vl) {757 return __riscv_vfncvt_f_tum(mask, maskedoff, src, vl);758}759 760// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfncvt_f_xu_w_f16mf4_tum761// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {762// CHECK-RV64-NEXT: entry:763// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv1f16.nxv1i32.i64(<vscale x 1 x half> [[MASKEDOFF]], <vscale x 1 x i32> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)764// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]765//766vfloat16mf4_t test_vfncvt_f_xu_w_f16mf4_tum(vbool64_t mask, vfloat16mf4_t maskedoff, vuint32mf2_t src, size_t vl) {767 return __riscv_vfncvt_f_tum(mask, maskedoff, src, vl);768}769 770// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfncvt_f_xu_w_f16mf2_tum771// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {772// CHECK-RV64-NEXT: entry:773// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv2f16.nxv2i32.i64(<vscale x 2 x half> [[MASKEDOFF]], <vscale x 2 x i32> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)774// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]775//776vfloat16mf2_t test_vfncvt_f_xu_w_f16mf2_tum(vbool32_t mask, vfloat16mf2_t maskedoff, vuint32m1_t src, size_t vl) {777 return __riscv_vfncvt_f_tum(mask, maskedoff, src, vl);778}779 780// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfncvt_f_xu_w_f16m1_tum781// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {782// CHECK-RV64-NEXT: entry:783// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv4f16.nxv4i32.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x i32> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)784// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]785//786vfloat16m1_t test_vfncvt_f_xu_w_f16m1_tum(vbool16_t mask, vfloat16m1_t maskedoff, vuint32m2_t src, size_t vl) {787 return __riscv_vfncvt_f_tum(mask, maskedoff, src, vl);788}789 790// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfncvt_f_xu_w_f16m2_tum791// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {792// CHECK-RV64-NEXT: entry:793// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv8f16.nxv8i32.i64(<vscale x 8 x half> [[MASKEDOFF]], <vscale x 8 x i32> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)794// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]795//796vfloat16m2_t test_vfncvt_f_xu_w_f16m2_tum(vbool8_t mask, vfloat16m2_t maskedoff, vuint32m4_t src, size_t vl) {797 return __riscv_vfncvt_f_tum(mask, maskedoff, src, vl);798}799 800// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfncvt_f_xu_w_f16m4_tum801// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {802// CHECK-RV64-NEXT: entry:803// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv16f16.nxv16i32.i64(<vscale x 16 x half> [[MASKEDOFF]], <vscale x 16 x i32> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)804// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]805//806vfloat16m4_t test_vfncvt_f_xu_w_f16m4_tum(vbool4_t mask, vfloat16m4_t maskedoff, vuint32m8_t src, size_t vl) {807 return __riscv_vfncvt_f_tum(mask, maskedoff, src, vl);808}809 810// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfncvt_x_f_w_i32mf2_tum811// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {812// CHECK-RV64-NEXT: entry:813// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfncvt.x.f.w.mask.nxv1i32.nxv1f64.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x double> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)814// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]815//816vint32mf2_t test_vfncvt_x_f_w_i32mf2_tum(vbool64_t mask, vint32mf2_t maskedoff, vfloat64m1_t src, size_t vl) {817 return __riscv_vfncvt_x_tum(mask, maskedoff, src, vl);818}819 820// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfncvt_x_f_w_i32m1_tum821// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {822// CHECK-RV64-NEXT: entry:823// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfncvt.x.f.w.mask.nxv2i32.nxv2f64.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x double> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)824// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]825//826vint32m1_t test_vfncvt_x_f_w_i32m1_tum(vbool32_t mask, vint32m1_t maskedoff, vfloat64m2_t src, size_t vl) {827 return __riscv_vfncvt_x_tum(mask, maskedoff, src, vl);828}829 830// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfncvt_x_f_w_i32m2_tum831// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {832// CHECK-RV64-NEXT: entry:833// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfncvt.x.f.w.mask.nxv4i32.nxv4f64.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x double> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)834// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]835//836vint32m2_t test_vfncvt_x_f_w_i32m2_tum(vbool16_t mask, vint32m2_t maskedoff, vfloat64m4_t src, size_t vl) {837 return __riscv_vfncvt_x_tum(mask, maskedoff, src, vl);838}839 840// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfncvt_x_f_w_i32m4_tum841// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {842// CHECK-RV64-NEXT: entry:843// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfncvt.x.f.w.mask.nxv8i32.nxv8f64.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x double> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)844// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]845//846vint32m4_t test_vfncvt_x_f_w_i32m4_tum(vbool8_t mask, vint32m4_t maskedoff, vfloat64m8_t src, size_t vl) {847 return __riscv_vfncvt_x_tum(mask, maskedoff, src, vl);848}849 850// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfncvt_xu_f_w_u32mf2_tum851// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {852// CHECK-RV64-NEXT: entry:853// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i32.nxv1f64.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x double> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)854// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]855//856vuint32mf2_t test_vfncvt_xu_f_w_u32mf2_tum(vbool64_t mask, vuint32mf2_t maskedoff, vfloat64m1_t src, size_t vl) {857 return __riscv_vfncvt_xu_tum(mask, maskedoff, src, vl);858}859 860// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfncvt_xu_f_w_u32m1_tum861// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {862// CHECK-RV64-NEXT: entry:863// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfncvt.xu.f.w.mask.nxv2i32.nxv2f64.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x double> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)864// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]865//866vuint32m1_t test_vfncvt_xu_f_w_u32m1_tum(vbool32_t mask, vuint32m1_t maskedoff, vfloat64m2_t src, size_t vl) {867 return __riscv_vfncvt_xu_tum(mask, maskedoff, src, vl);868}869 870// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfncvt_xu_f_w_u32m2_tum871// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {872// CHECK-RV64-NEXT: entry:873// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfncvt.xu.f.w.mask.nxv4i32.nxv4f64.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x double> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)874// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]875//876vuint32m2_t test_vfncvt_xu_f_w_u32m2_tum(vbool16_t mask, vuint32m2_t maskedoff, vfloat64m4_t src, size_t vl) {877 return __riscv_vfncvt_xu_tum(mask, maskedoff, src, vl);878}879 880// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfncvt_xu_f_w_u32m4_tum881// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {882// CHECK-RV64-NEXT: entry:883// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfncvt.xu.f.w.mask.nxv8i32.nxv8f64.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x double> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)884// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]885//886vuint32m4_t test_vfncvt_xu_f_w_u32m4_tum(vbool8_t mask, vuint32m4_t maskedoff, vfloat64m8_t src, size_t vl) {887 return __riscv_vfncvt_xu_tum(mask, maskedoff, src, vl);888}889 890// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfncvt_f_x_w_f32mf2_tum891// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {892// CHECK-RV64-NEXT: entry:893// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.x.w.mask.nxv1f32.nxv1i64.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x i64> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)894// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]895//896vfloat32mf2_t test_vfncvt_f_x_w_f32mf2_tum(vbool64_t mask, vfloat32mf2_t maskedoff, vint64m1_t src, size_t vl) {897 return __riscv_vfncvt_f_tum(mask, maskedoff, src, vl);898}899 900// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfncvt_f_x_w_f32m1_tum901// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {902// CHECK-RV64-NEXT: entry:903// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.x.w.mask.nxv2f32.nxv2i64.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x i64> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)904// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]905//906vfloat32m1_t test_vfncvt_f_x_w_f32m1_tum(vbool32_t mask, vfloat32m1_t maskedoff, vint64m2_t src, size_t vl) {907 return __riscv_vfncvt_f_tum(mask, maskedoff, src, vl);908}909 910// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfncvt_f_x_w_f32m2_tum911// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {912// CHECK-RV64-NEXT: entry:913// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.x.w.mask.nxv4f32.nxv4i64.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x i64> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)914// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]915//916vfloat32m2_t test_vfncvt_f_x_w_f32m2_tum(vbool16_t mask, vfloat32m2_t maskedoff, vint64m4_t src, size_t vl) {917 return __riscv_vfncvt_f_tum(mask, maskedoff, src, vl);918}919 920// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfncvt_f_x_w_f32m4_tum921// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {922// CHECK-RV64-NEXT: entry:923// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.x.w.mask.nxv8f32.nxv8i64.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x i64> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)924// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]925//926vfloat32m4_t test_vfncvt_f_x_w_f32m4_tum(vbool8_t mask, vfloat32m4_t maskedoff, vint64m8_t src, size_t vl) {927 return __riscv_vfncvt_f_tum(mask, maskedoff, src, vl);928}929 930// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfncvt_f_xu_w_f32mf2_tum931// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {932// CHECK-RV64-NEXT: entry:933// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.xu.w.mask.nxv1f32.nxv1i64.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x i64> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)934// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]935//936vfloat32mf2_t test_vfncvt_f_xu_w_f32mf2_tum(vbool64_t mask, vfloat32mf2_t maskedoff, vuint64m1_t src, size_t vl) {937 return __riscv_vfncvt_f_tum(mask, maskedoff, src, vl);938}939 940// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfncvt_f_xu_w_f32m1_tum941// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {942// CHECK-RV64-NEXT: entry:943// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.xu.w.mask.nxv2f32.nxv2i64.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x i64> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)944// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]945//946vfloat32m1_t test_vfncvt_f_xu_w_f32m1_tum(vbool32_t mask, vfloat32m1_t maskedoff, vuint64m2_t src, size_t vl) {947 return __riscv_vfncvt_f_tum(mask, maskedoff, src, vl);948}949 950// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfncvt_f_xu_w_f32m2_tum951// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {952// CHECK-RV64-NEXT: entry:953// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.xu.w.mask.nxv4f32.nxv4i64.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x i64> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)954// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]955//956vfloat32m2_t test_vfncvt_f_xu_w_f32m2_tum(vbool16_t mask, vfloat32m2_t maskedoff, vuint64m4_t src, size_t vl) {957 return __riscv_vfncvt_f_tum(mask, maskedoff, src, vl);958}959 960// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfncvt_f_xu_w_f32m4_tum961// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {962// CHECK-RV64-NEXT: entry:963// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.xu.w.mask.nxv8f32.nxv8i64.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x i64> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)964// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]965//966vfloat32m4_t test_vfncvt_f_xu_w_f32m4_tum(vbool8_t mask, vfloat32m4_t maskedoff, vuint64m8_t src, size_t vl) {967 return __riscv_vfncvt_f_tum(mask, maskedoff, src, vl);968}969 970// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_i8mf8_tumu971// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {972// CHECK-RV64-NEXT: entry:973// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> [[MASKEDOFF]], <vscale x 1 x half> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)974// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]975//976vint8mf8_t test_vfncvt_x_f_w_i8mf8_tumu(vbool64_t mask, vint8mf8_t maskedoff, vfloat16mf4_t src, size_t vl) {977 return __riscv_vfncvt_x_tumu(mask, maskedoff, src, vl);978}979 980// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vfncvt_x_f_w_i8mf4_tumu981// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {982// CHECK-RV64-NEXT: entry:983// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> [[MASKEDOFF]], <vscale x 2 x half> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)984// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]985//986vint8mf4_t test_vfncvt_x_f_w_i8mf4_tumu(vbool32_t mask, vint8mf4_t maskedoff, vfloat16mf2_t src, size_t vl) {987 return __riscv_vfncvt_x_tumu(mask, maskedoff, src, vl);988}989 990// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vfncvt_x_f_w_i8mf2_tumu991// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {992// CHECK-RV64-NEXT: entry:993// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> [[MASKEDOFF]], <vscale x 4 x half> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)994// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]995//996vint8mf2_t test_vfncvt_x_f_w_i8mf2_tumu(vbool16_t mask, vint8mf2_t maskedoff, vfloat16m1_t src, size_t vl) {997 return __riscv_vfncvt_x_tumu(mask, maskedoff, src, vl);998}999 1000// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vfncvt_x_f_w_i8m1_tumu1001// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1002// CHECK-RV64-NEXT: entry:1003// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> [[MASKEDOFF]], <vscale x 8 x half> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1004// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]1005//1006vint8m1_t test_vfncvt_x_f_w_i8m1_tumu(vbool8_t mask, vint8m1_t maskedoff, vfloat16m2_t src, size_t vl) {1007 return __riscv_vfncvt_x_tumu(mask, maskedoff, src, vl);1008}1009 1010// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vfncvt_x_f_w_i8m2_tumu1011// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1012// CHECK-RV64-NEXT: entry:1013// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> [[MASKEDOFF]], <vscale x 16 x half> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1014// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]1015//1016vint8m2_t test_vfncvt_x_f_w_i8m2_tumu(vbool4_t mask, vint8m2_t maskedoff, vfloat16m4_t src, size_t vl) {1017 return __riscv_vfncvt_x_tumu(mask, maskedoff, src, vl);1018}1019 1020// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vfncvt_x_f_w_i8m4_tumu1021// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1022// CHECK-RV64-NEXT: entry:1023// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> [[MASKEDOFF]], <vscale x 32 x half> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1024// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]1025//1026vint8m4_t test_vfncvt_x_f_w_i8m4_tumu(vbool2_t mask, vint8m4_t maskedoff, vfloat16m8_t src, size_t vl) {1027 return __riscv_vfncvt_x_tumu(mask, maskedoff, src, vl);1028}1029 1030// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vfncvt_xu_f_w_u8mf8_tumu1031// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1032// CHECK-RV64-NEXT: entry:1033// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> [[MASKEDOFF]], <vscale x 1 x half> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1034// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]1035//1036vuint8mf8_t test_vfncvt_xu_f_w_u8mf8_tumu(vbool64_t mask, vuint8mf8_t maskedoff, vfloat16mf4_t src, size_t vl) {1037 return __riscv_vfncvt_xu_tumu(mask, maskedoff, src, vl);1038}1039 1040// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vfncvt_xu_f_w_u8mf4_tumu1041// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1042// CHECK-RV64-NEXT: entry:1043// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> [[MASKEDOFF]], <vscale x 2 x half> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1044// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]1045//1046vuint8mf4_t test_vfncvt_xu_f_w_u8mf4_tumu(vbool32_t mask, vuint8mf4_t maskedoff, vfloat16mf2_t src, size_t vl) {1047 return __riscv_vfncvt_xu_tumu(mask, maskedoff, src, vl);1048}1049 1050// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vfncvt_xu_f_w_u8mf2_tumu1051// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1052// CHECK-RV64-NEXT: entry:1053// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> [[MASKEDOFF]], <vscale x 4 x half> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1054// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]1055//1056vuint8mf2_t test_vfncvt_xu_f_w_u8mf2_tumu(vbool16_t mask, vuint8mf2_t maskedoff, vfloat16m1_t src, size_t vl) {1057 return __riscv_vfncvt_xu_tumu(mask, maskedoff, src, vl);1058}1059 1060// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vfncvt_xu_f_w_u8m1_tumu1061// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1062// CHECK-RV64-NEXT: entry:1063// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> [[MASKEDOFF]], <vscale x 8 x half> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1064// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]1065//1066vuint8m1_t test_vfncvt_xu_f_w_u8m1_tumu(vbool8_t mask, vuint8m1_t maskedoff, vfloat16m2_t src, size_t vl) {1067 return __riscv_vfncvt_xu_tumu(mask, maskedoff, src, vl);1068}1069 1070// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vfncvt_xu_f_w_u8m2_tumu1071// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1072// CHECK-RV64-NEXT: entry:1073// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> [[MASKEDOFF]], <vscale x 16 x half> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1074// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]1075//1076vuint8m2_t test_vfncvt_xu_f_w_u8m2_tumu(vbool4_t mask, vuint8m2_t maskedoff, vfloat16m4_t src, size_t vl) {1077 return __riscv_vfncvt_xu_tumu(mask, maskedoff, src, vl);1078}1079 1080// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vfncvt_xu_f_w_u8m4_tumu1081// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1082// CHECK-RV64-NEXT: entry:1083// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> [[MASKEDOFF]], <vscale x 32 x half> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1084// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]1085//1086vuint8m4_t test_vfncvt_xu_f_w_u8m4_tumu(vbool2_t mask, vuint8m4_t maskedoff, vfloat16m8_t src, size_t vl) {1087 return __riscv_vfncvt_xu_tumu(mask, maskedoff, src, vl);1088}1089 1090// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vfncvt_x_f_w_i16mf4_tumu1091// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1092// CHECK-RV64-NEXT: entry:1093// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv1i16.nxv1f32.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x float> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1094// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]1095//1096vint16mf4_t test_vfncvt_x_f_w_i16mf4_tumu(vbool64_t mask, vint16mf4_t maskedoff, vfloat32mf2_t src, size_t vl) {1097 return __riscv_vfncvt_x_tumu(mask, maskedoff, src, vl);1098}1099 1100// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vfncvt_x_f_w_i16mf2_tumu1101// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1102// CHECK-RV64-NEXT: entry:1103// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv2i16.nxv2f32.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x float> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1104// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]1105//1106vint16mf2_t test_vfncvt_x_f_w_i16mf2_tumu(vbool32_t mask, vint16mf2_t maskedoff, vfloat32m1_t src, size_t vl) {1107 return __riscv_vfncvt_x_tumu(mask, maskedoff, src, vl);1108}1109 1110// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfncvt_x_f_w_i16m1_tumu1111// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1112// CHECK-RV64-NEXT: entry:1113// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv4i16.nxv4f32.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x float> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1114// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]1115//1116vint16m1_t test_vfncvt_x_f_w_i16m1_tumu(vbool16_t mask, vint16m1_t maskedoff, vfloat32m2_t src, size_t vl) {1117 return __riscv_vfncvt_x_tumu(mask, maskedoff, src, vl);1118}1119 1120// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfncvt_x_f_w_i16m2_tumu1121// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1122// CHECK-RV64-NEXT: entry:1123// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv8i16.nxv8f32.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x float> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1124// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]1125//1126vint16m2_t test_vfncvt_x_f_w_i16m2_tumu(vbool8_t mask, vint16m2_t maskedoff, vfloat32m4_t src, size_t vl) {1127 return __riscv_vfncvt_x_tumu(mask, maskedoff, src, vl);1128}1129 1130// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfncvt_x_f_w_i16m4_tumu1131// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1132// CHECK-RV64-NEXT: entry:1133// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv16i16.nxv16f32.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x float> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1134// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]1135//1136vint16m4_t test_vfncvt_x_f_w_i16m4_tumu(vbool4_t mask, vint16m4_t maskedoff, vfloat32m8_t src, size_t vl) {1137 return __riscv_vfncvt_x_tumu(mask, maskedoff, src, vl);1138}1139 1140// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vfncvt_xu_f_w_u16mf4_tumu1141// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1142// CHECK-RV64-NEXT: entry:1143// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i16.nxv1f32.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x float> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1144// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]1145//1146vuint16mf4_t test_vfncvt_xu_f_w_u16mf4_tumu(vbool64_t mask, vuint16mf4_t maskedoff, vfloat32mf2_t src, size_t vl) {1147 return __riscv_vfncvt_xu_tumu(mask, maskedoff, src, vl);1148}1149 1150// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vfncvt_xu_f_w_u16mf2_tumu1151// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1152// CHECK-RV64-NEXT: entry:1153// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv2i16.nxv2f32.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x float> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1154// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]1155//1156vuint16mf2_t test_vfncvt_xu_f_w_u16mf2_tumu(vbool32_t mask, vuint16mf2_t maskedoff, vfloat32m1_t src, size_t vl) {1157 return __riscv_vfncvt_xu_tumu(mask, maskedoff, src, vl);1158}1159 1160// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfncvt_xu_f_w_u16m1_tumu1161// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1162// CHECK-RV64-NEXT: entry:1163// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv4i16.nxv4f32.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x float> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1164// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]1165//1166vuint16m1_t test_vfncvt_xu_f_w_u16m1_tumu(vbool16_t mask, vuint16m1_t maskedoff, vfloat32m2_t src, size_t vl) {1167 return __riscv_vfncvt_xu_tumu(mask, maskedoff, src, vl);1168}1169 1170// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfncvt_xu_f_w_u16m2_tumu1171// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1172// CHECK-RV64-NEXT: entry:1173// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv8i16.nxv8f32.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x float> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1174// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]1175//1176vuint16m2_t test_vfncvt_xu_f_w_u16m2_tumu(vbool8_t mask, vuint16m2_t maskedoff, vfloat32m4_t src, size_t vl) {1177 return __riscv_vfncvt_xu_tumu(mask, maskedoff, src, vl);1178}1179 1180// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfncvt_xu_f_w_u16m4_tumu1181// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1182// CHECK-RV64-NEXT: entry:1183// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv16i16.nxv16f32.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x float> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1184// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]1185//1186vuint16m4_t test_vfncvt_xu_f_w_u16m4_tumu(vbool4_t mask, vuint16m4_t maskedoff, vfloat32m8_t src, size_t vl) {1187 return __riscv_vfncvt_xu_tumu(mask, maskedoff, src, vl);1188}1189 1190// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfncvt_f_x_w_f16mf4_tumu1191// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1192// CHECK-RV64-NEXT: entry:1193// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv1f16.nxv1i32.i64(<vscale x 1 x half> [[MASKEDOFF]], <vscale x 1 x i32> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1194// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]1195//1196vfloat16mf4_t test_vfncvt_f_x_w_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t maskedoff, vint32mf2_t src, size_t vl) {1197 return __riscv_vfncvt_f_tumu(mask, maskedoff, src, vl);1198}1199 1200// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfncvt_f_x_w_f16mf2_tumu1201// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1202// CHECK-RV64-NEXT: entry:1203// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv2f16.nxv2i32.i64(<vscale x 2 x half> [[MASKEDOFF]], <vscale x 2 x i32> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1204// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]1205//1206vfloat16mf2_t test_vfncvt_f_x_w_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t maskedoff, vint32m1_t src, size_t vl) {1207 return __riscv_vfncvt_f_tumu(mask, maskedoff, src, vl);1208}1209 1210// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfncvt_f_x_w_f16m1_tumu1211// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1212// CHECK-RV64-NEXT: entry:1213// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv4f16.nxv4i32.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x i32> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1214// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]1215//1216vfloat16m1_t test_vfncvt_f_x_w_f16m1_tumu(vbool16_t mask, vfloat16m1_t maskedoff, vint32m2_t src, size_t vl) {1217 return __riscv_vfncvt_f_tumu(mask, maskedoff, src, vl);1218}1219 1220// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfncvt_f_x_w_f16m2_tumu1221// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1222// CHECK-RV64-NEXT: entry:1223// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv8f16.nxv8i32.i64(<vscale x 8 x half> [[MASKEDOFF]], <vscale x 8 x i32> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1224// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]1225//1226vfloat16m2_t test_vfncvt_f_x_w_f16m2_tumu(vbool8_t mask, vfloat16m2_t maskedoff, vint32m4_t src, size_t vl) {1227 return __riscv_vfncvt_f_tumu(mask, maskedoff, src, vl);1228}1229 1230// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfncvt_f_x_w_f16m4_tumu1231// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1232// CHECK-RV64-NEXT: entry:1233// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv16f16.nxv16i32.i64(<vscale x 16 x half> [[MASKEDOFF]], <vscale x 16 x i32> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1234// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]1235//1236vfloat16m4_t test_vfncvt_f_x_w_f16m4_tumu(vbool4_t mask, vfloat16m4_t maskedoff, vint32m8_t src, size_t vl) {1237 return __riscv_vfncvt_f_tumu(mask, maskedoff, src, vl);1238}1239 1240// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfncvt_f_xu_w_f16mf4_tumu1241// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1242// CHECK-RV64-NEXT: entry:1243// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv1f16.nxv1i32.i64(<vscale x 1 x half> [[MASKEDOFF]], <vscale x 1 x i32> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1244// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]1245//1246vfloat16mf4_t test_vfncvt_f_xu_w_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t maskedoff, vuint32mf2_t src, size_t vl) {1247 return __riscv_vfncvt_f_tumu(mask, maskedoff, src, vl);1248}1249 1250// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfncvt_f_xu_w_f16mf2_tumu1251// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1252// CHECK-RV64-NEXT: entry:1253// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv2f16.nxv2i32.i64(<vscale x 2 x half> [[MASKEDOFF]], <vscale x 2 x i32> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1254// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]1255//1256vfloat16mf2_t test_vfncvt_f_xu_w_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t maskedoff, vuint32m1_t src, size_t vl) {1257 return __riscv_vfncvt_f_tumu(mask, maskedoff, src, vl);1258}1259 1260// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfncvt_f_xu_w_f16m1_tumu1261// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1262// CHECK-RV64-NEXT: entry:1263// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv4f16.nxv4i32.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x i32> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1264// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]1265//1266vfloat16m1_t test_vfncvt_f_xu_w_f16m1_tumu(vbool16_t mask, vfloat16m1_t maskedoff, vuint32m2_t src, size_t vl) {1267 return __riscv_vfncvt_f_tumu(mask, maskedoff, src, vl);1268}1269 1270// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfncvt_f_xu_w_f16m2_tumu1271// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1272// CHECK-RV64-NEXT: entry:1273// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv8f16.nxv8i32.i64(<vscale x 8 x half> [[MASKEDOFF]], <vscale x 8 x i32> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1274// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]1275//1276vfloat16m2_t test_vfncvt_f_xu_w_f16m2_tumu(vbool8_t mask, vfloat16m2_t maskedoff, vuint32m4_t src, size_t vl) {1277 return __riscv_vfncvt_f_tumu(mask, maskedoff, src, vl);1278}1279 1280// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfncvt_f_xu_w_f16m4_tumu1281// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1282// CHECK-RV64-NEXT: entry:1283// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv16f16.nxv16i32.i64(<vscale x 16 x half> [[MASKEDOFF]], <vscale x 16 x i32> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1284// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]1285//1286vfloat16m4_t test_vfncvt_f_xu_w_f16m4_tumu(vbool4_t mask, vfloat16m4_t maskedoff, vuint32m8_t src, size_t vl) {1287 return __riscv_vfncvt_f_tumu(mask, maskedoff, src, vl);1288}1289 1290// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfncvt_x_f_w_i32mf2_tumu1291// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1292// CHECK-RV64-NEXT: entry:1293// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfncvt.x.f.w.mask.nxv1i32.nxv1f64.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x double> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1294// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]1295//1296vint32mf2_t test_vfncvt_x_f_w_i32mf2_tumu(vbool64_t mask, vint32mf2_t maskedoff, vfloat64m1_t src, size_t vl) {1297 return __riscv_vfncvt_x_tumu(mask, maskedoff, src, vl);1298}1299 1300// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfncvt_x_f_w_i32m1_tumu1301// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1302// CHECK-RV64-NEXT: entry:1303// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfncvt.x.f.w.mask.nxv2i32.nxv2f64.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x double> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1304// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]1305//1306vint32m1_t test_vfncvt_x_f_w_i32m1_tumu(vbool32_t mask, vint32m1_t maskedoff, vfloat64m2_t src, size_t vl) {1307 return __riscv_vfncvt_x_tumu(mask, maskedoff, src, vl);1308}1309 1310// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfncvt_x_f_w_i32m2_tumu1311// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1312// CHECK-RV64-NEXT: entry:1313// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfncvt.x.f.w.mask.nxv4i32.nxv4f64.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x double> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1314// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]1315//1316vint32m2_t test_vfncvt_x_f_w_i32m2_tumu(vbool16_t mask, vint32m2_t maskedoff, vfloat64m4_t src, size_t vl) {1317 return __riscv_vfncvt_x_tumu(mask, maskedoff, src, vl);1318}1319 1320// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfncvt_x_f_w_i32m4_tumu1321// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1322// CHECK-RV64-NEXT: entry:1323// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfncvt.x.f.w.mask.nxv8i32.nxv8f64.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x double> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1324// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]1325//1326vint32m4_t test_vfncvt_x_f_w_i32m4_tumu(vbool8_t mask, vint32m4_t maskedoff, vfloat64m8_t src, size_t vl) {1327 return __riscv_vfncvt_x_tumu(mask, maskedoff, src, vl);1328}1329 1330// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfncvt_xu_f_w_u32mf2_tumu1331// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1332// CHECK-RV64-NEXT: entry:1333// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i32.nxv1f64.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x double> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1334// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]1335//1336vuint32mf2_t test_vfncvt_xu_f_w_u32mf2_tumu(vbool64_t mask, vuint32mf2_t maskedoff, vfloat64m1_t src, size_t vl) {1337 return __riscv_vfncvt_xu_tumu(mask, maskedoff, src, vl);1338}1339 1340// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfncvt_xu_f_w_u32m1_tumu1341// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1342// CHECK-RV64-NEXT: entry:1343// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfncvt.xu.f.w.mask.nxv2i32.nxv2f64.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x double> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1344// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]1345//1346vuint32m1_t test_vfncvt_xu_f_w_u32m1_tumu(vbool32_t mask, vuint32m1_t maskedoff, vfloat64m2_t src, size_t vl) {1347 return __riscv_vfncvt_xu_tumu(mask, maskedoff, src, vl);1348}1349 1350// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfncvt_xu_f_w_u32m2_tumu1351// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1352// CHECK-RV64-NEXT: entry:1353// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfncvt.xu.f.w.mask.nxv4i32.nxv4f64.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x double> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1354// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]1355//1356vuint32m2_t test_vfncvt_xu_f_w_u32m2_tumu(vbool16_t mask, vuint32m2_t maskedoff, vfloat64m4_t src, size_t vl) {1357 return __riscv_vfncvt_xu_tumu(mask, maskedoff, src, vl);1358}1359 1360// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfncvt_xu_f_w_u32m4_tumu1361// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1362// CHECK-RV64-NEXT: entry:1363// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfncvt.xu.f.w.mask.nxv8i32.nxv8f64.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x double> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1364// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]1365//1366vuint32m4_t test_vfncvt_xu_f_w_u32m4_tumu(vbool8_t mask, vuint32m4_t maskedoff, vfloat64m8_t src, size_t vl) {1367 return __riscv_vfncvt_xu_tumu(mask, maskedoff, src, vl);1368}1369 1370// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfncvt_f_x_w_f32mf2_tumu1371// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1372// CHECK-RV64-NEXT: entry:1373// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.x.w.mask.nxv1f32.nxv1i64.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x i64> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1374// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]1375//1376vfloat32mf2_t test_vfncvt_f_x_w_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t maskedoff, vint64m1_t src, size_t vl) {1377 return __riscv_vfncvt_f_tumu(mask, maskedoff, src, vl);1378}1379 1380// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfncvt_f_x_w_f32m1_tumu1381// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1382// CHECK-RV64-NEXT: entry:1383// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.x.w.mask.nxv2f32.nxv2i64.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x i64> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1384// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]1385//1386vfloat32m1_t test_vfncvt_f_x_w_f32m1_tumu(vbool32_t mask, vfloat32m1_t maskedoff, vint64m2_t src, size_t vl) {1387 return __riscv_vfncvt_f_tumu(mask, maskedoff, src, vl);1388}1389 1390// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfncvt_f_x_w_f32m2_tumu1391// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1392// CHECK-RV64-NEXT: entry:1393// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.x.w.mask.nxv4f32.nxv4i64.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x i64> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1394// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]1395//1396vfloat32m2_t test_vfncvt_f_x_w_f32m2_tumu(vbool16_t mask, vfloat32m2_t maskedoff, vint64m4_t src, size_t vl) {1397 return __riscv_vfncvt_f_tumu(mask, maskedoff, src, vl);1398}1399 1400// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfncvt_f_x_w_f32m4_tumu1401// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1402// CHECK-RV64-NEXT: entry:1403// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.x.w.mask.nxv8f32.nxv8i64.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x i64> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1404// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]1405//1406vfloat32m4_t test_vfncvt_f_x_w_f32m4_tumu(vbool8_t mask, vfloat32m4_t maskedoff, vint64m8_t src, size_t vl) {1407 return __riscv_vfncvt_f_tumu(mask, maskedoff, src, vl);1408}1409 1410// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfncvt_f_xu_w_f32mf2_tumu1411// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1412// CHECK-RV64-NEXT: entry:1413// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.xu.w.mask.nxv1f32.nxv1i64.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x i64> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1414// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]1415//1416vfloat32mf2_t test_vfncvt_f_xu_w_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t maskedoff, vuint64m1_t src, size_t vl) {1417 return __riscv_vfncvt_f_tumu(mask, maskedoff, src, vl);1418}1419 1420// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfncvt_f_xu_w_f32m1_tumu1421// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1422// CHECK-RV64-NEXT: entry:1423// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.xu.w.mask.nxv2f32.nxv2i64.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x i64> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1424// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]1425//1426vfloat32m1_t test_vfncvt_f_xu_w_f32m1_tumu(vbool32_t mask, vfloat32m1_t maskedoff, vuint64m2_t src, size_t vl) {1427 return __riscv_vfncvt_f_tumu(mask, maskedoff, src, vl);1428}1429 1430// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfncvt_f_xu_w_f32m2_tumu1431// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1432// CHECK-RV64-NEXT: entry:1433// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.xu.w.mask.nxv4f32.nxv4i64.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x i64> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1434// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]1435//1436vfloat32m2_t test_vfncvt_f_xu_w_f32m2_tumu(vbool16_t mask, vfloat32m2_t maskedoff, vuint64m4_t src, size_t vl) {1437 return __riscv_vfncvt_f_tumu(mask, maskedoff, src, vl);1438}1439 1440// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfncvt_f_xu_w_f32m4_tumu1441// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1442// CHECK-RV64-NEXT: entry:1443// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.xu.w.mask.nxv8f32.nxv8i64.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x i64> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1444// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]1445//1446vfloat32m4_t test_vfncvt_f_xu_w_f32m4_tumu(vbool8_t mask, vfloat32m4_t maskedoff, vuint64m8_t src, size_t vl) {1447 return __riscv_vfncvt_f_tumu(mask, maskedoff, src, vl);1448}1449 1450// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_i8mf8_mu1451// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1452// CHECK-RV64-NEXT: entry:1453// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> [[MASKEDOFF]], <vscale x 1 x half> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1454// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]1455//1456vint8mf8_t test_vfncvt_x_f_w_i8mf8_mu(vbool64_t mask, vint8mf8_t maskedoff, vfloat16mf4_t src, size_t vl) {1457 return __riscv_vfncvt_x_mu(mask, maskedoff, src, vl);1458}1459 1460// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vfncvt_x_f_w_i8mf4_mu1461// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1462// CHECK-RV64-NEXT: entry:1463// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> [[MASKEDOFF]], <vscale x 2 x half> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1464// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]1465//1466vint8mf4_t test_vfncvt_x_f_w_i8mf4_mu(vbool32_t mask, vint8mf4_t maskedoff, vfloat16mf2_t src, size_t vl) {1467 return __riscv_vfncvt_x_mu(mask, maskedoff, src, vl);1468}1469 1470// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vfncvt_x_f_w_i8mf2_mu1471// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1472// CHECK-RV64-NEXT: entry:1473// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> [[MASKEDOFF]], <vscale x 4 x half> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1474// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]1475//1476vint8mf2_t test_vfncvt_x_f_w_i8mf2_mu(vbool16_t mask, vint8mf2_t maskedoff, vfloat16m1_t src, size_t vl) {1477 return __riscv_vfncvt_x_mu(mask, maskedoff, src, vl);1478}1479 1480// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vfncvt_x_f_w_i8m1_mu1481// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1482// CHECK-RV64-NEXT: entry:1483// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> [[MASKEDOFF]], <vscale x 8 x half> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1484// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]1485//1486vint8m1_t test_vfncvt_x_f_w_i8m1_mu(vbool8_t mask, vint8m1_t maskedoff, vfloat16m2_t src, size_t vl) {1487 return __riscv_vfncvt_x_mu(mask, maskedoff, src, vl);1488}1489 1490// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vfncvt_x_f_w_i8m2_mu1491// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1492// CHECK-RV64-NEXT: entry:1493// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> [[MASKEDOFF]], <vscale x 16 x half> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1494// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]1495//1496vint8m2_t test_vfncvt_x_f_w_i8m2_mu(vbool4_t mask, vint8m2_t maskedoff, vfloat16m4_t src, size_t vl) {1497 return __riscv_vfncvt_x_mu(mask, maskedoff, src, vl);1498}1499 1500// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vfncvt_x_f_w_i8m4_mu1501// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1502// CHECK-RV64-NEXT: entry:1503// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> [[MASKEDOFF]], <vscale x 32 x half> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1504// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]1505//1506vint8m4_t test_vfncvt_x_f_w_i8m4_mu(vbool2_t mask, vint8m4_t maskedoff, vfloat16m8_t src, size_t vl) {1507 return __riscv_vfncvt_x_mu(mask, maskedoff, src, vl);1508}1509 1510// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vfncvt_xu_f_w_u8mf8_mu1511// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1512// CHECK-RV64-NEXT: entry:1513// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> [[MASKEDOFF]], <vscale x 1 x half> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1514// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]1515//1516vuint8mf8_t test_vfncvt_xu_f_w_u8mf8_mu(vbool64_t mask, vuint8mf8_t maskedoff, vfloat16mf4_t src, size_t vl) {1517 return __riscv_vfncvt_xu_mu(mask, maskedoff, src, vl);1518}1519 1520// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vfncvt_xu_f_w_u8mf4_mu1521// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1522// CHECK-RV64-NEXT: entry:1523// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> [[MASKEDOFF]], <vscale x 2 x half> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1524// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]1525//1526vuint8mf4_t test_vfncvt_xu_f_w_u8mf4_mu(vbool32_t mask, vuint8mf4_t maskedoff, vfloat16mf2_t src, size_t vl) {1527 return __riscv_vfncvt_xu_mu(mask, maskedoff, src, vl);1528}1529 1530// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vfncvt_xu_f_w_u8mf2_mu1531// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1532// CHECK-RV64-NEXT: entry:1533// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> [[MASKEDOFF]], <vscale x 4 x half> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1534// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]1535//1536vuint8mf2_t test_vfncvt_xu_f_w_u8mf2_mu(vbool16_t mask, vuint8mf2_t maskedoff, vfloat16m1_t src, size_t vl) {1537 return __riscv_vfncvt_xu_mu(mask, maskedoff, src, vl);1538}1539 1540// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vfncvt_xu_f_w_u8m1_mu1541// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1542// CHECK-RV64-NEXT: entry:1543// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> [[MASKEDOFF]], <vscale x 8 x half> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1544// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]1545//1546vuint8m1_t test_vfncvt_xu_f_w_u8m1_mu(vbool8_t mask, vuint8m1_t maskedoff, vfloat16m2_t src, size_t vl) {1547 return __riscv_vfncvt_xu_mu(mask, maskedoff, src, vl);1548}1549 1550// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vfncvt_xu_f_w_u8m2_mu1551// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1552// CHECK-RV64-NEXT: entry:1553// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> [[MASKEDOFF]], <vscale x 16 x half> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1554// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]1555//1556vuint8m2_t test_vfncvt_xu_f_w_u8m2_mu(vbool4_t mask, vuint8m2_t maskedoff, vfloat16m4_t src, size_t vl) {1557 return __riscv_vfncvt_xu_mu(mask, maskedoff, src, vl);1558}1559 1560// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vfncvt_xu_f_w_u8m4_mu1561// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1562// CHECK-RV64-NEXT: entry:1563// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> [[MASKEDOFF]], <vscale x 32 x half> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1564// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]1565//1566vuint8m4_t test_vfncvt_xu_f_w_u8m4_mu(vbool2_t mask, vuint8m4_t maskedoff, vfloat16m8_t src, size_t vl) {1567 return __riscv_vfncvt_xu_mu(mask, maskedoff, src, vl);1568}1569 1570// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vfncvt_x_f_w_i16mf4_mu1571// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1572// CHECK-RV64-NEXT: entry:1573// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv1i16.nxv1f32.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x float> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1574// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]1575//1576vint16mf4_t test_vfncvt_x_f_w_i16mf4_mu(vbool64_t mask, vint16mf4_t maskedoff, vfloat32mf2_t src, size_t vl) {1577 return __riscv_vfncvt_x_mu(mask, maskedoff, src, vl);1578}1579 1580// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vfncvt_x_f_w_i16mf2_mu1581// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1582// CHECK-RV64-NEXT: entry:1583// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv2i16.nxv2f32.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x float> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1584// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]1585//1586vint16mf2_t test_vfncvt_x_f_w_i16mf2_mu(vbool32_t mask, vint16mf2_t maskedoff, vfloat32m1_t src, size_t vl) {1587 return __riscv_vfncvt_x_mu(mask, maskedoff, src, vl);1588}1589 1590// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfncvt_x_f_w_i16m1_mu1591// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1592// CHECK-RV64-NEXT: entry:1593// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv4i16.nxv4f32.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x float> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1594// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]1595//1596vint16m1_t test_vfncvt_x_f_w_i16m1_mu(vbool16_t mask, vint16m1_t maskedoff, vfloat32m2_t src, size_t vl) {1597 return __riscv_vfncvt_x_mu(mask, maskedoff, src, vl);1598}1599 1600// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfncvt_x_f_w_i16m2_mu1601// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1602// CHECK-RV64-NEXT: entry:1603// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv8i16.nxv8f32.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x float> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1604// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]1605//1606vint16m2_t test_vfncvt_x_f_w_i16m2_mu(vbool8_t mask, vint16m2_t maskedoff, vfloat32m4_t src, size_t vl) {1607 return __riscv_vfncvt_x_mu(mask, maskedoff, src, vl);1608}1609 1610// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfncvt_x_f_w_i16m4_mu1611// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1612// CHECK-RV64-NEXT: entry:1613// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv16i16.nxv16f32.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x float> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1614// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]1615//1616vint16m4_t test_vfncvt_x_f_w_i16m4_mu(vbool4_t mask, vint16m4_t maskedoff, vfloat32m8_t src, size_t vl) {1617 return __riscv_vfncvt_x_mu(mask, maskedoff, src, vl);1618}1619 1620// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vfncvt_xu_f_w_u16mf4_mu1621// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1622// CHECK-RV64-NEXT: entry:1623// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i16.nxv1f32.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x float> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1624// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]1625//1626vuint16mf4_t test_vfncvt_xu_f_w_u16mf4_mu(vbool64_t mask, vuint16mf4_t maskedoff, vfloat32mf2_t src, size_t vl) {1627 return __riscv_vfncvt_xu_mu(mask, maskedoff, src, vl);1628}1629 1630// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vfncvt_xu_f_w_u16mf2_mu1631// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1632// CHECK-RV64-NEXT: entry:1633// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv2i16.nxv2f32.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x float> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1634// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]1635//1636vuint16mf2_t test_vfncvt_xu_f_w_u16mf2_mu(vbool32_t mask, vuint16mf2_t maskedoff, vfloat32m1_t src, size_t vl) {1637 return __riscv_vfncvt_xu_mu(mask, maskedoff, src, vl);1638}1639 1640// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfncvt_xu_f_w_u16m1_mu1641// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1642// CHECK-RV64-NEXT: entry:1643// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv4i16.nxv4f32.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x float> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1644// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]1645//1646vuint16m1_t test_vfncvt_xu_f_w_u16m1_mu(vbool16_t mask, vuint16m1_t maskedoff, vfloat32m2_t src, size_t vl) {1647 return __riscv_vfncvt_xu_mu(mask, maskedoff, src, vl);1648}1649 1650// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfncvt_xu_f_w_u16m2_mu1651// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1652// CHECK-RV64-NEXT: entry:1653// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv8i16.nxv8f32.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x float> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1654// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]1655//1656vuint16m2_t test_vfncvt_xu_f_w_u16m2_mu(vbool8_t mask, vuint16m2_t maskedoff, vfloat32m4_t src, size_t vl) {1657 return __riscv_vfncvt_xu_mu(mask, maskedoff, src, vl);1658}1659 1660// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfncvt_xu_f_w_u16m4_mu1661// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1662// CHECK-RV64-NEXT: entry:1663// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv16i16.nxv16f32.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x float> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1664// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]1665//1666vuint16m4_t test_vfncvt_xu_f_w_u16m4_mu(vbool4_t mask, vuint16m4_t maskedoff, vfloat32m8_t src, size_t vl) {1667 return __riscv_vfncvt_xu_mu(mask, maskedoff, src, vl);1668}1669 1670// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfncvt_f_x_w_f16mf4_mu1671// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1672// CHECK-RV64-NEXT: entry:1673// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv1f16.nxv1i32.i64(<vscale x 1 x half> [[MASKEDOFF]], <vscale x 1 x i32> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1674// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]1675//1676vfloat16mf4_t test_vfncvt_f_x_w_f16mf4_mu(vbool64_t mask, vfloat16mf4_t maskedoff, vint32mf2_t src, size_t vl) {1677 return __riscv_vfncvt_f_mu(mask, maskedoff, src, vl);1678}1679 1680// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfncvt_f_x_w_f16mf2_mu1681// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1682// CHECK-RV64-NEXT: entry:1683// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv2f16.nxv2i32.i64(<vscale x 2 x half> [[MASKEDOFF]], <vscale x 2 x i32> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1684// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]1685//1686vfloat16mf2_t test_vfncvt_f_x_w_f16mf2_mu(vbool32_t mask, vfloat16mf2_t maskedoff, vint32m1_t src, size_t vl) {1687 return __riscv_vfncvt_f_mu(mask, maskedoff, src, vl);1688}1689 1690// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfncvt_f_x_w_f16m1_mu1691// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1692// CHECK-RV64-NEXT: entry:1693// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv4f16.nxv4i32.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x i32> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1694// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]1695//1696vfloat16m1_t test_vfncvt_f_x_w_f16m1_mu(vbool16_t mask, vfloat16m1_t maskedoff, vint32m2_t src, size_t vl) {1697 return __riscv_vfncvt_f_mu(mask, maskedoff, src, vl);1698}1699 1700// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfncvt_f_x_w_f16m2_mu1701// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1702// CHECK-RV64-NEXT: entry:1703// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv8f16.nxv8i32.i64(<vscale x 8 x half> [[MASKEDOFF]], <vscale x 8 x i32> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1704// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]1705//1706vfloat16m2_t test_vfncvt_f_x_w_f16m2_mu(vbool8_t mask, vfloat16m2_t maskedoff, vint32m4_t src, size_t vl) {1707 return __riscv_vfncvt_f_mu(mask, maskedoff, src, vl);1708}1709 1710// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfncvt_f_x_w_f16m4_mu1711// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1712// CHECK-RV64-NEXT: entry:1713// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv16f16.nxv16i32.i64(<vscale x 16 x half> [[MASKEDOFF]], <vscale x 16 x i32> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1714// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]1715//1716vfloat16m4_t test_vfncvt_f_x_w_f16m4_mu(vbool4_t mask, vfloat16m4_t maskedoff, vint32m8_t src, size_t vl) {1717 return __riscv_vfncvt_f_mu(mask, maskedoff, src, vl);1718}1719 1720// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfncvt_f_xu_w_f16mf4_mu1721// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1722// CHECK-RV64-NEXT: entry:1723// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv1f16.nxv1i32.i64(<vscale x 1 x half> [[MASKEDOFF]], <vscale x 1 x i32> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1724// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]1725//1726vfloat16mf4_t test_vfncvt_f_xu_w_f16mf4_mu(vbool64_t mask, vfloat16mf4_t maskedoff, vuint32mf2_t src, size_t vl) {1727 return __riscv_vfncvt_f_mu(mask, maskedoff, src, vl);1728}1729 1730// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfncvt_f_xu_w_f16mf2_mu1731// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1732// CHECK-RV64-NEXT: entry:1733// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv2f16.nxv2i32.i64(<vscale x 2 x half> [[MASKEDOFF]], <vscale x 2 x i32> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1734// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]1735//1736vfloat16mf2_t test_vfncvt_f_xu_w_f16mf2_mu(vbool32_t mask, vfloat16mf2_t maskedoff, vuint32m1_t src, size_t vl) {1737 return __riscv_vfncvt_f_mu(mask, maskedoff, src, vl);1738}1739 1740// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfncvt_f_xu_w_f16m1_mu1741// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1742// CHECK-RV64-NEXT: entry:1743// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv4f16.nxv4i32.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x i32> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1744// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]1745//1746vfloat16m1_t test_vfncvt_f_xu_w_f16m1_mu(vbool16_t mask, vfloat16m1_t maskedoff, vuint32m2_t src, size_t vl) {1747 return __riscv_vfncvt_f_mu(mask, maskedoff, src, vl);1748}1749 1750// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfncvt_f_xu_w_f16m2_mu1751// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1752// CHECK-RV64-NEXT: entry:1753// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv8f16.nxv8i32.i64(<vscale x 8 x half> [[MASKEDOFF]], <vscale x 8 x i32> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1754// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]1755//1756vfloat16m2_t test_vfncvt_f_xu_w_f16m2_mu(vbool8_t mask, vfloat16m2_t maskedoff, vuint32m4_t src, size_t vl) {1757 return __riscv_vfncvt_f_mu(mask, maskedoff, src, vl);1758}1759 1760// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfncvt_f_xu_w_f16m4_mu1761// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1762// CHECK-RV64-NEXT: entry:1763// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv16f16.nxv16i32.i64(<vscale x 16 x half> [[MASKEDOFF]], <vscale x 16 x i32> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1764// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]1765//1766vfloat16m4_t test_vfncvt_f_xu_w_f16m4_mu(vbool4_t mask, vfloat16m4_t maskedoff, vuint32m8_t src, size_t vl) {1767 return __riscv_vfncvt_f_mu(mask, maskedoff, src, vl);1768}1769 1770// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfncvt_x_f_w_i32mf2_mu1771// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1772// CHECK-RV64-NEXT: entry:1773// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfncvt.x.f.w.mask.nxv1i32.nxv1f64.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x double> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1774// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]1775//1776vint32mf2_t test_vfncvt_x_f_w_i32mf2_mu(vbool64_t mask, vint32mf2_t maskedoff, vfloat64m1_t src, size_t vl) {1777 return __riscv_vfncvt_x_mu(mask, maskedoff, src, vl);1778}1779 1780// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfncvt_x_f_w_i32m1_mu1781// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1782// CHECK-RV64-NEXT: entry:1783// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfncvt.x.f.w.mask.nxv2i32.nxv2f64.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x double> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1784// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]1785//1786vint32m1_t test_vfncvt_x_f_w_i32m1_mu(vbool32_t mask, vint32m1_t maskedoff, vfloat64m2_t src, size_t vl) {1787 return __riscv_vfncvt_x_mu(mask, maskedoff, src, vl);1788}1789 1790// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfncvt_x_f_w_i32m2_mu1791// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1792// CHECK-RV64-NEXT: entry:1793// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfncvt.x.f.w.mask.nxv4i32.nxv4f64.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x double> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1794// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]1795//1796vint32m2_t test_vfncvt_x_f_w_i32m2_mu(vbool16_t mask, vint32m2_t maskedoff, vfloat64m4_t src, size_t vl) {1797 return __riscv_vfncvt_x_mu(mask, maskedoff, src, vl);1798}1799 1800// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfncvt_x_f_w_i32m4_mu1801// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1802// CHECK-RV64-NEXT: entry:1803// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfncvt.x.f.w.mask.nxv8i32.nxv8f64.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x double> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1804// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]1805//1806vint32m4_t test_vfncvt_x_f_w_i32m4_mu(vbool8_t mask, vint32m4_t maskedoff, vfloat64m8_t src, size_t vl) {1807 return __riscv_vfncvt_x_mu(mask, maskedoff, src, vl);1808}1809 1810// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfncvt_xu_f_w_u32mf2_mu1811// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1812// CHECK-RV64-NEXT: entry:1813// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i32.nxv1f64.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x double> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1814// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]1815//1816vuint32mf2_t test_vfncvt_xu_f_w_u32mf2_mu(vbool64_t mask, vuint32mf2_t maskedoff, vfloat64m1_t src, size_t vl) {1817 return __riscv_vfncvt_xu_mu(mask, maskedoff, src, vl);1818}1819 1820// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfncvt_xu_f_w_u32m1_mu1821// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1822// CHECK-RV64-NEXT: entry:1823// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfncvt.xu.f.w.mask.nxv2i32.nxv2f64.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x double> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1824// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]1825//1826vuint32m1_t test_vfncvt_xu_f_w_u32m1_mu(vbool32_t mask, vuint32m1_t maskedoff, vfloat64m2_t src, size_t vl) {1827 return __riscv_vfncvt_xu_mu(mask, maskedoff, src, vl);1828}1829 1830// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfncvt_xu_f_w_u32m2_mu1831// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1832// CHECK-RV64-NEXT: entry:1833// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfncvt.xu.f.w.mask.nxv4i32.nxv4f64.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x double> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1834// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]1835//1836vuint32m2_t test_vfncvt_xu_f_w_u32m2_mu(vbool16_t mask, vuint32m2_t maskedoff, vfloat64m4_t src, size_t vl) {1837 return __riscv_vfncvt_xu_mu(mask, maskedoff, src, vl);1838}1839 1840// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfncvt_xu_f_w_u32m4_mu1841// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1842// CHECK-RV64-NEXT: entry:1843// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfncvt.xu.f.w.mask.nxv8i32.nxv8f64.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x double> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1844// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]1845//1846vuint32m4_t test_vfncvt_xu_f_w_u32m4_mu(vbool8_t mask, vuint32m4_t maskedoff, vfloat64m8_t src, size_t vl) {1847 return __riscv_vfncvt_xu_mu(mask, maskedoff, src, vl);1848}1849 1850// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfncvt_f_x_w_f32mf2_mu1851// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1852// CHECK-RV64-NEXT: entry:1853// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.x.w.mask.nxv1f32.nxv1i64.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x i64> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1854// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]1855//1856vfloat32mf2_t test_vfncvt_f_x_w_f32mf2_mu(vbool64_t mask, vfloat32mf2_t maskedoff, vint64m1_t src, size_t vl) {1857 return __riscv_vfncvt_f_mu(mask, maskedoff, src, vl);1858}1859 1860// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfncvt_f_x_w_f32m1_mu1861// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1862// CHECK-RV64-NEXT: entry:1863// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.x.w.mask.nxv2f32.nxv2i64.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x i64> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1864// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]1865//1866vfloat32m1_t test_vfncvt_f_x_w_f32m1_mu(vbool32_t mask, vfloat32m1_t maskedoff, vint64m2_t src, size_t vl) {1867 return __riscv_vfncvt_f_mu(mask, maskedoff, src, vl);1868}1869 1870// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfncvt_f_x_w_f32m2_mu1871// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1872// CHECK-RV64-NEXT: entry:1873// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.x.w.mask.nxv4f32.nxv4i64.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x i64> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1874// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]1875//1876vfloat32m2_t test_vfncvt_f_x_w_f32m2_mu(vbool16_t mask, vfloat32m2_t maskedoff, vint64m4_t src, size_t vl) {1877 return __riscv_vfncvt_f_mu(mask, maskedoff, src, vl);1878}1879 1880// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfncvt_f_x_w_f32m4_mu1881// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1882// CHECK-RV64-NEXT: entry:1883// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.x.w.mask.nxv8f32.nxv8i64.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x i64> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1884// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]1885//1886vfloat32m4_t test_vfncvt_f_x_w_f32m4_mu(vbool8_t mask, vfloat32m4_t maskedoff, vint64m8_t src, size_t vl) {1887 return __riscv_vfncvt_f_mu(mask, maskedoff, src, vl);1888}1889 1890// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfncvt_f_xu_w_f32mf2_mu1891// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1892// CHECK-RV64-NEXT: entry:1893// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.xu.w.mask.nxv1f32.nxv1i64.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x i64> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1894// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]1895//1896vfloat32mf2_t test_vfncvt_f_xu_w_f32mf2_mu(vbool64_t mask, vfloat32mf2_t maskedoff, vuint64m1_t src, size_t vl) {1897 return __riscv_vfncvt_f_mu(mask, maskedoff, src, vl);1898}1899 1900// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfncvt_f_xu_w_f32m1_mu1901// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1902// CHECK-RV64-NEXT: entry:1903// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.xu.w.mask.nxv2f32.nxv2i64.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x i64> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1904// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]1905//1906vfloat32m1_t test_vfncvt_f_xu_w_f32m1_mu(vbool32_t mask, vfloat32m1_t maskedoff, vuint64m2_t src, size_t vl) {1907 return __riscv_vfncvt_f_mu(mask, maskedoff, src, vl);1908}1909 1910// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfncvt_f_xu_w_f32m2_mu1911// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1912// CHECK-RV64-NEXT: entry:1913// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.xu.w.mask.nxv4f32.nxv4i64.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x i64> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1914// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]1915//1916vfloat32m2_t test_vfncvt_f_xu_w_f32m2_mu(vbool16_t mask, vfloat32m2_t maskedoff, vuint64m4_t src, size_t vl) {1917 return __riscv_vfncvt_f_mu(mask, maskedoff, src, vl);1918}1919 1920// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfncvt_f_xu_w_f32m4_mu1921// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1922// CHECK-RV64-NEXT: entry:1923// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.xu.w.mask.nxv8f32.nxv8i64.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x i64> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1924// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]1925//1926vfloat32m4_t test_vfncvt_f_xu_w_f32m4_mu(vbool8_t mask, vfloat32m4_t maskedoff, vuint64m8_t src, size_t vl) {1927 return __riscv_vfncvt_f_mu(mask, maskedoff, src, vl);1928}1929 1930// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_i8mf8_rm_tu1931// CHECK-RV64-SAME: (<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1932// CHECK-RV64-NEXT: entry:1933// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> [[MASKEDOFF]], <vscale x 1 x half> [[SRC]], i64 0, i64 [[VL]])1934// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]1935//1936vint8mf8_t test_vfncvt_x_f_w_i8mf8_rm_tu(vint8mf8_t maskedoff, vfloat16mf4_t src, size_t vl) {1937 return __riscv_vfncvt_x_tu(maskedoff, src, __RISCV_FRM_RNE, vl);1938}1939 1940// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vfncvt_x_f_w_i8mf4_rm_tu1941// CHECK-RV64-SAME: (<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1942// CHECK-RV64-NEXT: entry:1943// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> [[MASKEDOFF]], <vscale x 2 x half> [[SRC]], i64 0, i64 [[VL]])1944// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]1945//1946vint8mf4_t test_vfncvt_x_f_w_i8mf4_rm_tu(vint8mf4_t maskedoff, vfloat16mf2_t src, size_t vl) {1947 return __riscv_vfncvt_x_tu(maskedoff, src, __RISCV_FRM_RNE, vl);1948}1949 1950// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vfncvt_x_f_w_i8mf2_rm_tu1951// CHECK-RV64-SAME: (<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1952// CHECK-RV64-NEXT: entry:1953// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> [[MASKEDOFF]], <vscale x 4 x half> [[SRC]], i64 0, i64 [[VL]])1954// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]1955//1956vint8mf2_t test_vfncvt_x_f_w_i8mf2_rm_tu(vint8mf2_t maskedoff, vfloat16m1_t src, size_t vl) {1957 return __riscv_vfncvt_x_tu(maskedoff, src, __RISCV_FRM_RNE, vl);1958}1959 1960// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vfncvt_x_f_w_i8m1_rm_tu1961// CHECK-RV64-SAME: (<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1962// CHECK-RV64-NEXT: entry:1963// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> [[MASKEDOFF]], <vscale x 8 x half> [[SRC]], i64 0, i64 [[VL]])1964// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]1965//1966vint8m1_t test_vfncvt_x_f_w_i8m1_rm_tu(vint8m1_t maskedoff, vfloat16m2_t src, size_t vl) {1967 return __riscv_vfncvt_x_tu(maskedoff, src, __RISCV_FRM_RNE, vl);1968}1969 1970// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vfncvt_x_f_w_i8m2_rm_tu1971// CHECK-RV64-SAME: (<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1972// CHECK-RV64-NEXT: entry:1973// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> [[MASKEDOFF]], <vscale x 16 x half> [[SRC]], i64 0, i64 [[VL]])1974// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]1975//1976vint8m2_t test_vfncvt_x_f_w_i8m2_rm_tu(vint8m2_t maskedoff, vfloat16m4_t src, size_t vl) {1977 return __riscv_vfncvt_x_tu(maskedoff, src, __RISCV_FRM_RNE, vl);1978}1979 1980// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vfncvt_x_f_w_i8m4_rm_tu1981// CHECK-RV64-SAME: (<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1982// CHECK-RV64-NEXT: entry:1983// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> [[MASKEDOFF]], <vscale x 32 x half> [[SRC]], i64 0, i64 [[VL]])1984// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]1985//1986vint8m4_t test_vfncvt_x_f_w_i8m4_rm_tu(vint8m4_t maskedoff, vfloat16m8_t src, size_t vl) {1987 return __riscv_vfncvt_x_tu(maskedoff, src, __RISCV_FRM_RNE, vl);1988}1989 1990// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vfncvt_xu_f_w_u8mf8_rm_tu1991// CHECK-RV64-SAME: (<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1992// CHECK-RV64-NEXT: entry:1993// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> [[MASKEDOFF]], <vscale x 1 x half> [[SRC]], i64 0, i64 [[VL]])1994// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]1995//1996vuint8mf8_t test_vfncvt_xu_f_w_u8mf8_rm_tu(vuint8mf8_t maskedoff, vfloat16mf4_t src, size_t vl) {1997 return __riscv_vfncvt_xu_tu(maskedoff, src, __RISCV_FRM_RNE, vl);1998}1999 2000// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vfncvt_xu_f_w_u8mf4_rm_tu2001// CHECK-RV64-SAME: (<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2002// CHECK-RV64-NEXT: entry:2003// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> [[MASKEDOFF]], <vscale x 2 x half> [[SRC]], i64 0, i64 [[VL]])2004// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]2005//2006vuint8mf4_t test_vfncvt_xu_f_w_u8mf4_rm_tu(vuint8mf4_t maskedoff, vfloat16mf2_t src, size_t vl) {2007 return __riscv_vfncvt_xu_tu(maskedoff, src, __RISCV_FRM_RNE, vl);2008}2009 2010// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vfncvt_xu_f_w_u8mf2_rm_tu2011// CHECK-RV64-SAME: (<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2012// CHECK-RV64-NEXT: entry:2013// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> [[MASKEDOFF]], <vscale x 4 x half> [[SRC]], i64 0, i64 [[VL]])2014// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]2015//2016vuint8mf2_t test_vfncvt_xu_f_w_u8mf2_rm_tu(vuint8mf2_t maskedoff, vfloat16m1_t src, size_t vl) {2017 return __riscv_vfncvt_xu_tu(maskedoff, src, __RISCV_FRM_RNE, vl);2018}2019 2020// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vfncvt_xu_f_w_u8m1_rm_tu2021// CHECK-RV64-SAME: (<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2022// CHECK-RV64-NEXT: entry:2023// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> [[MASKEDOFF]], <vscale x 8 x half> [[SRC]], i64 0, i64 [[VL]])2024// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]2025//2026vuint8m1_t test_vfncvt_xu_f_w_u8m1_rm_tu(vuint8m1_t maskedoff, vfloat16m2_t src, size_t vl) {2027 return __riscv_vfncvt_xu_tu(maskedoff, src, __RISCV_FRM_RNE, vl);2028}2029 2030// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vfncvt_xu_f_w_u8m2_rm_tu2031// CHECK-RV64-SAME: (<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2032// CHECK-RV64-NEXT: entry:2033// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> [[MASKEDOFF]], <vscale x 16 x half> [[SRC]], i64 0, i64 [[VL]])2034// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]2035//2036vuint8m2_t test_vfncvt_xu_f_w_u8m2_rm_tu(vuint8m2_t maskedoff, vfloat16m4_t src, size_t vl) {2037 return __riscv_vfncvt_xu_tu(maskedoff, src, __RISCV_FRM_RNE, vl);2038}2039 2040// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vfncvt_xu_f_w_u8m4_rm_tu2041// CHECK-RV64-SAME: (<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2042// CHECK-RV64-NEXT: entry:2043// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> [[MASKEDOFF]], <vscale x 32 x half> [[SRC]], i64 0, i64 [[VL]])2044// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]2045//2046vuint8m4_t test_vfncvt_xu_f_w_u8m4_rm_tu(vuint8m4_t maskedoff, vfloat16m8_t src, size_t vl) {2047 return __riscv_vfncvt_xu_tu(maskedoff, src, __RISCV_FRM_RNE, vl);2048}2049 2050// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vfncvt_x_f_w_i16mf4_rm_tu2051// CHECK-RV64-SAME: (<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2052// CHECK-RV64-NEXT: entry:2053// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfncvt.x.f.w.nxv1i16.nxv1f32.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x float> [[SRC]], i64 0, i64 [[VL]])2054// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]2055//2056vint16mf4_t test_vfncvt_x_f_w_i16mf4_rm_tu(vint16mf4_t maskedoff, vfloat32mf2_t src, size_t vl) {2057 return __riscv_vfncvt_x_tu(maskedoff, src, __RISCV_FRM_RNE, vl);2058}2059 2060// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vfncvt_x_f_w_i16mf2_rm_tu2061// CHECK-RV64-SAME: (<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2062// CHECK-RV64-NEXT: entry:2063// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfncvt.x.f.w.nxv2i16.nxv2f32.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x float> [[SRC]], i64 0, i64 [[VL]])2064// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]2065//2066vint16mf2_t test_vfncvt_x_f_w_i16mf2_rm_tu(vint16mf2_t maskedoff, vfloat32m1_t src, size_t vl) {2067 return __riscv_vfncvt_x_tu(maskedoff, src, __RISCV_FRM_RNE, vl);2068}2069 2070// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfncvt_x_f_w_i16m1_rm_tu2071// CHECK-RV64-SAME: (<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2072// CHECK-RV64-NEXT: entry:2073// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfncvt.x.f.w.nxv4i16.nxv4f32.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x float> [[SRC]], i64 0, i64 [[VL]])2074// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]2075//2076vint16m1_t test_vfncvt_x_f_w_i16m1_rm_tu(vint16m1_t maskedoff, vfloat32m2_t src, size_t vl) {2077 return __riscv_vfncvt_x_tu(maskedoff, src, __RISCV_FRM_RNE, vl);2078}2079 2080// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfncvt_x_f_w_i16m2_rm_tu2081// CHECK-RV64-SAME: (<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2082// CHECK-RV64-NEXT: entry:2083// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfncvt.x.f.w.nxv8i16.nxv8f32.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x float> [[SRC]], i64 0, i64 [[VL]])2084// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]2085//2086vint16m2_t test_vfncvt_x_f_w_i16m2_rm_tu(vint16m2_t maskedoff, vfloat32m4_t src, size_t vl) {2087 return __riscv_vfncvt_x_tu(maskedoff, src, __RISCV_FRM_RNE, vl);2088}2089 2090// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfncvt_x_f_w_i16m4_rm_tu2091// CHECK-RV64-SAME: (<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2092// CHECK-RV64-NEXT: entry:2093// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfncvt.x.f.w.nxv16i16.nxv16f32.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x float> [[SRC]], i64 0, i64 [[VL]])2094// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]2095//2096vint16m4_t test_vfncvt_x_f_w_i16m4_rm_tu(vint16m4_t maskedoff, vfloat32m8_t src, size_t vl) {2097 return __riscv_vfncvt_x_tu(maskedoff, src, __RISCV_FRM_RNE, vl);2098}2099 2100// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vfncvt_xu_f_w_u16mf4_rm_tu2101// CHECK-RV64-SAME: (<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2102// CHECK-RV64-NEXT: entry:2103// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv1i16.nxv1f32.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x float> [[SRC]], i64 0, i64 [[VL]])2104// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]2105//2106vuint16mf4_t test_vfncvt_xu_f_w_u16mf4_rm_tu(vuint16mf4_t maskedoff, vfloat32mf2_t src, size_t vl) {2107 return __riscv_vfncvt_xu_tu(maskedoff, src, __RISCV_FRM_RNE, vl);2108}2109 2110// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vfncvt_xu_f_w_u16mf2_rm_tu2111// CHECK-RV64-SAME: (<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2112// CHECK-RV64-NEXT: entry:2113// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv2i16.nxv2f32.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x float> [[SRC]], i64 0, i64 [[VL]])2114// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]2115//2116vuint16mf2_t test_vfncvt_xu_f_w_u16mf2_rm_tu(vuint16mf2_t maskedoff, vfloat32m1_t src, size_t vl) {2117 return __riscv_vfncvt_xu_tu(maskedoff, src, __RISCV_FRM_RNE, vl);2118}2119 2120// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfncvt_xu_f_w_u16m1_rm_tu2121// CHECK-RV64-SAME: (<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2122// CHECK-RV64-NEXT: entry:2123// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv4i16.nxv4f32.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x float> [[SRC]], i64 0, i64 [[VL]])2124// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]2125//2126vuint16m1_t test_vfncvt_xu_f_w_u16m1_rm_tu(vuint16m1_t maskedoff, vfloat32m2_t src, size_t vl) {2127 return __riscv_vfncvt_xu_tu(maskedoff, src, __RISCV_FRM_RNE, vl);2128}2129 2130// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfncvt_xu_f_w_u16m2_rm_tu2131// CHECK-RV64-SAME: (<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2132// CHECK-RV64-NEXT: entry:2133// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv8i16.nxv8f32.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x float> [[SRC]], i64 0, i64 [[VL]])2134// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]2135//2136vuint16m2_t test_vfncvt_xu_f_w_u16m2_rm_tu(vuint16m2_t maskedoff, vfloat32m4_t src, size_t vl) {2137 return __riscv_vfncvt_xu_tu(maskedoff, src, __RISCV_FRM_RNE, vl);2138}2139 2140// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfncvt_xu_f_w_u16m4_rm_tu2141// CHECK-RV64-SAME: (<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2142// CHECK-RV64-NEXT: entry:2143// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv16i16.nxv16f32.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x float> [[SRC]], i64 0, i64 [[VL]])2144// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]2145//2146vuint16m4_t test_vfncvt_xu_f_w_u16m4_rm_tu(vuint16m4_t maskedoff, vfloat32m8_t src, size_t vl) {2147 return __riscv_vfncvt_xu_tu(maskedoff, src, __RISCV_FRM_RNE, vl);2148}2149 2150// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfncvt_f_x_w_f16mf4_rm_tu2151// CHECK-RV64-SAME: (<vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2152// CHECK-RV64-NEXT: entry:2153// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.x.w.nxv1f16.nxv1i32.i64(<vscale x 1 x half> [[MASKEDOFF]], <vscale x 1 x i32> [[SRC]], i64 0, i64 [[VL]])2154// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]2155//2156vfloat16mf4_t test_vfncvt_f_x_w_f16mf4_rm_tu(vfloat16mf4_t maskedoff, vint32mf2_t src, size_t vl) {2157 return __riscv_vfncvt_f_tu(maskedoff, src, __RISCV_FRM_RNE, vl);2158}2159 2160// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfncvt_f_x_w_f16mf2_rm_tu2161// CHECK-RV64-SAME: (<vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2162// CHECK-RV64-NEXT: entry:2163// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.x.w.nxv2f16.nxv2i32.i64(<vscale x 2 x half> [[MASKEDOFF]], <vscale x 2 x i32> [[SRC]], i64 0, i64 [[VL]])2164// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]2165//2166vfloat16mf2_t test_vfncvt_f_x_w_f16mf2_rm_tu(vfloat16mf2_t maskedoff, vint32m1_t src, size_t vl) {2167 return __riscv_vfncvt_f_tu(maskedoff, src, __RISCV_FRM_RNE, vl);2168}2169 2170// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfncvt_f_x_w_f16m1_rm_tu2171// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2172// CHECK-RV64-NEXT: entry:2173// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.x.w.nxv4f16.nxv4i32.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x i32> [[SRC]], i64 0, i64 [[VL]])2174// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]2175//2176vfloat16m1_t test_vfncvt_f_x_w_f16m1_rm_tu(vfloat16m1_t maskedoff, vint32m2_t src, size_t vl) {2177 return __riscv_vfncvt_f_tu(maskedoff, src, __RISCV_FRM_RNE, vl);2178}2179 2180// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfncvt_f_x_w_f16m2_rm_tu2181// CHECK-RV64-SAME: (<vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2182// CHECK-RV64-NEXT: entry:2183// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.x.w.nxv8f16.nxv8i32.i64(<vscale x 8 x half> [[MASKEDOFF]], <vscale x 8 x i32> [[SRC]], i64 0, i64 [[VL]])2184// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]2185//2186vfloat16m2_t test_vfncvt_f_x_w_f16m2_rm_tu(vfloat16m2_t maskedoff, vint32m4_t src, size_t vl) {2187 return __riscv_vfncvt_f_tu(maskedoff, src, __RISCV_FRM_RNE, vl);2188}2189 2190// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfncvt_f_x_w_f16m4_rm_tu2191// CHECK-RV64-SAME: (<vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2192// CHECK-RV64-NEXT: entry:2193// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.x.w.nxv16f16.nxv16i32.i64(<vscale x 16 x half> [[MASKEDOFF]], <vscale x 16 x i32> [[SRC]], i64 0, i64 [[VL]])2194// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]2195//2196vfloat16m4_t test_vfncvt_f_x_w_f16m4_rm_tu(vfloat16m4_t maskedoff, vint32m8_t src, size_t vl) {2197 return __riscv_vfncvt_f_tu(maskedoff, src, __RISCV_FRM_RNE, vl);2198}2199 2200// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfncvt_f_xu_w_f16mf4_rm_tu2201// CHECK-RV64-SAME: (<vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2202// CHECK-RV64-NEXT: entry:2203// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.xu.w.nxv1f16.nxv1i32.i64(<vscale x 1 x half> [[MASKEDOFF]], <vscale x 1 x i32> [[SRC]], i64 0, i64 [[VL]])2204// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]2205//2206vfloat16mf4_t test_vfncvt_f_xu_w_f16mf4_rm_tu(vfloat16mf4_t maskedoff, vuint32mf2_t src, size_t vl) {2207 return __riscv_vfncvt_f_tu(maskedoff, src, __RISCV_FRM_RNE, vl);2208}2209 2210// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfncvt_f_xu_w_f16mf2_rm_tu2211// CHECK-RV64-SAME: (<vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2212// CHECK-RV64-NEXT: entry:2213// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.xu.w.nxv2f16.nxv2i32.i64(<vscale x 2 x half> [[MASKEDOFF]], <vscale x 2 x i32> [[SRC]], i64 0, i64 [[VL]])2214// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]2215//2216vfloat16mf2_t test_vfncvt_f_xu_w_f16mf2_rm_tu(vfloat16mf2_t maskedoff, vuint32m1_t src, size_t vl) {2217 return __riscv_vfncvt_f_tu(maskedoff, src, __RISCV_FRM_RNE, vl);2218}2219 2220// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfncvt_f_xu_w_f16m1_rm_tu2221// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2222// CHECK-RV64-NEXT: entry:2223// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.xu.w.nxv4f16.nxv4i32.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x i32> [[SRC]], i64 0, i64 [[VL]])2224// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]2225//2226vfloat16m1_t test_vfncvt_f_xu_w_f16m1_rm_tu(vfloat16m1_t maskedoff, vuint32m2_t src, size_t vl) {2227 return __riscv_vfncvt_f_tu(maskedoff, src, __RISCV_FRM_RNE, vl);2228}2229 2230// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfncvt_f_xu_w_f16m2_rm_tu2231// CHECK-RV64-SAME: (<vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2232// CHECK-RV64-NEXT: entry:2233// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.xu.w.nxv8f16.nxv8i32.i64(<vscale x 8 x half> [[MASKEDOFF]], <vscale x 8 x i32> [[SRC]], i64 0, i64 [[VL]])2234// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]2235//2236vfloat16m2_t test_vfncvt_f_xu_w_f16m2_rm_tu(vfloat16m2_t maskedoff, vuint32m4_t src, size_t vl) {2237 return __riscv_vfncvt_f_tu(maskedoff, src, __RISCV_FRM_RNE, vl);2238}2239 2240// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfncvt_f_xu_w_f16m4_rm_tu2241// CHECK-RV64-SAME: (<vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2242// CHECK-RV64-NEXT: entry:2243// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.xu.w.nxv16f16.nxv16i32.i64(<vscale x 16 x half> [[MASKEDOFF]], <vscale x 16 x i32> [[SRC]], i64 0, i64 [[VL]])2244// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]2245//2246vfloat16m4_t test_vfncvt_f_xu_w_f16m4_rm_tu(vfloat16m4_t maskedoff, vuint32m8_t src, size_t vl) {2247 return __riscv_vfncvt_f_tu(maskedoff, src, __RISCV_FRM_RNE, vl);2248}2249 2250// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfncvt_x_f_w_i32mf2_rm_tu2251// CHECK-RV64-SAME: (<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2252// CHECK-RV64-NEXT: entry:2253// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfncvt.x.f.w.nxv1i32.nxv1f64.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x double> [[SRC]], i64 0, i64 [[VL]])2254// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]2255//2256vint32mf2_t test_vfncvt_x_f_w_i32mf2_rm_tu(vint32mf2_t maskedoff, vfloat64m1_t src, size_t vl) {2257 return __riscv_vfncvt_x_tu(maskedoff, src, __RISCV_FRM_RNE, vl);2258}2259 2260// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfncvt_x_f_w_i32m1_rm_tu2261// CHECK-RV64-SAME: (<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2262// CHECK-RV64-NEXT: entry:2263// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfncvt.x.f.w.nxv2i32.nxv2f64.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x double> [[SRC]], i64 0, i64 [[VL]])2264// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]2265//2266vint32m1_t test_vfncvt_x_f_w_i32m1_rm_tu(vint32m1_t maskedoff, vfloat64m2_t src, size_t vl) {2267 return __riscv_vfncvt_x_tu(maskedoff, src, __RISCV_FRM_RNE, vl);2268}2269 2270// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfncvt_x_f_w_i32m2_rm_tu2271// CHECK-RV64-SAME: (<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2272// CHECK-RV64-NEXT: entry:2273// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfncvt.x.f.w.nxv4i32.nxv4f64.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x double> [[SRC]], i64 0, i64 [[VL]])2274// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]2275//2276vint32m2_t test_vfncvt_x_f_w_i32m2_rm_tu(vint32m2_t maskedoff, vfloat64m4_t src, size_t vl) {2277 return __riscv_vfncvt_x_tu(maskedoff, src, __RISCV_FRM_RNE, vl);2278}2279 2280// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfncvt_x_f_w_i32m4_rm_tu2281// CHECK-RV64-SAME: (<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2282// CHECK-RV64-NEXT: entry:2283// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfncvt.x.f.w.nxv8i32.nxv8f64.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x double> [[SRC]], i64 0, i64 [[VL]])2284// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]2285//2286vint32m4_t test_vfncvt_x_f_w_i32m4_rm_tu(vint32m4_t maskedoff, vfloat64m8_t src, size_t vl) {2287 return __riscv_vfncvt_x_tu(maskedoff, src, __RISCV_FRM_RNE, vl);2288}2289 2290// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfncvt_xu_f_w_u32mf2_rm_tu2291// CHECK-RV64-SAME: (<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2292// CHECK-RV64-NEXT: entry:2293// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv1i32.nxv1f64.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x double> [[SRC]], i64 0, i64 [[VL]])2294// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]2295//2296vuint32mf2_t test_vfncvt_xu_f_w_u32mf2_rm_tu(vuint32mf2_t maskedoff, vfloat64m1_t src, size_t vl) {2297 return __riscv_vfncvt_xu_tu(maskedoff, src, __RISCV_FRM_RNE, vl);2298}2299 2300// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfncvt_xu_f_w_u32m1_rm_tu2301// CHECK-RV64-SAME: (<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2302// CHECK-RV64-NEXT: entry:2303// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv2i32.nxv2f64.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x double> [[SRC]], i64 0, i64 [[VL]])2304// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]2305//2306vuint32m1_t test_vfncvt_xu_f_w_u32m1_rm_tu(vuint32m1_t maskedoff, vfloat64m2_t src, size_t vl) {2307 return __riscv_vfncvt_xu_tu(maskedoff, src, __RISCV_FRM_RNE, vl);2308}2309 2310// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfncvt_xu_f_w_u32m2_rm_tu2311// CHECK-RV64-SAME: (<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2312// CHECK-RV64-NEXT: entry:2313// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv4i32.nxv4f64.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x double> [[SRC]], i64 0, i64 [[VL]])2314// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]2315//2316vuint32m2_t test_vfncvt_xu_f_w_u32m2_rm_tu(vuint32m2_t maskedoff, vfloat64m4_t src, size_t vl) {2317 return __riscv_vfncvt_xu_tu(maskedoff, src, __RISCV_FRM_RNE, vl);2318}2319 2320// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfncvt_xu_f_w_u32m4_rm_tu2321// CHECK-RV64-SAME: (<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2322// CHECK-RV64-NEXT: entry:2323// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv8i32.nxv8f64.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x double> [[SRC]], i64 0, i64 [[VL]])2324// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]2325//2326vuint32m4_t test_vfncvt_xu_f_w_u32m4_rm_tu(vuint32m4_t maskedoff, vfloat64m8_t src, size_t vl) {2327 return __riscv_vfncvt_xu_tu(maskedoff, src, __RISCV_FRM_RNE, vl);2328}2329 2330// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfncvt_f_x_w_f32mf2_rm_tu2331// CHECK-RV64-SAME: (<vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2332// CHECK-RV64-NEXT: entry:2333// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.x.w.nxv1f32.nxv1i64.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x i64> [[SRC]], i64 0, i64 [[VL]])2334// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]2335//2336vfloat32mf2_t test_vfncvt_f_x_w_f32mf2_rm_tu(vfloat32mf2_t maskedoff, vint64m1_t src, size_t vl) {2337 return __riscv_vfncvt_f_tu(maskedoff, src, __RISCV_FRM_RNE, vl);2338}2339 2340// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfncvt_f_x_w_f32m1_rm_tu2341// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2342// CHECK-RV64-NEXT: entry:2343// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.x.w.nxv2f32.nxv2i64.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x i64> [[SRC]], i64 0, i64 [[VL]])2344// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]2345//2346vfloat32m1_t test_vfncvt_f_x_w_f32m1_rm_tu(vfloat32m1_t maskedoff, vint64m2_t src, size_t vl) {2347 return __riscv_vfncvt_f_tu(maskedoff, src, __RISCV_FRM_RNE, vl);2348}2349 2350// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfncvt_f_x_w_f32m2_rm_tu2351// CHECK-RV64-SAME: (<vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2352// CHECK-RV64-NEXT: entry:2353// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.x.w.nxv4f32.nxv4i64.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x i64> [[SRC]], i64 0, i64 [[VL]])2354// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]2355//2356vfloat32m2_t test_vfncvt_f_x_w_f32m2_rm_tu(vfloat32m2_t maskedoff, vint64m4_t src, size_t vl) {2357 return __riscv_vfncvt_f_tu(maskedoff, src, __RISCV_FRM_RNE, vl);2358}2359 2360// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfncvt_f_x_w_f32m4_rm_tu2361// CHECK-RV64-SAME: (<vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2362// CHECK-RV64-NEXT: entry:2363// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.x.w.nxv8f32.nxv8i64.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x i64> [[SRC]], i64 0, i64 [[VL]])2364// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]2365//2366vfloat32m4_t test_vfncvt_f_x_w_f32m4_rm_tu(vfloat32m4_t maskedoff, vint64m8_t src, size_t vl) {2367 return __riscv_vfncvt_f_tu(maskedoff, src, __RISCV_FRM_RNE, vl);2368}2369 2370// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfncvt_f_xu_w_f32mf2_rm_tu2371// CHECK-RV64-SAME: (<vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2372// CHECK-RV64-NEXT: entry:2373// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.xu.w.nxv1f32.nxv1i64.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x i64> [[SRC]], i64 0, i64 [[VL]])2374// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]2375//2376vfloat32mf2_t test_vfncvt_f_xu_w_f32mf2_rm_tu(vfloat32mf2_t maskedoff, vuint64m1_t src, size_t vl) {2377 return __riscv_vfncvt_f_tu(maskedoff, src, __RISCV_FRM_RNE, vl);2378}2379 2380// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfncvt_f_xu_w_f32m1_rm_tu2381// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2382// CHECK-RV64-NEXT: entry:2383// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.xu.w.nxv2f32.nxv2i64.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x i64> [[SRC]], i64 0, i64 [[VL]])2384// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]2385//2386vfloat32m1_t test_vfncvt_f_xu_w_f32m1_rm_tu(vfloat32m1_t maskedoff, vuint64m2_t src, size_t vl) {2387 return __riscv_vfncvt_f_tu(maskedoff, src, __RISCV_FRM_RNE, vl);2388}2389 2390// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfncvt_f_xu_w_f32m2_rm_tu2391// CHECK-RV64-SAME: (<vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2392// CHECK-RV64-NEXT: entry:2393// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.xu.w.nxv4f32.nxv4i64.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x i64> [[SRC]], i64 0, i64 [[VL]])2394// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]2395//2396vfloat32m2_t test_vfncvt_f_xu_w_f32m2_rm_tu(vfloat32m2_t maskedoff, vuint64m4_t src, size_t vl) {2397 return __riscv_vfncvt_f_tu(maskedoff, src, __RISCV_FRM_RNE, vl);2398}2399 2400// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfncvt_f_xu_w_f32m4_rm_tu2401// CHECK-RV64-SAME: (<vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2402// CHECK-RV64-NEXT: entry:2403// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.xu.w.nxv8f32.nxv8i64.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x i64> [[SRC]], i64 0, i64 [[VL]])2404// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]2405//2406vfloat32m4_t test_vfncvt_f_xu_w_f32m4_rm_tu(vfloat32m4_t maskedoff, vuint64m8_t src, size_t vl) {2407 return __riscv_vfncvt_f_tu(maskedoff, src, __RISCV_FRM_RNE, vl);2408}2409 2410// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_i8mf8_rm_tum2411// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2412// CHECK-RV64-NEXT: entry:2413// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> [[MASKEDOFF]], <vscale x 1 x half> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2414// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]2415//2416vint8mf8_t test_vfncvt_x_f_w_i8mf8_rm_tum(vbool64_t mask, vint8mf8_t maskedoff, vfloat16mf4_t src, size_t vl) {2417 return __riscv_vfncvt_x_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2418}2419 2420// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vfncvt_x_f_w_i8mf4_rm_tum2421// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2422// CHECK-RV64-NEXT: entry:2423// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> [[MASKEDOFF]], <vscale x 2 x half> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2424// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]2425//2426vint8mf4_t test_vfncvt_x_f_w_i8mf4_rm_tum(vbool32_t mask, vint8mf4_t maskedoff, vfloat16mf2_t src, size_t vl) {2427 return __riscv_vfncvt_x_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2428}2429 2430// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vfncvt_x_f_w_i8mf2_rm_tum2431// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2432// CHECK-RV64-NEXT: entry:2433// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> [[MASKEDOFF]], <vscale x 4 x half> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2434// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]2435//2436vint8mf2_t test_vfncvt_x_f_w_i8mf2_rm_tum(vbool16_t mask, vint8mf2_t maskedoff, vfloat16m1_t src, size_t vl) {2437 return __riscv_vfncvt_x_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2438}2439 2440// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vfncvt_x_f_w_i8m1_rm_tum2441// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2442// CHECK-RV64-NEXT: entry:2443// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> [[MASKEDOFF]], <vscale x 8 x half> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2444// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]2445//2446vint8m1_t test_vfncvt_x_f_w_i8m1_rm_tum(vbool8_t mask, vint8m1_t maskedoff, vfloat16m2_t src, size_t vl) {2447 return __riscv_vfncvt_x_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2448}2449 2450// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vfncvt_x_f_w_i8m2_rm_tum2451// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2452// CHECK-RV64-NEXT: entry:2453// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> [[MASKEDOFF]], <vscale x 16 x half> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2454// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]2455//2456vint8m2_t test_vfncvt_x_f_w_i8m2_rm_tum(vbool4_t mask, vint8m2_t maskedoff, vfloat16m4_t src, size_t vl) {2457 return __riscv_vfncvt_x_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2458}2459 2460// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vfncvt_x_f_w_i8m4_rm_tum2461// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2462// CHECK-RV64-NEXT: entry:2463// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> [[MASKEDOFF]], <vscale x 32 x half> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2464// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]2465//2466vint8m4_t test_vfncvt_x_f_w_i8m4_rm_tum(vbool2_t mask, vint8m4_t maskedoff, vfloat16m8_t src, size_t vl) {2467 return __riscv_vfncvt_x_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2468}2469 2470// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vfncvt_xu_f_w_u8mf8_rm_tum2471// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2472// CHECK-RV64-NEXT: entry:2473// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> [[MASKEDOFF]], <vscale x 1 x half> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2474// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]2475//2476vuint8mf8_t test_vfncvt_xu_f_w_u8mf8_rm_tum(vbool64_t mask, vuint8mf8_t maskedoff, vfloat16mf4_t src, size_t vl) {2477 return __riscv_vfncvt_xu_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2478}2479 2480// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vfncvt_xu_f_w_u8mf4_rm_tum2481// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2482// CHECK-RV64-NEXT: entry:2483// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> [[MASKEDOFF]], <vscale x 2 x half> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2484// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]2485//2486vuint8mf4_t test_vfncvt_xu_f_w_u8mf4_rm_tum(vbool32_t mask, vuint8mf4_t maskedoff, vfloat16mf2_t src, size_t vl) {2487 return __riscv_vfncvt_xu_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2488}2489 2490// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vfncvt_xu_f_w_u8mf2_rm_tum2491// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2492// CHECK-RV64-NEXT: entry:2493// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> [[MASKEDOFF]], <vscale x 4 x half> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2494// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]2495//2496vuint8mf2_t test_vfncvt_xu_f_w_u8mf2_rm_tum(vbool16_t mask, vuint8mf2_t maskedoff, vfloat16m1_t src, size_t vl) {2497 return __riscv_vfncvt_xu_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2498}2499 2500// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vfncvt_xu_f_w_u8m1_rm_tum2501// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2502// CHECK-RV64-NEXT: entry:2503// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> [[MASKEDOFF]], <vscale x 8 x half> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2504// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]2505//2506vuint8m1_t test_vfncvt_xu_f_w_u8m1_rm_tum(vbool8_t mask, vuint8m1_t maskedoff, vfloat16m2_t src, size_t vl) {2507 return __riscv_vfncvt_xu_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2508}2509 2510// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vfncvt_xu_f_w_u8m2_rm_tum2511// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2512// CHECK-RV64-NEXT: entry:2513// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> [[MASKEDOFF]], <vscale x 16 x half> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2514// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]2515//2516vuint8m2_t test_vfncvt_xu_f_w_u8m2_rm_tum(vbool4_t mask, vuint8m2_t maskedoff, vfloat16m4_t src, size_t vl) {2517 return __riscv_vfncvt_xu_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2518}2519 2520// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vfncvt_xu_f_w_u8m4_rm_tum2521// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2522// CHECK-RV64-NEXT: entry:2523// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> [[MASKEDOFF]], <vscale x 32 x half> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2524// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]2525//2526vuint8m4_t test_vfncvt_xu_f_w_u8m4_rm_tum(vbool2_t mask, vuint8m4_t maskedoff, vfloat16m8_t src, size_t vl) {2527 return __riscv_vfncvt_xu_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2528}2529 2530// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vfncvt_x_f_w_i16mf4_rm_tum2531// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2532// CHECK-RV64-NEXT: entry:2533// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv1i16.nxv1f32.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x float> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2534// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]2535//2536vint16mf4_t test_vfncvt_x_f_w_i16mf4_rm_tum(vbool64_t mask, vint16mf4_t maskedoff, vfloat32mf2_t src, size_t vl) {2537 return __riscv_vfncvt_x_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2538}2539 2540// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vfncvt_x_f_w_i16mf2_rm_tum2541// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2542// CHECK-RV64-NEXT: entry:2543// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv2i16.nxv2f32.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x float> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2544// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]2545//2546vint16mf2_t test_vfncvt_x_f_w_i16mf2_rm_tum(vbool32_t mask, vint16mf2_t maskedoff, vfloat32m1_t src, size_t vl) {2547 return __riscv_vfncvt_x_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2548}2549 2550// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfncvt_x_f_w_i16m1_rm_tum2551// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2552// CHECK-RV64-NEXT: entry:2553// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv4i16.nxv4f32.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x float> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2554// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]2555//2556vint16m1_t test_vfncvt_x_f_w_i16m1_rm_tum(vbool16_t mask, vint16m1_t maskedoff, vfloat32m2_t src, size_t vl) {2557 return __riscv_vfncvt_x_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2558}2559 2560// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfncvt_x_f_w_i16m2_rm_tum2561// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2562// CHECK-RV64-NEXT: entry:2563// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv8i16.nxv8f32.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x float> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2564// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]2565//2566vint16m2_t test_vfncvt_x_f_w_i16m2_rm_tum(vbool8_t mask, vint16m2_t maskedoff, vfloat32m4_t src, size_t vl) {2567 return __riscv_vfncvt_x_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2568}2569 2570// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfncvt_x_f_w_i16m4_rm_tum2571// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2572// CHECK-RV64-NEXT: entry:2573// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv16i16.nxv16f32.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x float> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2574// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]2575//2576vint16m4_t test_vfncvt_x_f_w_i16m4_rm_tum(vbool4_t mask, vint16m4_t maskedoff, vfloat32m8_t src, size_t vl) {2577 return __riscv_vfncvt_x_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2578}2579 2580// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vfncvt_xu_f_w_u16mf4_rm_tum2581// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2582// CHECK-RV64-NEXT: entry:2583// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i16.nxv1f32.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x float> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2584// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]2585//2586vuint16mf4_t test_vfncvt_xu_f_w_u16mf4_rm_tum(vbool64_t mask, vuint16mf4_t maskedoff, vfloat32mf2_t src, size_t vl) {2587 return __riscv_vfncvt_xu_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2588}2589 2590// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vfncvt_xu_f_w_u16mf2_rm_tum2591// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2592// CHECK-RV64-NEXT: entry:2593// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv2i16.nxv2f32.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x float> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2594// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]2595//2596vuint16mf2_t test_vfncvt_xu_f_w_u16mf2_rm_tum(vbool32_t mask, vuint16mf2_t maskedoff, vfloat32m1_t src, size_t vl) {2597 return __riscv_vfncvt_xu_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2598}2599 2600// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfncvt_xu_f_w_u16m1_rm_tum2601// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2602// CHECK-RV64-NEXT: entry:2603// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv4i16.nxv4f32.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x float> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2604// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]2605//2606vuint16m1_t test_vfncvt_xu_f_w_u16m1_rm_tum(vbool16_t mask, vuint16m1_t maskedoff, vfloat32m2_t src, size_t vl) {2607 return __riscv_vfncvt_xu_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2608}2609 2610// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfncvt_xu_f_w_u16m2_rm_tum2611// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2612// CHECK-RV64-NEXT: entry:2613// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv8i16.nxv8f32.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x float> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2614// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]2615//2616vuint16m2_t test_vfncvt_xu_f_w_u16m2_rm_tum(vbool8_t mask, vuint16m2_t maskedoff, vfloat32m4_t src, size_t vl) {2617 return __riscv_vfncvt_xu_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2618}2619 2620// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfncvt_xu_f_w_u16m4_rm_tum2621// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2622// CHECK-RV64-NEXT: entry:2623// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv16i16.nxv16f32.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x float> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2624// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]2625//2626vuint16m4_t test_vfncvt_xu_f_w_u16m4_rm_tum(vbool4_t mask, vuint16m4_t maskedoff, vfloat32m8_t src, size_t vl) {2627 return __riscv_vfncvt_xu_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2628}2629 2630// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfncvt_f_x_w_f16mf4_rm_tum2631// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2632// CHECK-RV64-NEXT: entry:2633// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv1f16.nxv1i32.i64(<vscale x 1 x half> [[MASKEDOFF]], <vscale x 1 x i32> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2634// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]2635//2636vfloat16mf4_t test_vfncvt_f_x_w_f16mf4_rm_tum(vbool64_t mask, vfloat16mf4_t maskedoff, vint32mf2_t src, size_t vl) {2637 return __riscv_vfncvt_f_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2638}2639 2640// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfncvt_f_x_w_f16mf2_rm_tum2641// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2642// CHECK-RV64-NEXT: entry:2643// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv2f16.nxv2i32.i64(<vscale x 2 x half> [[MASKEDOFF]], <vscale x 2 x i32> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2644// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]2645//2646vfloat16mf2_t test_vfncvt_f_x_w_f16mf2_rm_tum(vbool32_t mask, vfloat16mf2_t maskedoff, vint32m1_t src, size_t vl) {2647 return __riscv_vfncvt_f_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2648}2649 2650// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfncvt_f_x_w_f16m1_rm_tum2651// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2652// CHECK-RV64-NEXT: entry:2653// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv4f16.nxv4i32.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x i32> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2654// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]2655//2656vfloat16m1_t test_vfncvt_f_x_w_f16m1_rm_tum(vbool16_t mask, vfloat16m1_t maskedoff, vint32m2_t src, size_t vl) {2657 return __riscv_vfncvt_f_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2658}2659 2660// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfncvt_f_x_w_f16m2_rm_tum2661// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2662// CHECK-RV64-NEXT: entry:2663// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv8f16.nxv8i32.i64(<vscale x 8 x half> [[MASKEDOFF]], <vscale x 8 x i32> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2664// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]2665//2666vfloat16m2_t test_vfncvt_f_x_w_f16m2_rm_tum(vbool8_t mask, vfloat16m2_t maskedoff, vint32m4_t src, size_t vl) {2667 return __riscv_vfncvt_f_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2668}2669 2670// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfncvt_f_x_w_f16m4_rm_tum2671// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2672// CHECK-RV64-NEXT: entry:2673// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv16f16.nxv16i32.i64(<vscale x 16 x half> [[MASKEDOFF]], <vscale x 16 x i32> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2674// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]2675//2676vfloat16m4_t test_vfncvt_f_x_w_f16m4_rm_tum(vbool4_t mask, vfloat16m4_t maskedoff, vint32m8_t src, size_t vl) {2677 return __riscv_vfncvt_f_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2678}2679 2680// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfncvt_f_xu_w_f16mf4_rm_tum2681// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2682// CHECK-RV64-NEXT: entry:2683// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv1f16.nxv1i32.i64(<vscale x 1 x half> [[MASKEDOFF]], <vscale x 1 x i32> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2684// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]2685//2686vfloat16mf4_t test_vfncvt_f_xu_w_f16mf4_rm_tum(vbool64_t mask, vfloat16mf4_t maskedoff, vuint32mf2_t src, size_t vl) {2687 return __riscv_vfncvt_f_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2688}2689 2690// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfncvt_f_xu_w_f16mf2_rm_tum2691// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2692// CHECK-RV64-NEXT: entry:2693// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv2f16.nxv2i32.i64(<vscale x 2 x half> [[MASKEDOFF]], <vscale x 2 x i32> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2694// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]2695//2696vfloat16mf2_t test_vfncvt_f_xu_w_f16mf2_rm_tum(vbool32_t mask, vfloat16mf2_t maskedoff, vuint32m1_t src, size_t vl) {2697 return __riscv_vfncvt_f_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2698}2699 2700// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfncvt_f_xu_w_f16m1_rm_tum2701// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2702// CHECK-RV64-NEXT: entry:2703// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv4f16.nxv4i32.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x i32> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2704// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]2705//2706vfloat16m1_t test_vfncvt_f_xu_w_f16m1_rm_tum(vbool16_t mask, vfloat16m1_t maskedoff, vuint32m2_t src, size_t vl) {2707 return __riscv_vfncvt_f_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2708}2709 2710// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfncvt_f_xu_w_f16m2_rm_tum2711// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2712// CHECK-RV64-NEXT: entry:2713// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv8f16.nxv8i32.i64(<vscale x 8 x half> [[MASKEDOFF]], <vscale x 8 x i32> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2714// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]2715//2716vfloat16m2_t test_vfncvt_f_xu_w_f16m2_rm_tum(vbool8_t mask, vfloat16m2_t maskedoff, vuint32m4_t src, size_t vl) {2717 return __riscv_vfncvt_f_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2718}2719 2720// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfncvt_f_xu_w_f16m4_rm_tum2721// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2722// CHECK-RV64-NEXT: entry:2723// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv16f16.nxv16i32.i64(<vscale x 16 x half> [[MASKEDOFF]], <vscale x 16 x i32> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2724// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]2725//2726vfloat16m4_t test_vfncvt_f_xu_w_f16m4_rm_tum(vbool4_t mask, vfloat16m4_t maskedoff, vuint32m8_t src, size_t vl) {2727 return __riscv_vfncvt_f_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2728}2729 2730// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfncvt_x_f_w_i32mf2_rm_tum2731// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2732// CHECK-RV64-NEXT: entry:2733// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfncvt.x.f.w.mask.nxv1i32.nxv1f64.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x double> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2734// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]2735//2736vint32mf2_t test_vfncvt_x_f_w_i32mf2_rm_tum(vbool64_t mask, vint32mf2_t maskedoff, vfloat64m1_t src, size_t vl) {2737 return __riscv_vfncvt_x_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2738}2739 2740// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfncvt_x_f_w_i32m1_rm_tum2741// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2742// CHECK-RV64-NEXT: entry:2743// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfncvt.x.f.w.mask.nxv2i32.nxv2f64.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x double> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2744// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]2745//2746vint32m1_t test_vfncvt_x_f_w_i32m1_rm_tum(vbool32_t mask, vint32m1_t maskedoff, vfloat64m2_t src, size_t vl) {2747 return __riscv_vfncvt_x_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2748}2749 2750// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfncvt_x_f_w_i32m2_rm_tum2751// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2752// CHECK-RV64-NEXT: entry:2753// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfncvt.x.f.w.mask.nxv4i32.nxv4f64.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x double> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2754// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]2755//2756vint32m2_t test_vfncvt_x_f_w_i32m2_rm_tum(vbool16_t mask, vint32m2_t maskedoff, vfloat64m4_t src, size_t vl) {2757 return __riscv_vfncvt_x_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2758}2759 2760// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfncvt_x_f_w_i32m4_rm_tum2761// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2762// CHECK-RV64-NEXT: entry:2763// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfncvt.x.f.w.mask.nxv8i32.nxv8f64.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x double> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2764// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]2765//2766vint32m4_t test_vfncvt_x_f_w_i32m4_rm_tum(vbool8_t mask, vint32m4_t maskedoff, vfloat64m8_t src, size_t vl) {2767 return __riscv_vfncvt_x_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2768}2769 2770// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfncvt_xu_f_w_u32mf2_rm_tum2771// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2772// CHECK-RV64-NEXT: entry:2773// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i32.nxv1f64.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x double> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2774// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]2775//2776vuint32mf2_t test_vfncvt_xu_f_w_u32mf2_rm_tum(vbool64_t mask, vuint32mf2_t maskedoff, vfloat64m1_t src, size_t vl) {2777 return __riscv_vfncvt_xu_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2778}2779 2780// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfncvt_xu_f_w_u32m1_rm_tum2781// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2782// CHECK-RV64-NEXT: entry:2783// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfncvt.xu.f.w.mask.nxv2i32.nxv2f64.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x double> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2784// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]2785//2786vuint32m1_t test_vfncvt_xu_f_w_u32m1_rm_tum(vbool32_t mask, vuint32m1_t maskedoff, vfloat64m2_t src, size_t vl) {2787 return __riscv_vfncvt_xu_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2788}2789 2790// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfncvt_xu_f_w_u32m2_rm_tum2791// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2792// CHECK-RV64-NEXT: entry:2793// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfncvt.xu.f.w.mask.nxv4i32.nxv4f64.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x double> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2794// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]2795//2796vuint32m2_t test_vfncvt_xu_f_w_u32m2_rm_tum(vbool16_t mask, vuint32m2_t maskedoff, vfloat64m4_t src, size_t vl) {2797 return __riscv_vfncvt_xu_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2798}2799 2800// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfncvt_xu_f_w_u32m4_rm_tum2801// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2802// CHECK-RV64-NEXT: entry:2803// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfncvt.xu.f.w.mask.nxv8i32.nxv8f64.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x double> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2804// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]2805//2806vuint32m4_t test_vfncvt_xu_f_w_u32m4_rm_tum(vbool8_t mask, vuint32m4_t maskedoff, vfloat64m8_t src, size_t vl) {2807 return __riscv_vfncvt_xu_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2808}2809 2810// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfncvt_f_x_w_f32mf2_rm_tum2811// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2812// CHECK-RV64-NEXT: entry:2813// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.x.w.mask.nxv1f32.nxv1i64.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x i64> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2814// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]2815//2816vfloat32mf2_t test_vfncvt_f_x_w_f32mf2_rm_tum(vbool64_t mask, vfloat32mf2_t maskedoff, vint64m1_t src, size_t vl) {2817 return __riscv_vfncvt_f_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2818}2819 2820// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfncvt_f_x_w_f32m1_rm_tum2821// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2822// CHECK-RV64-NEXT: entry:2823// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.x.w.mask.nxv2f32.nxv2i64.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x i64> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2824// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]2825//2826vfloat32m1_t test_vfncvt_f_x_w_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t maskedoff, vint64m2_t src, size_t vl) {2827 return __riscv_vfncvt_f_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2828}2829 2830// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfncvt_f_x_w_f32m2_rm_tum2831// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2832// CHECK-RV64-NEXT: entry:2833// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.x.w.mask.nxv4f32.nxv4i64.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x i64> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2834// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]2835//2836vfloat32m2_t test_vfncvt_f_x_w_f32m2_rm_tum(vbool16_t mask, vfloat32m2_t maskedoff, vint64m4_t src, size_t vl) {2837 return __riscv_vfncvt_f_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2838}2839 2840// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfncvt_f_x_w_f32m4_rm_tum2841// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2842// CHECK-RV64-NEXT: entry:2843// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.x.w.mask.nxv8f32.nxv8i64.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x i64> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2844// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]2845//2846vfloat32m4_t test_vfncvt_f_x_w_f32m4_rm_tum(vbool8_t mask, vfloat32m4_t maskedoff, vint64m8_t src, size_t vl) {2847 return __riscv_vfncvt_f_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2848}2849 2850// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfncvt_f_xu_w_f32mf2_rm_tum2851// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2852// CHECK-RV64-NEXT: entry:2853// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.xu.w.mask.nxv1f32.nxv1i64.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x i64> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2854// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]2855//2856vfloat32mf2_t test_vfncvt_f_xu_w_f32mf2_rm_tum(vbool64_t mask, vfloat32mf2_t maskedoff, vuint64m1_t src, size_t vl) {2857 return __riscv_vfncvt_f_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2858}2859 2860// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfncvt_f_xu_w_f32m1_rm_tum2861// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2862// CHECK-RV64-NEXT: entry:2863// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.xu.w.mask.nxv2f32.nxv2i64.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x i64> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2864// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]2865//2866vfloat32m1_t test_vfncvt_f_xu_w_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t maskedoff, vuint64m2_t src, size_t vl) {2867 return __riscv_vfncvt_f_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2868}2869 2870// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfncvt_f_xu_w_f32m2_rm_tum2871// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2872// CHECK-RV64-NEXT: entry:2873// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.xu.w.mask.nxv4f32.nxv4i64.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x i64> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2874// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]2875//2876vfloat32m2_t test_vfncvt_f_xu_w_f32m2_rm_tum(vbool16_t mask, vfloat32m2_t maskedoff, vuint64m4_t src, size_t vl) {2877 return __riscv_vfncvt_f_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2878}2879 2880// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfncvt_f_xu_w_f32m4_rm_tum2881// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2882// CHECK-RV64-NEXT: entry:2883// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.xu.w.mask.nxv8f32.nxv8i64.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x i64> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2884// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]2885//2886vfloat32m4_t test_vfncvt_f_xu_w_f32m4_rm_tum(vbool8_t mask, vfloat32m4_t maskedoff, vuint64m8_t src, size_t vl) {2887 return __riscv_vfncvt_f_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2888}2889 2890// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_i8mf8_rm_tumu2891// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2892// CHECK-RV64-NEXT: entry:2893// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> [[MASKEDOFF]], <vscale x 1 x half> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)2894// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]2895//2896vint8mf8_t test_vfncvt_x_f_w_i8mf8_rm_tumu(vbool64_t mask, vint8mf8_t maskedoff, vfloat16mf4_t src, size_t vl) {2897 return __riscv_vfncvt_x_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2898}2899 2900// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vfncvt_x_f_w_i8mf4_rm_tumu2901// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2902// CHECK-RV64-NEXT: entry:2903// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> [[MASKEDOFF]], <vscale x 2 x half> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)2904// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]2905//2906vint8mf4_t test_vfncvt_x_f_w_i8mf4_rm_tumu(vbool32_t mask, vint8mf4_t maskedoff, vfloat16mf2_t src, size_t vl) {2907 return __riscv_vfncvt_x_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2908}2909 2910// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vfncvt_x_f_w_i8mf2_rm_tumu2911// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2912// CHECK-RV64-NEXT: entry:2913// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> [[MASKEDOFF]], <vscale x 4 x half> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)2914// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]2915//2916vint8mf2_t test_vfncvt_x_f_w_i8mf2_rm_tumu(vbool16_t mask, vint8mf2_t maskedoff, vfloat16m1_t src, size_t vl) {2917 return __riscv_vfncvt_x_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2918}2919 2920// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vfncvt_x_f_w_i8m1_rm_tumu2921// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2922// CHECK-RV64-NEXT: entry:2923// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> [[MASKEDOFF]], <vscale x 8 x half> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)2924// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]2925//2926vint8m1_t test_vfncvt_x_f_w_i8m1_rm_tumu(vbool8_t mask, vint8m1_t maskedoff, vfloat16m2_t src, size_t vl) {2927 return __riscv_vfncvt_x_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2928}2929 2930// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vfncvt_x_f_w_i8m2_rm_tumu2931// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2932// CHECK-RV64-NEXT: entry:2933// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> [[MASKEDOFF]], <vscale x 16 x half> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)2934// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]2935//2936vint8m2_t test_vfncvt_x_f_w_i8m2_rm_tumu(vbool4_t mask, vint8m2_t maskedoff, vfloat16m4_t src, size_t vl) {2937 return __riscv_vfncvt_x_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2938}2939 2940// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vfncvt_x_f_w_i8m4_rm_tumu2941// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2942// CHECK-RV64-NEXT: entry:2943// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> [[MASKEDOFF]], <vscale x 32 x half> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)2944// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]2945//2946vint8m4_t test_vfncvt_x_f_w_i8m4_rm_tumu(vbool2_t mask, vint8m4_t maskedoff, vfloat16m8_t src, size_t vl) {2947 return __riscv_vfncvt_x_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2948}2949 2950// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vfncvt_xu_f_w_u8mf8_rm_tumu2951// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2952// CHECK-RV64-NEXT: entry:2953// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> [[MASKEDOFF]], <vscale x 1 x half> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)2954// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]2955//2956vuint8mf8_t test_vfncvt_xu_f_w_u8mf8_rm_tumu(vbool64_t mask, vuint8mf8_t maskedoff, vfloat16mf4_t src, size_t vl) {2957 return __riscv_vfncvt_xu_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2958}2959 2960// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vfncvt_xu_f_w_u8mf4_rm_tumu2961// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2962// CHECK-RV64-NEXT: entry:2963// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> [[MASKEDOFF]], <vscale x 2 x half> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)2964// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]2965//2966vuint8mf4_t test_vfncvt_xu_f_w_u8mf4_rm_tumu(vbool32_t mask, vuint8mf4_t maskedoff, vfloat16mf2_t src, size_t vl) {2967 return __riscv_vfncvt_xu_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2968}2969 2970// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vfncvt_xu_f_w_u8mf2_rm_tumu2971// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2972// CHECK-RV64-NEXT: entry:2973// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> [[MASKEDOFF]], <vscale x 4 x half> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)2974// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]2975//2976vuint8mf2_t test_vfncvt_xu_f_w_u8mf2_rm_tumu(vbool16_t mask, vuint8mf2_t maskedoff, vfloat16m1_t src, size_t vl) {2977 return __riscv_vfncvt_xu_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2978}2979 2980// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vfncvt_xu_f_w_u8m1_rm_tumu2981// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2982// CHECK-RV64-NEXT: entry:2983// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> [[MASKEDOFF]], <vscale x 8 x half> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)2984// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]2985//2986vuint8m1_t test_vfncvt_xu_f_w_u8m1_rm_tumu(vbool8_t mask, vuint8m1_t maskedoff, vfloat16m2_t src, size_t vl) {2987 return __riscv_vfncvt_xu_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2988}2989 2990// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vfncvt_xu_f_w_u8m2_rm_tumu2991// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2992// CHECK-RV64-NEXT: entry:2993// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> [[MASKEDOFF]], <vscale x 16 x half> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)2994// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]2995//2996vuint8m2_t test_vfncvt_xu_f_w_u8m2_rm_tumu(vbool4_t mask, vuint8m2_t maskedoff, vfloat16m4_t src, size_t vl) {2997 return __riscv_vfncvt_xu_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2998}2999 3000// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vfncvt_xu_f_w_u8m4_rm_tumu3001// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3002// CHECK-RV64-NEXT: entry:3003// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> [[MASKEDOFF]], <vscale x 32 x half> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)3004// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]3005//3006vuint8m4_t test_vfncvt_xu_f_w_u8m4_rm_tumu(vbool2_t mask, vuint8m4_t maskedoff, vfloat16m8_t src, size_t vl) {3007 return __riscv_vfncvt_xu_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3008}3009 3010// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vfncvt_x_f_w_i16mf4_rm_tumu3011// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3012// CHECK-RV64-NEXT: entry:3013// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv1i16.nxv1f32.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x float> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)3014// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]3015//3016vint16mf4_t test_vfncvt_x_f_w_i16mf4_rm_tumu(vbool64_t mask, vint16mf4_t maskedoff, vfloat32mf2_t src, size_t vl) {3017 return __riscv_vfncvt_x_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3018}3019 3020// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vfncvt_x_f_w_i16mf2_rm_tumu3021// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3022// CHECK-RV64-NEXT: entry:3023// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv2i16.nxv2f32.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x float> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)3024// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]3025//3026vint16mf2_t test_vfncvt_x_f_w_i16mf2_rm_tumu(vbool32_t mask, vint16mf2_t maskedoff, vfloat32m1_t src, size_t vl) {3027 return __riscv_vfncvt_x_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3028}3029 3030// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfncvt_x_f_w_i16m1_rm_tumu3031// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3032// CHECK-RV64-NEXT: entry:3033// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv4i16.nxv4f32.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x float> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)3034// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]3035//3036vint16m1_t test_vfncvt_x_f_w_i16m1_rm_tumu(vbool16_t mask, vint16m1_t maskedoff, vfloat32m2_t src, size_t vl) {3037 return __riscv_vfncvt_x_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3038}3039 3040// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfncvt_x_f_w_i16m2_rm_tumu3041// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3042// CHECK-RV64-NEXT: entry:3043// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv8i16.nxv8f32.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x float> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)3044// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]3045//3046vint16m2_t test_vfncvt_x_f_w_i16m2_rm_tumu(vbool8_t mask, vint16m2_t maskedoff, vfloat32m4_t src, size_t vl) {3047 return __riscv_vfncvt_x_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3048}3049 3050// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfncvt_x_f_w_i16m4_rm_tumu3051// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3052// CHECK-RV64-NEXT: entry:3053// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv16i16.nxv16f32.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x float> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)3054// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]3055//3056vint16m4_t test_vfncvt_x_f_w_i16m4_rm_tumu(vbool4_t mask, vint16m4_t maskedoff, vfloat32m8_t src, size_t vl) {3057 return __riscv_vfncvt_x_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3058}3059 3060// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vfncvt_xu_f_w_u16mf4_rm_tumu3061// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3062// CHECK-RV64-NEXT: entry:3063// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i16.nxv1f32.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x float> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)3064// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]3065//3066vuint16mf4_t test_vfncvt_xu_f_w_u16mf4_rm_tumu(vbool64_t mask, vuint16mf4_t maskedoff, vfloat32mf2_t src, size_t vl) {3067 return __riscv_vfncvt_xu_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3068}3069 3070// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vfncvt_xu_f_w_u16mf2_rm_tumu3071// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3072// CHECK-RV64-NEXT: entry:3073// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv2i16.nxv2f32.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x float> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)3074// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]3075//3076vuint16mf2_t test_vfncvt_xu_f_w_u16mf2_rm_tumu(vbool32_t mask, vuint16mf2_t maskedoff, vfloat32m1_t src, size_t vl) {3077 return __riscv_vfncvt_xu_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3078}3079 3080// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfncvt_xu_f_w_u16m1_rm_tumu3081// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3082// CHECK-RV64-NEXT: entry:3083// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv4i16.nxv4f32.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x float> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)3084// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]3085//3086vuint16m1_t test_vfncvt_xu_f_w_u16m1_rm_tumu(vbool16_t mask, vuint16m1_t maskedoff, vfloat32m2_t src, size_t vl) {3087 return __riscv_vfncvt_xu_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3088}3089 3090// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfncvt_xu_f_w_u16m2_rm_tumu3091// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3092// CHECK-RV64-NEXT: entry:3093// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv8i16.nxv8f32.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x float> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)3094// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]3095//3096vuint16m2_t test_vfncvt_xu_f_w_u16m2_rm_tumu(vbool8_t mask, vuint16m2_t maskedoff, vfloat32m4_t src, size_t vl) {3097 return __riscv_vfncvt_xu_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3098}3099 3100// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfncvt_xu_f_w_u16m4_rm_tumu3101// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3102// CHECK-RV64-NEXT: entry:3103// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv16i16.nxv16f32.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x float> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)3104// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]3105//3106vuint16m4_t test_vfncvt_xu_f_w_u16m4_rm_tumu(vbool4_t mask, vuint16m4_t maskedoff, vfloat32m8_t src, size_t vl) {3107 return __riscv_vfncvt_xu_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3108}3109 3110// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfncvt_f_x_w_f16mf4_rm_tumu3111// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3112// CHECK-RV64-NEXT: entry:3113// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv1f16.nxv1i32.i64(<vscale x 1 x half> [[MASKEDOFF]], <vscale x 1 x i32> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)3114// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]3115//3116vfloat16mf4_t test_vfncvt_f_x_w_f16mf4_rm_tumu(vbool64_t mask, vfloat16mf4_t maskedoff, vint32mf2_t src, size_t vl) {3117 return __riscv_vfncvt_f_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3118}3119 3120// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfncvt_f_x_w_f16mf2_rm_tumu3121// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3122// CHECK-RV64-NEXT: entry:3123// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv2f16.nxv2i32.i64(<vscale x 2 x half> [[MASKEDOFF]], <vscale x 2 x i32> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)3124// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]3125//3126vfloat16mf2_t test_vfncvt_f_x_w_f16mf2_rm_tumu(vbool32_t mask, vfloat16mf2_t maskedoff, vint32m1_t src, size_t vl) {3127 return __riscv_vfncvt_f_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3128}3129 3130// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfncvt_f_x_w_f16m1_rm_tumu3131// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3132// CHECK-RV64-NEXT: entry:3133// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv4f16.nxv4i32.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x i32> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)3134// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]3135//3136vfloat16m1_t test_vfncvt_f_x_w_f16m1_rm_tumu(vbool16_t mask, vfloat16m1_t maskedoff, vint32m2_t src, size_t vl) {3137 return __riscv_vfncvt_f_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3138}3139 3140// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfncvt_f_x_w_f16m2_rm_tumu3141// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3142// CHECK-RV64-NEXT: entry:3143// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv8f16.nxv8i32.i64(<vscale x 8 x half> [[MASKEDOFF]], <vscale x 8 x i32> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)3144// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]3145//3146vfloat16m2_t test_vfncvt_f_x_w_f16m2_rm_tumu(vbool8_t mask, vfloat16m2_t maskedoff, vint32m4_t src, size_t vl) {3147 return __riscv_vfncvt_f_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3148}3149 3150// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfncvt_f_x_w_f16m4_rm_tumu3151// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3152// CHECK-RV64-NEXT: entry:3153// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv16f16.nxv16i32.i64(<vscale x 16 x half> [[MASKEDOFF]], <vscale x 16 x i32> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)3154// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]3155//3156vfloat16m4_t test_vfncvt_f_x_w_f16m4_rm_tumu(vbool4_t mask, vfloat16m4_t maskedoff, vint32m8_t src, size_t vl) {3157 return __riscv_vfncvt_f_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3158}3159 3160// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfncvt_f_xu_w_f16mf4_rm_tumu3161// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3162// CHECK-RV64-NEXT: entry:3163// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv1f16.nxv1i32.i64(<vscale x 1 x half> [[MASKEDOFF]], <vscale x 1 x i32> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)3164// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]3165//3166vfloat16mf4_t test_vfncvt_f_xu_w_f16mf4_rm_tumu(vbool64_t mask, vfloat16mf4_t maskedoff, vuint32mf2_t src, size_t vl) {3167 return __riscv_vfncvt_f_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3168}3169 3170// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfncvt_f_xu_w_f16mf2_rm_tumu3171// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3172// CHECK-RV64-NEXT: entry:3173// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv2f16.nxv2i32.i64(<vscale x 2 x half> [[MASKEDOFF]], <vscale x 2 x i32> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)3174// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]3175//3176vfloat16mf2_t test_vfncvt_f_xu_w_f16mf2_rm_tumu(vbool32_t mask, vfloat16mf2_t maskedoff, vuint32m1_t src, size_t vl) {3177 return __riscv_vfncvt_f_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3178}3179 3180// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfncvt_f_xu_w_f16m1_rm_tumu3181// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3182// CHECK-RV64-NEXT: entry:3183// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv4f16.nxv4i32.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x i32> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)3184// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]3185//3186vfloat16m1_t test_vfncvt_f_xu_w_f16m1_rm_tumu(vbool16_t mask, vfloat16m1_t maskedoff, vuint32m2_t src, size_t vl) {3187 return __riscv_vfncvt_f_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3188}3189 3190// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfncvt_f_xu_w_f16m2_rm_tumu3191// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3192// CHECK-RV64-NEXT: entry:3193// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv8f16.nxv8i32.i64(<vscale x 8 x half> [[MASKEDOFF]], <vscale x 8 x i32> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)3194// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]3195//3196vfloat16m2_t test_vfncvt_f_xu_w_f16m2_rm_tumu(vbool8_t mask, vfloat16m2_t maskedoff, vuint32m4_t src, size_t vl) {3197 return __riscv_vfncvt_f_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3198}3199 3200// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfncvt_f_xu_w_f16m4_rm_tumu3201// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3202// CHECK-RV64-NEXT: entry:3203// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv16f16.nxv16i32.i64(<vscale x 16 x half> [[MASKEDOFF]], <vscale x 16 x i32> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)3204// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]3205//3206vfloat16m4_t test_vfncvt_f_xu_w_f16m4_rm_tumu(vbool4_t mask, vfloat16m4_t maskedoff, vuint32m8_t src, size_t vl) {3207 return __riscv_vfncvt_f_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3208}3209 3210// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfncvt_x_f_w_i32mf2_rm_tumu3211// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3212// CHECK-RV64-NEXT: entry:3213// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfncvt.x.f.w.mask.nxv1i32.nxv1f64.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x double> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)3214// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]3215//3216vint32mf2_t test_vfncvt_x_f_w_i32mf2_rm_tumu(vbool64_t mask, vint32mf2_t maskedoff, vfloat64m1_t src, size_t vl) {3217 return __riscv_vfncvt_x_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3218}3219 3220// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfncvt_x_f_w_i32m1_rm_tumu3221// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3222// CHECK-RV64-NEXT: entry:3223// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfncvt.x.f.w.mask.nxv2i32.nxv2f64.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x double> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)3224// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]3225//3226vint32m1_t test_vfncvt_x_f_w_i32m1_rm_tumu(vbool32_t mask, vint32m1_t maskedoff, vfloat64m2_t src, size_t vl) {3227 return __riscv_vfncvt_x_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3228}3229 3230// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfncvt_x_f_w_i32m2_rm_tumu3231// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3232// CHECK-RV64-NEXT: entry:3233// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfncvt.x.f.w.mask.nxv4i32.nxv4f64.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x double> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)3234// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]3235//3236vint32m2_t test_vfncvt_x_f_w_i32m2_rm_tumu(vbool16_t mask, vint32m2_t maskedoff, vfloat64m4_t src, size_t vl) {3237 return __riscv_vfncvt_x_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3238}3239 3240// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfncvt_x_f_w_i32m4_rm_tumu3241// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3242// CHECK-RV64-NEXT: entry:3243// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfncvt.x.f.w.mask.nxv8i32.nxv8f64.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x double> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)3244// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]3245//3246vint32m4_t test_vfncvt_x_f_w_i32m4_rm_tumu(vbool8_t mask, vint32m4_t maskedoff, vfloat64m8_t src, size_t vl) {3247 return __riscv_vfncvt_x_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3248}3249 3250// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfncvt_xu_f_w_u32mf2_rm_tumu3251// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3252// CHECK-RV64-NEXT: entry:3253// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i32.nxv1f64.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x double> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)3254// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]3255//3256vuint32mf2_t test_vfncvt_xu_f_w_u32mf2_rm_tumu(vbool64_t mask, vuint32mf2_t maskedoff, vfloat64m1_t src, size_t vl) {3257 return __riscv_vfncvt_xu_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3258}3259 3260// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfncvt_xu_f_w_u32m1_rm_tumu3261// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3262// CHECK-RV64-NEXT: entry:3263// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfncvt.xu.f.w.mask.nxv2i32.nxv2f64.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x double> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)3264// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]3265//3266vuint32m1_t test_vfncvt_xu_f_w_u32m1_rm_tumu(vbool32_t mask, vuint32m1_t maskedoff, vfloat64m2_t src, size_t vl) {3267 return __riscv_vfncvt_xu_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3268}3269 3270// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfncvt_xu_f_w_u32m2_rm_tumu3271// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3272// CHECK-RV64-NEXT: entry:3273// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfncvt.xu.f.w.mask.nxv4i32.nxv4f64.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x double> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)3274// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]3275//3276vuint32m2_t test_vfncvt_xu_f_w_u32m2_rm_tumu(vbool16_t mask, vuint32m2_t maskedoff, vfloat64m4_t src, size_t vl) {3277 return __riscv_vfncvt_xu_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3278}3279 3280// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfncvt_xu_f_w_u32m4_rm_tumu3281// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3282// CHECK-RV64-NEXT: entry:3283// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfncvt.xu.f.w.mask.nxv8i32.nxv8f64.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x double> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)3284// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]3285//3286vuint32m4_t test_vfncvt_xu_f_w_u32m4_rm_tumu(vbool8_t mask, vuint32m4_t maskedoff, vfloat64m8_t src, size_t vl) {3287 return __riscv_vfncvt_xu_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3288}3289 3290// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfncvt_f_x_w_f32mf2_rm_tumu3291// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3292// CHECK-RV64-NEXT: entry:3293// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.x.w.mask.nxv1f32.nxv1i64.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x i64> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)3294// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]3295//3296vfloat32mf2_t test_vfncvt_f_x_w_f32mf2_rm_tumu(vbool64_t mask, vfloat32mf2_t maskedoff, vint64m1_t src, size_t vl) {3297 return __riscv_vfncvt_f_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3298}3299 3300// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfncvt_f_x_w_f32m1_rm_tumu3301// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3302// CHECK-RV64-NEXT: entry:3303// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.x.w.mask.nxv2f32.nxv2i64.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x i64> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)3304// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]3305//3306vfloat32m1_t test_vfncvt_f_x_w_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t maskedoff, vint64m2_t src, size_t vl) {3307 return __riscv_vfncvt_f_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3308}3309 3310// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfncvt_f_x_w_f32m2_rm_tumu3311// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3312// CHECK-RV64-NEXT: entry:3313// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.x.w.mask.nxv4f32.nxv4i64.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x i64> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)3314// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]3315//3316vfloat32m2_t test_vfncvt_f_x_w_f32m2_rm_tumu(vbool16_t mask, vfloat32m2_t maskedoff, vint64m4_t src, size_t vl) {3317 return __riscv_vfncvt_f_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3318}3319 3320// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfncvt_f_x_w_f32m4_rm_tumu3321// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3322// CHECK-RV64-NEXT: entry:3323// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.x.w.mask.nxv8f32.nxv8i64.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x i64> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)3324// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]3325//3326vfloat32m4_t test_vfncvt_f_x_w_f32m4_rm_tumu(vbool8_t mask, vfloat32m4_t maskedoff, vint64m8_t src, size_t vl) {3327 return __riscv_vfncvt_f_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3328}3329 3330// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfncvt_f_xu_w_f32mf2_rm_tumu3331// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3332// CHECK-RV64-NEXT: entry:3333// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.xu.w.mask.nxv1f32.nxv1i64.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x i64> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)3334// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]3335//3336vfloat32mf2_t test_vfncvt_f_xu_w_f32mf2_rm_tumu(vbool64_t mask, vfloat32mf2_t maskedoff, vuint64m1_t src, size_t vl) {3337 return __riscv_vfncvt_f_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3338}3339 3340// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfncvt_f_xu_w_f32m1_rm_tumu3341// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3342// CHECK-RV64-NEXT: entry:3343// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.xu.w.mask.nxv2f32.nxv2i64.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x i64> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)3344// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]3345//3346vfloat32m1_t test_vfncvt_f_xu_w_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t maskedoff, vuint64m2_t src, size_t vl) {3347 return __riscv_vfncvt_f_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3348}3349 3350// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfncvt_f_xu_w_f32m2_rm_tumu3351// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3352// CHECK-RV64-NEXT: entry:3353// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.xu.w.mask.nxv4f32.nxv4i64.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x i64> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)3354// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]3355//3356vfloat32m2_t test_vfncvt_f_xu_w_f32m2_rm_tumu(vbool16_t mask, vfloat32m2_t maskedoff, vuint64m4_t src, size_t vl) {3357 return __riscv_vfncvt_f_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3358}3359 3360// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfncvt_f_xu_w_f32m4_rm_tumu3361// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3362// CHECK-RV64-NEXT: entry:3363// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.xu.w.mask.nxv8f32.nxv8i64.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x i64> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)3364// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]3365//3366vfloat32m4_t test_vfncvt_f_xu_w_f32m4_rm_tumu(vbool8_t mask, vfloat32m4_t maskedoff, vuint64m8_t src, size_t vl) {3367 return __riscv_vfncvt_f_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3368}3369 3370// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_i8mf8_rm_mu3371// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3372// CHECK-RV64-NEXT: entry:3373// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> [[MASKEDOFF]], <vscale x 1 x half> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)3374// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]3375//3376vint8mf8_t test_vfncvt_x_f_w_i8mf8_rm_mu(vbool64_t mask, vint8mf8_t maskedoff, vfloat16mf4_t src, size_t vl) {3377 return __riscv_vfncvt_x_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3378}3379 3380// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vfncvt_x_f_w_i8mf4_rm_mu3381// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3382// CHECK-RV64-NEXT: entry:3383// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> [[MASKEDOFF]], <vscale x 2 x half> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)3384// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]3385//3386vint8mf4_t test_vfncvt_x_f_w_i8mf4_rm_mu(vbool32_t mask, vint8mf4_t maskedoff, vfloat16mf2_t src, size_t vl) {3387 return __riscv_vfncvt_x_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3388}3389 3390// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vfncvt_x_f_w_i8mf2_rm_mu3391// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3392// CHECK-RV64-NEXT: entry:3393// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> [[MASKEDOFF]], <vscale x 4 x half> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)3394// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]3395//3396vint8mf2_t test_vfncvt_x_f_w_i8mf2_rm_mu(vbool16_t mask, vint8mf2_t maskedoff, vfloat16m1_t src, size_t vl) {3397 return __riscv_vfncvt_x_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3398}3399 3400// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vfncvt_x_f_w_i8m1_rm_mu3401// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3402// CHECK-RV64-NEXT: entry:3403// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> [[MASKEDOFF]], <vscale x 8 x half> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)3404// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]3405//3406vint8m1_t test_vfncvt_x_f_w_i8m1_rm_mu(vbool8_t mask, vint8m1_t maskedoff, vfloat16m2_t src, size_t vl) {3407 return __riscv_vfncvt_x_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3408}3409 3410// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vfncvt_x_f_w_i8m2_rm_mu3411// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3412// CHECK-RV64-NEXT: entry:3413// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> [[MASKEDOFF]], <vscale x 16 x half> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)3414// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]3415//3416vint8m2_t test_vfncvt_x_f_w_i8m2_rm_mu(vbool4_t mask, vint8m2_t maskedoff, vfloat16m4_t src, size_t vl) {3417 return __riscv_vfncvt_x_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3418}3419 3420// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vfncvt_x_f_w_i8m4_rm_mu3421// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3422// CHECK-RV64-NEXT: entry:3423// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> [[MASKEDOFF]], <vscale x 32 x half> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)3424// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]3425//3426vint8m4_t test_vfncvt_x_f_w_i8m4_rm_mu(vbool2_t mask, vint8m4_t maskedoff, vfloat16m8_t src, size_t vl) {3427 return __riscv_vfncvt_x_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3428}3429 3430// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vfncvt_xu_f_w_u8mf8_rm_mu3431// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3432// CHECK-RV64-NEXT: entry:3433// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> [[MASKEDOFF]], <vscale x 1 x half> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)3434// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]3435//3436vuint8mf8_t test_vfncvt_xu_f_w_u8mf8_rm_mu(vbool64_t mask, vuint8mf8_t maskedoff, vfloat16mf4_t src, size_t vl) {3437 return __riscv_vfncvt_xu_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3438}3439 3440// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vfncvt_xu_f_w_u8mf4_rm_mu3441// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3442// CHECK-RV64-NEXT: entry:3443// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> [[MASKEDOFF]], <vscale x 2 x half> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)3444// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]3445//3446vuint8mf4_t test_vfncvt_xu_f_w_u8mf4_rm_mu(vbool32_t mask, vuint8mf4_t maskedoff, vfloat16mf2_t src, size_t vl) {3447 return __riscv_vfncvt_xu_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3448}3449 3450// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vfncvt_xu_f_w_u8mf2_rm_mu3451// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3452// CHECK-RV64-NEXT: entry:3453// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> [[MASKEDOFF]], <vscale x 4 x half> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)3454// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]3455//3456vuint8mf2_t test_vfncvt_xu_f_w_u8mf2_rm_mu(vbool16_t mask, vuint8mf2_t maskedoff, vfloat16m1_t src, size_t vl) {3457 return __riscv_vfncvt_xu_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3458}3459 3460// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vfncvt_xu_f_w_u8m1_rm_mu3461// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3462// CHECK-RV64-NEXT: entry:3463// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> [[MASKEDOFF]], <vscale x 8 x half> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)3464// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]3465//3466vuint8m1_t test_vfncvt_xu_f_w_u8m1_rm_mu(vbool8_t mask, vuint8m1_t maskedoff, vfloat16m2_t src, size_t vl) {3467 return __riscv_vfncvt_xu_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3468}3469 3470// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vfncvt_xu_f_w_u8m2_rm_mu3471// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3472// CHECK-RV64-NEXT: entry:3473// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> [[MASKEDOFF]], <vscale x 16 x half> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)3474// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]3475//3476vuint8m2_t test_vfncvt_xu_f_w_u8m2_rm_mu(vbool4_t mask, vuint8m2_t maskedoff, vfloat16m4_t src, size_t vl) {3477 return __riscv_vfncvt_xu_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3478}3479 3480// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vfncvt_xu_f_w_u8m4_rm_mu3481// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3482// CHECK-RV64-NEXT: entry:3483// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> [[MASKEDOFF]], <vscale x 32 x half> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)3484// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]3485//3486vuint8m4_t test_vfncvt_xu_f_w_u8m4_rm_mu(vbool2_t mask, vuint8m4_t maskedoff, vfloat16m8_t src, size_t vl) {3487 return __riscv_vfncvt_xu_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3488}3489 3490// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vfncvt_x_f_w_i16mf4_rm_mu3491// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3492// CHECK-RV64-NEXT: entry:3493// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv1i16.nxv1f32.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x float> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)3494// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]3495//3496vint16mf4_t test_vfncvt_x_f_w_i16mf4_rm_mu(vbool64_t mask, vint16mf4_t maskedoff, vfloat32mf2_t src, size_t vl) {3497 return __riscv_vfncvt_x_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3498}3499 3500// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vfncvt_x_f_w_i16mf2_rm_mu3501// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3502// CHECK-RV64-NEXT: entry:3503// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv2i16.nxv2f32.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x float> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)3504// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]3505//3506vint16mf2_t test_vfncvt_x_f_w_i16mf2_rm_mu(vbool32_t mask, vint16mf2_t maskedoff, vfloat32m1_t src, size_t vl) {3507 return __riscv_vfncvt_x_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3508}3509 3510// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfncvt_x_f_w_i16m1_rm_mu3511// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3512// CHECK-RV64-NEXT: entry:3513// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv4i16.nxv4f32.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x float> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)3514// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]3515//3516vint16m1_t test_vfncvt_x_f_w_i16m1_rm_mu(vbool16_t mask, vint16m1_t maskedoff, vfloat32m2_t src, size_t vl) {3517 return __riscv_vfncvt_x_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3518}3519 3520// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfncvt_x_f_w_i16m2_rm_mu3521// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3522// CHECK-RV64-NEXT: entry:3523// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv8i16.nxv8f32.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x float> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)3524// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]3525//3526vint16m2_t test_vfncvt_x_f_w_i16m2_rm_mu(vbool8_t mask, vint16m2_t maskedoff, vfloat32m4_t src, size_t vl) {3527 return __riscv_vfncvt_x_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3528}3529 3530// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfncvt_x_f_w_i16m4_rm_mu3531// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3532// CHECK-RV64-NEXT: entry:3533// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv16i16.nxv16f32.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x float> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)3534// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]3535//3536vint16m4_t test_vfncvt_x_f_w_i16m4_rm_mu(vbool4_t mask, vint16m4_t maskedoff, vfloat32m8_t src, size_t vl) {3537 return __riscv_vfncvt_x_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3538}3539 3540// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vfncvt_xu_f_w_u16mf4_rm_mu3541// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3542// CHECK-RV64-NEXT: entry:3543// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i16.nxv1f32.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x float> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)3544// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]3545//3546vuint16mf4_t test_vfncvt_xu_f_w_u16mf4_rm_mu(vbool64_t mask, vuint16mf4_t maskedoff, vfloat32mf2_t src, size_t vl) {3547 return __riscv_vfncvt_xu_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3548}3549 3550// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vfncvt_xu_f_w_u16mf2_rm_mu3551// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3552// CHECK-RV64-NEXT: entry:3553// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv2i16.nxv2f32.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x float> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)3554// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]3555//3556vuint16mf2_t test_vfncvt_xu_f_w_u16mf2_rm_mu(vbool32_t mask, vuint16mf2_t maskedoff, vfloat32m1_t src, size_t vl) {3557 return __riscv_vfncvt_xu_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3558}3559 3560// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfncvt_xu_f_w_u16m1_rm_mu3561// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3562// CHECK-RV64-NEXT: entry:3563// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv4i16.nxv4f32.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x float> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)3564// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]3565//3566vuint16m1_t test_vfncvt_xu_f_w_u16m1_rm_mu(vbool16_t mask, vuint16m1_t maskedoff, vfloat32m2_t src, size_t vl) {3567 return __riscv_vfncvt_xu_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3568}3569 3570// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfncvt_xu_f_w_u16m2_rm_mu3571// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3572// CHECK-RV64-NEXT: entry:3573// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv8i16.nxv8f32.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x float> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)3574// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]3575//3576vuint16m2_t test_vfncvt_xu_f_w_u16m2_rm_mu(vbool8_t mask, vuint16m2_t maskedoff, vfloat32m4_t src, size_t vl) {3577 return __riscv_vfncvt_xu_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3578}3579 3580// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfncvt_xu_f_w_u16m4_rm_mu3581// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3582// CHECK-RV64-NEXT: entry:3583// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv16i16.nxv16f32.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x float> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)3584// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]3585//3586vuint16m4_t test_vfncvt_xu_f_w_u16m4_rm_mu(vbool4_t mask, vuint16m4_t maskedoff, vfloat32m8_t src, size_t vl) {3587 return __riscv_vfncvt_xu_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3588}3589 3590// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfncvt_f_x_w_f16mf4_rm_mu3591// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3592// CHECK-RV64-NEXT: entry:3593// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv1f16.nxv1i32.i64(<vscale x 1 x half> [[MASKEDOFF]], <vscale x 1 x i32> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)3594// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]3595//3596vfloat16mf4_t test_vfncvt_f_x_w_f16mf4_rm_mu(vbool64_t mask, vfloat16mf4_t maskedoff, vint32mf2_t src, size_t vl) {3597 return __riscv_vfncvt_f_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3598}3599 3600// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfncvt_f_x_w_f16mf2_rm_mu3601// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3602// CHECK-RV64-NEXT: entry:3603// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv2f16.nxv2i32.i64(<vscale x 2 x half> [[MASKEDOFF]], <vscale x 2 x i32> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)3604// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]3605//3606vfloat16mf2_t test_vfncvt_f_x_w_f16mf2_rm_mu(vbool32_t mask, vfloat16mf2_t maskedoff, vint32m1_t src, size_t vl) {3607 return __riscv_vfncvt_f_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3608}3609 3610// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfncvt_f_x_w_f16m1_rm_mu3611// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3612// CHECK-RV64-NEXT: entry:3613// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv4f16.nxv4i32.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x i32> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)3614// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]3615//3616vfloat16m1_t test_vfncvt_f_x_w_f16m1_rm_mu(vbool16_t mask, vfloat16m1_t maskedoff, vint32m2_t src, size_t vl) {3617 return __riscv_vfncvt_f_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3618}3619 3620// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfncvt_f_x_w_f16m2_rm_mu3621// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3622// CHECK-RV64-NEXT: entry:3623// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv8f16.nxv8i32.i64(<vscale x 8 x half> [[MASKEDOFF]], <vscale x 8 x i32> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)3624// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]3625//3626vfloat16m2_t test_vfncvt_f_x_w_f16m2_rm_mu(vbool8_t mask, vfloat16m2_t maskedoff, vint32m4_t src, size_t vl) {3627 return __riscv_vfncvt_f_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3628}3629 3630// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfncvt_f_x_w_f16m4_rm_mu3631// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3632// CHECK-RV64-NEXT: entry:3633// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv16f16.nxv16i32.i64(<vscale x 16 x half> [[MASKEDOFF]], <vscale x 16 x i32> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)3634// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]3635//3636vfloat16m4_t test_vfncvt_f_x_w_f16m4_rm_mu(vbool4_t mask, vfloat16m4_t maskedoff, vint32m8_t src, size_t vl) {3637 return __riscv_vfncvt_f_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3638}3639 3640// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfncvt_f_xu_w_f16mf4_rm_mu3641// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3642// CHECK-RV64-NEXT: entry:3643// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv1f16.nxv1i32.i64(<vscale x 1 x half> [[MASKEDOFF]], <vscale x 1 x i32> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)3644// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]3645//3646vfloat16mf4_t test_vfncvt_f_xu_w_f16mf4_rm_mu(vbool64_t mask, vfloat16mf4_t maskedoff, vuint32mf2_t src, size_t vl) {3647 return __riscv_vfncvt_f_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3648}3649 3650// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfncvt_f_xu_w_f16mf2_rm_mu3651// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3652// CHECK-RV64-NEXT: entry:3653// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv2f16.nxv2i32.i64(<vscale x 2 x half> [[MASKEDOFF]], <vscale x 2 x i32> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)3654// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]3655//3656vfloat16mf2_t test_vfncvt_f_xu_w_f16mf2_rm_mu(vbool32_t mask, vfloat16mf2_t maskedoff, vuint32m1_t src, size_t vl) {3657 return __riscv_vfncvt_f_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3658}3659 3660// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfncvt_f_xu_w_f16m1_rm_mu3661// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3662// CHECK-RV64-NEXT: entry:3663// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv4f16.nxv4i32.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x i32> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)3664// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]3665//3666vfloat16m1_t test_vfncvt_f_xu_w_f16m1_rm_mu(vbool16_t mask, vfloat16m1_t maskedoff, vuint32m2_t src, size_t vl) {3667 return __riscv_vfncvt_f_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3668}3669 3670// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfncvt_f_xu_w_f16m2_rm_mu3671// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3672// CHECK-RV64-NEXT: entry:3673// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv8f16.nxv8i32.i64(<vscale x 8 x half> [[MASKEDOFF]], <vscale x 8 x i32> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)3674// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]3675//3676vfloat16m2_t test_vfncvt_f_xu_w_f16m2_rm_mu(vbool8_t mask, vfloat16m2_t maskedoff, vuint32m4_t src, size_t vl) {3677 return __riscv_vfncvt_f_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3678}3679 3680// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfncvt_f_xu_w_f16m4_rm_mu3681// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3682// CHECK-RV64-NEXT: entry:3683// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv16f16.nxv16i32.i64(<vscale x 16 x half> [[MASKEDOFF]], <vscale x 16 x i32> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)3684// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]3685//3686vfloat16m4_t test_vfncvt_f_xu_w_f16m4_rm_mu(vbool4_t mask, vfloat16m4_t maskedoff, vuint32m8_t src, size_t vl) {3687 return __riscv_vfncvt_f_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3688}3689 3690// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfncvt_x_f_w_i32mf2_rm_mu3691// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3692// CHECK-RV64-NEXT: entry:3693// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfncvt.x.f.w.mask.nxv1i32.nxv1f64.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x double> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)3694// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]3695//3696vint32mf2_t test_vfncvt_x_f_w_i32mf2_rm_mu(vbool64_t mask, vint32mf2_t maskedoff, vfloat64m1_t src, size_t vl) {3697 return __riscv_vfncvt_x_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3698}3699 3700// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfncvt_x_f_w_i32m1_rm_mu3701// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3702// CHECK-RV64-NEXT: entry:3703// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfncvt.x.f.w.mask.nxv2i32.nxv2f64.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x double> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)3704// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]3705//3706vint32m1_t test_vfncvt_x_f_w_i32m1_rm_mu(vbool32_t mask, vint32m1_t maskedoff, vfloat64m2_t src, size_t vl) {3707 return __riscv_vfncvt_x_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3708}3709 3710// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfncvt_x_f_w_i32m2_rm_mu3711// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3712// CHECK-RV64-NEXT: entry:3713// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfncvt.x.f.w.mask.nxv4i32.nxv4f64.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x double> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)3714// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]3715//3716vint32m2_t test_vfncvt_x_f_w_i32m2_rm_mu(vbool16_t mask, vint32m2_t maskedoff, vfloat64m4_t src, size_t vl) {3717 return __riscv_vfncvt_x_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3718}3719 3720// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfncvt_x_f_w_i32m4_rm_mu3721// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3722// CHECK-RV64-NEXT: entry:3723// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfncvt.x.f.w.mask.nxv8i32.nxv8f64.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x double> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)3724// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]3725//3726vint32m4_t test_vfncvt_x_f_w_i32m4_rm_mu(vbool8_t mask, vint32m4_t maskedoff, vfloat64m8_t src, size_t vl) {3727 return __riscv_vfncvt_x_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3728}3729 3730// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfncvt_xu_f_w_u32mf2_rm_mu3731// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3732// CHECK-RV64-NEXT: entry:3733// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i32.nxv1f64.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x double> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)3734// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]3735//3736vuint32mf2_t test_vfncvt_xu_f_w_u32mf2_rm_mu(vbool64_t mask, vuint32mf2_t maskedoff, vfloat64m1_t src, size_t vl) {3737 return __riscv_vfncvt_xu_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3738}3739 3740// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfncvt_xu_f_w_u32m1_rm_mu3741// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3742// CHECK-RV64-NEXT: entry:3743// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfncvt.xu.f.w.mask.nxv2i32.nxv2f64.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x double> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)3744// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]3745//3746vuint32m1_t test_vfncvt_xu_f_w_u32m1_rm_mu(vbool32_t mask, vuint32m1_t maskedoff, vfloat64m2_t src, size_t vl) {3747 return __riscv_vfncvt_xu_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3748}3749 3750// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfncvt_xu_f_w_u32m2_rm_mu3751// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3752// CHECK-RV64-NEXT: entry:3753// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfncvt.xu.f.w.mask.nxv4i32.nxv4f64.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x double> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)3754// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]3755//3756vuint32m2_t test_vfncvt_xu_f_w_u32m2_rm_mu(vbool16_t mask, vuint32m2_t maskedoff, vfloat64m4_t src, size_t vl) {3757 return __riscv_vfncvt_xu_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3758}3759 3760// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfncvt_xu_f_w_u32m4_rm_mu3761// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3762// CHECK-RV64-NEXT: entry:3763// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfncvt.xu.f.w.mask.nxv8i32.nxv8f64.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x double> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)3764// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]3765//3766vuint32m4_t test_vfncvt_xu_f_w_u32m4_rm_mu(vbool8_t mask, vuint32m4_t maskedoff, vfloat64m8_t src, size_t vl) {3767 return __riscv_vfncvt_xu_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3768}3769 3770// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfncvt_f_x_w_f32mf2_rm_mu3771// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3772// CHECK-RV64-NEXT: entry:3773// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.x.w.mask.nxv1f32.nxv1i64.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x i64> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)3774// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]3775//3776vfloat32mf2_t test_vfncvt_f_x_w_f32mf2_rm_mu(vbool64_t mask, vfloat32mf2_t maskedoff, vint64m1_t src, size_t vl) {3777 return __riscv_vfncvt_f_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3778}3779 3780// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfncvt_f_x_w_f32m1_rm_mu3781// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3782// CHECK-RV64-NEXT: entry:3783// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.x.w.mask.nxv2f32.nxv2i64.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x i64> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)3784// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]3785//3786vfloat32m1_t test_vfncvt_f_x_w_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t maskedoff, vint64m2_t src, size_t vl) {3787 return __riscv_vfncvt_f_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3788}3789 3790// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfncvt_f_x_w_f32m2_rm_mu3791// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3792// CHECK-RV64-NEXT: entry:3793// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.x.w.mask.nxv4f32.nxv4i64.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x i64> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)3794// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]3795//3796vfloat32m2_t test_vfncvt_f_x_w_f32m2_rm_mu(vbool16_t mask, vfloat32m2_t maskedoff, vint64m4_t src, size_t vl) {3797 return __riscv_vfncvt_f_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3798}3799 3800// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfncvt_f_x_w_f32m4_rm_mu3801// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3802// CHECK-RV64-NEXT: entry:3803// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.x.w.mask.nxv8f32.nxv8i64.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x i64> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)3804// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]3805//3806vfloat32m4_t test_vfncvt_f_x_w_f32m4_rm_mu(vbool8_t mask, vfloat32m4_t maskedoff, vint64m8_t src, size_t vl) {3807 return __riscv_vfncvt_f_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3808}3809 3810// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfncvt_f_xu_w_f32mf2_rm_mu3811// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3812// CHECK-RV64-NEXT: entry:3813// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.xu.w.mask.nxv1f32.nxv1i64.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x i64> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)3814// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]3815//3816vfloat32mf2_t test_vfncvt_f_xu_w_f32mf2_rm_mu(vbool64_t mask, vfloat32mf2_t maskedoff, vuint64m1_t src, size_t vl) {3817 return __riscv_vfncvt_f_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3818}3819 3820// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfncvt_f_xu_w_f32m1_rm_mu3821// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3822// CHECK-RV64-NEXT: entry:3823// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.xu.w.mask.nxv2f32.nxv2i64.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x i64> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)3824// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]3825//3826vfloat32m1_t test_vfncvt_f_xu_w_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t maskedoff, vuint64m2_t src, size_t vl) {3827 return __riscv_vfncvt_f_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3828}3829 3830// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfncvt_f_xu_w_f32m2_rm_mu3831// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3832// CHECK-RV64-NEXT: entry:3833// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.xu.w.mask.nxv4f32.nxv4i64.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x i64> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)3834// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]3835//3836vfloat32m2_t test_vfncvt_f_xu_w_f32m2_rm_mu(vbool16_t mask, vfloat32m2_t maskedoff, vuint64m4_t src, size_t vl) {3837 return __riscv_vfncvt_f_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3838}3839 3840// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfncvt_f_xu_w_f32m4_rm_mu3841// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3842// CHECK-RV64-NEXT: entry:3843// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.xu.w.mask.nxv8f32.nxv8i64.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x i64> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)3844// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]3845//3846vfloat32m4_t test_vfncvt_f_xu_w_f32m4_rm_mu(vbool8_t mask, vfloat32m4_t maskedoff, vuint64m8_t src, size_t vl) {3847 return __riscv_vfncvt_f_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);3848}3849 3850