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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 22// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \4// RUN:   -target-feature +zvfh -disable-O0-optnone  \5// RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \6// RUN:   FileCheck --check-prefix=CHECK-RV64 %s7 8#include <riscv_vector.h>9 10// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfwcvt_f_x_v_f16mf4_tu11// CHECK-RV64-SAME: (<vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {12// CHECK-RV64-NEXT:  entry:13// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half> [[MASKEDOFF]], <vscale x 1 x i8> [[SRC]], i64 [[VL]])14// CHECK-RV64-NEXT:    ret <vscale x 1 x half> [[TMP0]]15//16vfloat16mf4_t test_vfwcvt_f_x_v_f16mf4_tu(vfloat16mf4_t maskedoff, vint8mf8_t src, size_t vl) {17  return __riscv_vfwcvt_f_tu(maskedoff, src, vl);18}19 20// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfwcvt_f_x_v_f16mf2_tu21// CHECK-RV64-SAME: (<vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {22// CHECK-RV64-NEXT:  entry:23// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half> [[MASKEDOFF]], <vscale x 2 x i8> [[SRC]], i64 [[VL]])24// CHECK-RV64-NEXT:    ret <vscale x 2 x half> [[TMP0]]25//26vfloat16mf2_t test_vfwcvt_f_x_v_f16mf2_tu(vfloat16mf2_t maskedoff, vint8mf4_t src, size_t vl) {27  return __riscv_vfwcvt_f_tu(maskedoff, src, vl);28}29 30// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfwcvt_f_x_v_f16m1_tu31// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {32// CHECK-RV64-NEXT:  entry:33// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x i8> [[SRC]], i64 [[VL]])34// CHECK-RV64-NEXT:    ret <vscale x 4 x half> [[TMP0]]35//36vfloat16m1_t test_vfwcvt_f_x_v_f16m1_tu(vfloat16m1_t maskedoff, vint8mf2_t src, size_t vl) {37  return __riscv_vfwcvt_f_tu(maskedoff, src, vl);38}39 40// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfwcvt_f_x_v_f16m2_tu41// CHECK-RV64-SAME: (<vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {42// CHECK-RV64-NEXT:  entry:43// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half> [[MASKEDOFF]], <vscale x 8 x i8> [[SRC]], i64 [[VL]])44// CHECK-RV64-NEXT:    ret <vscale x 8 x half> [[TMP0]]45//46vfloat16m2_t test_vfwcvt_f_x_v_f16m2_tu(vfloat16m2_t maskedoff, vint8m1_t src, size_t vl) {47  return __riscv_vfwcvt_f_tu(maskedoff, src, vl);48}49 50// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfwcvt_f_x_v_f16m4_tu51// CHECK-RV64-SAME: (<vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {52// CHECK-RV64-NEXT:  entry:53// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half> [[MASKEDOFF]], <vscale x 16 x i8> [[SRC]], i64 [[VL]])54// CHECK-RV64-NEXT:    ret <vscale x 16 x half> [[TMP0]]55//56vfloat16m4_t test_vfwcvt_f_x_v_f16m4_tu(vfloat16m4_t maskedoff, vint8m2_t src, size_t vl) {57  return __riscv_vfwcvt_f_tu(maskedoff, src, vl);58}59 60// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfwcvt_f_x_v_f16m8_tu61// CHECK-RV64-SAME: (<vscale x 32 x half> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {62// CHECK-RV64-NEXT:  entry:63// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half> [[MASKEDOFF]], <vscale x 32 x i8> [[SRC]], i64 [[VL]])64// CHECK-RV64-NEXT:    ret <vscale x 32 x half> [[TMP0]]65//66vfloat16m8_t test_vfwcvt_f_x_v_f16m8_tu(vfloat16m8_t maskedoff, vint8m4_t src, size_t vl) {67  return __riscv_vfwcvt_f_tu(maskedoff, src, vl);68}69 70// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfwcvt_f_xu_v_f16mf4_tu71// CHECK-RV64-SAME: (<vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {72// CHECK-RV64-NEXT:  entry:73// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half> [[MASKEDOFF]], <vscale x 1 x i8> [[SRC]], i64 [[VL]])74// CHECK-RV64-NEXT:    ret <vscale x 1 x half> [[TMP0]]75//76vfloat16mf4_t test_vfwcvt_f_xu_v_f16mf4_tu(vfloat16mf4_t maskedoff, vuint8mf8_t src, size_t vl) {77  return __riscv_vfwcvt_f_tu(maskedoff, src, vl);78}79 80// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfwcvt_f_xu_v_f16mf2_tu81// CHECK-RV64-SAME: (<vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {82// CHECK-RV64-NEXT:  entry:83// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half> [[MASKEDOFF]], <vscale x 2 x i8> [[SRC]], i64 [[VL]])84// CHECK-RV64-NEXT:    ret <vscale x 2 x half> [[TMP0]]85//86vfloat16mf2_t test_vfwcvt_f_xu_v_f16mf2_tu(vfloat16mf2_t maskedoff, vuint8mf4_t src, size_t vl) {87  return __riscv_vfwcvt_f_tu(maskedoff, src, vl);88}89 90// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfwcvt_f_xu_v_f16m1_tu91// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {92// CHECK-RV64-NEXT:  entry:93// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x i8> [[SRC]], i64 [[VL]])94// CHECK-RV64-NEXT:    ret <vscale x 4 x half> [[TMP0]]95//96vfloat16m1_t test_vfwcvt_f_xu_v_f16m1_tu(vfloat16m1_t maskedoff, vuint8mf2_t src, size_t vl) {97  return __riscv_vfwcvt_f_tu(maskedoff, src, vl);98}99 100// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfwcvt_f_xu_v_f16m2_tu101// CHECK-RV64-SAME: (<vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {102// CHECK-RV64-NEXT:  entry:103// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half> [[MASKEDOFF]], <vscale x 8 x i8> [[SRC]], i64 [[VL]])104// CHECK-RV64-NEXT:    ret <vscale x 8 x half> [[TMP0]]105//106vfloat16m2_t test_vfwcvt_f_xu_v_f16m2_tu(vfloat16m2_t maskedoff, vuint8m1_t src, size_t vl) {107  return __riscv_vfwcvt_f_tu(maskedoff, src, vl);108}109 110// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfwcvt_f_xu_v_f16m4_tu111// CHECK-RV64-SAME: (<vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {112// CHECK-RV64-NEXT:  entry:113// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half> [[MASKEDOFF]], <vscale x 16 x i8> [[SRC]], i64 [[VL]])114// CHECK-RV64-NEXT:    ret <vscale x 16 x half> [[TMP0]]115//116vfloat16m4_t test_vfwcvt_f_xu_v_f16m4_tu(vfloat16m4_t maskedoff, vuint8m2_t src, size_t vl) {117  return __riscv_vfwcvt_f_tu(maskedoff, src, vl);118}119 120// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfwcvt_f_xu_v_f16m8_tu121// CHECK-RV64-SAME: (<vscale x 32 x half> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {122// CHECK-RV64-NEXT:  entry:123// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half> [[MASKEDOFF]], <vscale x 32 x i8> [[SRC]], i64 [[VL]])124// CHECK-RV64-NEXT:    ret <vscale x 32 x half> [[TMP0]]125//126vfloat16m8_t test_vfwcvt_f_xu_v_f16m8_tu(vfloat16m8_t maskedoff, vuint8m4_t src, size_t vl) {127  return __riscv_vfwcvt_f_tu(maskedoff, src, vl);128}129 130// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfwcvt_x_f_v_i32mf2_tu131// CHECK-RV64-SAME: (<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {132// CHECK-RV64-NEXT:  entry:133// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.x.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x half> [[SRC]], i64 7, i64 [[VL]])134// CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]135//136vint32mf2_t test_vfwcvt_x_f_v_i32mf2_tu(vint32mf2_t maskedoff, vfloat16mf4_t src, size_t vl) {137  return __riscv_vfwcvt_x_tu(maskedoff, src, vl);138}139 140// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfwcvt_x_f_v_i32m1_tu141// CHECK-RV64-SAME: (<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {142// CHECK-RV64-NEXT:  entry:143// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.x.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x half> [[SRC]], i64 7, i64 [[VL]])144// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]145//146vint32m1_t test_vfwcvt_x_f_v_i32m1_tu(vint32m1_t maskedoff, vfloat16mf2_t src, size_t vl) {147  return __riscv_vfwcvt_x_tu(maskedoff, src, vl);148}149 150// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfwcvt_x_f_v_i32m2_tu151// CHECK-RV64-SAME: (<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {152// CHECK-RV64-NEXT:  entry:153// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.x.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x half> [[SRC]], i64 7, i64 [[VL]])154// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]155//156vint32m2_t test_vfwcvt_x_f_v_i32m2_tu(vint32m2_t maskedoff, vfloat16m1_t src, size_t vl) {157  return __riscv_vfwcvt_x_tu(maskedoff, src, vl);158}159 160// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfwcvt_x_f_v_i32m4_tu161// CHECK-RV64-SAME: (<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {162// CHECK-RV64-NEXT:  entry:163// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.x.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x half> [[SRC]], i64 7, i64 [[VL]])164// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]165//166vint32m4_t test_vfwcvt_x_f_v_i32m4_tu(vint32m4_t maskedoff, vfloat16m2_t src, size_t vl) {167  return __riscv_vfwcvt_x_tu(maskedoff, src, vl);168}169 170// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfwcvt_x_f_v_i32m8_tu171// CHECK-RV64-SAME: (<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {172// CHECK-RV64-NEXT:  entry:173// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.x.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x half> [[SRC]], i64 7, i64 [[VL]])174// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]175//176vint32m8_t test_vfwcvt_x_f_v_i32m8_tu(vint32m8_t maskedoff, vfloat16m4_t src, size_t vl) {177  return __riscv_vfwcvt_x_tu(maskedoff, src, vl);178}179 180// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfwcvt_xu_f_v_u32mf2_tu181// CHECK-RV64-SAME: (<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {182// CHECK-RV64-NEXT:  entry:183// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.xu.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x half> [[SRC]], i64 7, i64 [[VL]])184// CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]185//186vuint32mf2_t test_vfwcvt_xu_f_v_u32mf2_tu(vuint32mf2_t maskedoff, vfloat16mf4_t src, size_t vl) {187  return __riscv_vfwcvt_xu_tu(maskedoff, src, vl);188}189 190// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfwcvt_xu_f_v_u32m1_tu191// CHECK-RV64-SAME: (<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {192// CHECK-RV64-NEXT:  entry:193// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.xu.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x half> [[SRC]], i64 7, i64 [[VL]])194// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]195//196vuint32m1_t test_vfwcvt_xu_f_v_u32m1_tu(vuint32m1_t maskedoff, vfloat16mf2_t src, size_t vl) {197  return __riscv_vfwcvt_xu_tu(maskedoff, src, vl);198}199 200// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfwcvt_xu_f_v_u32m2_tu201// CHECK-RV64-SAME: (<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {202// CHECK-RV64-NEXT:  entry:203// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.xu.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x half> [[SRC]], i64 7, i64 [[VL]])204// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]205//206vuint32m2_t test_vfwcvt_xu_f_v_u32m2_tu(vuint32m2_t maskedoff, vfloat16m1_t src, size_t vl) {207  return __riscv_vfwcvt_xu_tu(maskedoff, src, vl);208}209 210// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfwcvt_xu_f_v_u32m4_tu211// CHECK-RV64-SAME: (<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {212// CHECK-RV64-NEXT:  entry:213// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.xu.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x half> [[SRC]], i64 7, i64 [[VL]])214// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]215//216vuint32m4_t test_vfwcvt_xu_f_v_u32m4_tu(vuint32m4_t maskedoff, vfloat16m2_t src, size_t vl) {217  return __riscv_vfwcvt_xu_tu(maskedoff, src, vl);218}219 220// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfwcvt_xu_f_v_u32m8_tu221// CHECK-RV64-SAME: (<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {222// CHECK-RV64-NEXT:  entry:223// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.xu.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x half> [[SRC]], i64 7, i64 [[VL]])224// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]225//226vuint32m8_t test_vfwcvt_xu_f_v_u32m8_tu(vuint32m8_t maskedoff, vfloat16m4_t src, size_t vl) {227  return __riscv_vfwcvt_xu_tu(maskedoff, src, vl);228}229 230// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwcvt_f_x_v_f32mf2_tu231// CHECK-RV64-SAME: (<vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {232// CHECK-RV64-NEXT:  entry:233// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.x.v.nxv1f32.nxv1i16.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x i16> [[SRC]], i64 [[VL]])234// CHECK-RV64-NEXT:    ret <vscale x 1 x float> [[TMP0]]235//236vfloat32mf2_t test_vfwcvt_f_x_v_f32mf2_tu(vfloat32mf2_t maskedoff, vint16mf4_t src, size_t vl) {237  return __riscv_vfwcvt_f_tu(maskedoff, src, vl);238}239 240// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwcvt_f_x_v_f32m1_tu241// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {242// CHECK-RV64-NEXT:  entry:243// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.x.v.nxv2f32.nxv2i16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x i16> [[SRC]], i64 [[VL]])244// CHECK-RV64-NEXT:    ret <vscale x 2 x float> [[TMP0]]245//246vfloat32m1_t test_vfwcvt_f_x_v_f32m1_tu(vfloat32m1_t maskedoff, vint16mf2_t src, size_t vl) {247  return __riscv_vfwcvt_f_tu(maskedoff, src, vl);248}249 250// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwcvt_f_x_v_f32m2_tu251// CHECK-RV64-SAME: (<vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {252// CHECK-RV64-NEXT:  entry:253// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.x.v.nxv4f32.nxv4i16.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x i16> [[SRC]], i64 [[VL]])254// CHECK-RV64-NEXT:    ret <vscale x 4 x float> [[TMP0]]255//256vfloat32m2_t test_vfwcvt_f_x_v_f32m2_tu(vfloat32m2_t maskedoff, vint16m1_t src, size_t vl) {257  return __riscv_vfwcvt_f_tu(maskedoff, src, vl);258}259 260// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwcvt_f_x_v_f32m4_tu261// CHECK-RV64-SAME: (<vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {262// CHECK-RV64-NEXT:  entry:263// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.x.v.nxv8f32.nxv8i16.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x i16> [[SRC]], i64 [[VL]])264// CHECK-RV64-NEXT:    ret <vscale x 8 x float> [[TMP0]]265//266vfloat32m4_t test_vfwcvt_f_x_v_f32m4_tu(vfloat32m4_t maskedoff, vint16m2_t src, size_t vl) {267  return __riscv_vfwcvt_f_tu(maskedoff, src, vl);268}269 270// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwcvt_f_x_v_f32m8_tu271// CHECK-RV64-SAME: (<vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {272// CHECK-RV64-NEXT:  entry:273// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.x.v.nxv16f32.nxv16i16.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x i16> [[SRC]], i64 [[VL]])274// CHECK-RV64-NEXT:    ret <vscale x 16 x float> [[TMP0]]275//276vfloat32m8_t test_vfwcvt_f_x_v_f32m8_tu(vfloat32m8_t maskedoff, vint16m4_t src, size_t vl) {277  return __riscv_vfwcvt_f_tu(maskedoff, src, vl);278}279 280// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwcvt_f_xu_v_f32mf2_tu281// CHECK-RV64-SAME: (<vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {282// CHECK-RV64-NEXT:  entry:283// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv1f32.nxv1i16.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x i16> [[SRC]], i64 [[VL]])284// CHECK-RV64-NEXT:    ret <vscale x 1 x float> [[TMP0]]285//286vfloat32mf2_t test_vfwcvt_f_xu_v_f32mf2_tu(vfloat32mf2_t maskedoff, vuint16mf4_t src, size_t vl) {287  return __riscv_vfwcvt_f_tu(maskedoff, src, vl);288}289 290// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwcvt_f_xu_v_f32m1_tu291// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {292// CHECK-RV64-NEXT:  entry:293// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv2f32.nxv2i16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x i16> [[SRC]], i64 [[VL]])294// CHECK-RV64-NEXT:    ret <vscale x 2 x float> [[TMP0]]295//296vfloat32m1_t test_vfwcvt_f_xu_v_f32m1_tu(vfloat32m1_t maskedoff, vuint16mf2_t src, size_t vl) {297  return __riscv_vfwcvt_f_tu(maskedoff, src, vl);298}299 300// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwcvt_f_xu_v_f32m2_tu301// CHECK-RV64-SAME: (<vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {302// CHECK-RV64-NEXT:  entry:303// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv4f32.nxv4i16.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x i16> [[SRC]], i64 [[VL]])304// CHECK-RV64-NEXT:    ret <vscale x 4 x float> [[TMP0]]305//306vfloat32m2_t test_vfwcvt_f_xu_v_f32m2_tu(vfloat32m2_t maskedoff, vuint16m1_t src, size_t vl) {307  return __riscv_vfwcvt_f_tu(maskedoff, src, vl);308}309 310// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwcvt_f_xu_v_f32m4_tu311// CHECK-RV64-SAME: (<vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {312// CHECK-RV64-NEXT:  entry:313// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv8f32.nxv8i16.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x i16> [[SRC]], i64 [[VL]])314// CHECK-RV64-NEXT:    ret <vscale x 8 x float> [[TMP0]]315//316vfloat32m4_t test_vfwcvt_f_xu_v_f32m4_tu(vfloat32m4_t maskedoff, vuint16m2_t src, size_t vl) {317  return __riscv_vfwcvt_f_tu(maskedoff, src, vl);318}319 320// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwcvt_f_xu_v_f32m8_tu321// CHECK-RV64-SAME: (<vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {322// CHECK-RV64-NEXT:  entry:323// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv16f32.nxv16i16.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x i16> [[SRC]], i64 [[VL]])324// CHECK-RV64-NEXT:    ret <vscale x 16 x float> [[TMP0]]325//326vfloat32m8_t test_vfwcvt_f_xu_v_f32m8_tu(vfloat32m8_t maskedoff, vuint16m4_t src, size_t vl) {327  return __riscv_vfwcvt_f_tu(maskedoff, src, vl);328}329 330// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfwcvt_x_f_v_i64m1_tu331// CHECK-RV64-SAME: (<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {332// CHECK-RV64-NEXT:  entry:333// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv1i64.nxv1f32.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x float> [[SRC]], i64 7, i64 [[VL]])334// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]335//336vint64m1_t test_vfwcvt_x_f_v_i64m1_tu(vint64m1_t maskedoff, vfloat32mf2_t src, size_t vl) {337  return __riscv_vfwcvt_x_tu(maskedoff, src, vl);338}339 340// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfwcvt_x_f_v_i64m2_tu341// CHECK-RV64-SAME: (<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {342// CHECK-RV64-NEXT:  entry:343// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv2i64.nxv2f32.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x float> [[SRC]], i64 7, i64 [[VL]])344// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]345//346vint64m2_t test_vfwcvt_x_f_v_i64m2_tu(vint64m2_t maskedoff, vfloat32m1_t src, size_t vl) {347  return __riscv_vfwcvt_x_tu(maskedoff, src, vl);348}349 350// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfwcvt_x_f_v_i64m4_tu351// CHECK-RV64-SAME: (<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {352// CHECK-RV64-NEXT:  entry:353// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv4i64.nxv4f32.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x float> [[SRC]], i64 7, i64 [[VL]])354// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]355//356vint64m4_t test_vfwcvt_x_f_v_i64m4_tu(vint64m4_t maskedoff, vfloat32m2_t src, size_t vl) {357  return __riscv_vfwcvt_x_tu(maskedoff, src, vl);358}359 360// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfwcvt_x_f_v_i64m8_tu361// CHECK-RV64-SAME: (<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {362// CHECK-RV64-NEXT:  entry:363// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv8i64.nxv8f32.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x float> [[SRC]], i64 7, i64 [[VL]])364// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]365//366vint64m8_t test_vfwcvt_x_f_v_i64m8_tu(vint64m8_t maskedoff, vfloat32m4_t src, size_t vl) {367  return __riscv_vfwcvt_x_tu(maskedoff, src, vl);368}369 370// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfwcvt_xu_f_v_u64m1_tu371// CHECK-RV64-SAME: (<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {372// CHECK-RV64-NEXT:  entry:373// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv1i64.nxv1f32.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x float> [[SRC]], i64 7, i64 [[VL]])374// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]375//376vuint64m1_t test_vfwcvt_xu_f_v_u64m1_tu(vuint64m1_t maskedoff, vfloat32mf2_t src, size_t vl) {377  return __riscv_vfwcvt_xu_tu(maskedoff, src, vl);378}379 380// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfwcvt_xu_f_v_u64m2_tu381// CHECK-RV64-SAME: (<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {382// CHECK-RV64-NEXT:  entry:383// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv2i64.nxv2f32.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x float> [[SRC]], i64 7, i64 [[VL]])384// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]385//386vuint64m2_t test_vfwcvt_xu_f_v_u64m2_tu(vuint64m2_t maskedoff, vfloat32m1_t src, size_t vl) {387  return __riscv_vfwcvt_xu_tu(maskedoff, src, vl);388}389 390// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfwcvt_xu_f_v_u64m4_tu391// CHECK-RV64-SAME: (<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {392// CHECK-RV64-NEXT:  entry:393// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv4i64.nxv4f32.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x float> [[SRC]], i64 7, i64 [[VL]])394// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]395//396vuint64m4_t test_vfwcvt_xu_f_v_u64m4_tu(vuint64m4_t maskedoff, vfloat32m2_t src, size_t vl) {397  return __riscv_vfwcvt_xu_tu(maskedoff, src, vl);398}399 400// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfwcvt_xu_f_v_u64m8_tu401// CHECK-RV64-SAME: (<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {402// CHECK-RV64-NEXT:  entry:403// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv8i64.nxv8f32.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x float> [[SRC]], i64 7, i64 [[VL]])404// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]405//406vuint64m8_t test_vfwcvt_xu_f_v_u64m8_tu(vuint64m8_t maskedoff, vfloat32m4_t src, size_t vl) {407  return __riscv_vfwcvt_xu_tu(maskedoff, src, vl);408}409 410// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwcvt_f_x_v_f64m1_tu411// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {412// CHECK-RV64-NEXT:  entry:413// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.x.v.nxv1f64.nxv1i32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x i32> [[SRC]], i64 [[VL]])414// CHECK-RV64-NEXT:    ret <vscale x 1 x double> [[TMP0]]415//416vfloat64m1_t test_vfwcvt_f_x_v_f64m1_tu(vfloat64m1_t maskedoff, vint32mf2_t src, size_t vl) {417  return __riscv_vfwcvt_f_tu(maskedoff, src, vl);418}419 420// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfwcvt_f_x_v_f64m2_tu421// CHECK-RV64-SAME: (<vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {422// CHECK-RV64-NEXT:  entry:423// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.x.v.nxv2f64.nxv2i32.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x i32> [[SRC]], i64 [[VL]])424// CHECK-RV64-NEXT:    ret <vscale x 2 x double> [[TMP0]]425//426vfloat64m2_t test_vfwcvt_f_x_v_f64m2_tu(vfloat64m2_t maskedoff, vint32m1_t src, size_t vl) {427  return __riscv_vfwcvt_f_tu(maskedoff, src, vl);428}429 430// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfwcvt_f_x_v_f64m4_tu431// CHECK-RV64-SAME: (<vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {432// CHECK-RV64-NEXT:  entry:433// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.x.v.nxv4f64.nxv4i32.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x i32> [[SRC]], i64 [[VL]])434// CHECK-RV64-NEXT:    ret <vscale x 4 x double> [[TMP0]]435//436vfloat64m4_t test_vfwcvt_f_x_v_f64m4_tu(vfloat64m4_t maskedoff, vint32m2_t src, size_t vl) {437  return __riscv_vfwcvt_f_tu(maskedoff, src, vl);438}439 440// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfwcvt_f_x_v_f64m8_tu441// CHECK-RV64-SAME: (<vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {442// CHECK-RV64-NEXT:  entry:443// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.x.v.nxv8f64.nxv8i32.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x i32> [[SRC]], i64 [[VL]])444// CHECK-RV64-NEXT:    ret <vscale x 8 x double> [[TMP0]]445//446vfloat64m8_t test_vfwcvt_f_x_v_f64m8_tu(vfloat64m8_t maskedoff, vint32m4_t src, size_t vl) {447  return __riscv_vfwcvt_f_tu(maskedoff, src, vl);448}449 450// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwcvt_f_xu_v_f64m1_tu451// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {452// CHECK-RV64-NEXT:  entry:453// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.xu.v.nxv1f64.nxv1i32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x i32> [[SRC]], i64 [[VL]])454// CHECK-RV64-NEXT:    ret <vscale x 1 x double> [[TMP0]]455//456vfloat64m1_t test_vfwcvt_f_xu_v_f64m1_tu(vfloat64m1_t maskedoff, vuint32mf2_t src, size_t vl) {457  return __riscv_vfwcvt_f_tu(maskedoff, src, vl);458}459 460// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfwcvt_f_xu_v_f64m2_tu461// CHECK-RV64-SAME: (<vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {462// CHECK-RV64-NEXT:  entry:463// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.xu.v.nxv2f64.nxv2i32.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x i32> [[SRC]], i64 [[VL]])464// CHECK-RV64-NEXT:    ret <vscale x 2 x double> [[TMP0]]465//466vfloat64m2_t test_vfwcvt_f_xu_v_f64m2_tu(vfloat64m2_t maskedoff, vuint32m1_t src, size_t vl) {467  return __riscv_vfwcvt_f_tu(maskedoff, src, vl);468}469 470// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfwcvt_f_xu_v_f64m4_tu471// CHECK-RV64-SAME: (<vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {472// CHECK-RV64-NEXT:  entry:473// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.xu.v.nxv4f64.nxv4i32.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x i32> [[SRC]], i64 [[VL]])474// CHECK-RV64-NEXT:    ret <vscale x 4 x double> [[TMP0]]475//476vfloat64m4_t test_vfwcvt_f_xu_v_f64m4_tu(vfloat64m4_t maskedoff, vuint32m2_t src, size_t vl) {477  return __riscv_vfwcvt_f_tu(maskedoff, src, vl);478}479 480// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfwcvt_f_xu_v_f64m8_tu481// CHECK-RV64-SAME: (<vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {482// CHECK-RV64-NEXT:  entry:483// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.xu.v.nxv8f64.nxv8i32.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x i32> [[SRC]], i64 [[VL]])484// CHECK-RV64-NEXT:    ret <vscale x 8 x double> [[TMP0]]485//486vfloat64m8_t test_vfwcvt_f_xu_v_f64m8_tu(vfloat64m8_t maskedoff, vuint32m4_t src, size_t vl) {487  return __riscv_vfwcvt_f_tu(maskedoff, src, vl);488}489 490// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfwcvt_f_x_v_f16mf4_tum491// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {492// CHECK-RV64-NEXT:  entry:493// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.mask.nxv1f16.nxv1i8.i64(<vscale x 1 x half> [[MASKEDOFF]], <vscale x 1 x i8> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)494// CHECK-RV64-NEXT:    ret <vscale x 1 x half> [[TMP0]]495//496vfloat16mf4_t test_vfwcvt_f_x_v_f16mf4_tum(vbool64_t mask, vfloat16mf4_t maskedoff, vint8mf8_t src, size_t vl) {497  return __riscv_vfwcvt_f_tum(mask, maskedoff, src, vl);498}499 500// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfwcvt_f_x_v_f16mf2_tum501// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {502// CHECK-RV64-NEXT:  entry:503// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.mask.nxv2f16.nxv2i8.i64(<vscale x 2 x half> [[MASKEDOFF]], <vscale x 2 x i8> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)504// CHECK-RV64-NEXT:    ret <vscale x 2 x half> [[TMP0]]505//506vfloat16mf2_t test_vfwcvt_f_x_v_f16mf2_tum(vbool32_t mask, vfloat16mf2_t maskedoff, vint8mf4_t src, size_t vl) {507  return __riscv_vfwcvt_f_tum(mask, maskedoff, src, vl);508}509 510// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfwcvt_f_x_v_f16m1_tum511// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {512// CHECK-RV64-NEXT:  entry:513// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.mask.nxv4f16.nxv4i8.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x i8> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)514// CHECK-RV64-NEXT:    ret <vscale x 4 x half> [[TMP0]]515//516vfloat16m1_t test_vfwcvt_f_x_v_f16m1_tum(vbool16_t mask, vfloat16m1_t maskedoff, vint8mf2_t src, size_t vl) {517  return __riscv_vfwcvt_f_tum(mask, maskedoff, src, vl);518}519 520// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfwcvt_f_x_v_f16m2_tum521// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {522// CHECK-RV64-NEXT:  entry:523// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.mask.nxv8f16.nxv8i8.i64(<vscale x 8 x half> [[MASKEDOFF]], <vscale x 8 x i8> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)524// CHECK-RV64-NEXT:    ret <vscale x 8 x half> [[TMP0]]525//526vfloat16m2_t test_vfwcvt_f_x_v_f16m2_tum(vbool8_t mask, vfloat16m2_t maskedoff, vint8m1_t src, size_t vl) {527  return __riscv_vfwcvt_f_tum(mask, maskedoff, src, vl);528}529 530// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfwcvt_f_x_v_f16m4_tum531// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {532// CHECK-RV64-NEXT:  entry:533// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.mask.nxv16f16.nxv16i8.i64(<vscale x 16 x half> [[MASKEDOFF]], <vscale x 16 x i8> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)534// CHECK-RV64-NEXT:    ret <vscale x 16 x half> [[TMP0]]535//536vfloat16m4_t test_vfwcvt_f_x_v_f16m4_tum(vbool4_t mask, vfloat16m4_t maskedoff, vint8m2_t src, size_t vl) {537  return __riscv_vfwcvt_f_tum(mask, maskedoff, src, vl);538}539 540// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfwcvt_f_x_v_f16m8_tum541// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {542// CHECK-RV64-NEXT:  entry:543// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.mask.nxv32f16.nxv32i8.i64(<vscale x 32 x half> [[MASKEDOFF]], <vscale x 32 x i8> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2)544// CHECK-RV64-NEXT:    ret <vscale x 32 x half> [[TMP0]]545//546vfloat16m8_t test_vfwcvt_f_x_v_f16m8_tum(vbool2_t mask, vfloat16m8_t maskedoff, vint8m4_t src, size_t vl) {547  return __riscv_vfwcvt_f_tum(mask, maskedoff, src, vl);548}549 550// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfwcvt_f_xu_v_f16mf4_tum551// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {552// CHECK-RV64-NEXT:  entry:553// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv1f16.nxv1i8.i64(<vscale x 1 x half> [[MASKEDOFF]], <vscale x 1 x i8> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)554// CHECK-RV64-NEXT:    ret <vscale x 1 x half> [[TMP0]]555//556vfloat16mf4_t test_vfwcvt_f_xu_v_f16mf4_tum(vbool64_t mask, vfloat16mf4_t maskedoff, vuint8mf8_t src, size_t vl) {557  return __riscv_vfwcvt_f_tum(mask, maskedoff, src, vl);558}559 560// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfwcvt_f_xu_v_f16mf2_tum561// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {562// CHECK-RV64-NEXT:  entry:563// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv2f16.nxv2i8.i64(<vscale x 2 x half> [[MASKEDOFF]], <vscale x 2 x i8> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)564// CHECK-RV64-NEXT:    ret <vscale x 2 x half> [[TMP0]]565//566vfloat16mf2_t test_vfwcvt_f_xu_v_f16mf2_tum(vbool32_t mask, vfloat16mf2_t maskedoff, vuint8mf4_t src, size_t vl) {567  return __riscv_vfwcvt_f_tum(mask, maskedoff, src, vl);568}569 570// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfwcvt_f_xu_v_f16m1_tum571// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {572// CHECK-RV64-NEXT:  entry:573// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv4f16.nxv4i8.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x i8> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)574// CHECK-RV64-NEXT:    ret <vscale x 4 x half> [[TMP0]]575//576vfloat16m1_t test_vfwcvt_f_xu_v_f16m1_tum(vbool16_t mask, vfloat16m1_t maskedoff, vuint8mf2_t src, size_t vl) {577  return __riscv_vfwcvt_f_tum(mask, maskedoff, src, vl);578}579 580// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfwcvt_f_xu_v_f16m2_tum581// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {582// CHECK-RV64-NEXT:  entry:583// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv8f16.nxv8i8.i64(<vscale x 8 x half> [[MASKEDOFF]], <vscale x 8 x i8> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)584// CHECK-RV64-NEXT:    ret <vscale x 8 x half> [[TMP0]]585//586vfloat16m2_t test_vfwcvt_f_xu_v_f16m2_tum(vbool8_t mask, vfloat16m2_t maskedoff, vuint8m1_t src, size_t vl) {587  return __riscv_vfwcvt_f_tum(mask, maskedoff, src, vl);588}589 590// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfwcvt_f_xu_v_f16m4_tum591// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {592// CHECK-RV64-NEXT:  entry:593// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv16f16.nxv16i8.i64(<vscale x 16 x half> [[MASKEDOFF]], <vscale x 16 x i8> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)594// CHECK-RV64-NEXT:    ret <vscale x 16 x half> [[TMP0]]595//596vfloat16m4_t test_vfwcvt_f_xu_v_f16m4_tum(vbool4_t mask, vfloat16m4_t maskedoff, vuint8m2_t src, size_t vl) {597  return __riscv_vfwcvt_f_tum(mask, maskedoff, src, vl);598}599 600// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfwcvt_f_xu_v_f16m8_tum601// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {602// CHECK-RV64-NEXT:  entry:603// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv32f16.nxv32i8.i64(<vscale x 32 x half> [[MASKEDOFF]], <vscale x 32 x i8> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2)604// CHECK-RV64-NEXT:    ret <vscale x 32 x half> [[TMP0]]605//606vfloat16m8_t test_vfwcvt_f_xu_v_f16m8_tum(vbool2_t mask, vfloat16m8_t maskedoff, vuint8m4_t src, size_t vl) {607  return __riscv_vfwcvt_f_tum(mask, maskedoff, src, vl);608}609 610// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfwcvt_x_f_v_i32mf2_tum611// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {612// CHECK-RV64-NEXT:  entry:613// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.x.f.v.mask.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x half> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)614// CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]615//616vint32mf2_t test_vfwcvt_x_f_v_i32mf2_tum(vbool64_t mask, vint32mf2_t maskedoff, vfloat16mf4_t src, size_t vl) {617  return __riscv_vfwcvt_x_tum(mask, maskedoff, src, vl);618}619 620// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfwcvt_x_f_v_i32m1_tum621// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {622// CHECK-RV64-NEXT:  entry:623// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.x.f.v.mask.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x half> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)624// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]625//626vint32m1_t test_vfwcvt_x_f_v_i32m1_tum(vbool32_t mask, vint32m1_t maskedoff, vfloat16mf2_t src, size_t vl) {627  return __riscv_vfwcvt_x_tum(mask, maskedoff, src, vl);628}629 630// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfwcvt_x_f_v_i32m2_tum631// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {632// CHECK-RV64-NEXT:  entry:633// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.x.f.v.mask.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x half> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)634// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]635//636vint32m2_t test_vfwcvt_x_f_v_i32m2_tum(vbool16_t mask, vint32m2_t maskedoff, vfloat16m1_t src, size_t vl) {637  return __riscv_vfwcvt_x_tum(mask, maskedoff, src, vl);638}639 640// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfwcvt_x_f_v_i32m4_tum641// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {642// CHECK-RV64-NEXT:  entry:643// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.x.f.v.mask.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x half> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)644// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]645//646vint32m4_t test_vfwcvt_x_f_v_i32m4_tum(vbool8_t mask, vint32m4_t maskedoff, vfloat16m2_t src, size_t vl) {647  return __riscv_vfwcvt_x_tum(mask, maskedoff, src, vl);648}649 650// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfwcvt_x_f_v_i32m8_tum651// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {652// CHECK-RV64-NEXT:  entry:653// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.x.f.v.mask.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x half> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)654// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]655//656vint32m8_t test_vfwcvt_x_f_v_i32m8_tum(vbool4_t mask, vint32m8_t maskedoff, vfloat16m4_t src, size_t vl) {657  return __riscv_vfwcvt_x_tum(mask, maskedoff, src, vl);658}659 660// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfwcvt_xu_f_v_u32mf2_tum661// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {662// CHECK-RV64-NEXT:  entry:663// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x half> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)664// CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]665//666vuint32mf2_t test_vfwcvt_xu_f_v_u32mf2_tum(vbool64_t mask, vuint32mf2_t maskedoff, vfloat16mf4_t src, size_t vl) {667  return __riscv_vfwcvt_xu_tum(mask, maskedoff, src, vl);668}669 670// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfwcvt_xu_f_v_u32m1_tum671// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {672// CHECK-RV64-NEXT:  entry:673// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x half> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)674// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]675//676vuint32m1_t test_vfwcvt_xu_f_v_u32m1_tum(vbool32_t mask, vuint32m1_t maskedoff, vfloat16mf2_t src, size_t vl) {677  return __riscv_vfwcvt_xu_tum(mask, maskedoff, src, vl);678}679 680// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfwcvt_xu_f_v_u32m2_tum681// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {682// CHECK-RV64-NEXT:  entry:683// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x half> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)684// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]685//686vuint32m2_t test_vfwcvt_xu_f_v_u32m2_tum(vbool16_t mask, vuint32m2_t maskedoff, vfloat16m1_t src, size_t vl) {687  return __riscv_vfwcvt_xu_tum(mask, maskedoff, src, vl);688}689 690// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfwcvt_xu_f_v_u32m4_tum691// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {692// CHECK-RV64-NEXT:  entry:693// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x half> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)694// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]695//696vuint32m4_t test_vfwcvt_xu_f_v_u32m4_tum(vbool8_t mask, vuint32m4_t maskedoff, vfloat16m2_t src, size_t vl) {697  return __riscv_vfwcvt_xu_tum(mask, maskedoff, src, vl);698}699 700// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfwcvt_xu_f_v_u32m8_tum701// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {702// CHECK-RV64-NEXT:  entry:703// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x half> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)704// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]705//706vuint32m8_t test_vfwcvt_xu_f_v_u32m8_tum(vbool4_t mask, vuint32m8_t maskedoff, vfloat16m4_t src, size_t vl) {707  return __riscv_vfwcvt_xu_tum(mask, maskedoff, src, vl);708}709 710// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwcvt_f_x_v_f32mf2_tum711// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {712// CHECK-RV64-NEXT:  entry:713// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.x.v.mask.nxv1f32.nxv1i16.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x i16> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)714// CHECK-RV64-NEXT:    ret <vscale x 1 x float> [[TMP0]]715//716vfloat32mf2_t test_vfwcvt_f_x_v_f32mf2_tum(vbool64_t mask, vfloat32mf2_t maskedoff, vint16mf4_t src, size_t vl) {717  return __riscv_vfwcvt_f_tum(mask, maskedoff, src, vl);718}719 720// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwcvt_f_x_v_f32m1_tum721// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {722// CHECK-RV64-NEXT:  entry:723// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.x.v.mask.nxv2f32.nxv2i16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x i16> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)724// CHECK-RV64-NEXT:    ret <vscale x 2 x float> [[TMP0]]725//726vfloat32m1_t test_vfwcvt_f_x_v_f32m1_tum(vbool32_t mask, vfloat32m1_t maskedoff, vint16mf2_t src, size_t vl) {727  return __riscv_vfwcvt_f_tum(mask, maskedoff, src, vl);728}729 730// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwcvt_f_x_v_f32m2_tum731// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {732// CHECK-RV64-NEXT:  entry:733// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.x.v.mask.nxv4f32.nxv4i16.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x i16> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)734// CHECK-RV64-NEXT:    ret <vscale x 4 x float> [[TMP0]]735//736vfloat32m2_t test_vfwcvt_f_x_v_f32m2_tum(vbool16_t mask, vfloat32m2_t maskedoff, vint16m1_t src, size_t vl) {737  return __riscv_vfwcvt_f_tum(mask, maskedoff, src, vl);738}739 740// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwcvt_f_x_v_f32m4_tum741// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {742// CHECK-RV64-NEXT:  entry:743// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.x.v.mask.nxv8f32.nxv8i16.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x i16> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)744// CHECK-RV64-NEXT:    ret <vscale x 8 x float> [[TMP0]]745//746vfloat32m4_t test_vfwcvt_f_x_v_f32m4_tum(vbool8_t mask, vfloat32m4_t maskedoff, vint16m2_t src, size_t vl) {747  return __riscv_vfwcvt_f_tum(mask, maskedoff, src, vl);748}749 750// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwcvt_f_x_v_f32m8_tum751// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {752// CHECK-RV64-NEXT:  entry:753// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.x.v.mask.nxv16f32.nxv16i16.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x i16> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)754// CHECK-RV64-NEXT:    ret <vscale x 16 x float> [[TMP0]]755//756vfloat32m8_t test_vfwcvt_f_x_v_f32m8_tum(vbool4_t mask, vfloat32m8_t maskedoff, vint16m4_t src, size_t vl) {757  return __riscv_vfwcvt_f_tum(mask, maskedoff, src, vl);758}759 760// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwcvt_f_xu_v_f32mf2_tum761// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {762// CHECK-RV64-NEXT:  entry:763// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv1f32.nxv1i16.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x i16> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)764// CHECK-RV64-NEXT:    ret <vscale x 1 x float> [[TMP0]]765//766vfloat32mf2_t test_vfwcvt_f_xu_v_f32mf2_tum(vbool64_t mask, vfloat32mf2_t maskedoff, vuint16mf4_t src, size_t vl) {767  return __riscv_vfwcvt_f_tum(mask, maskedoff, src, vl);768}769 770// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwcvt_f_xu_v_f32m1_tum771// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {772// CHECK-RV64-NEXT:  entry:773// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv2f32.nxv2i16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x i16> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)774// CHECK-RV64-NEXT:    ret <vscale x 2 x float> [[TMP0]]775//776vfloat32m1_t test_vfwcvt_f_xu_v_f32m1_tum(vbool32_t mask, vfloat32m1_t maskedoff, vuint16mf2_t src, size_t vl) {777  return __riscv_vfwcvt_f_tum(mask, maskedoff, src, vl);778}779 780// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwcvt_f_xu_v_f32m2_tum781// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {782// CHECK-RV64-NEXT:  entry:783// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv4f32.nxv4i16.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x i16> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)784// CHECK-RV64-NEXT:    ret <vscale x 4 x float> [[TMP0]]785//786vfloat32m2_t test_vfwcvt_f_xu_v_f32m2_tum(vbool16_t mask, vfloat32m2_t maskedoff, vuint16m1_t src, size_t vl) {787  return __riscv_vfwcvt_f_tum(mask, maskedoff, src, vl);788}789 790// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwcvt_f_xu_v_f32m4_tum791// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {792// CHECK-RV64-NEXT:  entry:793// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv8f32.nxv8i16.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x i16> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)794// CHECK-RV64-NEXT:    ret <vscale x 8 x float> [[TMP0]]795//796vfloat32m4_t test_vfwcvt_f_xu_v_f32m4_tum(vbool8_t mask, vfloat32m4_t maskedoff, vuint16m2_t src, size_t vl) {797  return __riscv_vfwcvt_f_tum(mask, maskedoff, src, vl);798}799 800// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwcvt_f_xu_v_f32m8_tum801// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {802// CHECK-RV64-NEXT:  entry:803// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv16f32.nxv16i16.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x i16> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)804// CHECK-RV64-NEXT:    ret <vscale x 16 x float> [[TMP0]]805//806vfloat32m8_t test_vfwcvt_f_xu_v_f32m8_tum(vbool4_t mask, vfloat32m8_t maskedoff, vuint16m4_t src, size_t vl) {807  return __riscv_vfwcvt_f_tum(mask, maskedoff, src, vl);808}809 810// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfwcvt_x_f_v_i64m1_tum811// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {812// CHECK-RV64-NEXT:  entry:813// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.x.f.v.mask.nxv1i64.nxv1f32.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x float> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)814// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]815//816vint64m1_t test_vfwcvt_x_f_v_i64m1_tum(vbool64_t mask, vint64m1_t maskedoff, vfloat32mf2_t src, size_t vl) {817  return __riscv_vfwcvt_x_tum(mask, maskedoff, src, vl);818}819 820// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfwcvt_x_f_v_i64m2_tum821// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {822// CHECK-RV64-NEXT:  entry:823// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.x.f.v.mask.nxv2i64.nxv2f32.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x float> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)824// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]825//826vint64m2_t test_vfwcvt_x_f_v_i64m2_tum(vbool32_t mask, vint64m2_t maskedoff, vfloat32m1_t src, size_t vl) {827  return __riscv_vfwcvt_x_tum(mask, maskedoff, src, vl);828}829 830// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfwcvt_x_f_v_i64m4_tum831// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {832// CHECK-RV64-NEXT:  entry:833// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.x.f.v.mask.nxv4i64.nxv4f32.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x float> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)834// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]835//836vint64m4_t test_vfwcvt_x_f_v_i64m4_tum(vbool16_t mask, vint64m4_t maskedoff, vfloat32m2_t src, size_t vl) {837  return __riscv_vfwcvt_x_tum(mask, maskedoff, src, vl);838}839 840// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfwcvt_x_f_v_i64m8_tum841// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {842// CHECK-RV64-NEXT:  entry:843// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.x.f.v.mask.nxv8i64.nxv8f32.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x float> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)844// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]845//846vint64m8_t test_vfwcvt_x_f_v_i64m8_tum(vbool8_t mask, vint64m8_t maskedoff, vfloat32m4_t src, size_t vl) {847  return __riscv_vfwcvt_x_tum(mask, maskedoff, src, vl);848}849 850// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfwcvt_xu_f_v_u64m1_tum851// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {852// CHECK-RV64-NEXT:  entry:853// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv1i64.nxv1f32.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x float> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)854// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]855//856vuint64m1_t test_vfwcvt_xu_f_v_u64m1_tum(vbool64_t mask, vuint64m1_t maskedoff, vfloat32mf2_t src, size_t vl) {857  return __riscv_vfwcvt_xu_tum(mask, maskedoff, src, vl);858}859 860// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfwcvt_xu_f_v_u64m2_tum861// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {862// CHECK-RV64-NEXT:  entry:863// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv2i64.nxv2f32.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x float> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)864// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]865//866vuint64m2_t test_vfwcvt_xu_f_v_u64m2_tum(vbool32_t mask, vuint64m2_t maskedoff, vfloat32m1_t src, size_t vl) {867  return __riscv_vfwcvt_xu_tum(mask, maskedoff, src, vl);868}869 870// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfwcvt_xu_f_v_u64m4_tum871// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {872// CHECK-RV64-NEXT:  entry:873// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv4i64.nxv4f32.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x float> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)874// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]875//876vuint64m4_t test_vfwcvt_xu_f_v_u64m4_tum(vbool16_t mask, vuint64m4_t maskedoff, vfloat32m2_t src, size_t vl) {877  return __riscv_vfwcvt_xu_tum(mask, maskedoff, src, vl);878}879 880// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfwcvt_xu_f_v_u64m8_tum881// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {882// CHECK-RV64-NEXT:  entry:883// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv8i64.nxv8f32.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x float> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)884// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]885//886vuint64m8_t test_vfwcvt_xu_f_v_u64m8_tum(vbool8_t mask, vuint64m8_t maskedoff, vfloat32m4_t src, size_t vl) {887  return __riscv_vfwcvt_xu_tum(mask, maskedoff, src, vl);888}889 890// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwcvt_f_x_v_f64m1_tum891// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {892// CHECK-RV64-NEXT:  entry:893// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.x.v.mask.nxv1f64.nxv1i32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x i32> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)894// CHECK-RV64-NEXT:    ret <vscale x 1 x double> [[TMP0]]895//896vfloat64m1_t test_vfwcvt_f_x_v_f64m1_tum(vbool64_t mask, vfloat64m1_t maskedoff, vint32mf2_t src, size_t vl) {897  return __riscv_vfwcvt_f_tum(mask, maskedoff, src, vl);898}899 900// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfwcvt_f_x_v_f64m2_tum901// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {902// CHECK-RV64-NEXT:  entry:903// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.x.v.mask.nxv2f64.nxv2i32.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x i32> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)904// CHECK-RV64-NEXT:    ret <vscale x 2 x double> [[TMP0]]905//906vfloat64m2_t test_vfwcvt_f_x_v_f64m2_tum(vbool32_t mask, vfloat64m2_t maskedoff, vint32m1_t src, size_t vl) {907  return __riscv_vfwcvt_f_tum(mask, maskedoff, src, vl);908}909 910// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfwcvt_f_x_v_f64m4_tum911// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {912// CHECK-RV64-NEXT:  entry:913// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.x.v.mask.nxv4f64.nxv4i32.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x i32> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)914// CHECK-RV64-NEXT:    ret <vscale x 4 x double> [[TMP0]]915//916vfloat64m4_t test_vfwcvt_f_x_v_f64m4_tum(vbool16_t mask, vfloat64m4_t maskedoff, vint32m2_t src, size_t vl) {917  return __riscv_vfwcvt_f_tum(mask, maskedoff, src, vl);918}919 920// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfwcvt_f_x_v_f64m8_tum921// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {922// CHECK-RV64-NEXT:  entry:923// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.x.v.mask.nxv8f64.nxv8i32.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x i32> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)924// CHECK-RV64-NEXT:    ret <vscale x 8 x double> [[TMP0]]925//926vfloat64m8_t test_vfwcvt_f_x_v_f64m8_tum(vbool8_t mask, vfloat64m8_t maskedoff, vint32m4_t src, size_t vl) {927  return __riscv_vfwcvt_f_tum(mask, maskedoff, src, vl);928}929 930// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwcvt_f_xu_v_f64m1_tum931// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {932// CHECK-RV64-NEXT:  entry:933// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv1f64.nxv1i32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x i32> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)934// CHECK-RV64-NEXT:    ret <vscale x 1 x double> [[TMP0]]935//936vfloat64m1_t test_vfwcvt_f_xu_v_f64m1_tum(vbool64_t mask, vfloat64m1_t maskedoff, vuint32mf2_t src, size_t vl) {937  return __riscv_vfwcvt_f_tum(mask, maskedoff, src, vl);938}939 940// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfwcvt_f_xu_v_f64m2_tum941// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {942// CHECK-RV64-NEXT:  entry:943// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv2f64.nxv2i32.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x i32> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)944// CHECK-RV64-NEXT:    ret <vscale x 2 x double> [[TMP0]]945//946vfloat64m2_t test_vfwcvt_f_xu_v_f64m2_tum(vbool32_t mask, vfloat64m2_t maskedoff, vuint32m1_t src, size_t vl) {947  return __riscv_vfwcvt_f_tum(mask, maskedoff, src, vl);948}949 950// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfwcvt_f_xu_v_f64m4_tum951// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {952// CHECK-RV64-NEXT:  entry:953// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv4f64.nxv4i32.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x i32> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)954// CHECK-RV64-NEXT:    ret <vscale x 4 x double> [[TMP0]]955//956vfloat64m4_t test_vfwcvt_f_xu_v_f64m4_tum(vbool16_t mask, vfloat64m4_t maskedoff, vuint32m2_t src, size_t vl) {957  return __riscv_vfwcvt_f_tum(mask, maskedoff, src, vl);958}959 960// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfwcvt_f_xu_v_f64m8_tum961// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {962// CHECK-RV64-NEXT:  entry:963// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv8f64.nxv8i32.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x i32> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)964// CHECK-RV64-NEXT:    ret <vscale x 8 x double> [[TMP0]]965//966vfloat64m8_t test_vfwcvt_f_xu_v_f64m8_tum(vbool8_t mask, vfloat64m8_t maskedoff, vuint32m4_t src, size_t vl) {967  return __riscv_vfwcvt_f_tum(mask, maskedoff, src, vl);968}969 970 971// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfwcvt_f_x_v_f16mf4_tumu972// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {973// CHECK-RV64-NEXT:  entry:974// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.mask.nxv1f16.nxv1i8.i64(<vscale x 1 x half> [[MASKEDOFF]], <vscale x 1 x i8> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)975// CHECK-RV64-NEXT:    ret <vscale x 1 x half> [[TMP0]]976//977vfloat16mf4_t test_vfwcvt_f_x_v_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t maskedoff, vint8mf8_t src, size_t vl) {978  return __riscv_vfwcvt_f_tumu(mask, maskedoff, src, vl);979}980 981// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfwcvt_f_x_v_f16mf2_tumu982// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {983// CHECK-RV64-NEXT:  entry:984// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.mask.nxv2f16.nxv2i8.i64(<vscale x 2 x half> [[MASKEDOFF]], <vscale x 2 x i8> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)985// CHECK-RV64-NEXT:    ret <vscale x 2 x half> [[TMP0]]986//987vfloat16mf2_t test_vfwcvt_f_x_v_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t maskedoff, vint8mf4_t src, size_t vl) {988  return __riscv_vfwcvt_f_tumu(mask, maskedoff, src, vl);989}990 991// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfwcvt_f_x_v_f16m1_tumu992// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {993// CHECK-RV64-NEXT:  entry:994// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.mask.nxv4f16.nxv4i8.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x i8> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)995// CHECK-RV64-NEXT:    ret <vscale x 4 x half> [[TMP0]]996//997vfloat16m1_t test_vfwcvt_f_x_v_f16m1_tumu(vbool16_t mask, vfloat16m1_t maskedoff, vint8mf2_t src, size_t vl) {998  return __riscv_vfwcvt_f_tumu(mask, maskedoff, src, vl);999}1000 1001// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfwcvt_f_x_v_f16m2_tumu1002// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1003// CHECK-RV64-NEXT:  entry:1004// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.mask.nxv8f16.nxv8i8.i64(<vscale x 8 x half> [[MASKEDOFF]], <vscale x 8 x i8> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)1005// CHECK-RV64-NEXT:    ret <vscale x 8 x half> [[TMP0]]1006//1007vfloat16m2_t test_vfwcvt_f_x_v_f16m2_tumu(vbool8_t mask, vfloat16m2_t maskedoff, vint8m1_t src, size_t vl) {1008  return __riscv_vfwcvt_f_tumu(mask, maskedoff, src, vl);1009}1010 1011// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfwcvt_f_x_v_f16m4_tumu1012// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1013// CHECK-RV64-NEXT:  entry:1014// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.mask.nxv16f16.nxv16i8.i64(<vscale x 16 x half> [[MASKEDOFF]], <vscale x 16 x i8> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)1015// CHECK-RV64-NEXT:    ret <vscale x 16 x half> [[TMP0]]1016//1017vfloat16m4_t test_vfwcvt_f_x_v_f16m4_tumu(vbool4_t mask, vfloat16m4_t maskedoff, vint8m2_t src, size_t vl) {1018  return __riscv_vfwcvt_f_tumu(mask, maskedoff, src, vl);1019}1020 1021// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfwcvt_f_x_v_f16m8_tumu1022// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1023// CHECK-RV64-NEXT:  entry:1024// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.mask.nxv32f16.nxv32i8.i64(<vscale x 32 x half> [[MASKEDOFF]], <vscale x 32 x i8> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0)1025// CHECK-RV64-NEXT:    ret <vscale x 32 x half> [[TMP0]]1026//1027vfloat16m8_t test_vfwcvt_f_x_v_f16m8_tumu(vbool2_t mask, vfloat16m8_t maskedoff, vint8m4_t src, size_t vl) {1028  return __riscv_vfwcvt_f_tumu(mask, maskedoff, src, vl);1029}1030 1031// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfwcvt_f_xu_v_f16mf4_tumu1032// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1033// CHECK-RV64-NEXT:  entry:1034// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv1f16.nxv1i8.i64(<vscale x 1 x half> [[MASKEDOFF]], <vscale x 1 x i8> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)1035// CHECK-RV64-NEXT:    ret <vscale x 1 x half> [[TMP0]]1036//1037vfloat16mf4_t test_vfwcvt_f_xu_v_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t maskedoff, vuint8mf8_t src, size_t vl) {1038  return __riscv_vfwcvt_f_tumu(mask, maskedoff, src, vl);1039}1040 1041// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfwcvt_f_xu_v_f16mf2_tumu1042// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1043// CHECK-RV64-NEXT:  entry:1044// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv2f16.nxv2i8.i64(<vscale x 2 x half> [[MASKEDOFF]], <vscale x 2 x i8> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)1045// CHECK-RV64-NEXT:    ret <vscale x 2 x half> [[TMP0]]1046//1047vfloat16mf2_t test_vfwcvt_f_xu_v_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t maskedoff, vuint8mf4_t src, size_t vl) {1048  return __riscv_vfwcvt_f_tumu(mask, maskedoff, src, vl);1049}1050 1051// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfwcvt_f_xu_v_f16m1_tumu1052// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1053// CHECK-RV64-NEXT:  entry:1054// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv4f16.nxv4i8.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x i8> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)1055// CHECK-RV64-NEXT:    ret <vscale x 4 x half> [[TMP0]]1056//1057vfloat16m1_t test_vfwcvt_f_xu_v_f16m1_tumu(vbool16_t mask, vfloat16m1_t maskedoff, vuint8mf2_t src, size_t vl) {1058  return __riscv_vfwcvt_f_tumu(mask, maskedoff, src, vl);1059}1060 1061// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfwcvt_f_xu_v_f16m2_tumu1062// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1063// CHECK-RV64-NEXT:  entry:1064// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv8f16.nxv8i8.i64(<vscale x 8 x half> [[MASKEDOFF]], <vscale x 8 x i8> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)1065// CHECK-RV64-NEXT:    ret <vscale x 8 x half> [[TMP0]]1066//1067vfloat16m2_t test_vfwcvt_f_xu_v_f16m2_tumu(vbool8_t mask, vfloat16m2_t maskedoff, vuint8m1_t src, size_t vl) {1068  return __riscv_vfwcvt_f_tumu(mask, maskedoff, src, vl);1069}1070 1071// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfwcvt_f_xu_v_f16m4_tumu1072// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1073// CHECK-RV64-NEXT:  entry:1074// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv16f16.nxv16i8.i64(<vscale x 16 x half> [[MASKEDOFF]], <vscale x 16 x i8> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)1075// CHECK-RV64-NEXT:    ret <vscale x 16 x half> [[TMP0]]1076//1077vfloat16m4_t test_vfwcvt_f_xu_v_f16m4_tumu(vbool4_t mask, vfloat16m4_t maskedoff, vuint8m2_t src, size_t vl) {1078  return __riscv_vfwcvt_f_tumu(mask, maskedoff, src, vl);1079}1080 1081// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfwcvt_f_xu_v_f16m8_tumu1082// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1083// CHECK-RV64-NEXT:  entry:1084// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv32f16.nxv32i8.i64(<vscale x 32 x half> [[MASKEDOFF]], <vscale x 32 x i8> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0)1085// CHECK-RV64-NEXT:    ret <vscale x 32 x half> [[TMP0]]1086//1087vfloat16m8_t test_vfwcvt_f_xu_v_f16m8_tumu(vbool2_t mask, vfloat16m8_t maskedoff, vuint8m4_t src, size_t vl) {1088  return __riscv_vfwcvt_f_tumu(mask, maskedoff, src, vl);1089}1090 1091// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfwcvt_x_f_v_i32mf2_tumu1092// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1093// CHECK-RV64-NEXT:  entry:1094// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.x.f.v.mask.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x half> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1095// CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]1096//1097vint32mf2_t test_vfwcvt_x_f_v_i32mf2_tumu(vbool64_t mask, vint32mf2_t maskedoff, vfloat16mf4_t src, size_t vl) {1098  return __riscv_vfwcvt_x_tumu(mask, maskedoff, src, vl);1099}1100 1101// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfwcvt_x_f_v_i32m1_tumu1102// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1103// CHECK-RV64-NEXT:  entry:1104// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.x.f.v.mask.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x half> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1105// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]1106//1107vint32m1_t test_vfwcvt_x_f_v_i32m1_tumu(vbool32_t mask, vint32m1_t maskedoff, vfloat16mf2_t src, size_t vl) {1108  return __riscv_vfwcvt_x_tumu(mask, maskedoff, src, vl);1109}1110 1111// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfwcvt_x_f_v_i32m2_tumu1112// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1113// CHECK-RV64-NEXT:  entry:1114// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.x.f.v.mask.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x half> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1115// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]1116//1117vint32m2_t test_vfwcvt_x_f_v_i32m2_tumu(vbool16_t mask, vint32m2_t maskedoff, vfloat16m1_t src, size_t vl) {1118  return __riscv_vfwcvt_x_tumu(mask, maskedoff, src, vl);1119}1120 1121// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfwcvt_x_f_v_i32m4_tumu1122// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1123// CHECK-RV64-NEXT:  entry:1124// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.x.f.v.mask.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x half> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1125// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]1126//1127vint32m4_t test_vfwcvt_x_f_v_i32m4_tumu(vbool8_t mask, vint32m4_t maskedoff, vfloat16m2_t src, size_t vl) {1128  return __riscv_vfwcvt_x_tumu(mask, maskedoff, src, vl);1129}1130 1131// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfwcvt_x_f_v_i32m8_tumu1132// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1133// CHECK-RV64-NEXT:  entry:1134// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.x.f.v.mask.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x half> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1135// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]1136//1137vint32m8_t test_vfwcvt_x_f_v_i32m8_tumu(vbool4_t mask, vint32m8_t maskedoff, vfloat16m4_t src, size_t vl) {1138  return __riscv_vfwcvt_x_tumu(mask, maskedoff, src, vl);1139}1140 1141// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfwcvt_xu_f_v_u32mf2_tumu1142// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1143// CHECK-RV64-NEXT:  entry:1144// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x half> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1145// CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]1146//1147vuint32mf2_t test_vfwcvt_xu_f_v_u32mf2_tumu(vbool64_t mask, vuint32mf2_t maskedoff, vfloat16mf4_t src, size_t vl) {1148  return __riscv_vfwcvt_xu_tumu(mask, maskedoff, src, vl);1149}1150 1151// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfwcvt_xu_f_v_u32m1_tumu1152// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1153// CHECK-RV64-NEXT:  entry:1154// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x half> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1155// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]1156//1157vuint32m1_t test_vfwcvt_xu_f_v_u32m1_tumu(vbool32_t mask, vuint32m1_t maskedoff, vfloat16mf2_t src, size_t vl) {1158  return __riscv_vfwcvt_xu_tumu(mask, maskedoff, src, vl);1159}1160 1161// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfwcvt_xu_f_v_u32m2_tumu1162// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1163// CHECK-RV64-NEXT:  entry:1164// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x half> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1165// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]1166//1167vuint32m2_t test_vfwcvt_xu_f_v_u32m2_tumu(vbool16_t mask, vuint32m2_t maskedoff, vfloat16m1_t src, size_t vl) {1168  return __riscv_vfwcvt_xu_tumu(mask, maskedoff, src, vl);1169}1170 1171// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfwcvt_xu_f_v_u32m4_tumu1172// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1173// CHECK-RV64-NEXT:  entry:1174// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x half> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1175// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]1176//1177vuint32m4_t test_vfwcvt_xu_f_v_u32m4_tumu(vbool8_t mask, vuint32m4_t maskedoff, vfloat16m2_t src, size_t vl) {1178  return __riscv_vfwcvt_xu_tumu(mask, maskedoff, src, vl);1179}1180 1181// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfwcvt_xu_f_v_u32m8_tumu1182// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1183// CHECK-RV64-NEXT:  entry:1184// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x half> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1185// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]1186//1187vuint32m8_t test_vfwcvt_xu_f_v_u32m8_tumu(vbool4_t mask, vuint32m8_t maskedoff, vfloat16m4_t src, size_t vl) {1188  return __riscv_vfwcvt_xu_tumu(mask, maskedoff, src, vl);1189}1190 1191// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwcvt_f_x_v_f32mf2_tumu1192// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1193// CHECK-RV64-NEXT:  entry:1194// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.x.v.mask.nxv1f32.nxv1i16.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x i16> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)1195// CHECK-RV64-NEXT:    ret <vscale x 1 x float> [[TMP0]]1196//1197vfloat32mf2_t test_vfwcvt_f_x_v_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t maskedoff, vint16mf4_t src, size_t vl) {1198  return __riscv_vfwcvt_f_tumu(mask, maskedoff, src, vl);1199}1200 1201// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwcvt_f_x_v_f32m1_tumu1202// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1203// CHECK-RV64-NEXT:  entry:1204// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.x.v.mask.nxv2f32.nxv2i16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x i16> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)1205// CHECK-RV64-NEXT:    ret <vscale x 2 x float> [[TMP0]]1206//1207vfloat32m1_t test_vfwcvt_f_x_v_f32m1_tumu(vbool32_t mask, vfloat32m1_t maskedoff, vint16mf2_t src, size_t vl) {1208  return __riscv_vfwcvt_f_tumu(mask, maskedoff, src, vl);1209}1210 1211// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwcvt_f_x_v_f32m2_tumu1212// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1213// CHECK-RV64-NEXT:  entry:1214// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.x.v.mask.nxv4f32.nxv4i16.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x i16> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)1215// CHECK-RV64-NEXT:    ret <vscale x 4 x float> [[TMP0]]1216//1217vfloat32m2_t test_vfwcvt_f_x_v_f32m2_tumu(vbool16_t mask, vfloat32m2_t maskedoff, vint16m1_t src, size_t vl) {1218  return __riscv_vfwcvt_f_tumu(mask, maskedoff, src, vl);1219}1220 1221// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwcvt_f_x_v_f32m4_tumu1222// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1223// CHECK-RV64-NEXT:  entry:1224// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.x.v.mask.nxv8f32.nxv8i16.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x i16> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)1225// CHECK-RV64-NEXT:    ret <vscale x 8 x float> [[TMP0]]1226//1227vfloat32m4_t test_vfwcvt_f_x_v_f32m4_tumu(vbool8_t mask, vfloat32m4_t maskedoff, vint16m2_t src, size_t vl) {1228  return __riscv_vfwcvt_f_tumu(mask, maskedoff, src, vl);1229}1230 1231// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwcvt_f_x_v_f32m8_tumu1232// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1233// CHECK-RV64-NEXT:  entry:1234// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.x.v.mask.nxv16f32.nxv16i16.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x i16> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)1235// CHECK-RV64-NEXT:    ret <vscale x 16 x float> [[TMP0]]1236//1237vfloat32m8_t test_vfwcvt_f_x_v_f32m8_tumu(vbool4_t mask, vfloat32m8_t maskedoff, vint16m4_t src, size_t vl) {1238  return __riscv_vfwcvt_f_tumu(mask, maskedoff, src, vl);1239}1240 1241// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwcvt_f_xu_v_f32mf2_tumu1242// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1243// CHECK-RV64-NEXT:  entry:1244// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv1f32.nxv1i16.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x i16> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)1245// CHECK-RV64-NEXT:    ret <vscale x 1 x float> [[TMP0]]1246//1247vfloat32mf2_t test_vfwcvt_f_xu_v_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t maskedoff, vuint16mf4_t src, size_t vl) {1248  return __riscv_vfwcvt_f_tumu(mask, maskedoff, src, vl);1249}1250 1251// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwcvt_f_xu_v_f32m1_tumu1252// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1253// CHECK-RV64-NEXT:  entry:1254// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv2f32.nxv2i16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x i16> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)1255// CHECK-RV64-NEXT:    ret <vscale x 2 x float> [[TMP0]]1256//1257vfloat32m1_t test_vfwcvt_f_xu_v_f32m1_tumu(vbool32_t mask, vfloat32m1_t maskedoff, vuint16mf2_t src, size_t vl) {1258  return __riscv_vfwcvt_f_tumu(mask, maskedoff, src, vl);1259}1260 1261// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwcvt_f_xu_v_f32m2_tumu1262// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1263// CHECK-RV64-NEXT:  entry:1264// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv4f32.nxv4i16.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x i16> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)1265// CHECK-RV64-NEXT:    ret <vscale x 4 x float> [[TMP0]]1266//1267vfloat32m2_t test_vfwcvt_f_xu_v_f32m2_tumu(vbool16_t mask, vfloat32m2_t maskedoff, vuint16m1_t src, size_t vl) {1268  return __riscv_vfwcvt_f_tumu(mask, maskedoff, src, vl);1269}1270 1271// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwcvt_f_xu_v_f32m4_tumu1272// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1273// CHECK-RV64-NEXT:  entry:1274// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv8f32.nxv8i16.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x i16> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)1275// CHECK-RV64-NEXT:    ret <vscale x 8 x float> [[TMP0]]1276//1277vfloat32m4_t test_vfwcvt_f_xu_v_f32m4_tumu(vbool8_t mask, vfloat32m4_t maskedoff, vuint16m2_t src, size_t vl) {1278  return __riscv_vfwcvt_f_tumu(mask, maskedoff, src, vl);1279}1280 1281// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwcvt_f_xu_v_f32m8_tumu1282// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1283// CHECK-RV64-NEXT:  entry:1284// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv16f32.nxv16i16.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x i16> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)1285// CHECK-RV64-NEXT:    ret <vscale x 16 x float> [[TMP0]]1286//1287vfloat32m8_t test_vfwcvt_f_xu_v_f32m8_tumu(vbool4_t mask, vfloat32m8_t maskedoff, vuint16m4_t src, size_t vl) {1288  return __riscv_vfwcvt_f_tumu(mask, maskedoff, src, vl);1289}1290 1291// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfwcvt_x_f_v_i64m1_tumu1292// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1293// CHECK-RV64-NEXT:  entry:1294// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.x.f.v.mask.nxv1i64.nxv1f32.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x float> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1295// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]1296//1297vint64m1_t test_vfwcvt_x_f_v_i64m1_tumu(vbool64_t mask, vint64m1_t maskedoff, vfloat32mf2_t src, size_t vl) {1298  return __riscv_vfwcvt_x_tumu(mask, maskedoff, src, vl);1299}1300 1301// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfwcvt_x_f_v_i64m2_tumu1302// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1303// CHECK-RV64-NEXT:  entry:1304// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.x.f.v.mask.nxv2i64.nxv2f32.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x float> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1305// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]1306//1307vint64m2_t test_vfwcvt_x_f_v_i64m2_tumu(vbool32_t mask, vint64m2_t maskedoff, vfloat32m1_t src, size_t vl) {1308  return __riscv_vfwcvt_x_tumu(mask, maskedoff, src, vl);1309}1310 1311// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfwcvt_x_f_v_i64m4_tumu1312// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1313// CHECK-RV64-NEXT:  entry:1314// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.x.f.v.mask.nxv4i64.nxv4f32.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x float> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1315// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]1316//1317vint64m4_t test_vfwcvt_x_f_v_i64m4_tumu(vbool16_t mask, vint64m4_t maskedoff, vfloat32m2_t src, size_t vl) {1318  return __riscv_vfwcvt_x_tumu(mask, maskedoff, src, vl);1319}1320 1321// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfwcvt_x_f_v_i64m8_tumu1322// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1323// CHECK-RV64-NEXT:  entry:1324// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.x.f.v.mask.nxv8i64.nxv8f32.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x float> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1325// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]1326//1327vint64m8_t test_vfwcvt_x_f_v_i64m8_tumu(vbool8_t mask, vint64m8_t maskedoff, vfloat32m4_t src, size_t vl) {1328  return __riscv_vfwcvt_x_tumu(mask, maskedoff, src, vl);1329}1330 1331// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfwcvt_xu_f_v_u64m1_tumu1332// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1333// CHECK-RV64-NEXT:  entry:1334// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv1i64.nxv1f32.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x float> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1335// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]1336//1337vuint64m1_t test_vfwcvt_xu_f_v_u64m1_tumu(vbool64_t mask, vuint64m1_t maskedoff, vfloat32mf2_t src, size_t vl) {1338  return __riscv_vfwcvt_xu_tumu(mask, maskedoff, src, vl);1339}1340 1341// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfwcvt_xu_f_v_u64m2_tumu1342// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1343// CHECK-RV64-NEXT:  entry:1344// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv2i64.nxv2f32.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x float> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1345// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]1346//1347vuint64m2_t test_vfwcvt_xu_f_v_u64m2_tumu(vbool32_t mask, vuint64m2_t maskedoff, vfloat32m1_t src, size_t vl) {1348  return __riscv_vfwcvt_xu_tumu(mask, maskedoff, src, vl);1349}1350 1351// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfwcvt_xu_f_v_u64m4_tumu1352// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1353// CHECK-RV64-NEXT:  entry:1354// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv4i64.nxv4f32.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x float> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1355// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]1356//1357vuint64m4_t test_vfwcvt_xu_f_v_u64m4_tumu(vbool16_t mask, vuint64m4_t maskedoff, vfloat32m2_t src, size_t vl) {1358  return __riscv_vfwcvt_xu_tumu(mask, maskedoff, src, vl);1359}1360 1361// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfwcvt_xu_f_v_u64m8_tumu1362// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1363// CHECK-RV64-NEXT:  entry:1364// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv8i64.nxv8f32.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x float> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)1365// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]1366//1367vuint64m8_t test_vfwcvt_xu_f_v_u64m8_tumu(vbool8_t mask, vuint64m8_t maskedoff, vfloat32m4_t src, size_t vl) {1368  return __riscv_vfwcvt_xu_tumu(mask, maskedoff, src, vl);1369}1370 1371// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwcvt_f_x_v_f64m1_tumu1372// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1373// CHECK-RV64-NEXT:  entry:1374// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.x.v.mask.nxv1f64.nxv1i32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x i32> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)1375// CHECK-RV64-NEXT:    ret <vscale x 1 x double> [[TMP0]]1376//1377vfloat64m1_t test_vfwcvt_f_x_v_f64m1_tumu(vbool64_t mask, vfloat64m1_t maskedoff, vint32mf2_t src, size_t vl) {1378  return __riscv_vfwcvt_f_tumu(mask, maskedoff, src, vl);1379}1380 1381// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfwcvt_f_x_v_f64m2_tumu1382// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1383// CHECK-RV64-NEXT:  entry:1384// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.x.v.mask.nxv2f64.nxv2i32.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x i32> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)1385// CHECK-RV64-NEXT:    ret <vscale x 2 x double> [[TMP0]]1386//1387vfloat64m2_t test_vfwcvt_f_x_v_f64m2_tumu(vbool32_t mask, vfloat64m2_t maskedoff, vint32m1_t src, size_t vl) {1388  return __riscv_vfwcvt_f_tumu(mask, maskedoff, src, vl);1389}1390 1391// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfwcvt_f_x_v_f64m4_tumu1392// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1393// CHECK-RV64-NEXT:  entry:1394// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.x.v.mask.nxv4f64.nxv4i32.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x i32> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)1395// CHECK-RV64-NEXT:    ret <vscale x 4 x double> [[TMP0]]1396//1397vfloat64m4_t test_vfwcvt_f_x_v_f64m4_tumu(vbool16_t mask, vfloat64m4_t maskedoff, vint32m2_t src, size_t vl) {1398  return __riscv_vfwcvt_f_tumu(mask, maskedoff, src, vl);1399}1400 1401// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfwcvt_f_x_v_f64m8_tumu1402// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1403// CHECK-RV64-NEXT:  entry:1404// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.x.v.mask.nxv8f64.nxv8i32.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x i32> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)1405// CHECK-RV64-NEXT:    ret <vscale x 8 x double> [[TMP0]]1406//1407vfloat64m8_t test_vfwcvt_f_x_v_f64m8_tumu(vbool8_t mask, vfloat64m8_t maskedoff, vint32m4_t src, size_t vl) {1408  return __riscv_vfwcvt_f_tumu(mask, maskedoff, src, vl);1409}1410 1411// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwcvt_f_xu_v_f64m1_tumu1412// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1413// CHECK-RV64-NEXT:  entry:1414// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv1f64.nxv1i32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x i32> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)1415// CHECK-RV64-NEXT:    ret <vscale x 1 x double> [[TMP0]]1416//1417vfloat64m1_t test_vfwcvt_f_xu_v_f64m1_tumu(vbool64_t mask, vfloat64m1_t maskedoff, vuint32mf2_t src, size_t vl) {1418  return __riscv_vfwcvt_f_tumu(mask, maskedoff, src, vl);1419}1420 1421// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfwcvt_f_xu_v_f64m2_tumu1422// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1423// CHECK-RV64-NEXT:  entry:1424// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv2f64.nxv2i32.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x i32> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)1425// CHECK-RV64-NEXT:    ret <vscale x 2 x double> [[TMP0]]1426//1427vfloat64m2_t test_vfwcvt_f_xu_v_f64m2_tumu(vbool32_t mask, vfloat64m2_t maskedoff, vuint32m1_t src, size_t vl) {1428  return __riscv_vfwcvt_f_tumu(mask, maskedoff, src, vl);1429}1430 1431// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfwcvt_f_xu_v_f64m4_tumu1432// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1433// CHECK-RV64-NEXT:  entry:1434// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv4f64.nxv4i32.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x i32> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)1435// CHECK-RV64-NEXT:    ret <vscale x 4 x double> [[TMP0]]1436//1437vfloat64m4_t test_vfwcvt_f_xu_v_f64m4_tumu(vbool16_t mask, vfloat64m4_t maskedoff, vuint32m2_t src, size_t vl) {1438  return __riscv_vfwcvt_f_tumu(mask, maskedoff, src, vl);1439}1440 1441// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfwcvt_f_xu_v_f64m8_tumu1442// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1443// CHECK-RV64-NEXT:  entry:1444// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv8f64.nxv8i32.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x i32> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)1445// CHECK-RV64-NEXT:    ret <vscale x 8 x double> [[TMP0]]1446//1447vfloat64m8_t test_vfwcvt_f_xu_v_f64m8_tumu(vbool8_t mask, vfloat64m8_t maskedoff, vuint32m4_t src, size_t vl) {1448  return __riscv_vfwcvt_f_tumu(mask, maskedoff, src, vl);1449}1450 1451// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfwcvt_f_x_v_f16mf4_mu1452// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1453// CHECK-RV64-NEXT:  entry:1454// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.mask.nxv1f16.nxv1i8.i64(<vscale x 1 x half> [[MASKEDOFF]], <vscale x 1 x i8> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)1455// CHECK-RV64-NEXT:    ret <vscale x 1 x half> [[TMP0]]1456//1457vfloat16mf4_t test_vfwcvt_f_x_v_f16mf4_mu(vbool64_t mask, vfloat16mf4_t maskedoff, vint8mf8_t src, size_t vl) {1458  return __riscv_vfwcvt_f_mu(mask, maskedoff, src, vl);1459}1460 1461// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfwcvt_f_x_v_f16mf2_mu1462// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1463// CHECK-RV64-NEXT:  entry:1464// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.mask.nxv2f16.nxv2i8.i64(<vscale x 2 x half> [[MASKEDOFF]], <vscale x 2 x i8> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)1465// CHECK-RV64-NEXT:    ret <vscale x 2 x half> [[TMP0]]1466//1467vfloat16mf2_t test_vfwcvt_f_x_v_f16mf2_mu(vbool32_t mask, vfloat16mf2_t maskedoff, vint8mf4_t src, size_t vl) {1468  return __riscv_vfwcvt_f_mu(mask, maskedoff, src, vl);1469}1470 1471// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfwcvt_f_x_v_f16m1_mu1472// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1473// CHECK-RV64-NEXT:  entry:1474// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.mask.nxv4f16.nxv4i8.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x i8> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)1475// CHECK-RV64-NEXT:    ret <vscale x 4 x half> [[TMP0]]1476//1477vfloat16m1_t test_vfwcvt_f_x_v_f16m1_mu(vbool16_t mask, vfloat16m1_t maskedoff, vint8mf2_t src, size_t vl) {1478  return __riscv_vfwcvt_f_mu(mask, maskedoff, src, vl);1479}1480 1481// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfwcvt_f_x_v_f16m2_mu1482// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1483// CHECK-RV64-NEXT:  entry:1484// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.mask.nxv8f16.nxv8i8.i64(<vscale x 8 x half> [[MASKEDOFF]], <vscale x 8 x i8> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)1485// CHECK-RV64-NEXT:    ret <vscale x 8 x half> [[TMP0]]1486//1487vfloat16m2_t test_vfwcvt_f_x_v_f16m2_mu(vbool8_t mask, vfloat16m2_t maskedoff, vint8m1_t src, size_t vl) {1488  return __riscv_vfwcvt_f_mu(mask, maskedoff, src, vl);1489}1490 1491// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfwcvt_f_x_v_f16m4_mu1492// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1493// CHECK-RV64-NEXT:  entry:1494// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.mask.nxv16f16.nxv16i8.i64(<vscale x 16 x half> [[MASKEDOFF]], <vscale x 16 x i8> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)1495// CHECK-RV64-NEXT:    ret <vscale x 16 x half> [[TMP0]]1496//1497vfloat16m4_t test_vfwcvt_f_x_v_f16m4_mu(vbool4_t mask, vfloat16m4_t maskedoff, vint8m2_t src, size_t vl) {1498  return __riscv_vfwcvt_f_mu(mask, maskedoff, src, vl);1499}1500 1501// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfwcvt_f_x_v_f16m8_mu1502// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1503// CHECK-RV64-NEXT:  entry:1504// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.mask.nxv32f16.nxv32i8.i64(<vscale x 32 x half> [[MASKEDOFF]], <vscale x 32 x i8> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1)1505// CHECK-RV64-NEXT:    ret <vscale x 32 x half> [[TMP0]]1506//1507vfloat16m8_t test_vfwcvt_f_x_v_f16m8_mu(vbool2_t mask, vfloat16m8_t maskedoff, vint8m4_t src, size_t vl) {1508  return __riscv_vfwcvt_f_mu(mask, maskedoff, src, vl);1509}1510 1511// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfwcvt_f_xu_v_f16mf4_mu1512// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1513// CHECK-RV64-NEXT:  entry:1514// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv1f16.nxv1i8.i64(<vscale x 1 x half> [[MASKEDOFF]], <vscale x 1 x i8> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)1515// CHECK-RV64-NEXT:    ret <vscale x 1 x half> [[TMP0]]1516//1517vfloat16mf4_t test_vfwcvt_f_xu_v_f16mf4_mu(vbool64_t mask, vfloat16mf4_t maskedoff, vuint8mf8_t src, size_t vl) {1518  return __riscv_vfwcvt_f_mu(mask, maskedoff, src, vl);1519}1520 1521// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfwcvt_f_xu_v_f16mf2_mu1522// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1523// CHECK-RV64-NEXT:  entry:1524// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv2f16.nxv2i8.i64(<vscale x 2 x half> [[MASKEDOFF]], <vscale x 2 x i8> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)1525// CHECK-RV64-NEXT:    ret <vscale x 2 x half> [[TMP0]]1526//1527vfloat16mf2_t test_vfwcvt_f_xu_v_f16mf2_mu(vbool32_t mask, vfloat16mf2_t maskedoff, vuint8mf4_t src, size_t vl) {1528  return __riscv_vfwcvt_f_mu(mask, maskedoff, src, vl);1529}1530 1531// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfwcvt_f_xu_v_f16m1_mu1532// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1533// CHECK-RV64-NEXT:  entry:1534// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv4f16.nxv4i8.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x i8> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)1535// CHECK-RV64-NEXT:    ret <vscale x 4 x half> [[TMP0]]1536//1537vfloat16m1_t test_vfwcvt_f_xu_v_f16m1_mu(vbool16_t mask, vfloat16m1_t maskedoff, vuint8mf2_t src, size_t vl) {1538  return __riscv_vfwcvt_f_mu(mask, maskedoff, src, vl);1539}1540 1541// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfwcvt_f_xu_v_f16m2_mu1542// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1543// CHECK-RV64-NEXT:  entry:1544// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv8f16.nxv8i8.i64(<vscale x 8 x half> [[MASKEDOFF]], <vscale x 8 x i8> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)1545// CHECK-RV64-NEXT:    ret <vscale x 8 x half> [[TMP0]]1546//1547vfloat16m2_t test_vfwcvt_f_xu_v_f16m2_mu(vbool8_t mask, vfloat16m2_t maskedoff, vuint8m1_t src, size_t vl) {1548  return __riscv_vfwcvt_f_mu(mask, maskedoff, src, vl);1549}1550 1551// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfwcvt_f_xu_v_f16m4_mu1552// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1553// CHECK-RV64-NEXT:  entry:1554// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv16f16.nxv16i8.i64(<vscale x 16 x half> [[MASKEDOFF]], <vscale x 16 x i8> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)1555// CHECK-RV64-NEXT:    ret <vscale x 16 x half> [[TMP0]]1556//1557vfloat16m4_t test_vfwcvt_f_xu_v_f16m4_mu(vbool4_t mask, vfloat16m4_t maskedoff, vuint8m2_t src, size_t vl) {1558  return __riscv_vfwcvt_f_mu(mask, maskedoff, src, vl);1559}1560 1561// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfwcvt_f_xu_v_f16m8_mu1562// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1563// CHECK-RV64-NEXT:  entry:1564// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv32f16.nxv32i8.i64(<vscale x 32 x half> [[MASKEDOFF]], <vscale x 32 x i8> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1)1565// CHECK-RV64-NEXT:    ret <vscale x 32 x half> [[TMP0]]1566//1567vfloat16m8_t test_vfwcvt_f_xu_v_f16m8_mu(vbool2_t mask, vfloat16m8_t maskedoff, vuint8m4_t src, size_t vl) {1568  return __riscv_vfwcvt_f_mu(mask, maskedoff, src, vl);1569}1570 1571// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfwcvt_x_f_v_i32mf2_mu1572// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1573// CHECK-RV64-NEXT:  entry:1574// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.x.f.v.mask.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x half> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1575// CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]1576//1577vint32mf2_t test_vfwcvt_x_f_v_i32mf2_mu(vbool64_t mask, vint32mf2_t maskedoff, vfloat16mf4_t src, size_t vl) {1578  return __riscv_vfwcvt_x_mu(mask, maskedoff, src, vl);1579}1580 1581// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfwcvt_x_f_v_i32m1_mu1582// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1583// CHECK-RV64-NEXT:  entry:1584// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.x.f.v.mask.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x half> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1585// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]1586//1587vint32m1_t test_vfwcvt_x_f_v_i32m1_mu(vbool32_t mask, vint32m1_t maskedoff, vfloat16mf2_t src, size_t vl) {1588  return __riscv_vfwcvt_x_mu(mask, maskedoff, src, vl);1589}1590 1591// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfwcvt_x_f_v_i32m2_mu1592// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1593// CHECK-RV64-NEXT:  entry:1594// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.x.f.v.mask.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x half> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1595// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]1596//1597vint32m2_t test_vfwcvt_x_f_v_i32m2_mu(vbool16_t mask, vint32m2_t maskedoff, vfloat16m1_t src, size_t vl) {1598  return __riscv_vfwcvt_x_mu(mask, maskedoff, src, vl);1599}1600 1601// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfwcvt_x_f_v_i32m4_mu1602// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1603// CHECK-RV64-NEXT:  entry:1604// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.x.f.v.mask.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x half> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1605// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]1606//1607vint32m4_t test_vfwcvt_x_f_v_i32m4_mu(vbool8_t mask, vint32m4_t maskedoff, vfloat16m2_t src, size_t vl) {1608  return __riscv_vfwcvt_x_mu(mask, maskedoff, src, vl);1609}1610 1611// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfwcvt_x_f_v_i32m8_mu1612// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1613// CHECK-RV64-NEXT:  entry:1614// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.x.f.v.mask.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x half> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1615// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]1616//1617vint32m8_t test_vfwcvt_x_f_v_i32m8_mu(vbool4_t mask, vint32m8_t maskedoff, vfloat16m4_t src, size_t vl) {1618  return __riscv_vfwcvt_x_mu(mask, maskedoff, src, vl);1619}1620 1621// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfwcvt_xu_f_v_u32mf2_mu1622// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1623// CHECK-RV64-NEXT:  entry:1624// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x half> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1625// CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]1626//1627vuint32mf2_t test_vfwcvt_xu_f_v_u32mf2_mu(vbool64_t mask, vuint32mf2_t maskedoff, vfloat16mf4_t src, size_t vl) {1628  return __riscv_vfwcvt_xu_mu(mask, maskedoff, src, vl);1629}1630 1631// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfwcvt_xu_f_v_u32m1_mu1632// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1633// CHECK-RV64-NEXT:  entry:1634// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x half> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1635// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]1636//1637vuint32m1_t test_vfwcvt_xu_f_v_u32m1_mu(vbool32_t mask, vuint32m1_t maskedoff, vfloat16mf2_t src, size_t vl) {1638  return __riscv_vfwcvt_xu_mu(mask, maskedoff, src, vl);1639}1640 1641// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfwcvt_xu_f_v_u32m2_mu1642// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1643// CHECK-RV64-NEXT:  entry:1644// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x half> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1645// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]1646//1647vuint32m2_t test_vfwcvt_xu_f_v_u32m2_mu(vbool16_t mask, vuint32m2_t maskedoff, vfloat16m1_t src, size_t vl) {1648  return __riscv_vfwcvt_xu_mu(mask, maskedoff, src, vl);1649}1650 1651// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfwcvt_xu_f_v_u32m4_mu1652// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1653// CHECK-RV64-NEXT:  entry:1654// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x half> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1655// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]1656//1657vuint32m4_t test_vfwcvt_xu_f_v_u32m4_mu(vbool8_t mask, vuint32m4_t maskedoff, vfloat16m2_t src, size_t vl) {1658  return __riscv_vfwcvt_xu_mu(mask, maskedoff, src, vl);1659}1660 1661// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfwcvt_xu_f_v_u32m8_mu1662// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1663// CHECK-RV64-NEXT:  entry:1664// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x half> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1665// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]1666//1667vuint32m8_t test_vfwcvt_xu_f_v_u32m8_mu(vbool4_t mask, vuint32m8_t maskedoff, vfloat16m4_t src, size_t vl) {1668  return __riscv_vfwcvt_xu_mu(mask, maskedoff, src, vl);1669}1670 1671// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwcvt_f_x_v_f32mf2_mu1672// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1673// CHECK-RV64-NEXT:  entry:1674// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.x.v.mask.nxv1f32.nxv1i16.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x i16> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)1675// CHECK-RV64-NEXT:    ret <vscale x 1 x float> [[TMP0]]1676//1677vfloat32mf2_t test_vfwcvt_f_x_v_f32mf2_mu(vbool64_t mask, vfloat32mf2_t maskedoff, vint16mf4_t src, size_t vl) {1678  return __riscv_vfwcvt_f_mu(mask, maskedoff, src, vl);1679}1680 1681// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwcvt_f_x_v_f32m1_mu1682// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1683// CHECK-RV64-NEXT:  entry:1684// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.x.v.mask.nxv2f32.nxv2i16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x i16> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)1685// CHECK-RV64-NEXT:    ret <vscale x 2 x float> [[TMP0]]1686//1687vfloat32m1_t test_vfwcvt_f_x_v_f32m1_mu(vbool32_t mask, vfloat32m1_t maskedoff, vint16mf2_t src, size_t vl) {1688  return __riscv_vfwcvt_f_mu(mask, maskedoff, src, vl);1689}1690 1691// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwcvt_f_x_v_f32m2_mu1692// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1693// CHECK-RV64-NEXT:  entry:1694// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.x.v.mask.nxv4f32.nxv4i16.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x i16> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)1695// CHECK-RV64-NEXT:    ret <vscale x 4 x float> [[TMP0]]1696//1697vfloat32m2_t test_vfwcvt_f_x_v_f32m2_mu(vbool16_t mask, vfloat32m2_t maskedoff, vint16m1_t src, size_t vl) {1698  return __riscv_vfwcvt_f_mu(mask, maskedoff, src, vl);1699}1700 1701// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwcvt_f_x_v_f32m4_mu1702// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1703// CHECK-RV64-NEXT:  entry:1704// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.x.v.mask.nxv8f32.nxv8i16.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x i16> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)1705// CHECK-RV64-NEXT:    ret <vscale x 8 x float> [[TMP0]]1706//1707vfloat32m4_t test_vfwcvt_f_x_v_f32m4_mu(vbool8_t mask, vfloat32m4_t maskedoff, vint16m2_t src, size_t vl) {1708  return __riscv_vfwcvt_f_mu(mask, maskedoff, src, vl);1709}1710 1711// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwcvt_f_x_v_f32m8_mu1712// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1713// CHECK-RV64-NEXT:  entry:1714// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.x.v.mask.nxv16f32.nxv16i16.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x i16> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)1715// CHECK-RV64-NEXT:    ret <vscale x 16 x float> [[TMP0]]1716//1717vfloat32m8_t test_vfwcvt_f_x_v_f32m8_mu(vbool4_t mask, vfloat32m8_t maskedoff, vint16m4_t src, size_t vl) {1718  return __riscv_vfwcvt_f_mu(mask, maskedoff, src, vl);1719}1720 1721// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwcvt_f_xu_v_f32mf2_mu1722// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1723// CHECK-RV64-NEXT:  entry:1724// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv1f32.nxv1i16.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x i16> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)1725// CHECK-RV64-NEXT:    ret <vscale x 1 x float> [[TMP0]]1726//1727vfloat32mf2_t test_vfwcvt_f_xu_v_f32mf2_mu(vbool64_t mask, vfloat32mf2_t maskedoff, vuint16mf4_t src, size_t vl) {1728  return __riscv_vfwcvt_f_mu(mask, maskedoff, src, vl);1729}1730 1731// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwcvt_f_xu_v_f32m1_mu1732// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1733// CHECK-RV64-NEXT:  entry:1734// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv2f32.nxv2i16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x i16> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)1735// CHECK-RV64-NEXT:    ret <vscale x 2 x float> [[TMP0]]1736//1737vfloat32m1_t test_vfwcvt_f_xu_v_f32m1_mu(vbool32_t mask, vfloat32m1_t maskedoff, vuint16mf2_t src, size_t vl) {1738  return __riscv_vfwcvt_f_mu(mask, maskedoff, src, vl);1739}1740 1741// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwcvt_f_xu_v_f32m2_mu1742// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1743// CHECK-RV64-NEXT:  entry:1744// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv4f32.nxv4i16.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x i16> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)1745// CHECK-RV64-NEXT:    ret <vscale x 4 x float> [[TMP0]]1746//1747vfloat32m2_t test_vfwcvt_f_xu_v_f32m2_mu(vbool16_t mask, vfloat32m2_t maskedoff, vuint16m1_t src, size_t vl) {1748  return __riscv_vfwcvt_f_mu(mask, maskedoff, src, vl);1749}1750 1751// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwcvt_f_xu_v_f32m4_mu1752// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1753// CHECK-RV64-NEXT:  entry:1754// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv8f32.nxv8i16.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x i16> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)1755// CHECK-RV64-NEXT:    ret <vscale x 8 x float> [[TMP0]]1756//1757vfloat32m4_t test_vfwcvt_f_xu_v_f32m4_mu(vbool8_t mask, vfloat32m4_t maskedoff, vuint16m2_t src, size_t vl) {1758  return __riscv_vfwcvt_f_mu(mask, maskedoff, src, vl);1759}1760 1761// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwcvt_f_xu_v_f32m8_mu1762// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1763// CHECK-RV64-NEXT:  entry:1764// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv16f32.nxv16i16.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x i16> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)1765// CHECK-RV64-NEXT:    ret <vscale x 16 x float> [[TMP0]]1766//1767vfloat32m8_t test_vfwcvt_f_xu_v_f32m8_mu(vbool4_t mask, vfloat32m8_t maskedoff, vuint16m4_t src, size_t vl) {1768  return __riscv_vfwcvt_f_mu(mask, maskedoff, src, vl);1769}1770 1771// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfwcvt_x_f_v_i64m1_mu1772// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1773// CHECK-RV64-NEXT:  entry:1774// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.x.f.v.mask.nxv1i64.nxv1f32.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x float> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1775// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]1776//1777vint64m1_t test_vfwcvt_x_f_v_i64m1_mu(vbool64_t mask, vint64m1_t maskedoff, vfloat32mf2_t src, size_t vl) {1778  return __riscv_vfwcvt_x_mu(mask, maskedoff, src, vl);1779}1780 1781// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfwcvt_x_f_v_i64m2_mu1782// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1783// CHECK-RV64-NEXT:  entry:1784// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.x.f.v.mask.nxv2i64.nxv2f32.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x float> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1785// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]1786//1787vint64m2_t test_vfwcvt_x_f_v_i64m2_mu(vbool32_t mask, vint64m2_t maskedoff, vfloat32m1_t src, size_t vl) {1788  return __riscv_vfwcvt_x_mu(mask, maskedoff, src, vl);1789}1790 1791// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfwcvt_x_f_v_i64m4_mu1792// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1793// CHECK-RV64-NEXT:  entry:1794// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.x.f.v.mask.nxv4i64.nxv4f32.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x float> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1795// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]1796//1797vint64m4_t test_vfwcvt_x_f_v_i64m4_mu(vbool16_t mask, vint64m4_t maskedoff, vfloat32m2_t src, size_t vl) {1798  return __riscv_vfwcvt_x_mu(mask, maskedoff, src, vl);1799}1800 1801// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfwcvt_x_f_v_i64m8_mu1802// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1803// CHECK-RV64-NEXT:  entry:1804// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.x.f.v.mask.nxv8i64.nxv8f32.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x float> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1805// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]1806//1807vint64m8_t test_vfwcvt_x_f_v_i64m8_mu(vbool8_t mask, vint64m8_t maskedoff, vfloat32m4_t src, size_t vl) {1808  return __riscv_vfwcvt_x_mu(mask, maskedoff, src, vl);1809}1810 1811// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfwcvt_xu_f_v_u64m1_mu1812// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1813// CHECK-RV64-NEXT:  entry:1814// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv1i64.nxv1f32.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x float> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1815// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]1816//1817vuint64m1_t test_vfwcvt_xu_f_v_u64m1_mu(vbool64_t mask, vuint64m1_t maskedoff, vfloat32mf2_t src, size_t vl) {1818  return __riscv_vfwcvt_xu_mu(mask, maskedoff, src, vl);1819}1820 1821// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfwcvt_xu_f_v_u64m2_mu1822// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1823// CHECK-RV64-NEXT:  entry:1824// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv2i64.nxv2f32.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x float> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1825// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]1826//1827vuint64m2_t test_vfwcvt_xu_f_v_u64m2_mu(vbool32_t mask, vuint64m2_t maskedoff, vfloat32m1_t src, size_t vl) {1828  return __riscv_vfwcvt_xu_mu(mask, maskedoff, src, vl);1829}1830 1831// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfwcvt_xu_f_v_u64m4_mu1832// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1833// CHECK-RV64-NEXT:  entry:1834// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv4i64.nxv4f32.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x float> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1835// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]1836//1837vuint64m4_t test_vfwcvt_xu_f_v_u64m4_mu(vbool16_t mask, vuint64m4_t maskedoff, vfloat32m2_t src, size_t vl) {1838  return __riscv_vfwcvt_xu_mu(mask, maskedoff, src, vl);1839}1840 1841// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfwcvt_xu_f_v_u64m8_mu1842// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1843// CHECK-RV64-NEXT:  entry:1844// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv8i64.nxv8f32.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x float> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)1845// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]1846//1847vuint64m8_t test_vfwcvt_xu_f_v_u64m8_mu(vbool8_t mask, vuint64m8_t maskedoff, vfloat32m4_t src, size_t vl) {1848  return __riscv_vfwcvt_xu_mu(mask, maskedoff, src, vl);1849}1850 1851// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwcvt_f_x_v_f64m1_mu1852// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1853// CHECK-RV64-NEXT:  entry:1854// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.x.v.mask.nxv1f64.nxv1i32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x i32> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)1855// CHECK-RV64-NEXT:    ret <vscale x 1 x double> [[TMP0]]1856//1857vfloat64m1_t test_vfwcvt_f_x_v_f64m1_mu(vbool64_t mask, vfloat64m1_t maskedoff, vint32mf2_t src, size_t vl) {1858  return __riscv_vfwcvt_f_mu(mask, maskedoff, src, vl);1859}1860 1861// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfwcvt_f_x_v_f64m2_mu1862// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1863// CHECK-RV64-NEXT:  entry:1864// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.x.v.mask.nxv2f64.nxv2i32.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x i32> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)1865// CHECK-RV64-NEXT:    ret <vscale x 2 x double> [[TMP0]]1866//1867vfloat64m2_t test_vfwcvt_f_x_v_f64m2_mu(vbool32_t mask, vfloat64m2_t maskedoff, vint32m1_t src, size_t vl) {1868  return __riscv_vfwcvt_f_mu(mask, maskedoff, src, vl);1869}1870 1871// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfwcvt_f_x_v_f64m4_mu1872// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1873// CHECK-RV64-NEXT:  entry:1874// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.x.v.mask.nxv4f64.nxv4i32.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x i32> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)1875// CHECK-RV64-NEXT:    ret <vscale x 4 x double> [[TMP0]]1876//1877vfloat64m4_t test_vfwcvt_f_x_v_f64m4_mu(vbool16_t mask, vfloat64m4_t maskedoff, vint32m2_t src, size_t vl) {1878  return __riscv_vfwcvt_f_mu(mask, maskedoff, src, vl);1879}1880 1881// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfwcvt_f_x_v_f64m8_mu1882// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1883// CHECK-RV64-NEXT:  entry:1884// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.x.v.mask.nxv8f64.nxv8i32.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x i32> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)1885// CHECK-RV64-NEXT:    ret <vscale x 8 x double> [[TMP0]]1886//1887vfloat64m8_t test_vfwcvt_f_x_v_f64m8_mu(vbool8_t mask, vfloat64m8_t maskedoff, vint32m4_t src, size_t vl) {1888  return __riscv_vfwcvt_f_mu(mask, maskedoff, src, vl);1889}1890 1891// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwcvt_f_xu_v_f64m1_mu1892// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1893// CHECK-RV64-NEXT:  entry:1894// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv1f64.nxv1i32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x i32> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)1895// CHECK-RV64-NEXT:    ret <vscale x 1 x double> [[TMP0]]1896//1897vfloat64m1_t test_vfwcvt_f_xu_v_f64m1_mu(vbool64_t mask, vfloat64m1_t maskedoff, vuint32mf2_t src, size_t vl) {1898  return __riscv_vfwcvt_f_mu(mask, maskedoff, src, vl);1899}1900 1901// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfwcvt_f_xu_v_f64m2_mu1902// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1903// CHECK-RV64-NEXT:  entry:1904// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv2f64.nxv2i32.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x i32> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)1905// CHECK-RV64-NEXT:    ret <vscale x 2 x double> [[TMP0]]1906//1907vfloat64m2_t test_vfwcvt_f_xu_v_f64m2_mu(vbool32_t mask, vfloat64m2_t maskedoff, vuint32m1_t src, size_t vl) {1908  return __riscv_vfwcvt_f_mu(mask, maskedoff, src, vl);1909}1910 1911// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfwcvt_f_xu_v_f64m4_mu1912// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1913// CHECK-RV64-NEXT:  entry:1914// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv4f64.nxv4i32.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x i32> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)1915// CHECK-RV64-NEXT:    ret <vscale x 4 x double> [[TMP0]]1916//1917vfloat64m4_t test_vfwcvt_f_xu_v_f64m4_mu(vbool16_t mask, vfloat64m4_t maskedoff, vuint32m2_t src, size_t vl) {1918  return __riscv_vfwcvt_f_mu(mask, maskedoff, src, vl);1919}1920 1921// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfwcvt_f_xu_v_f64m8_mu1922// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1923// CHECK-RV64-NEXT:  entry:1924// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv8f64.nxv8i32.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x i32> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)1925// CHECK-RV64-NEXT:    ret <vscale x 8 x double> [[TMP0]]1926//1927vfloat64m8_t test_vfwcvt_f_xu_v_f64m8_mu(vbool8_t mask, vfloat64m8_t maskedoff, vuint32m4_t src, size_t vl) {1928  return __riscv_vfwcvt_f_mu(mask, maskedoff, src, vl);1929}1930 1931// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfwcvt_x_f_v_i32mf2_rm_tu1932// CHECK-RV64-SAME: (<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1933// CHECK-RV64-NEXT:  entry:1934// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.x.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x half> [[SRC]], i64 0, i64 [[VL]])1935// CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]1936//1937vint32mf2_t test_vfwcvt_x_f_v_i32mf2_rm_tu(vint32mf2_t maskedoff, vfloat16mf4_t src, size_t vl) {1938  return __riscv_vfwcvt_x_tu(maskedoff, src, __RISCV_FRM_RNE, vl);1939}1940 1941// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfwcvt_x_f_v_i32m1_rm_tu1942// CHECK-RV64-SAME: (<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1943// CHECK-RV64-NEXT:  entry:1944// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.x.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x half> [[SRC]], i64 0, i64 [[VL]])1945// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]1946//1947vint32m1_t test_vfwcvt_x_f_v_i32m1_rm_tu(vint32m1_t maskedoff, vfloat16mf2_t src, size_t vl) {1948  return __riscv_vfwcvt_x_tu(maskedoff, src, __RISCV_FRM_RNE, vl);1949}1950 1951// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfwcvt_x_f_v_i32m2_rm_tu1952// CHECK-RV64-SAME: (<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1953// CHECK-RV64-NEXT:  entry:1954// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.x.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x half> [[SRC]], i64 0, i64 [[VL]])1955// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]1956//1957vint32m2_t test_vfwcvt_x_f_v_i32m2_rm_tu(vint32m2_t maskedoff, vfloat16m1_t src, size_t vl) {1958  return __riscv_vfwcvt_x_tu(maskedoff, src, __RISCV_FRM_RNE, vl);1959}1960 1961// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfwcvt_x_f_v_i32m4_rm_tu1962// CHECK-RV64-SAME: (<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1963// CHECK-RV64-NEXT:  entry:1964// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.x.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x half> [[SRC]], i64 0, i64 [[VL]])1965// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]1966//1967vint32m4_t test_vfwcvt_x_f_v_i32m4_rm_tu(vint32m4_t maskedoff, vfloat16m2_t src, size_t vl) {1968  return __riscv_vfwcvt_x_tu(maskedoff, src, __RISCV_FRM_RNE, vl);1969}1970 1971// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfwcvt_x_f_v_i32m8_rm_tu1972// CHECK-RV64-SAME: (<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1973// CHECK-RV64-NEXT:  entry:1974// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.x.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x half> [[SRC]], i64 0, i64 [[VL]])1975// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]1976//1977vint32m8_t test_vfwcvt_x_f_v_i32m8_rm_tu(vint32m8_t maskedoff, vfloat16m4_t src, size_t vl) {1978  return __riscv_vfwcvt_x_tu(maskedoff, src, __RISCV_FRM_RNE, vl);1979}1980 1981// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfwcvt_xu_f_v_u32mf2_rm_tu1982// CHECK-RV64-SAME: (<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1983// CHECK-RV64-NEXT:  entry:1984// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.xu.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x half> [[SRC]], i64 0, i64 [[VL]])1985// CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]1986//1987vuint32mf2_t test_vfwcvt_xu_f_v_u32mf2_rm_tu(vuint32mf2_t maskedoff, vfloat16mf4_t src, size_t vl) {1988  return __riscv_vfwcvt_xu_tu(maskedoff, src, __RISCV_FRM_RNE, vl);1989}1990 1991// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfwcvt_xu_f_v_u32m1_rm_tu1992// CHECK-RV64-SAME: (<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1993// CHECK-RV64-NEXT:  entry:1994// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.xu.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x half> [[SRC]], i64 0, i64 [[VL]])1995// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]1996//1997vuint32m1_t test_vfwcvt_xu_f_v_u32m1_rm_tu(vuint32m1_t maskedoff, vfloat16mf2_t src, size_t vl) {1998  return __riscv_vfwcvt_xu_tu(maskedoff, src, __RISCV_FRM_RNE, vl);1999}2000 2001// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfwcvt_xu_f_v_u32m2_rm_tu2002// CHECK-RV64-SAME: (<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2003// CHECK-RV64-NEXT:  entry:2004// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.xu.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x half> [[SRC]], i64 0, i64 [[VL]])2005// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]2006//2007vuint32m2_t test_vfwcvt_xu_f_v_u32m2_rm_tu(vuint32m2_t maskedoff, vfloat16m1_t src, size_t vl) {2008  return __riscv_vfwcvt_xu_tu(maskedoff, src, __RISCV_FRM_RNE, vl);2009}2010 2011// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfwcvt_xu_f_v_u32m4_rm_tu2012// CHECK-RV64-SAME: (<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2013// CHECK-RV64-NEXT:  entry:2014// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.xu.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x half> [[SRC]], i64 0, i64 [[VL]])2015// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]2016//2017vuint32m4_t test_vfwcvt_xu_f_v_u32m4_rm_tu(vuint32m4_t maskedoff, vfloat16m2_t src, size_t vl) {2018  return __riscv_vfwcvt_xu_tu(maskedoff, src, __RISCV_FRM_RNE, vl);2019}2020 2021// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfwcvt_xu_f_v_u32m8_rm_tu2022// CHECK-RV64-SAME: (<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2023// CHECK-RV64-NEXT:  entry:2024// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.xu.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x half> [[SRC]], i64 0, i64 [[VL]])2025// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]2026//2027vuint32m8_t test_vfwcvt_xu_f_v_u32m8_rm_tu(vuint32m8_t maskedoff, vfloat16m4_t src, size_t vl) {2028  return __riscv_vfwcvt_xu_tu(maskedoff, src, __RISCV_FRM_RNE, vl);2029}2030 2031// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfwcvt_x_f_v_i64m1_rm_tu2032// CHECK-RV64-SAME: (<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2033// CHECK-RV64-NEXT:  entry:2034// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv1i64.nxv1f32.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x float> [[SRC]], i64 0, i64 [[VL]])2035// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]2036//2037vint64m1_t test_vfwcvt_x_f_v_i64m1_rm_tu(vint64m1_t maskedoff, vfloat32mf2_t src, size_t vl) {2038  return __riscv_vfwcvt_x_tu(maskedoff, src, __RISCV_FRM_RNE, vl);2039}2040 2041// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfwcvt_x_f_v_i64m2_rm_tu2042// CHECK-RV64-SAME: (<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2043// CHECK-RV64-NEXT:  entry:2044// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv2i64.nxv2f32.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x float> [[SRC]], i64 0, i64 [[VL]])2045// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]2046//2047vint64m2_t test_vfwcvt_x_f_v_i64m2_rm_tu(vint64m2_t maskedoff, vfloat32m1_t src, size_t vl) {2048  return __riscv_vfwcvt_x_tu(maskedoff, src, __RISCV_FRM_RNE, vl);2049}2050 2051// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfwcvt_x_f_v_i64m4_rm_tu2052// CHECK-RV64-SAME: (<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2053// CHECK-RV64-NEXT:  entry:2054// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv4i64.nxv4f32.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x float> [[SRC]], i64 0, i64 [[VL]])2055// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]2056//2057vint64m4_t test_vfwcvt_x_f_v_i64m4_rm_tu(vint64m4_t maskedoff, vfloat32m2_t src, size_t vl) {2058  return __riscv_vfwcvt_x_tu(maskedoff, src, __RISCV_FRM_RNE, vl);2059}2060 2061// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfwcvt_x_f_v_i64m8_rm_tu2062// CHECK-RV64-SAME: (<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2063// CHECK-RV64-NEXT:  entry:2064// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv8i64.nxv8f32.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x float> [[SRC]], i64 0, i64 [[VL]])2065// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]2066//2067vint64m8_t test_vfwcvt_x_f_v_i64m8_rm_tu(vint64m8_t maskedoff, vfloat32m4_t src, size_t vl) {2068  return __riscv_vfwcvt_x_tu(maskedoff, src, __RISCV_FRM_RNE, vl);2069}2070 2071// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfwcvt_xu_f_v_u64m1_rm_tu2072// CHECK-RV64-SAME: (<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2073// CHECK-RV64-NEXT:  entry:2074// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv1i64.nxv1f32.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x float> [[SRC]], i64 0, i64 [[VL]])2075// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]2076//2077vuint64m1_t test_vfwcvt_xu_f_v_u64m1_rm_tu(vuint64m1_t maskedoff, vfloat32mf2_t src, size_t vl) {2078  return __riscv_vfwcvt_xu_tu(maskedoff, src, __RISCV_FRM_RNE, vl);2079}2080 2081// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfwcvt_xu_f_v_u64m2_rm_tu2082// CHECK-RV64-SAME: (<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2083// CHECK-RV64-NEXT:  entry:2084// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv2i64.nxv2f32.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x float> [[SRC]], i64 0, i64 [[VL]])2085// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]2086//2087vuint64m2_t test_vfwcvt_xu_f_v_u64m2_rm_tu(vuint64m2_t maskedoff, vfloat32m1_t src, size_t vl) {2088  return __riscv_vfwcvt_xu_tu(maskedoff, src, __RISCV_FRM_RNE, vl);2089}2090 2091// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfwcvt_xu_f_v_u64m4_rm_tu2092// CHECK-RV64-SAME: (<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2093// CHECK-RV64-NEXT:  entry:2094// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv4i64.nxv4f32.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x float> [[SRC]], i64 0, i64 [[VL]])2095// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]2096//2097vuint64m4_t test_vfwcvt_xu_f_v_u64m4_rm_tu(vuint64m4_t maskedoff, vfloat32m2_t src, size_t vl) {2098  return __riscv_vfwcvt_xu_tu(maskedoff, src, __RISCV_FRM_RNE, vl);2099}2100 2101// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfwcvt_xu_f_v_u64m8_rm_tu2102// CHECK-RV64-SAME: (<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2103// CHECK-RV64-NEXT:  entry:2104// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv8i64.nxv8f32.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x float> [[SRC]], i64 0, i64 [[VL]])2105// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]2106//2107vuint64m8_t test_vfwcvt_xu_f_v_u64m8_rm_tu(vuint64m8_t maskedoff, vfloat32m4_t src, size_t vl) {2108  return __riscv_vfwcvt_xu_tu(maskedoff, src, __RISCV_FRM_RNE, vl);2109}2110 2111// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfwcvt_x_f_v_i32mf2_rm_tum2112// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2113// CHECK-RV64-NEXT:  entry:2114// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.x.f.v.mask.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x half> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2115// CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]2116//2117vint32mf2_t test_vfwcvt_x_f_v_i32mf2_rm_tum(vbool64_t mask, vint32mf2_t maskedoff, vfloat16mf4_t src, size_t vl) {2118  return __riscv_vfwcvt_x_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2119}2120 2121// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfwcvt_x_f_v_i32m1_rm_tum2122// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2123// CHECK-RV64-NEXT:  entry:2124// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.x.f.v.mask.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x half> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2125// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]2126//2127vint32m1_t test_vfwcvt_x_f_v_i32m1_rm_tum(vbool32_t mask, vint32m1_t maskedoff, vfloat16mf2_t src, size_t vl) {2128  return __riscv_vfwcvt_x_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2129}2130 2131// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfwcvt_x_f_v_i32m2_rm_tum2132// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2133// CHECK-RV64-NEXT:  entry:2134// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.x.f.v.mask.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x half> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2135// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]2136//2137vint32m2_t test_vfwcvt_x_f_v_i32m2_rm_tum(vbool16_t mask, vint32m2_t maskedoff, vfloat16m1_t src, size_t vl) {2138  return __riscv_vfwcvt_x_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2139}2140 2141// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfwcvt_x_f_v_i32m4_rm_tum2142// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2143// CHECK-RV64-NEXT:  entry:2144// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.x.f.v.mask.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x half> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2145// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]2146//2147vint32m4_t test_vfwcvt_x_f_v_i32m4_rm_tum(vbool8_t mask, vint32m4_t maskedoff, vfloat16m2_t src, size_t vl) {2148  return __riscv_vfwcvt_x_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2149}2150 2151// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfwcvt_x_f_v_i32m8_rm_tum2152// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2153// CHECK-RV64-NEXT:  entry:2154// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.x.f.v.mask.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x half> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2155// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]2156//2157vint32m8_t test_vfwcvt_x_f_v_i32m8_rm_tum(vbool4_t mask, vint32m8_t maskedoff, vfloat16m4_t src, size_t vl) {2158  return __riscv_vfwcvt_x_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2159}2160 2161// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfwcvt_xu_f_v_u32mf2_rm_tum2162// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2163// CHECK-RV64-NEXT:  entry:2164// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x half> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2165// CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]2166//2167vuint32mf2_t test_vfwcvt_xu_f_v_u32mf2_rm_tum(vbool64_t mask, vuint32mf2_t maskedoff, vfloat16mf4_t src, size_t vl) {2168  return __riscv_vfwcvt_xu_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2169}2170 2171// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfwcvt_xu_f_v_u32m1_rm_tum2172// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2173// CHECK-RV64-NEXT:  entry:2174// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x half> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2175// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]2176//2177vuint32m1_t test_vfwcvt_xu_f_v_u32m1_rm_tum(vbool32_t mask, vuint32m1_t maskedoff, vfloat16mf2_t src, size_t vl) {2178  return __riscv_vfwcvt_xu_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2179}2180 2181// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfwcvt_xu_f_v_u32m2_rm_tum2182// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2183// CHECK-RV64-NEXT:  entry:2184// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x half> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2185// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]2186//2187vuint32m2_t test_vfwcvt_xu_f_v_u32m2_rm_tum(vbool16_t mask, vuint32m2_t maskedoff, vfloat16m1_t src, size_t vl) {2188  return __riscv_vfwcvt_xu_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2189}2190 2191// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfwcvt_xu_f_v_u32m4_rm_tum2192// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2193// CHECK-RV64-NEXT:  entry:2194// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x half> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2195// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]2196//2197vuint32m4_t test_vfwcvt_xu_f_v_u32m4_rm_tum(vbool8_t mask, vuint32m4_t maskedoff, vfloat16m2_t src, size_t vl) {2198  return __riscv_vfwcvt_xu_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2199}2200 2201// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfwcvt_xu_f_v_u32m8_rm_tum2202// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2203// CHECK-RV64-NEXT:  entry:2204// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x half> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2205// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]2206//2207vuint32m8_t test_vfwcvt_xu_f_v_u32m8_rm_tum(vbool4_t mask, vuint32m8_t maskedoff, vfloat16m4_t src, size_t vl) {2208  return __riscv_vfwcvt_xu_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2209}2210 2211// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfwcvt_x_f_v_i64m1_rm_tum2212// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2213// CHECK-RV64-NEXT:  entry:2214// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.x.f.v.mask.nxv1i64.nxv1f32.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x float> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2215// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]2216//2217vint64m1_t test_vfwcvt_x_f_v_i64m1_rm_tum(vbool64_t mask, vint64m1_t maskedoff, vfloat32mf2_t src, size_t vl) {2218  return __riscv_vfwcvt_x_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2219}2220 2221// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfwcvt_x_f_v_i64m2_rm_tum2222// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2223// CHECK-RV64-NEXT:  entry:2224// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.x.f.v.mask.nxv2i64.nxv2f32.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x float> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2225// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]2226//2227vint64m2_t test_vfwcvt_x_f_v_i64m2_rm_tum(vbool32_t mask, vint64m2_t maskedoff, vfloat32m1_t src, size_t vl) {2228  return __riscv_vfwcvt_x_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2229}2230 2231// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfwcvt_x_f_v_i64m4_rm_tum2232// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2233// CHECK-RV64-NEXT:  entry:2234// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.x.f.v.mask.nxv4i64.nxv4f32.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x float> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2235// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]2236//2237vint64m4_t test_vfwcvt_x_f_v_i64m4_rm_tum(vbool16_t mask, vint64m4_t maskedoff, vfloat32m2_t src, size_t vl) {2238  return __riscv_vfwcvt_x_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2239}2240 2241// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfwcvt_x_f_v_i64m8_rm_tum2242// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2243// CHECK-RV64-NEXT:  entry:2244// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.x.f.v.mask.nxv8i64.nxv8f32.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x float> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2245// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]2246//2247vint64m8_t test_vfwcvt_x_f_v_i64m8_rm_tum(vbool8_t mask, vint64m8_t maskedoff, vfloat32m4_t src, size_t vl) {2248  return __riscv_vfwcvt_x_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2249}2250 2251// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfwcvt_xu_f_v_u64m1_rm_tum2252// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2253// CHECK-RV64-NEXT:  entry:2254// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv1i64.nxv1f32.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x float> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2255// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]2256//2257vuint64m1_t test_vfwcvt_xu_f_v_u64m1_rm_tum(vbool64_t mask, vuint64m1_t maskedoff, vfloat32mf2_t src, size_t vl) {2258  return __riscv_vfwcvt_xu_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2259}2260 2261// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfwcvt_xu_f_v_u64m2_rm_tum2262// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2263// CHECK-RV64-NEXT:  entry:2264// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv2i64.nxv2f32.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x float> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2265// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]2266//2267vuint64m2_t test_vfwcvt_xu_f_v_u64m2_rm_tum(vbool32_t mask, vuint64m2_t maskedoff, vfloat32m1_t src, size_t vl) {2268  return __riscv_vfwcvt_xu_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2269}2270 2271// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfwcvt_xu_f_v_u64m4_rm_tum2272// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2273// CHECK-RV64-NEXT:  entry:2274// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv4i64.nxv4f32.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x float> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2275// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]2276//2277vuint64m4_t test_vfwcvt_xu_f_v_u64m4_rm_tum(vbool16_t mask, vuint64m4_t maskedoff, vfloat32m2_t src, size_t vl) {2278  return __riscv_vfwcvt_xu_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2279}2280 2281// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfwcvt_xu_f_v_u64m8_rm_tum2282// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2283// CHECK-RV64-NEXT:  entry:2284// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv8i64.nxv8f32.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x float> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)2285// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]2286//2287vuint64m8_t test_vfwcvt_xu_f_v_u64m8_rm_tum(vbool8_t mask, vuint64m8_t maskedoff, vfloat32m4_t src, size_t vl) {2288  return __riscv_vfwcvt_xu_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2289}2290 2291// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfwcvt_x_f_v_i32mf2_rm_tumu2292// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2293// CHECK-RV64-NEXT:  entry:2294// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.x.f.v.mask.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x half> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)2295// CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]2296//2297vint32mf2_t test_vfwcvt_x_f_v_i32mf2_rm_tumu(vbool64_t mask, vint32mf2_t maskedoff, vfloat16mf4_t src, size_t vl) {2298  return __riscv_vfwcvt_x_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2299}2300 2301// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfwcvt_x_f_v_i32m1_rm_tumu2302// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2303// CHECK-RV64-NEXT:  entry:2304// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.x.f.v.mask.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x half> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)2305// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]2306//2307vint32m1_t test_vfwcvt_x_f_v_i32m1_rm_tumu(vbool32_t mask, vint32m1_t maskedoff, vfloat16mf2_t src, size_t vl) {2308  return __riscv_vfwcvt_x_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2309}2310 2311// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfwcvt_x_f_v_i32m2_rm_tumu2312// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2313// CHECK-RV64-NEXT:  entry:2314// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.x.f.v.mask.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x half> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)2315// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]2316//2317vint32m2_t test_vfwcvt_x_f_v_i32m2_rm_tumu(vbool16_t mask, vint32m2_t maskedoff, vfloat16m1_t src, size_t vl) {2318  return __riscv_vfwcvt_x_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2319}2320 2321// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfwcvt_x_f_v_i32m4_rm_tumu2322// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2323// CHECK-RV64-NEXT:  entry:2324// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.x.f.v.mask.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x half> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)2325// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]2326//2327vint32m4_t test_vfwcvt_x_f_v_i32m4_rm_tumu(vbool8_t mask, vint32m4_t maskedoff, vfloat16m2_t src, size_t vl) {2328  return __riscv_vfwcvt_x_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2329}2330 2331// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfwcvt_x_f_v_i32m8_rm_tumu2332// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2333// CHECK-RV64-NEXT:  entry:2334// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.x.f.v.mask.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x half> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)2335// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]2336//2337vint32m8_t test_vfwcvt_x_f_v_i32m8_rm_tumu(vbool4_t mask, vint32m8_t maskedoff, vfloat16m4_t src, size_t vl) {2338  return __riscv_vfwcvt_x_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2339}2340 2341// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfwcvt_xu_f_v_u32mf2_rm_tumu2342// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2343// CHECK-RV64-NEXT:  entry:2344// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x half> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)2345// CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]2346//2347vuint32mf2_t test_vfwcvt_xu_f_v_u32mf2_rm_tumu(vbool64_t mask, vuint32mf2_t maskedoff, vfloat16mf4_t src, size_t vl) {2348  return __riscv_vfwcvt_xu_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2349}2350 2351// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfwcvt_xu_f_v_u32m1_rm_tumu2352// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2353// CHECK-RV64-NEXT:  entry:2354// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x half> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)2355// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]2356//2357vuint32m1_t test_vfwcvt_xu_f_v_u32m1_rm_tumu(vbool32_t mask, vuint32m1_t maskedoff, vfloat16mf2_t src, size_t vl) {2358  return __riscv_vfwcvt_xu_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2359}2360 2361// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfwcvt_xu_f_v_u32m2_rm_tumu2362// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2363// CHECK-RV64-NEXT:  entry:2364// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x half> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)2365// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]2366//2367vuint32m2_t test_vfwcvt_xu_f_v_u32m2_rm_tumu(vbool16_t mask, vuint32m2_t maskedoff, vfloat16m1_t src, size_t vl) {2368  return __riscv_vfwcvt_xu_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2369}2370 2371// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfwcvt_xu_f_v_u32m4_rm_tumu2372// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2373// CHECK-RV64-NEXT:  entry:2374// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x half> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)2375// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]2376//2377vuint32m4_t test_vfwcvt_xu_f_v_u32m4_rm_tumu(vbool8_t mask, vuint32m4_t maskedoff, vfloat16m2_t src, size_t vl) {2378  return __riscv_vfwcvt_xu_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2379}2380 2381// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfwcvt_xu_f_v_u32m8_rm_tumu2382// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2383// CHECK-RV64-NEXT:  entry:2384// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x half> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)2385// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]2386//2387vuint32m8_t test_vfwcvt_xu_f_v_u32m8_rm_tumu(vbool4_t mask, vuint32m8_t maskedoff, vfloat16m4_t src, size_t vl) {2388  return __riscv_vfwcvt_xu_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2389}2390 2391// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfwcvt_x_f_v_i64m1_rm_tumu2392// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2393// CHECK-RV64-NEXT:  entry:2394// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.x.f.v.mask.nxv1i64.nxv1f32.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x float> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)2395// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]2396//2397vint64m1_t test_vfwcvt_x_f_v_i64m1_rm_tumu(vbool64_t mask, vint64m1_t maskedoff, vfloat32mf2_t src, size_t vl) {2398  return __riscv_vfwcvt_x_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2399}2400 2401// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfwcvt_x_f_v_i64m2_rm_tumu2402// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2403// CHECK-RV64-NEXT:  entry:2404// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.x.f.v.mask.nxv2i64.nxv2f32.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x float> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)2405// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]2406//2407vint64m2_t test_vfwcvt_x_f_v_i64m2_rm_tumu(vbool32_t mask, vint64m2_t maskedoff, vfloat32m1_t src, size_t vl) {2408  return __riscv_vfwcvt_x_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2409}2410 2411// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfwcvt_x_f_v_i64m4_rm_tumu2412// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2413// CHECK-RV64-NEXT:  entry:2414// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.x.f.v.mask.nxv4i64.nxv4f32.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x float> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)2415// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]2416//2417vint64m4_t test_vfwcvt_x_f_v_i64m4_rm_tumu(vbool16_t mask, vint64m4_t maskedoff, vfloat32m2_t src, size_t vl) {2418  return __riscv_vfwcvt_x_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2419}2420 2421// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfwcvt_x_f_v_i64m8_rm_tumu2422// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2423// CHECK-RV64-NEXT:  entry:2424// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.x.f.v.mask.nxv8i64.nxv8f32.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x float> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)2425// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]2426//2427vint64m8_t test_vfwcvt_x_f_v_i64m8_rm_tumu(vbool8_t mask, vint64m8_t maskedoff, vfloat32m4_t src, size_t vl) {2428  return __riscv_vfwcvt_x_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2429}2430 2431// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfwcvt_xu_f_v_u64m1_rm_tumu2432// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2433// CHECK-RV64-NEXT:  entry:2434// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv1i64.nxv1f32.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x float> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)2435// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]2436//2437vuint64m1_t test_vfwcvt_xu_f_v_u64m1_rm_tumu(vbool64_t mask, vuint64m1_t maskedoff, vfloat32mf2_t src, size_t vl) {2438  return __riscv_vfwcvt_xu_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2439}2440 2441// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfwcvt_xu_f_v_u64m2_rm_tumu2442// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2443// CHECK-RV64-NEXT:  entry:2444// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv2i64.nxv2f32.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x float> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)2445// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]2446//2447vuint64m2_t test_vfwcvt_xu_f_v_u64m2_rm_tumu(vbool32_t mask, vuint64m2_t maskedoff, vfloat32m1_t src, size_t vl) {2448  return __riscv_vfwcvt_xu_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2449}2450 2451// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfwcvt_xu_f_v_u64m4_rm_tumu2452// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2453// CHECK-RV64-NEXT:  entry:2454// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv4i64.nxv4f32.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x float> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)2455// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]2456//2457vuint64m4_t test_vfwcvt_xu_f_v_u64m4_rm_tumu(vbool16_t mask, vuint64m4_t maskedoff, vfloat32m2_t src, size_t vl) {2458  return __riscv_vfwcvt_xu_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2459}2460 2461// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfwcvt_xu_f_v_u64m8_rm_tumu2462// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2463// CHECK-RV64-NEXT:  entry:2464// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv8i64.nxv8f32.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x float> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)2465// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]2466//2467vuint64m8_t test_vfwcvt_xu_f_v_u64m8_rm_tumu(vbool8_t mask, vuint64m8_t maskedoff, vfloat32m4_t src, size_t vl) {2468  return __riscv_vfwcvt_xu_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2469}2470 2471// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfwcvt_x_f_v_i32mf2_rm_mu2472// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2473// CHECK-RV64-NEXT:  entry:2474// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.x.f.v.mask.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x half> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)2475// CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]2476//2477vint32mf2_t test_vfwcvt_x_f_v_i32mf2_rm_mu(vbool64_t mask, vint32mf2_t maskedoff, vfloat16mf4_t src, size_t vl) {2478  return __riscv_vfwcvt_x_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2479}2480 2481// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfwcvt_x_f_v_i32m1_rm_mu2482// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2483// CHECK-RV64-NEXT:  entry:2484// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.x.f.v.mask.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x half> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)2485// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]2486//2487vint32m1_t test_vfwcvt_x_f_v_i32m1_rm_mu(vbool32_t mask, vint32m1_t maskedoff, vfloat16mf2_t src, size_t vl) {2488  return __riscv_vfwcvt_x_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2489}2490 2491// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfwcvt_x_f_v_i32m2_rm_mu2492// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2493// CHECK-RV64-NEXT:  entry:2494// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.x.f.v.mask.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x half> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)2495// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]2496//2497vint32m2_t test_vfwcvt_x_f_v_i32m2_rm_mu(vbool16_t mask, vint32m2_t maskedoff, vfloat16m1_t src, size_t vl) {2498  return __riscv_vfwcvt_x_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2499}2500 2501// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfwcvt_x_f_v_i32m4_rm_mu2502// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2503// CHECK-RV64-NEXT:  entry:2504// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.x.f.v.mask.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x half> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)2505// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]2506//2507vint32m4_t test_vfwcvt_x_f_v_i32m4_rm_mu(vbool8_t mask, vint32m4_t maskedoff, vfloat16m2_t src, size_t vl) {2508  return __riscv_vfwcvt_x_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2509}2510 2511// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfwcvt_x_f_v_i32m8_rm_mu2512// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2513// CHECK-RV64-NEXT:  entry:2514// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.x.f.v.mask.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x half> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)2515// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]2516//2517vint32m8_t test_vfwcvt_x_f_v_i32m8_rm_mu(vbool4_t mask, vint32m8_t maskedoff, vfloat16m4_t src, size_t vl) {2518  return __riscv_vfwcvt_x_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2519}2520 2521// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfwcvt_xu_f_v_u32mf2_rm_mu2522// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2523// CHECK-RV64-NEXT:  entry:2524// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x half> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)2525// CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]2526//2527vuint32mf2_t test_vfwcvt_xu_f_v_u32mf2_rm_mu(vbool64_t mask, vuint32mf2_t maskedoff, vfloat16mf4_t src, size_t vl) {2528  return __riscv_vfwcvt_xu_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2529}2530 2531// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfwcvt_xu_f_v_u32m1_rm_mu2532// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2533// CHECK-RV64-NEXT:  entry:2534// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x half> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)2535// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]2536//2537vuint32m1_t test_vfwcvt_xu_f_v_u32m1_rm_mu(vbool32_t mask, vuint32m1_t maskedoff, vfloat16mf2_t src, size_t vl) {2538  return __riscv_vfwcvt_xu_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2539}2540 2541// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfwcvt_xu_f_v_u32m2_rm_mu2542// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2543// CHECK-RV64-NEXT:  entry:2544// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x half> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)2545// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]2546//2547vuint32m2_t test_vfwcvt_xu_f_v_u32m2_rm_mu(vbool16_t mask, vuint32m2_t maskedoff, vfloat16m1_t src, size_t vl) {2548  return __riscv_vfwcvt_xu_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2549}2550 2551// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfwcvt_xu_f_v_u32m4_rm_mu2552// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2553// CHECK-RV64-NEXT:  entry:2554// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x half> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)2555// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]2556//2557vuint32m4_t test_vfwcvt_xu_f_v_u32m4_rm_mu(vbool8_t mask, vuint32m4_t maskedoff, vfloat16m2_t src, size_t vl) {2558  return __riscv_vfwcvt_xu_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2559}2560 2561// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfwcvt_xu_f_v_u32m8_rm_mu2562// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2563// CHECK-RV64-NEXT:  entry:2564// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x half> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)2565// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]2566//2567vuint32m8_t test_vfwcvt_xu_f_v_u32m8_rm_mu(vbool4_t mask, vuint32m8_t maskedoff, vfloat16m4_t src, size_t vl) {2568  return __riscv_vfwcvt_xu_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2569}2570 2571// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfwcvt_x_f_v_i64m1_rm_mu2572// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2573// CHECK-RV64-NEXT:  entry:2574// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.x.f.v.mask.nxv1i64.nxv1f32.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x float> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)2575// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]2576//2577vint64m1_t test_vfwcvt_x_f_v_i64m1_rm_mu(vbool64_t mask, vint64m1_t maskedoff, vfloat32mf2_t src, size_t vl) {2578  return __riscv_vfwcvt_x_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2579}2580 2581// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfwcvt_x_f_v_i64m2_rm_mu2582// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2583// CHECK-RV64-NEXT:  entry:2584// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.x.f.v.mask.nxv2i64.nxv2f32.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x float> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)2585// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]2586//2587vint64m2_t test_vfwcvt_x_f_v_i64m2_rm_mu(vbool32_t mask, vint64m2_t maskedoff, vfloat32m1_t src, size_t vl) {2588  return __riscv_vfwcvt_x_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2589}2590 2591// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfwcvt_x_f_v_i64m4_rm_mu2592// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2593// CHECK-RV64-NEXT:  entry:2594// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.x.f.v.mask.nxv4i64.nxv4f32.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x float> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)2595// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]2596//2597vint64m4_t test_vfwcvt_x_f_v_i64m4_rm_mu(vbool16_t mask, vint64m4_t maskedoff, vfloat32m2_t src, size_t vl) {2598  return __riscv_vfwcvt_x_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2599}2600 2601// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfwcvt_x_f_v_i64m8_rm_mu2602// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2603// CHECK-RV64-NEXT:  entry:2604// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.x.f.v.mask.nxv8i64.nxv8f32.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x float> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)2605// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]2606//2607vint64m8_t test_vfwcvt_x_f_v_i64m8_rm_mu(vbool8_t mask, vint64m8_t maskedoff, vfloat32m4_t src, size_t vl) {2608  return __riscv_vfwcvt_x_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2609}2610 2611// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfwcvt_xu_f_v_u64m1_rm_mu2612// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2613// CHECK-RV64-NEXT:  entry:2614// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv1i64.nxv1f32.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x float> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)2615// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]2616//2617vuint64m1_t test_vfwcvt_xu_f_v_u64m1_rm_mu(vbool64_t mask, vuint64m1_t maskedoff, vfloat32mf2_t src, size_t vl) {2618  return __riscv_vfwcvt_xu_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2619}2620 2621// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfwcvt_xu_f_v_u64m2_rm_mu2622// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2623// CHECK-RV64-NEXT:  entry:2624// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv2i64.nxv2f32.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x float> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)2625// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]2626//2627vuint64m2_t test_vfwcvt_xu_f_v_u64m2_rm_mu(vbool32_t mask, vuint64m2_t maskedoff, vfloat32m1_t src, size_t vl) {2628  return __riscv_vfwcvt_xu_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2629}2630 2631// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfwcvt_xu_f_v_u64m4_rm_mu2632// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2633// CHECK-RV64-NEXT:  entry:2634// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv4i64.nxv4f32.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x float> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)2635// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]2636//2637vuint64m4_t test_vfwcvt_xu_f_v_u64m4_rm_mu(vbool16_t mask, vuint64m4_t maskedoff, vfloat32m2_t src, size_t vl) {2638  return __riscv_vfwcvt_xu_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2639}2640 2641// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfwcvt_xu_f_v_u64m8_rm_mu2642// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2643// CHECK-RV64-NEXT:  entry:2644// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv8i64.nxv8f32.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x float> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)2645// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]2646//2647vuint64m8_t test_vfwcvt_xu_f_v_u64m8_rm_mu(vbool8_t mask, vuint64m8_t maskedoff, vfloat32m4_t src, size_t vl) {2648  return __riscv_vfwcvt_xu_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);2649}2650 2651