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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 22// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone \4// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \5// RUN: FileCheck --check-prefix=CHECK-RV64 %s6 7#include <riscv_vector.h>8 9// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vid_v_u8mf8_tu10// CHECK-RV64-SAME: (<vscale x 1 x i8> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {11// CHECK-RV64-NEXT: entry:12// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF]], i64 [[VL]])13// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]14//15vuint8mf8_t test_vid_v_u8mf8_tu(vuint8mf8_t maskedoff, size_t vl) {16 return __riscv_vid_tu(maskedoff, vl);17}18 19// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vid_v_u8mf4_tu20// CHECK-RV64-SAME: (<vscale x 2 x i8> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {21// CHECK-RV64-NEXT: entry:22// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vid.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF]], i64 [[VL]])23// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]24//25vuint8mf4_t test_vid_v_u8mf4_tu(vuint8mf4_t maskedoff, size_t vl) {26 return __riscv_vid_tu(maskedoff, vl);27}28 29// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vid_v_u8mf2_tu30// CHECK-RV64-SAME: (<vscale x 4 x i8> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {31// CHECK-RV64-NEXT: entry:32// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vid.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF]], i64 [[VL]])33// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]34//35vuint8mf2_t test_vid_v_u8mf2_tu(vuint8mf2_t maskedoff, size_t vl) {36 return __riscv_vid_tu(maskedoff, vl);37}38 39// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vid_v_u8m1_tu40// CHECK-RV64-SAME: (<vscale x 8 x i8> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {41// CHECK-RV64-NEXT: entry:42// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vid.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF]], i64 [[VL]])43// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]44//45vuint8m1_t test_vid_v_u8m1_tu(vuint8m1_t maskedoff, size_t vl) {46 return __riscv_vid_tu(maskedoff, vl);47}48 49// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vid_v_u8m2_tu50// CHECK-RV64-SAME: (<vscale x 16 x i8> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {51// CHECK-RV64-NEXT: entry:52// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vid.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF]], i64 [[VL]])53// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]54//55vuint8m2_t test_vid_v_u8m2_tu(vuint8m2_t maskedoff, size_t vl) {56 return __riscv_vid_tu(maskedoff, vl);57}58 59// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vid_v_u8m4_tu60// CHECK-RV64-SAME: (<vscale x 32 x i8> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {61// CHECK-RV64-NEXT: entry:62// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vid.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF]], i64 [[VL]])63// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]64//65vuint8m4_t test_vid_v_u8m4_tu(vuint8m4_t maskedoff, size_t vl) {66 return __riscv_vid_tu(maskedoff, vl);67}68 69// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vid_v_u8m8_tu70// CHECK-RV64-SAME: (<vscale x 64 x i8> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {71// CHECK-RV64-NEXT: entry:72// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vid.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF]], i64 [[VL]])73// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]74//75vuint8m8_t test_vid_v_u8m8_tu(vuint8m8_t maskedoff, size_t vl) {76 return __riscv_vid_tu(maskedoff, vl);77}78 79// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vid_v_u16mf4_tu80// CHECK-RV64-SAME: (<vscale x 1 x i16> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {81// CHECK-RV64-NEXT: entry:82// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vid.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF]], i64 [[VL]])83// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]84//85vuint16mf4_t test_vid_v_u16mf4_tu(vuint16mf4_t maskedoff, size_t vl) {86 return __riscv_vid_tu(maskedoff, vl);87}88 89// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vid_v_u16mf2_tu90// CHECK-RV64-SAME: (<vscale x 2 x i16> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {91// CHECK-RV64-NEXT: entry:92// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vid.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF]], i64 [[VL]])93// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]94//95vuint16mf2_t test_vid_v_u16mf2_tu(vuint16mf2_t maskedoff, size_t vl) {96 return __riscv_vid_tu(maskedoff, vl);97}98 99// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vid_v_u16m1_tu100// CHECK-RV64-SAME: (<vscale x 4 x i16> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {101// CHECK-RV64-NEXT: entry:102// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vid.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF]], i64 [[VL]])103// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]104//105vuint16m1_t test_vid_v_u16m1_tu(vuint16m1_t maskedoff, size_t vl) {106 return __riscv_vid_tu(maskedoff, vl);107}108 109// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vid_v_u16m2_tu110// CHECK-RV64-SAME: (<vscale x 8 x i16> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {111// CHECK-RV64-NEXT: entry:112// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vid.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF]], i64 [[VL]])113// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]114//115vuint16m2_t test_vid_v_u16m2_tu(vuint16m2_t maskedoff, size_t vl) {116 return __riscv_vid_tu(maskedoff, vl);117}118 119// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vid_v_u16m4_tu120// CHECK-RV64-SAME: (<vscale x 16 x i16> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {121// CHECK-RV64-NEXT: entry:122// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vid.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF]], i64 [[VL]])123// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]124//125vuint16m4_t test_vid_v_u16m4_tu(vuint16m4_t maskedoff, size_t vl) {126 return __riscv_vid_tu(maskedoff, vl);127}128 129// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vid_v_u16m8_tu130// CHECK-RV64-SAME: (<vscale x 32 x i16> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {131// CHECK-RV64-NEXT: entry:132// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vid.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF]], i64 [[VL]])133// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]134//135vuint16m8_t test_vid_v_u16m8_tu(vuint16m8_t maskedoff, size_t vl) {136 return __riscv_vid_tu(maskedoff, vl);137}138 139// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vid_v_u32mf2_tu140// CHECK-RV64-SAME: (<vscale x 1 x i32> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {141// CHECK-RV64-NEXT: entry:142// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vid.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF]], i64 [[VL]])143// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]144//145vuint32mf2_t test_vid_v_u32mf2_tu(vuint32mf2_t maskedoff, size_t vl) {146 return __riscv_vid_tu(maskedoff, vl);147}148 149// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vid_v_u32m1_tu150// CHECK-RV64-SAME: (<vscale x 2 x i32> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {151// CHECK-RV64-NEXT: entry:152// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vid.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF]], i64 [[VL]])153// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]154//155vuint32m1_t test_vid_v_u32m1_tu(vuint32m1_t maskedoff, size_t vl) {156 return __riscv_vid_tu(maskedoff, vl);157}158 159// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vid_v_u32m2_tu160// CHECK-RV64-SAME: (<vscale x 4 x i32> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {161// CHECK-RV64-NEXT: entry:162// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vid.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF]], i64 [[VL]])163// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]164//165vuint32m2_t test_vid_v_u32m2_tu(vuint32m2_t maskedoff, size_t vl) {166 return __riscv_vid_tu(maskedoff, vl);167}168 169// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vid_v_u32m4_tu170// CHECK-RV64-SAME: (<vscale x 8 x i32> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {171// CHECK-RV64-NEXT: entry:172// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vid.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF]], i64 [[VL]])173// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]174//175vuint32m4_t test_vid_v_u32m4_tu(vuint32m4_t maskedoff, size_t vl) {176 return __riscv_vid_tu(maskedoff, vl);177}178 179// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vid_v_u32m8_tu180// CHECK-RV64-SAME: (<vscale x 16 x i32> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {181// CHECK-RV64-NEXT: entry:182// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vid.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF]], i64 [[VL]])183// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]184//185vuint32m8_t test_vid_v_u32m8_tu(vuint32m8_t maskedoff, size_t vl) {186 return __riscv_vid_tu(maskedoff, vl);187}188 189// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vid_v_u64m1_tu190// CHECK-RV64-SAME: (<vscale x 1 x i64> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {191// CHECK-RV64-NEXT: entry:192// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vid.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF]], i64 [[VL]])193// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]194//195vuint64m1_t test_vid_v_u64m1_tu(vuint64m1_t maskedoff, size_t vl) {196 return __riscv_vid_tu(maskedoff, vl);197}198 199// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vid_v_u64m2_tu200// CHECK-RV64-SAME: (<vscale x 2 x i64> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {201// CHECK-RV64-NEXT: entry:202// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vid.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF]], i64 [[VL]])203// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]204//205vuint64m2_t test_vid_v_u64m2_tu(vuint64m2_t maskedoff, size_t vl) {206 return __riscv_vid_tu(maskedoff, vl);207}208 209// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vid_v_u64m4_tu210// CHECK-RV64-SAME: (<vscale x 4 x i64> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {211// CHECK-RV64-NEXT: entry:212// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vid.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF]], i64 [[VL]])213// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]214//215vuint64m4_t test_vid_v_u64m4_tu(vuint64m4_t maskedoff, size_t vl) {216 return __riscv_vid_tu(maskedoff, vl);217}218 219// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vid_v_u64m8_tu220// CHECK-RV64-SAME: (<vscale x 8 x i64> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {221// CHECK-RV64-NEXT: entry:222// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vid.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF]], i64 [[VL]])223// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]224//225vuint64m8_t test_vid_v_u64m8_tu(vuint64m8_t maskedoff, size_t vl) {226 return __riscv_vid_tu(maskedoff, vl);227}228 229// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vid_v_u8mf8_tum230// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {231// CHECK-RV64-NEXT: entry:232// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vid.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)233// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]234//235vuint8mf8_t test_vid_v_u8mf8_tum(vbool64_t mask, vuint8mf8_t maskedoff, size_t vl) {236 return __riscv_vid_tum(mask, maskedoff, vl);237}238 239// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vid_v_u8mf4_tum240// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {241// CHECK-RV64-NEXT: entry:242// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vid.mask.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)243// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]244//245vuint8mf4_t test_vid_v_u8mf4_tum(vbool32_t mask, vuint8mf4_t maskedoff, size_t vl) {246 return __riscv_vid_tum(mask, maskedoff, vl);247}248 249// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vid_v_u8mf2_tum250// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {251// CHECK-RV64-NEXT: entry:252// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vid.mask.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)253// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]254//255vuint8mf2_t test_vid_v_u8mf2_tum(vbool16_t mask, vuint8mf2_t maskedoff, size_t vl) {256 return __riscv_vid_tum(mask, maskedoff, vl);257}258 259// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vid_v_u8m1_tum260// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {261// CHECK-RV64-NEXT: entry:262// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vid.mask.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)263// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]264//265vuint8m1_t test_vid_v_u8m1_tum(vbool8_t mask, vuint8m1_t maskedoff, size_t vl) {266 return __riscv_vid_tum(mask, maskedoff, vl);267}268 269// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vid_v_u8m2_tum270// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {271// CHECK-RV64-NEXT: entry:272// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vid.mask.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)273// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]274//275vuint8m2_t test_vid_v_u8m2_tum(vbool4_t mask, vuint8m2_t maskedoff, size_t vl) {276 return __riscv_vid_tum(mask, maskedoff, vl);277}278 279// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vid_v_u8m4_tum280// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {281// CHECK-RV64-NEXT: entry:282// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vid.mask.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2)283// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]284//285vuint8m4_t test_vid_v_u8m4_tum(vbool2_t mask, vuint8m4_t maskedoff, size_t vl) {286 return __riscv_vid_tum(mask, maskedoff, vl);287}288 289// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vid_v_u8m8_tum290// CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {291// CHECK-RV64-NEXT: entry:292// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vid.mask.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 2)293// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]294//295vuint8m8_t test_vid_v_u8m8_tum(vbool1_t mask, vuint8m8_t maskedoff, size_t vl) {296 return __riscv_vid_tum(mask, maskedoff, vl);297}298 299// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vid_v_u16mf4_tum300// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {301// CHECK-RV64-NEXT: entry:302// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vid.mask.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)303// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]304//305vuint16mf4_t test_vid_v_u16mf4_tum(vbool64_t mask, vuint16mf4_t maskedoff, size_t vl) {306 return __riscv_vid_tum(mask, maskedoff, vl);307}308 309// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vid_v_u16mf2_tum310// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {311// CHECK-RV64-NEXT: entry:312// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vid.mask.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)313// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]314//315vuint16mf2_t test_vid_v_u16mf2_tum(vbool32_t mask, vuint16mf2_t maskedoff, size_t vl) {316 return __riscv_vid_tum(mask, maskedoff, vl);317}318 319// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vid_v_u16m1_tum320// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {321// CHECK-RV64-NEXT: entry:322// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vid.mask.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)323// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]324//325vuint16m1_t test_vid_v_u16m1_tum(vbool16_t mask, vuint16m1_t maskedoff, size_t vl) {326 return __riscv_vid_tum(mask, maskedoff, vl);327}328 329// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vid_v_u16m2_tum330// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {331// CHECK-RV64-NEXT: entry:332// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vid.mask.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)333// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]334//335vuint16m2_t test_vid_v_u16m2_tum(vbool8_t mask, vuint16m2_t maskedoff, size_t vl) {336 return __riscv_vid_tum(mask, maskedoff, vl);337}338 339// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vid_v_u16m4_tum340// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {341// CHECK-RV64-NEXT: entry:342// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vid.mask.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)343// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]344//345vuint16m4_t test_vid_v_u16m4_tum(vbool4_t mask, vuint16m4_t maskedoff, size_t vl) {346 return __riscv_vid_tum(mask, maskedoff, vl);347}348 349// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vid_v_u16m8_tum350// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {351// CHECK-RV64-NEXT: entry:352// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vid.mask.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2)353// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]354//355vuint16m8_t test_vid_v_u16m8_tum(vbool2_t mask, vuint16m8_t maskedoff, size_t vl) {356 return __riscv_vid_tum(mask, maskedoff, vl);357}358 359// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vid_v_u32mf2_tum360// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {361// CHECK-RV64-NEXT: entry:362// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vid.mask.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)363// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]364//365vuint32mf2_t test_vid_v_u32mf2_tum(vbool64_t mask, vuint32mf2_t maskedoff, size_t vl) {366 return __riscv_vid_tum(mask, maskedoff, vl);367}368 369// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vid_v_u32m1_tum370// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {371// CHECK-RV64-NEXT: entry:372// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vid.mask.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)373// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]374//375vuint32m1_t test_vid_v_u32m1_tum(vbool32_t mask, vuint32m1_t maskedoff, size_t vl) {376 return __riscv_vid_tum(mask, maskedoff, vl);377}378 379// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vid_v_u32m2_tum380// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {381// CHECK-RV64-NEXT: entry:382// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vid.mask.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)383// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]384//385vuint32m2_t test_vid_v_u32m2_tum(vbool16_t mask, vuint32m2_t maskedoff, size_t vl) {386 return __riscv_vid_tum(mask, maskedoff, vl);387}388 389// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vid_v_u32m4_tum390// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {391// CHECK-RV64-NEXT: entry:392// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vid.mask.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)393// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]394//395vuint32m4_t test_vid_v_u32m4_tum(vbool8_t mask, vuint32m4_t maskedoff, size_t vl) {396 return __riscv_vid_tum(mask, maskedoff, vl);397}398 399// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vid_v_u32m8_tum400// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {401// CHECK-RV64-NEXT: entry:402// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vid.mask.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)403// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]404//405vuint32m8_t test_vid_v_u32m8_tum(vbool4_t mask, vuint32m8_t maskedoff, size_t vl) {406 return __riscv_vid_tum(mask, maskedoff, vl);407}408 409// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vid_v_u64m1_tum410// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {411// CHECK-RV64-NEXT: entry:412// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vid.mask.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)413// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]414//415vuint64m1_t test_vid_v_u64m1_tum(vbool64_t mask, vuint64m1_t maskedoff, size_t vl) {416 return __riscv_vid_tum(mask, maskedoff, vl);417}418 419// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vid_v_u64m2_tum420// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {421// CHECK-RV64-NEXT: entry:422// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vid.mask.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)423// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]424//425vuint64m2_t test_vid_v_u64m2_tum(vbool32_t mask, vuint64m2_t maskedoff, size_t vl) {426 return __riscv_vid_tum(mask, maskedoff, vl);427}428 429// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vid_v_u64m4_tum430// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {431// CHECK-RV64-NEXT: entry:432// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vid.mask.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)433// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]434//435vuint64m4_t test_vid_v_u64m4_tum(vbool16_t mask, vuint64m4_t maskedoff, size_t vl) {436 return __riscv_vid_tum(mask, maskedoff, vl);437}438 439// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vid_v_u64m8_tum440// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {441// CHECK-RV64-NEXT: entry:442// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vid.mask.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)443// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]444//445vuint64m8_t test_vid_v_u64m8_tum(vbool8_t mask, vuint64m8_t maskedoff, size_t vl) {446 return __riscv_vid_tum(mask, maskedoff, vl);447}448 449// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vid_v_u8mf8_tumu450// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {451// CHECK-RV64-NEXT: entry:452// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vid.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)453// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]454//455vuint8mf8_t test_vid_v_u8mf8_tumu(vbool64_t mask, vuint8mf8_t maskedoff, size_t vl) {456 return __riscv_vid_tumu(mask, maskedoff, vl);457}458 459// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vid_v_u8mf4_tumu460// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {461// CHECK-RV64-NEXT: entry:462// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vid.mask.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)463// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]464//465vuint8mf4_t test_vid_v_u8mf4_tumu(vbool32_t mask, vuint8mf4_t maskedoff, size_t vl) {466 return __riscv_vid_tumu(mask, maskedoff, vl);467}468 469// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vid_v_u8mf2_tumu470// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {471// CHECK-RV64-NEXT: entry:472// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vid.mask.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)473// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]474//475vuint8mf2_t test_vid_v_u8mf2_tumu(vbool16_t mask, vuint8mf2_t maskedoff, size_t vl) {476 return __riscv_vid_tumu(mask, maskedoff, vl);477}478 479// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vid_v_u8m1_tumu480// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {481// CHECK-RV64-NEXT: entry:482// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vid.mask.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)483// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]484//485vuint8m1_t test_vid_v_u8m1_tumu(vbool8_t mask, vuint8m1_t maskedoff, size_t vl) {486 return __riscv_vid_tumu(mask, maskedoff, vl);487}488 489// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vid_v_u8m2_tumu490// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {491// CHECK-RV64-NEXT: entry:492// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vid.mask.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)493// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]494//495vuint8m2_t test_vid_v_u8m2_tumu(vbool4_t mask, vuint8m2_t maskedoff, size_t vl) {496 return __riscv_vid_tumu(mask, maskedoff, vl);497}498 499// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vid_v_u8m4_tumu500// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {501// CHECK-RV64-NEXT: entry:502// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vid.mask.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0)503// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]504//505vuint8m4_t test_vid_v_u8m4_tumu(vbool2_t mask, vuint8m4_t maskedoff, size_t vl) {506 return __riscv_vid_tumu(mask, maskedoff, vl);507}508 509// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vid_v_u8m8_tumu510// CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {511// CHECK-RV64-NEXT: entry:512// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vid.mask.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 0)513// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]514//515vuint8m8_t test_vid_v_u8m8_tumu(vbool1_t mask, vuint8m8_t maskedoff, size_t vl) {516 return __riscv_vid_tumu(mask, maskedoff, vl);517}518 519// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vid_v_u16mf4_tumu520// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {521// CHECK-RV64-NEXT: entry:522// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vid.mask.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)523// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]524//525vuint16mf4_t test_vid_v_u16mf4_tumu(vbool64_t mask, vuint16mf4_t maskedoff, size_t vl) {526 return __riscv_vid_tumu(mask, maskedoff, vl);527}528 529// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vid_v_u16mf2_tumu530// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {531// CHECK-RV64-NEXT: entry:532// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vid.mask.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)533// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]534//535vuint16mf2_t test_vid_v_u16mf2_tumu(vbool32_t mask, vuint16mf2_t maskedoff, size_t vl) {536 return __riscv_vid_tumu(mask, maskedoff, vl);537}538 539// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vid_v_u16m1_tumu540// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {541// CHECK-RV64-NEXT: entry:542// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vid.mask.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)543// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]544//545vuint16m1_t test_vid_v_u16m1_tumu(vbool16_t mask, vuint16m1_t maskedoff, size_t vl) {546 return __riscv_vid_tumu(mask, maskedoff, vl);547}548 549// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vid_v_u16m2_tumu550// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {551// CHECK-RV64-NEXT: entry:552// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vid.mask.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)553// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]554//555vuint16m2_t test_vid_v_u16m2_tumu(vbool8_t mask, vuint16m2_t maskedoff, size_t vl) {556 return __riscv_vid_tumu(mask, maskedoff, vl);557}558 559// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vid_v_u16m4_tumu560// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {561// CHECK-RV64-NEXT: entry:562// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vid.mask.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)563// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]564//565vuint16m4_t test_vid_v_u16m4_tumu(vbool4_t mask, vuint16m4_t maskedoff, size_t vl) {566 return __riscv_vid_tumu(mask, maskedoff, vl);567}568 569// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vid_v_u16m8_tumu570// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {571// CHECK-RV64-NEXT: entry:572// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vid.mask.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0)573// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]574//575vuint16m8_t test_vid_v_u16m8_tumu(vbool2_t mask, vuint16m8_t maskedoff, size_t vl) {576 return __riscv_vid_tumu(mask, maskedoff, vl);577}578 579// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vid_v_u32mf2_tumu580// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {581// CHECK-RV64-NEXT: entry:582// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vid.mask.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)583// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]584//585vuint32mf2_t test_vid_v_u32mf2_tumu(vbool64_t mask, vuint32mf2_t maskedoff, size_t vl) {586 return __riscv_vid_tumu(mask, maskedoff, vl);587}588 589// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vid_v_u32m1_tumu590// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {591// CHECK-RV64-NEXT: entry:592// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vid.mask.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)593// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]594//595vuint32m1_t test_vid_v_u32m1_tumu(vbool32_t mask, vuint32m1_t maskedoff, size_t vl) {596 return __riscv_vid_tumu(mask, maskedoff, vl);597}598 599// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vid_v_u32m2_tumu600// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {601// CHECK-RV64-NEXT: entry:602// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vid.mask.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)603// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]604//605vuint32m2_t test_vid_v_u32m2_tumu(vbool16_t mask, vuint32m2_t maskedoff, size_t vl) {606 return __riscv_vid_tumu(mask, maskedoff, vl);607}608 609// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vid_v_u32m4_tumu610// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {611// CHECK-RV64-NEXT: entry:612// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vid.mask.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)613// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]614//615vuint32m4_t test_vid_v_u32m4_tumu(vbool8_t mask, vuint32m4_t maskedoff, size_t vl) {616 return __riscv_vid_tumu(mask, maskedoff, vl);617}618 619// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vid_v_u32m8_tumu620// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {621// CHECK-RV64-NEXT: entry:622// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vid.mask.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)623// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]624//625vuint32m8_t test_vid_v_u32m8_tumu(vbool4_t mask, vuint32m8_t maskedoff, size_t vl) {626 return __riscv_vid_tumu(mask, maskedoff, vl);627}628 629// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vid_v_u64m1_tumu630// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {631// CHECK-RV64-NEXT: entry:632// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vid.mask.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)633// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]634//635vuint64m1_t test_vid_v_u64m1_tumu(vbool64_t mask, vuint64m1_t maskedoff, size_t vl) {636 return __riscv_vid_tumu(mask, maskedoff, vl);637}638 639// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vid_v_u64m2_tumu640// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {641// CHECK-RV64-NEXT: entry:642// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vid.mask.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)643// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]644//645vuint64m2_t test_vid_v_u64m2_tumu(vbool32_t mask, vuint64m2_t maskedoff, size_t vl) {646 return __riscv_vid_tumu(mask, maskedoff, vl);647}648 649// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vid_v_u64m4_tumu650// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {651// CHECK-RV64-NEXT: entry:652// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vid.mask.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)653// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]654//655vuint64m4_t test_vid_v_u64m4_tumu(vbool16_t mask, vuint64m4_t maskedoff, size_t vl) {656 return __riscv_vid_tumu(mask, maskedoff, vl);657}658 659// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vid_v_u64m8_tumu660// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {661// CHECK-RV64-NEXT: entry:662// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vid.mask.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)663// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]664//665vuint64m8_t test_vid_v_u64m8_tumu(vbool8_t mask, vuint64m8_t maskedoff, size_t vl) {666 return __riscv_vid_tumu(mask, maskedoff, vl);667}668 669// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vid_v_u8mf8_mu670// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {671// CHECK-RV64-NEXT: entry:672// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vid.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)673// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]674//675vuint8mf8_t test_vid_v_u8mf8_mu(vbool64_t mask, vuint8mf8_t maskedoff, size_t vl) {676 return __riscv_vid_mu(mask, maskedoff, vl);677}678 679// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vid_v_u8mf4_mu680// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {681// CHECK-RV64-NEXT: entry:682// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vid.mask.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)683// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]684//685vuint8mf4_t test_vid_v_u8mf4_mu(vbool32_t mask, vuint8mf4_t maskedoff, size_t vl) {686 return __riscv_vid_mu(mask, maskedoff, vl);687}688 689// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vid_v_u8mf2_mu690// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {691// CHECK-RV64-NEXT: entry:692// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vid.mask.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)693// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]694//695vuint8mf2_t test_vid_v_u8mf2_mu(vbool16_t mask, vuint8mf2_t maskedoff, size_t vl) {696 return __riscv_vid_mu(mask, maskedoff, vl);697}698 699// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vid_v_u8m1_mu700// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {701// CHECK-RV64-NEXT: entry:702// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vid.mask.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)703// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]704//705vuint8m1_t test_vid_v_u8m1_mu(vbool8_t mask, vuint8m1_t maskedoff, size_t vl) {706 return __riscv_vid_mu(mask, maskedoff, vl);707}708 709// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vid_v_u8m2_mu710// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {711// CHECK-RV64-NEXT: entry:712// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vid.mask.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)713// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]714//715vuint8m2_t test_vid_v_u8m2_mu(vbool4_t mask, vuint8m2_t maskedoff, size_t vl) {716 return __riscv_vid_mu(mask, maskedoff, vl);717}718 719// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vid_v_u8m4_mu720// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {721// CHECK-RV64-NEXT: entry:722// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vid.mask.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1)723// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]724//725vuint8m4_t test_vid_v_u8m4_mu(vbool2_t mask, vuint8m4_t maskedoff, size_t vl) {726 return __riscv_vid_mu(mask, maskedoff, vl);727}728 729// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vid_v_u8m8_mu730// CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {731// CHECK-RV64-NEXT: entry:732// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vid.mask.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 1)733// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]734//735vuint8m8_t test_vid_v_u8m8_mu(vbool1_t mask, vuint8m8_t maskedoff, size_t vl) {736 return __riscv_vid_mu(mask, maskedoff, vl);737}738 739// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vid_v_u16mf4_mu740// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {741// CHECK-RV64-NEXT: entry:742// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vid.mask.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)743// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]744//745vuint16mf4_t test_vid_v_u16mf4_mu(vbool64_t mask, vuint16mf4_t maskedoff, size_t vl) {746 return __riscv_vid_mu(mask, maskedoff, vl);747}748 749// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vid_v_u16mf2_mu750// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {751// CHECK-RV64-NEXT: entry:752// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vid.mask.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)753// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]754//755vuint16mf2_t test_vid_v_u16mf2_mu(vbool32_t mask, vuint16mf2_t maskedoff, size_t vl) {756 return __riscv_vid_mu(mask, maskedoff, vl);757}758 759// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vid_v_u16m1_mu760// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {761// CHECK-RV64-NEXT: entry:762// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vid.mask.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)763// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]764//765vuint16m1_t test_vid_v_u16m1_mu(vbool16_t mask, vuint16m1_t maskedoff, size_t vl) {766 return __riscv_vid_mu(mask, maskedoff, vl);767}768 769// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vid_v_u16m2_mu770// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {771// CHECK-RV64-NEXT: entry:772// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vid.mask.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)773// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]774//775vuint16m2_t test_vid_v_u16m2_mu(vbool8_t mask, vuint16m2_t maskedoff, size_t vl) {776 return __riscv_vid_mu(mask, maskedoff, vl);777}778 779// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vid_v_u16m4_mu780// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {781// CHECK-RV64-NEXT: entry:782// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vid.mask.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)783// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]784//785vuint16m4_t test_vid_v_u16m4_mu(vbool4_t mask, vuint16m4_t maskedoff, size_t vl) {786 return __riscv_vid_mu(mask, maskedoff, vl);787}788 789// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vid_v_u16m8_mu790// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {791// CHECK-RV64-NEXT: entry:792// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vid.mask.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1)793// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]794//795vuint16m8_t test_vid_v_u16m8_mu(vbool2_t mask, vuint16m8_t maskedoff, size_t vl) {796 return __riscv_vid_mu(mask, maskedoff, vl);797}798 799// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vid_v_u32mf2_mu800// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {801// CHECK-RV64-NEXT: entry:802// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vid.mask.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)803// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]804//805vuint32mf2_t test_vid_v_u32mf2_mu(vbool64_t mask, vuint32mf2_t maskedoff, size_t vl) {806 return __riscv_vid_mu(mask, maskedoff, vl);807}808 809// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vid_v_u32m1_mu810// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {811// CHECK-RV64-NEXT: entry:812// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vid.mask.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)813// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]814//815vuint32m1_t test_vid_v_u32m1_mu(vbool32_t mask, vuint32m1_t maskedoff, size_t vl) {816 return __riscv_vid_mu(mask, maskedoff, vl);817}818 819// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vid_v_u32m2_mu820// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {821// CHECK-RV64-NEXT: entry:822// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vid.mask.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)823// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]824//825vuint32m2_t test_vid_v_u32m2_mu(vbool16_t mask, vuint32m2_t maskedoff, size_t vl) {826 return __riscv_vid_mu(mask, maskedoff, vl);827}828 829// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vid_v_u32m4_mu830// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {831// CHECK-RV64-NEXT: entry:832// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vid.mask.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)833// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]834//835vuint32m4_t test_vid_v_u32m4_mu(vbool8_t mask, vuint32m4_t maskedoff, size_t vl) {836 return __riscv_vid_mu(mask, maskedoff, vl);837}838 839// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vid_v_u32m8_mu840// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {841// CHECK-RV64-NEXT: entry:842// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vid.mask.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)843// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]844//845vuint32m8_t test_vid_v_u32m8_mu(vbool4_t mask, vuint32m8_t maskedoff, size_t vl) {846 return __riscv_vid_mu(mask, maskedoff, vl);847}848 849// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vid_v_u64m1_mu850// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {851// CHECK-RV64-NEXT: entry:852// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vid.mask.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)853// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]854//855vuint64m1_t test_vid_v_u64m1_mu(vbool64_t mask, vuint64m1_t maskedoff, size_t vl) {856 return __riscv_vid_mu(mask, maskedoff, vl);857}858 859// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vid_v_u64m2_mu860// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {861// CHECK-RV64-NEXT: entry:862// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vid.mask.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)863// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]864//865vuint64m2_t test_vid_v_u64m2_mu(vbool32_t mask, vuint64m2_t maskedoff, size_t vl) {866 return __riscv_vid_mu(mask, maskedoff, vl);867}868 869// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vid_v_u64m4_mu870// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {871// CHECK-RV64-NEXT: entry:872// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vid.mask.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)873// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]874//875vuint64m4_t test_vid_v_u64m4_mu(vbool16_t mask, vuint64m4_t maskedoff, size_t vl) {876 return __riscv_vid_mu(mask, maskedoff, vl);877}878 879// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vid_v_u64m8_mu880// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {881// CHECK-RV64-NEXT: entry:882// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vid.mask.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)883// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]884//885vuint64m8_t test_vid_v_u64m8_mu(vbool8_t mask, vuint64m8_t maskedoff, size_t vl) {886 return __riscv_vid_mu(mask, maskedoff, vl);887}888 889