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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 22// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone \4// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \5// RUN: FileCheck --check-prefix=CHECK-RV64 %s6 7#include <riscv_vector.h>8 9// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vsll_vv_i8mf8_tu10// CHECK-RV64-SAME: (<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {11// CHECK-RV64-NEXT: entry:12// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], <vscale x 1 x i8> [[SHIFT]], i64 [[VL]])13// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]14//15vint8mf8_t test_vsll_vv_i8mf8_tu(vint8mf8_t maskedoff, vint8mf8_t op1, vuint8mf8_t shift, size_t vl) {16 return __riscv_vsll_tu(maskedoff, op1, shift, vl);17}18 19// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vsll_vx_i8mf8_tu20// CHECK-RV64-SAME: (<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {21// CHECK-RV64-NEXT: entry:22// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.i64.i64(<vscale x 1 x i8> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], i64 [[SHIFT]], i64 [[VL]])23// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]24//25vint8mf8_t test_vsll_vx_i8mf8_tu(vint8mf8_t maskedoff, vint8mf8_t op1, size_t shift, size_t vl) {26 return __riscv_vsll_tu(maskedoff, op1, shift, vl);27}28 29// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vsll_vv_i8mf4_tu30// CHECK-RV64-SAME: (<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {31// CHECK-RV64-NEXT: entry:32// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], <vscale x 2 x i8> [[SHIFT]], i64 [[VL]])33// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]34//35vint8mf4_t test_vsll_vv_i8mf4_tu(vint8mf4_t maskedoff, vint8mf4_t op1, vuint8mf4_t shift, size_t vl) {36 return __riscv_vsll_tu(maskedoff, op1, shift, vl);37}38 39// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vsll_vx_i8mf4_tu40// CHECK-RV64-SAME: (<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {41// CHECK-RV64-NEXT: entry:42// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.i64.i64(<vscale x 2 x i8> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], i64 [[SHIFT]], i64 [[VL]])43// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]44//45vint8mf4_t test_vsll_vx_i8mf4_tu(vint8mf4_t maskedoff, vint8mf4_t op1, size_t shift, size_t vl) {46 return __riscv_vsll_tu(maskedoff, op1, shift, vl);47}48 49// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vsll_vv_i8mf2_tu50// CHECK-RV64-SAME: (<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {51// CHECK-RV64-NEXT: entry:52// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF]], <vscale x 4 x i8> [[OP1]], <vscale x 4 x i8> [[SHIFT]], i64 [[VL]])53// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]54//55vint8mf2_t test_vsll_vv_i8mf2_tu(vint8mf2_t maskedoff, vint8mf2_t op1, vuint8mf2_t shift, size_t vl) {56 return __riscv_vsll_tu(maskedoff, op1, shift, vl);57}58 59// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vsll_vx_i8mf2_tu60// CHECK-RV64-SAME: (<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {61// CHECK-RV64-NEXT: entry:62// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.i64.i64(<vscale x 4 x i8> [[MASKEDOFF]], <vscale x 4 x i8> [[OP1]], i64 [[SHIFT]], i64 [[VL]])63// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]64//65vint8mf2_t test_vsll_vx_i8mf2_tu(vint8mf2_t maskedoff, vint8mf2_t op1, size_t shift, size_t vl) {66 return __riscv_vsll_tu(maskedoff, op1, shift, vl);67}68 69// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vsll_vv_i8m1_tu70// CHECK-RV64-SAME: (<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {71// CHECK-RV64-NEXT: entry:72// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF]], <vscale x 8 x i8> [[OP1]], <vscale x 8 x i8> [[SHIFT]], i64 [[VL]])73// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]74//75vint8m1_t test_vsll_vv_i8m1_tu(vint8m1_t maskedoff, vint8m1_t op1, vuint8m1_t shift, size_t vl) {76 return __riscv_vsll_tu(maskedoff, op1, shift, vl);77}78 79// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vsll_vx_i8m1_tu80// CHECK-RV64-SAME: (<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {81// CHECK-RV64-NEXT: entry:82// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.i64.i64(<vscale x 8 x i8> [[MASKEDOFF]], <vscale x 8 x i8> [[OP1]], i64 [[SHIFT]], i64 [[VL]])83// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]84//85vint8m1_t test_vsll_vx_i8m1_tu(vint8m1_t maskedoff, vint8m1_t op1, size_t shift, size_t vl) {86 return __riscv_vsll_tu(maskedoff, op1, shift, vl);87}88 89// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vsll_vv_i8m2_tu90// CHECK-RV64-SAME: (<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {91// CHECK-RV64-NEXT: entry:92// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF]], <vscale x 16 x i8> [[OP1]], <vscale x 16 x i8> [[SHIFT]], i64 [[VL]])93// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]94//95vint8m2_t test_vsll_vv_i8m2_tu(vint8m2_t maskedoff, vint8m2_t op1, vuint8m2_t shift, size_t vl) {96 return __riscv_vsll_tu(maskedoff, op1, shift, vl);97}98 99// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vsll_vx_i8m2_tu100// CHECK-RV64-SAME: (<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {101// CHECK-RV64-NEXT: entry:102// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.i64.i64(<vscale x 16 x i8> [[MASKEDOFF]], <vscale x 16 x i8> [[OP1]], i64 [[SHIFT]], i64 [[VL]])103// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]104//105vint8m2_t test_vsll_vx_i8m2_tu(vint8m2_t maskedoff, vint8m2_t op1, size_t shift, size_t vl) {106 return __riscv_vsll_tu(maskedoff, op1, shift, vl);107}108 109// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vsll_vv_i8m4_tu110// CHECK-RV64-SAME: (<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {111// CHECK-RV64-NEXT: entry:112// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vsll.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF]], <vscale x 32 x i8> [[OP1]], <vscale x 32 x i8> [[SHIFT]], i64 [[VL]])113// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]114//115vint8m4_t test_vsll_vv_i8m4_tu(vint8m4_t maskedoff, vint8m4_t op1, vuint8m4_t shift, size_t vl) {116 return __riscv_vsll_tu(maskedoff, op1, shift, vl);117}118 119// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vsll_vx_i8m4_tu120// CHECK-RV64-SAME: (<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {121// CHECK-RV64-NEXT: entry:122// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vsll.nxv32i8.i64.i64(<vscale x 32 x i8> [[MASKEDOFF]], <vscale x 32 x i8> [[OP1]], i64 [[SHIFT]], i64 [[VL]])123// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]124//125vint8m4_t test_vsll_vx_i8m4_tu(vint8m4_t maskedoff, vint8m4_t op1, size_t shift, size_t vl) {126 return __riscv_vsll_tu(maskedoff, op1, shift, vl);127}128 129// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vsll_vv_i8m8_tu130// CHECK-RV64-SAME: (<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {131// CHECK-RV64-NEXT: entry:132// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vsll.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF]], <vscale x 64 x i8> [[OP1]], <vscale x 64 x i8> [[SHIFT]], i64 [[VL]])133// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]134//135vint8m8_t test_vsll_vv_i8m8_tu(vint8m8_t maskedoff, vint8m8_t op1, vuint8m8_t shift, size_t vl) {136 return __riscv_vsll_tu(maskedoff, op1, shift, vl);137}138 139// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vsll_vx_i8m8_tu140// CHECK-RV64-SAME: (<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {141// CHECK-RV64-NEXT: entry:142// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vsll.nxv64i8.i64.i64(<vscale x 64 x i8> [[MASKEDOFF]], <vscale x 64 x i8> [[OP1]], i64 [[SHIFT]], i64 [[VL]])143// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]144//145vint8m8_t test_vsll_vx_i8m8_tu(vint8m8_t maskedoff, vint8m8_t op1, size_t shift, size_t vl) {146 return __riscv_vsll_tu(maskedoff, op1, shift, vl);147}148 149// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vsll_vv_i16mf4_tu150// CHECK-RV64-SAME: (<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {151// CHECK-RV64-NEXT: entry:152// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vsll.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]], <vscale x 1 x i16> [[SHIFT]], i64 [[VL]])153// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]154//155vint16mf4_t test_vsll_vv_i16mf4_tu(vint16mf4_t maskedoff, vint16mf4_t op1, vuint16mf4_t shift, size_t vl) {156 return __riscv_vsll_tu(maskedoff, op1, shift, vl);157}158 159// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vsll_vx_i16mf4_tu160// CHECK-RV64-SAME: (<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {161// CHECK-RV64-NEXT: entry:162// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vsll.nxv1i16.i64.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]], i64 [[SHIFT]], i64 [[VL]])163// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]164//165vint16mf4_t test_vsll_vx_i16mf4_tu(vint16mf4_t maskedoff, vint16mf4_t op1, size_t shift, size_t vl) {166 return __riscv_vsll_tu(maskedoff, op1, shift, vl);167}168 169// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vsll_vv_i16mf2_tu170// CHECK-RV64-SAME: (<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {171// CHECK-RV64-NEXT: entry:172// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vsll.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]], <vscale x 2 x i16> [[SHIFT]], i64 [[VL]])173// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]174//175vint16mf2_t test_vsll_vv_i16mf2_tu(vint16mf2_t maskedoff, vint16mf2_t op1, vuint16mf2_t shift, size_t vl) {176 return __riscv_vsll_tu(maskedoff, op1, shift, vl);177}178 179// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vsll_vx_i16mf2_tu180// CHECK-RV64-SAME: (<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {181// CHECK-RV64-NEXT: entry:182// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vsll.nxv2i16.i64.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]], i64 [[SHIFT]], i64 [[VL]])183// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]184//185vint16mf2_t test_vsll_vx_i16mf2_tu(vint16mf2_t maskedoff, vint16mf2_t op1, size_t shift, size_t vl) {186 return __riscv_vsll_tu(maskedoff, op1, shift, vl);187}188 189// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vsll_vv_i16m1_tu190// CHECK-RV64-SAME: (<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {191// CHECK-RV64-NEXT: entry:192// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vsll.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]], <vscale x 4 x i16> [[SHIFT]], i64 [[VL]])193// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]194//195vint16m1_t test_vsll_vv_i16m1_tu(vint16m1_t maskedoff, vint16m1_t op1, vuint16m1_t shift, size_t vl) {196 return __riscv_vsll_tu(maskedoff, op1, shift, vl);197}198 199// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vsll_vx_i16m1_tu200// CHECK-RV64-SAME: (<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {201// CHECK-RV64-NEXT: entry:202// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vsll.nxv4i16.i64.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]], i64 [[SHIFT]], i64 [[VL]])203// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]204//205vint16m1_t test_vsll_vx_i16m1_tu(vint16m1_t maskedoff, vint16m1_t op1, size_t shift, size_t vl) {206 return __riscv_vsll_tu(maskedoff, op1, shift, vl);207}208 209// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vsll_vv_i16m2_tu210// CHECK-RV64-SAME: (<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {211// CHECK-RV64-NEXT: entry:212// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vsll.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]], <vscale x 8 x i16> [[SHIFT]], i64 [[VL]])213// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]214//215vint16m2_t test_vsll_vv_i16m2_tu(vint16m2_t maskedoff, vint16m2_t op1, vuint16m2_t shift, size_t vl) {216 return __riscv_vsll_tu(maskedoff, op1, shift, vl);217}218 219// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vsll_vx_i16m2_tu220// CHECK-RV64-SAME: (<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {221// CHECK-RV64-NEXT: entry:222// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vsll.nxv8i16.i64.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]], i64 [[SHIFT]], i64 [[VL]])223// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]224//225vint16m2_t test_vsll_vx_i16m2_tu(vint16m2_t maskedoff, vint16m2_t op1, size_t shift, size_t vl) {226 return __riscv_vsll_tu(maskedoff, op1, shift, vl);227}228 229// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vsll_vv_i16m4_tu230// CHECK-RV64-SAME: (<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {231// CHECK-RV64-NEXT: entry:232// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vsll.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x i16> [[OP1]], <vscale x 16 x i16> [[SHIFT]], i64 [[VL]])233// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]234//235vint16m4_t test_vsll_vv_i16m4_tu(vint16m4_t maskedoff, vint16m4_t op1, vuint16m4_t shift, size_t vl) {236 return __riscv_vsll_tu(maskedoff, op1, shift, vl);237}238 239// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vsll_vx_i16m4_tu240// CHECK-RV64-SAME: (<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {241// CHECK-RV64-NEXT: entry:242// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vsll.nxv16i16.i64.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x i16> [[OP1]], i64 [[SHIFT]], i64 [[VL]])243// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]244//245vint16m4_t test_vsll_vx_i16m4_tu(vint16m4_t maskedoff, vint16m4_t op1, size_t shift, size_t vl) {246 return __riscv_vsll_tu(maskedoff, op1, shift, vl);247}248 249// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vsll_vv_i16m8_tu250// CHECK-RV64-SAME: (<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {251// CHECK-RV64-NEXT: entry:252// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vsll.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x i16> [[OP1]], <vscale x 32 x i16> [[SHIFT]], i64 [[VL]])253// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]254//255vint16m8_t test_vsll_vv_i16m8_tu(vint16m8_t maskedoff, vint16m8_t op1, vuint16m8_t shift, size_t vl) {256 return __riscv_vsll_tu(maskedoff, op1, shift, vl);257}258 259// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vsll_vx_i16m8_tu260// CHECK-RV64-SAME: (<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {261// CHECK-RV64-NEXT: entry:262// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vsll.nxv32i16.i64.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x i16> [[OP1]], i64 [[SHIFT]], i64 [[VL]])263// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]264//265vint16m8_t test_vsll_vx_i16m8_tu(vint16m8_t maskedoff, vint16m8_t op1, size_t shift, size_t vl) {266 return __riscv_vsll_tu(maskedoff, op1, shift, vl);267}268 269// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vsll_vv_i32mf2_tu270// CHECK-RV64-SAME: (<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {271// CHECK-RV64-NEXT: entry:272// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vsll.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x i32> [[OP1]], <vscale x 1 x i32> [[SHIFT]], i64 [[VL]])273// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]274//275vint32mf2_t test_vsll_vv_i32mf2_tu(vint32mf2_t maskedoff, vint32mf2_t op1, vuint32mf2_t shift, size_t vl) {276 return __riscv_vsll_tu(maskedoff, op1, shift, vl);277}278 279// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vsll_vx_i32mf2_tu280// CHECK-RV64-SAME: (<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {281// CHECK-RV64-NEXT: entry:282// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vsll.nxv1i32.i64.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x i32> [[OP1]], i64 [[SHIFT]], i64 [[VL]])283// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]284//285vint32mf2_t test_vsll_vx_i32mf2_tu(vint32mf2_t maskedoff, vint32mf2_t op1, size_t shift, size_t vl) {286 return __riscv_vsll_tu(maskedoff, op1, shift, vl);287}288 289// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vsll_vv_i32m1_tu290// CHECK-RV64-SAME: (<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {291// CHECK-RV64-NEXT: entry:292// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vsll.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i32> [[OP1]], <vscale x 2 x i32> [[SHIFT]], i64 [[VL]])293// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]294//295vint32m1_t test_vsll_vv_i32m1_tu(vint32m1_t maskedoff, vint32m1_t op1, vuint32m1_t shift, size_t vl) {296 return __riscv_vsll_tu(maskedoff, op1, shift, vl);297}298 299// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vsll_vx_i32m1_tu300// CHECK-RV64-SAME: (<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {301// CHECK-RV64-NEXT: entry:302// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vsll.nxv2i32.i64.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i32> [[OP1]], i64 [[SHIFT]], i64 [[VL]])303// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]304//305vint32m1_t test_vsll_vx_i32m1_tu(vint32m1_t maskedoff, vint32m1_t op1, size_t shift, size_t vl) {306 return __riscv_vsll_tu(maskedoff, op1, shift, vl);307}308 309// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vsll_vv_i32m2_tu310// CHECK-RV64-SAME: (<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {311// CHECK-RV64-NEXT: entry:312// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vsll.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x i32> [[OP1]], <vscale x 4 x i32> [[SHIFT]], i64 [[VL]])313// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]314//315vint32m2_t test_vsll_vv_i32m2_tu(vint32m2_t maskedoff, vint32m2_t op1, vuint32m2_t shift, size_t vl) {316 return __riscv_vsll_tu(maskedoff, op1, shift, vl);317}318 319// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vsll_vx_i32m2_tu320// CHECK-RV64-SAME: (<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {321// CHECK-RV64-NEXT: entry:322// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vsll.nxv4i32.i64.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x i32> [[OP1]], i64 [[SHIFT]], i64 [[VL]])323// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]324//325vint32m2_t test_vsll_vx_i32m2_tu(vint32m2_t maskedoff, vint32m2_t op1, size_t shift, size_t vl) {326 return __riscv_vsll_tu(maskedoff, op1, shift, vl);327}328 329// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vsll_vv_i32m4_tu330// CHECK-RV64-SAME: (<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {331// CHECK-RV64-NEXT: entry:332// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vsll.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x i32> [[OP1]], <vscale x 8 x i32> [[SHIFT]], i64 [[VL]])333// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]334//335vint32m4_t test_vsll_vv_i32m4_tu(vint32m4_t maskedoff, vint32m4_t op1, vuint32m4_t shift, size_t vl) {336 return __riscv_vsll_tu(maskedoff, op1, shift, vl);337}338 339// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vsll_vx_i32m4_tu340// CHECK-RV64-SAME: (<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {341// CHECK-RV64-NEXT: entry:342// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vsll.nxv8i32.i64.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x i32> [[OP1]], i64 [[SHIFT]], i64 [[VL]])343// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]344//345vint32m4_t test_vsll_vx_i32m4_tu(vint32m4_t maskedoff, vint32m4_t op1, size_t shift, size_t vl) {346 return __riscv_vsll_tu(maskedoff, op1, shift, vl);347}348 349// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vsll_vv_i32m8_tu350// CHECK-RV64-SAME: (<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {351// CHECK-RV64-NEXT: entry:352// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vsll.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x i32> [[OP1]], <vscale x 16 x i32> [[SHIFT]], i64 [[VL]])353// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]354//355vint32m8_t test_vsll_vv_i32m8_tu(vint32m8_t maskedoff, vint32m8_t op1, vuint32m8_t shift, size_t vl) {356 return __riscv_vsll_tu(maskedoff, op1, shift, vl);357}358 359// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vsll_vx_i32m8_tu360// CHECK-RV64-SAME: (<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {361// CHECK-RV64-NEXT: entry:362// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vsll.nxv16i32.i64.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x i32> [[OP1]], i64 [[SHIFT]], i64 [[VL]])363// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]364//365vint32m8_t test_vsll_vx_i32m8_tu(vint32m8_t maskedoff, vint32m8_t op1, size_t shift, size_t vl) {366 return __riscv_vsll_tu(maskedoff, op1, shift, vl);367}368 369// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vsll_vv_i64m1_tu370// CHECK-RV64-SAME: (<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {371// CHECK-RV64-NEXT: entry:372// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vsll.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i64> [[OP1]], <vscale x 1 x i64> [[SHIFT]], i64 [[VL]])373// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]374//375vint64m1_t test_vsll_vv_i64m1_tu(vint64m1_t maskedoff, vint64m1_t op1, vuint64m1_t shift, size_t vl) {376 return __riscv_vsll_tu(maskedoff, op1, shift, vl);377}378 379// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vsll_vx_i64m1_tu380// CHECK-RV64-SAME: (<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {381// CHECK-RV64-NEXT: entry:382// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vsll.nxv1i64.i64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i64> [[OP1]], i64 [[SHIFT]], i64 [[VL]])383// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]384//385vint64m1_t test_vsll_vx_i64m1_tu(vint64m1_t maskedoff, vint64m1_t op1, size_t shift, size_t vl) {386 return __riscv_vsll_tu(maskedoff, op1, shift, vl);387}388 389// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vsll_vv_i64m2_tu390// CHECK-RV64-SAME: (<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {391// CHECK-RV64-NEXT: entry:392// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vsll.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i64> [[OP1]], <vscale x 2 x i64> [[SHIFT]], i64 [[VL]])393// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]394//395vint64m2_t test_vsll_vv_i64m2_tu(vint64m2_t maskedoff, vint64m2_t op1, vuint64m2_t shift, size_t vl) {396 return __riscv_vsll_tu(maskedoff, op1, shift, vl);397}398 399// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vsll_vx_i64m2_tu400// CHECK-RV64-SAME: (<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {401// CHECK-RV64-NEXT: entry:402// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vsll.nxv2i64.i64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i64> [[OP1]], i64 [[SHIFT]], i64 [[VL]])403// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]404//405vint64m2_t test_vsll_vx_i64m2_tu(vint64m2_t maskedoff, vint64m2_t op1, size_t shift, size_t vl) {406 return __riscv_vsll_tu(maskedoff, op1, shift, vl);407}408 409// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vsll_vv_i64m4_tu410// CHECK-RV64-SAME: (<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {411// CHECK-RV64-NEXT: entry:412// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vsll.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i64> [[OP1]], <vscale x 4 x i64> [[SHIFT]], i64 [[VL]])413// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]414//415vint64m4_t test_vsll_vv_i64m4_tu(vint64m4_t maskedoff, vint64m4_t op1, vuint64m4_t shift, size_t vl) {416 return __riscv_vsll_tu(maskedoff, op1, shift, vl);417}418 419// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vsll_vx_i64m4_tu420// CHECK-RV64-SAME: (<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {421// CHECK-RV64-NEXT: entry:422// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vsll.nxv4i64.i64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i64> [[OP1]], i64 [[SHIFT]], i64 [[VL]])423// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]424//425vint64m4_t test_vsll_vx_i64m4_tu(vint64m4_t maskedoff, vint64m4_t op1, size_t shift, size_t vl) {426 return __riscv_vsll_tu(maskedoff, op1, shift, vl);427}428 429// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vsll_vv_i64m8_tu430// CHECK-RV64-SAME: (<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {431// CHECK-RV64-NEXT: entry:432// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vsll.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i64> [[OP1]], <vscale x 8 x i64> [[SHIFT]], i64 [[VL]])433// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]434//435vint64m8_t test_vsll_vv_i64m8_tu(vint64m8_t maskedoff, vint64m8_t op1, vuint64m8_t shift, size_t vl) {436 return __riscv_vsll_tu(maskedoff, op1, shift, vl);437}438 439// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vsll_vx_i64m8_tu440// CHECK-RV64-SAME: (<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {441// CHECK-RV64-NEXT: entry:442// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vsll.nxv8i64.i64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i64> [[OP1]], i64 [[SHIFT]], i64 [[VL]])443// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]444//445vint64m8_t test_vsll_vx_i64m8_tu(vint64m8_t maskedoff, vint64m8_t op1, size_t shift, size_t vl) {446 return __riscv_vsll_tu(maskedoff, op1, shift, vl);447}448 449// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vsll_vv_u8mf8_tu450// CHECK-RV64-SAME: (<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {451// CHECK-RV64-NEXT: entry:452// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], <vscale x 1 x i8> [[SHIFT]], i64 [[VL]])453// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]454//455vuint8mf8_t test_vsll_vv_u8mf8_tu(vuint8mf8_t maskedoff, vuint8mf8_t op1, vuint8mf8_t shift, size_t vl) {456 return __riscv_vsll_tu(maskedoff, op1, shift, vl);457}458 459// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vsll_vx_u8mf8_tu460// CHECK-RV64-SAME: (<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {461// CHECK-RV64-NEXT: entry:462// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.i64.i64(<vscale x 1 x i8> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], i64 [[SHIFT]], i64 [[VL]])463// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]464//465vuint8mf8_t test_vsll_vx_u8mf8_tu(vuint8mf8_t maskedoff, vuint8mf8_t op1, size_t shift, size_t vl) {466 return __riscv_vsll_tu(maskedoff, op1, shift, vl);467}468 469// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vsll_vv_u8mf4_tu470// CHECK-RV64-SAME: (<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {471// CHECK-RV64-NEXT: entry:472// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], <vscale x 2 x i8> [[SHIFT]], i64 [[VL]])473// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]474//475vuint8mf4_t test_vsll_vv_u8mf4_tu(vuint8mf4_t maskedoff, vuint8mf4_t op1, vuint8mf4_t shift, size_t vl) {476 return __riscv_vsll_tu(maskedoff, op1, shift, vl);477}478 479// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vsll_vx_u8mf4_tu480// CHECK-RV64-SAME: (<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {481// CHECK-RV64-NEXT: entry:482// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.i64.i64(<vscale x 2 x i8> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], i64 [[SHIFT]], i64 [[VL]])483// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]484//485vuint8mf4_t test_vsll_vx_u8mf4_tu(vuint8mf4_t maskedoff, vuint8mf4_t op1, size_t shift, size_t vl) {486 return __riscv_vsll_tu(maskedoff, op1, shift, vl);487}488 489// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vsll_vv_u8mf2_tu490// CHECK-RV64-SAME: (<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {491// CHECK-RV64-NEXT: entry:492// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF]], <vscale x 4 x i8> [[OP1]], <vscale x 4 x i8> [[SHIFT]], i64 [[VL]])493// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]494//495vuint8mf2_t test_vsll_vv_u8mf2_tu(vuint8mf2_t maskedoff, vuint8mf2_t op1, vuint8mf2_t shift, size_t vl) {496 return __riscv_vsll_tu(maskedoff, op1, shift, vl);497}498 499// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vsll_vx_u8mf2_tu500// CHECK-RV64-SAME: (<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {501// CHECK-RV64-NEXT: entry:502// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.i64.i64(<vscale x 4 x i8> [[MASKEDOFF]], <vscale x 4 x i8> [[OP1]], i64 [[SHIFT]], i64 [[VL]])503// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]504//505vuint8mf2_t test_vsll_vx_u8mf2_tu(vuint8mf2_t maskedoff, vuint8mf2_t op1, size_t shift, size_t vl) {506 return __riscv_vsll_tu(maskedoff, op1, shift, vl);507}508 509// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vsll_vv_u8m1_tu510// CHECK-RV64-SAME: (<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {511// CHECK-RV64-NEXT: entry:512// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF]], <vscale x 8 x i8> [[OP1]], <vscale x 8 x i8> [[SHIFT]], i64 [[VL]])513// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]514//515vuint8m1_t test_vsll_vv_u8m1_tu(vuint8m1_t maskedoff, vuint8m1_t op1, vuint8m1_t shift, size_t vl) {516 return __riscv_vsll_tu(maskedoff, op1, shift, vl);517}518 519// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vsll_vx_u8m1_tu520// CHECK-RV64-SAME: (<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {521// CHECK-RV64-NEXT: entry:522// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.i64.i64(<vscale x 8 x i8> [[MASKEDOFF]], <vscale x 8 x i8> [[OP1]], i64 [[SHIFT]], i64 [[VL]])523// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]524//525vuint8m1_t test_vsll_vx_u8m1_tu(vuint8m1_t maskedoff, vuint8m1_t op1, size_t shift, size_t vl) {526 return __riscv_vsll_tu(maskedoff, op1, shift, vl);527}528 529// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vsll_vv_u8m2_tu530// CHECK-RV64-SAME: (<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {531// CHECK-RV64-NEXT: entry:532// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF]], <vscale x 16 x i8> [[OP1]], <vscale x 16 x i8> [[SHIFT]], i64 [[VL]])533// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]534//535vuint8m2_t test_vsll_vv_u8m2_tu(vuint8m2_t maskedoff, vuint8m2_t op1, vuint8m2_t shift, size_t vl) {536 return __riscv_vsll_tu(maskedoff, op1, shift, vl);537}538 539// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vsll_vx_u8m2_tu540// CHECK-RV64-SAME: (<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {541// CHECK-RV64-NEXT: entry:542// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.i64.i64(<vscale x 16 x i8> [[MASKEDOFF]], <vscale x 16 x i8> [[OP1]], i64 [[SHIFT]], i64 [[VL]])543// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]544//545vuint8m2_t test_vsll_vx_u8m2_tu(vuint8m2_t maskedoff, vuint8m2_t op1, size_t shift, size_t vl) {546 return __riscv_vsll_tu(maskedoff, op1, shift, vl);547}548 549// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vsll_vv_u8m4_tu550// CHECK-RV64-SAME: (<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {551// CHECK-RV64-NEXT: entry:552// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vsll.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF]], <vscale x 32 x i8> [[OP1]], <vscale x 32 x i8> [[SHIFT]], i64 [[VL]])553// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]554//555vuint8m4_t test_vsll_vv_u8m4_tu(vuint8m4_t maskedoff, vuint8m4_t op1, vuint8m4_t shift, size_t vl) {556 return __riscv_vsll_tu(maskedoff, op1, shift, vl);557}558 559// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vsll_vx_u8m4_tu560// CHECK-RV64-SAME: (<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {561// CHECK-RV64-NEXT: entry:562// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vsll.nxv32i8.i64.i64(<vscale x 32 x i8> [[MASKEDOFF]], <vscale x 32 x i8> [[OP1]], i64 [[SHIFT]], i64 [[VL]])563// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]564//565vuint8m4_t test_vsll_vx_u8m4_tu(vuint8m4_t maskedoff, vuint8m4_t op1, size_t shift, size_t vl) {566 return __riscv_vsll_tu(maskedoff, op1, shift, vl);567}568 569// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vsll_vv_u8m8_tu570// CHECK-RV64-SAME: (<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {571// CHECK-RV64-NEXT: entry:572// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vsll.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF]], <vscale x 64 x i8> [[OP1]], <vscale x 64 x i8> [[SHIFT]], i64 [[VL]])573// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]574//575vuint8m8_t test_vsll_vv_u8m8_tu(vuint8m8_t maskedoff, vuint8m8_t op1, vuint8m8_t shift, size_t vl) {576 return __riscv_vsll_tu(maskedoff, op1, shift, vl);577}578 579// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vsll_vx_u8m8_tu580// CHECK-RV64-SAME: (<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {581// CHECK-RV64-NEXT: entry:582// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vsll.nxv64i8.i64.i64(<vscale x 64 x i8> [[MASKEDOFF]], <vscale x 64 x i8> [[OP1]], i64 [[SHIFT]], i64 [[VL]])583// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]584//585vuint8m8_t test_vsll_vx_u8m8_tu(vuint8m8_t maskedoff, vuint8m8_t op1, size_t shift, size_t vl) {586 return __riscv_vsll_tu(maskedoff, op1, shift, vl);587}588 589// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vsll_vv_u16mf4_tu590// CHECK-RV64-SAME: (<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {591// CHECK-RV64-NEXT: entry:592// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vsll.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]], <vscale x 1 x i16> [[SHIFT]], i64 [[VL]])593// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]594//595vuint16mf4_t test_vsll_vv_u16mf4_tu(vuint16mf4_t maskedoff, vuint16mf4_t op1, vuint16mf4_t shift, size_t vl) {596 return __riscv_vsll_tu(maskedoff, op1, shift, vl);597}598 599// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vsll_vx_u16mf4_tu600// CHECK-RV64-SAME: (<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {601// CHECK-RV64-NEXT: entry:602// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vsll.nxv1i16.i64.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]], i64 [[SHIFT]], i64 [[VL]])603// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]604//605vuint16mf4_t test_vsll_vx_u16mf4_tu(vuint16mf4_t maskedoff, vuint16mf4_t op1, size_t shift, size_t vl) {606 return __riscv_vsll_tu(maskedoff, op1, shift, vl);607}608 609// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vsll_vv_u16mf2_tu610// CHECK-RV64-SAME: (<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {611// CHECK-RV64-NEXT: entry:612// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vsll.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]], <vscale x 2 x i16> [[SHIFT]], i64 [[VL]])613// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]614//615vuint16mf2_t test_vsll_vv_u16mf2_tu(vuint16mf2_t maskedoff, vuint16mf2_t op1, vuint16mf2_t shift, size_t vl) {616 return __riscv_vsll_tu(maskedoff, op1, shift, vl);617}618 619// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vsll_vx_u16mf2_tu620// CHECK-RV64-SAME: (<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {621// CHECK-RV64-NEXT: entry:622// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vsll.nxv2i16.i64.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]], i64 [[SHIFT]], i64 [[VL]])623// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]624//625vuint16mf2_t test_vsll_vx_u16mf2_tu(vuint16mf2_t maskedoff, vuint16mf2_t op1, size_t shift, size_t vl) {626 return __riscv_vsll_tu(maskedoff, op1, shift, vl);627}628 629// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vsll_vv_u16m1_tu630// CHECK-RV64-SAME: (<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {631// CHECK-RV64-NEXT: entry:632// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vsll.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]], <vscale x 4 x i16> [[SHIFT]], i64 [[VL]])633// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]634//635vuint16m1_t test_vsll_vv_u16m1_tu(vuint16m1_t maskedoff, vuint16m1_t op1, vuint16m1_t shift, size_t vl) {636 return __riscv_vsll_tu(maskedoff, op1, shift, vl);637}638 639// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vsll_vx_u16m1_tu640// CHECK-RV64-SAME: (<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {641// CHECK-RV64-NEXT: entry:642// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vsll.nxv4i16.i64.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]], i64 [[SHIFT]], i64 [[VL]])643// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]644//645vuint16m1_t test_vsll_vx_u16m1_tu(vuint16m1_t maskedoff, vuint16m1_t op1, size_t shift, size_t vl) {646 return __riscv_vsll_tu(maskedoff, op1, shift, vl);647}648 649// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vsll_vv_u16m2_tu650// CHECK-RV64-SAME: (<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {651// CHECK-RV64-NEXT: entry:652// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vsll.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]], <vscale x 8 x i16> [[SHIFT]], i64 [[VL]])653// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]654//655vuint16m2_t test_vsll_vv_u16m2_tu(vuint16m2_t maskedoff, vuint16m2_t op1, vuint16m2_t shift, size_t vl) {656 return __riscv_vsll_tu(maskedoff, op1, shift, vl);657}658 659// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vsll_vx_u16m2_tu660// CHECK-RV64-SAME: (<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {661// CHECK-RV64-NEXT: entry:662// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vsll.nxv8i16.i64.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]], i64 [[SHIFT]], i64 [[VL]])663// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]664//665vuint16m2_t test_vsll_vx_u16m2_tu(vuint16m2_t maskedoff, vuint16m2_t op1, size_t shift, size_t vl) {666 return __riscv_vsll_tu(maskedoff, op1, shift, vl);667}668 669// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vsll_vv_u16m4_tu670// CHECK-RV64-SAME: (<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {671// CHECK-RV64-NEXT: entry:672// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vsll.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x i16> [[OP1]], <vscale x 16 x i16> [[SHIFT]], i64 [[VL]])673// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]674//675vuint16m4_t test_vsll_vv_u16m4_tu(vuint16m4_t maskedoff, vuint16m4_t op1, vuint16m4_t shift, size_t vl) {676 return __riscv_vsll_tu(maskedoff, op1, shift, vl);677}678 679// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vsll_vx_u16m4_tu680// CHECK-RV64-SAME: (<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {681// CHECK-RV64-NEXT: entry:682// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vsll.nxv16i16.i64.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x i16> [[OP1]], i64 [[SHIFT]], i64 [[VL]])683// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]684//685vuint16m4_t test_vsll_vx_u16m4_tu(vuint16m4_t maskedoff, vuint16m4_t op1, size_t shift, size_t vl) {686 return __riscv_vsll_tu(maskedoff, op1, shift, vl);687}688 689// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vsll_vv_u16m8_tu690// CHECK-RV64-SAME: (<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {691// CHECK-RV64-NEXT: entry:692// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vsll.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x i16> [[OP1]], <vscale x 32 x i16> [[SHIFT]], i64 [[VL]])693// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]694//695vuint16m8_t test_vsll_vv_u16m8_tu(vuint16m8_t maskedoff, vuint16m8_t op1, vuint16m8_t shift, size_t vl) {696 return __riscv_vsll_tu(maskedoff, op1, shift, vl);697}698 699// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vsll_vx_u16m8_tu700// CHECK-RV64-SAME: (<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {701// CHECK-RV64-NEXT: entry:702// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vsll.nxv32i16.i64.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x i16> [[OP1]], i64 [[SHIFT]], i64 [[VL]])703// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]704//705vuint16m8_t test_vsll_vx_u16m8_tu(vuint16m8_t maskedoff, vuint16m8_t op1, size_t shift, size_t vl) {706 return __riscv_vsll_tu(maskedoff, op1, shift, vl);707}708 709// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vsll_vv_u32mf2_tu710// CHECK-RV64-SAME: (<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {711// CHECK-RV64-NEXT: entry:712// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vsll.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x i32> [[OP1]], <vscale x 1 x i32> [[SHIFT]], i64 [[VL]])713// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]714//715vuint32mf2_t test_vsll_vv_u32mf2_tu(vuint32mf2_t maskedoff, vuint32mf2_t op1, vuint32mf2_t shift, size_t vl) {716 return __riscv_vsll_tu(maskedoff, op1, shift, vl);717}718 719// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vsll_vx_u32mf2_tu720// CHECK-RV64-SAME: (<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {721// CHECK-RV64-NEXT: entry:722// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vsll.nxv1i32.i64.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x i32> [[OP1]], i64 [[SHIFT]], i64 [[VL]])723// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]724//725vuint32mf2_t test_vsll_vx_u32mf2_tu(vuint32mf2_t maskedoff, vuint32mf2_t op1, size_t shift, size_t vl) {726 return __riscv_vsll_tu(maskedoff, op1, shift, vl);727}728 729// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vsll_vv_u32m1_tu730// CHECK-RV64-SAME: (<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {731// CHECK-RV64-NEXT: entry:732// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vsll.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i32> [[OP1]], <vscale x 2 x i32> [[SHIFT]], i64 [[VL]])733// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]734//735vuint32m1_t test_vsll_vv_u32m1_tu(vuint32m1_t maskedoff, vuint32m1_t op1, vuint32m1_t shift, size_t vl) {736 return __riscv_vsll_tu(maskedoff, op1, shift, vl);737}738 739// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vsll_vx_u32m1_tu740// CHECK-RV64-SAME: (<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {741// CHECK-RV64-NEXT: entry:742// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vsll.nxv2i32.i64.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i32> [[OP1]], i64 [[SHIFT]], i64 [[VL]])743// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]744//745vuint32m1_t test_vsll_vx_u32m1_tu(vuint32m1_t maskedoff, vuint32m1_t op1, size_t shift, size_t vl) {746 return __riscv_vsll_tu(maskedoff, op1, shift, vl);747}748 749// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vsll_vv_u32m2_tu750// CHECK-RV64-SAME: (<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {751// CHECK-RV64-NEXT: entry:752// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vsll.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x i32> [[OP1]], <vscale x 4 x i32> [[SHIFT]], i64 [[VL]])753// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]754//755vuint32m2_t test_vsll_vv_u32m2_tu(vuint32m2_t maskedoff, vuint32m2_t op1, vuint32m2_t shift, size_t vl) {756 return __riscv_vsll_tu(maskedoff, op1, shift, vl);757}758 759// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vsll_vx_u32m2_tu760// CHECK-RV64-SAME: (<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {761// CHECK-RV64-NEXT: entry:762// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vsll.nxv4i32.i64.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x i32> [[OP1]], i64 [[SHIFT]], i64 [[VL]])763// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]764//765vuint32m2_t test_vsll_vx_u32m2_tu(vuint32m2_t maskedoff, vuint32m2_t op1, size_t shift, size_t vl) {766 return __riscv_vsll_tu(maskedoff, op1, shift, vl);767}768 769// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vsll_vv_u32m4_tu770// CHECK-RV64-SAME: (<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {771// CHECK-RV64-NEXT: entry:772// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vsll.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x i32> [[OP1]], <vscale x 8 x i32> [[SHIFT]], i64 [[VL]])773// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]774//775vuint32m4_t test_vsll_vv_u32m4_tu(vuint32m4_t maskedoff, vuint32m4_t op1, vuint32m4_t shift, size_t vl) {776 return __riscv_vsll_tu(maskedoff, op1, shift, vl);777}778 779// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vsll_vx_u32m4_tu780// CHECK-RV64-SAME: (<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {781// CHECK-RV64-NEXT: entry:782// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vsll.nxv8i32.i64.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x i32> [[OP1]], i64 [[SHIFT]], i64 [[VL]])783// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]784//785vuint32m4_t test_vsll_vx_u32m4_tu(vuint32m4_t maskedoff, vuint32m4_t op1, size_t shift, size_t vl) {786 return __riscv_vsll_tu(maskedoff, op1, shift, vl);787}788 789// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vsll_vv_u32m8_tu790// CHECK-RV64-SAME: (<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {791// CHECK-RV64-NEXT: entry:792// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vsll.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x i32> [[OP1]], <vscale x 16 x i32> [[SHIFT]], i64 [[VL]])793// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]794//795vuint32m8_t test_vsll_vv_u32m8_tu(vuint32m8_t maskedoff, vuint32m8_t op1, vuint32m8_t shift, size_t vl) {796 return __riscv_vsll_tu(maskedoff, op1, shift, vl);797}798 799// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vsll_vx_u32m8_tu800// CHECK-RV64-SAME: (<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {801// CHECK-RV64-NEXT: entry:802// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vsll.nxv16i32.i64.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x i32> [[OP1]], i64 [[SHIFT]], i64 [[VL]])803// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]804//805vuint32m8_t test_vsll_vx_u32m8_tu(vuint32m8_t maskedoff, vuint32m8_t op1, size_t shift, size_t vl) {806 return __riscv_vsll_tu(maskedoff, op1, shift, vl);807}808 809// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vsll_vv_u64m1_tu810// CHECK-RV64-SAME: (<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {811// CHECK-RV64-NEXT: entry:812// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vsll.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i64> [[OP1]], <vscale x 1 x i64> [[SHIFT]], i64 [[VL]])813// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]814//815vuint64m1_t test_vsll_vv_u64m1_tu(vuint64m1_t maskedoff, vuint64m1_t op1, vuint64m1_t shift, size_t vl) {816 return __riscv_vsll_tu(maskedoff, op1, shift, vl);817}818 819// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vsll_vx_u64m1_tu820// CHECK-RV64-SAME: (<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {821// CHECK-RV64-NEXT: entry:822// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vsll.nxv1i64.i64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i64> [[OP1]], i64 [[SHIFT]], i64 [[VL]])823// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]824//825vuint64m1_t test_vsll_vx_u64m1_tu(vuint64m1_t maskedoff, vuint64m1_t op1, size_t shift, size_t vl) {826 return __riscv_vsll_tu(maskedoff, op1, shift, vl);827}828 829// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vsll_vv_u64m2_tu830// CHECK-RV64-SAME: (<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {831// CHECK-RV64-NEXT: entry:832// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vsll.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i64> [[OP1]], <vscale x 2 x i64> [[SHIFT]], i64 [[VL]])833// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]834//835vuint64m2_t test_vsll_vv_u64m2_tu(vuint64m2_t maskedoff, vuint64m2_t op1, vuint64m2_t shift, size_t vl) {836 return __riscv_vsll_tu(maskedoff, op1, shift, vl);837}838 839// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vsll_vx_u64m2_tu840// CHECK-RV64-SAME: (<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {841// CHECK-RV64-NEXT: entry:842// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vsll.nxv2i64.i64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i64> [[OP1]], i64 [[SHIFT]], i64 [[VL]])843// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]844//845vuint64m2_t test_vsll_vx_u64m2_tu(vuint64m2_t maskedoff, vuint64m2_t op1, size_t shift, size_t vl) {846 return __riscv_vsll_tu(maskedoff, op1, shift, vl);847}848 849// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vsll_vv_u64m4_tu850// CHECK-RV64-SAME: (<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {851// CHECK-RV64-NEXT: entry:852// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vsll.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i64> [[OP1]], <vscale x 4 x i64> [[SHIFT]], i64 [[VL]])853// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]854//855vuint64m4_t test_vsll_vv_u64m4_tu(vuint64m4_t maskedoff, vuint64m4_t op1, vuint64m4_t shift, size_t vl) {856 return __riscv_vsll_tu(maskedoff, op1, shift, vl);857}858 859// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vsll_vx_u64m4_tu860// CHECK-RV64-SAME: (<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {861// CHECK-RV64-NEXT: entry:862// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vsll.nxv4i64.i64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i64> [[OP1]], i64 [[SHIFT]], i64 [[VL]])863// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]864//865vuint64m4_t test_vsll_vx_u64m4_tu(vuint64m4_t maskedoff, vuint64m4_t op1, size_t shift, size_t vl) {866 return __riscv_vsll_tu(maskedoff, op1, shift, vl);867}868 869// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vsll_vv_u64m8_tu870// CHECK-RV64-SAME: (<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {871// CHECK-RV64-NEXT: entry:872// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vsll.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i64> [[OP1]], <vscale x 8 x i64> [[SHIFT]], i64 [[VL]])873// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]874//875vuint64m8_t test_vsll_vv_u64m8_tu(vuint64m8_t maskedoff, vuint64m8_t op1, vuint64m8_t shift, size_t vl) {876 return __riscv_vsll_tu(maskedoff, op1, shift, vl);877}878 879// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vsll_vx_u64m8_tu880// CHECK-RV64-SAME: (<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {881// CHECK-RV64-NEXT: entry:882// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vsll.nxv8i64.i64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i64> [[OP1]], i64 [[SHIFT]], i64 [[VL]])883// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]884//885vuint64m8_t test_vsll_vx_u64m8_tu(vuint64m8_t maskedoff, vuint64m8_t op1, size_t shift, size_t vl) {886 return __riscv_vsll_tu(maskedoff, op1, shift, vl);887}888 889// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vsll_vv_i8mf8_tum890// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {891// CHECK-RV64-NEXT: entry:892// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vsll.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], <vscale x 1 x i8> [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)893// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]894//895vint8mf8_t test_vsll_vv_i8mf8_tum(vbool64_t mask, vint8mf8_t maskedoff, vint8mf8_t op1, vuint8mf8_t shift, size_t vl) {896 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);897}898 899// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vsll_vx_i8mf8_tum900// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {901// CHECK-RV64-NEXT: entry:902// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vsll.mask.nxv1i8.i64.i64(<vscale x 1 x i8> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)903// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]904//905vint8mf8_t test_vsll_vx_i8mf8_tum(vbool64_t mask, vint8mf8_t maskedoff, vint8mf8_t op1, size_t shift, size_t vl) {906 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);907}908 909// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vsll_vv_i8mf4_tum910// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {911// CHECK-RV64-NEXT: entry:912// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vsll.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], <vscale x 2 x i8> [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)913// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]914//915vint8mf4_t test_vsll_vv_i8mf4_tum(vbool32_t mask, vint8mf4_t maskedoff, vint8mf4_t op1, vuint8mf4_t shift, size_t vl) {916 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);917}918 919// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vsll_vx_i8mf4_tum920// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {921// CHECK-RV64-NEXT: entry:922// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vsll.mask.nxv2i8.i64.i64(<vscale x 2 x i8> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)923// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]924//925vint8mf4_t test_vsll_vx_i8mf4_tum(vbool32_t mask, vint8mf4_t maskedoff, vint8mf4_t op1, size_t shift, size_t vl) {926 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);927}928 929// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vsll_vv_i8mf2_tum930// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {931// CHECK-RV64-NEXT: entry:932// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vsll.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF]], <vscale x 4 x i8> [[OP1]], <vscale x 4 x i8> [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)933// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]934//935vint8mf2_t test_vsll_vv_i8mf2_tum(vbool16_t mask, vint8mf2_t maskedoff, vint8mf2_t op1, vuint8mf2_t shift, size_t vl) {936 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);937}938 939// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vsll_vx_i8mf2_tum940// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {941// CHECK-RV64-NEXT: entry:942// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vsll.mask.nxv4i8.i64.i64(<vscale x 4 x i8> [[MASKEDOFF]], <vscale x 4 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)943// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]944//945vint8mf2_t test_vsll_vx_i8mf2_tum(vbool16_t mask, vint8mf2_t maskedoff, vint8mf2_t op1, size_t shift, size_t vl) {946 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);947}948 949// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vsll_vv_i8m1_tum950// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {951// CHECK-RV64-NEXT: entry:952// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vsll.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF]], <vscale x 8 x i8> [[OP1]], <vscale x 8 x i8> [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)953// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]954//955vint8m1_t test_vsll_vv_i8m1_tum(vbool8_t mask, vint8m1_t maskedoff, vint8m1_t op1, vuint8m1_t shift, size_t vl) {956 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);957}958 959// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vsll_vx_i8m1_tum960// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {961// CHECK-RV64-NEXT: entry:962// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vsll.mask.nxv8i8.i64.i64(<vscale x 8 x i8> [[MASKEDOFF]], <vscale x 8 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)963// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]964//965vint8m1_t test_vsll_vx_i8m1_tum(vbool8_t mask, vint8m1_t maskedoff, vint8m1_t op1, size_t shift, size_t vl) {966 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);967}968 969// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vsll_vv_i8m2_tum970// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {971// CHECK-RV64-NEXT: entry:972// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vsll.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF]], <vscale x 16 x i8> [[OP1]], <vscale x 16 x i8> [[SHIFT]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)973// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]974//975vint8m2_t test_vsll_vv_i8m2_tum(vbool4_t mask, vint8m2_t maskedoff, vint8m2_t op1, vuint8m2_t shift, size_t vl) {976 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);977}978 979// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vsll_vx_i8m2_tum980// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {981// CHECK-RV64-NEXT: entry:982// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vsll.mask.nxv16i8.i64.i64(<vscale x 16 x i8> [[MASKEDOFF]], <vscale x 16 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)983// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]984//985vint8m2_t test_vsll_vx_i8m2_tum(vbool4_t mask, vint8m2_t maskedoff, vint8m2_t op1, size_t shift, size_t vl) {986 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);987}988 989// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vsll_vv_i8m4_tum990// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {991// CHECK-RV64-NEXT: entry:992// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vsll.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF]], <vscale x 32 x i8> [[OP1]], <vscale x 32 x i8> [[SHIFT]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2)993// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]994//995vint8m4_t test_vsll_vv_i8m4_tum(vbool2_t mask, vint8m4_t maskedoff, vint8m4_t op1, vuint8m4_t shift, size_t vl) {996 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);997}998 999// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vsll_vx_i8m4_tum1000// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1001// CHECK-RV64-NEXT: entry:1002// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vsll.mask.nxv32i8.i64.i64(<vscale x 32 x i8> [[MASKEDOFF]], <vscale x 32 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2)1003// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]1004//1005vint8m4_t test_vsll_vx_i8m4_tum(vbool2_t mask, vint8m4_t maskedoff, vint8m4_t op1, size_t shift, size_t vl) {1006 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1007}1008 1009// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vsll_vv_i8m8_tum1010// CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1011// CHECK-RV64-NEXT: entry:1012// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vsll.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF]], <vscale x 64 x i8> [[OP1]], <vscale x 64 x i8> [[SHIFT]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 2)1013// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]1014//1015vint8m8_t test_vsll_vv_i8m8_tum(vbool1_t mask, vint8m8_t maskedoff, vint8m8_t op1, vuint8m8_t shift, size_t vl) {1016 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1017}1018 1019// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vsll_vx_i8m8_tum1020// CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1021// CHECK-RV64-NEXT: entry:1022// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vsll.mask.nxv64i8.i64.i64(<vscale x 64 x i8> [[MASKEDOFF]], <vscale x 64 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 2)1023// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]1024//1025vint8m8_t test_vsll_vx_i8m8_tum(vbool1_t mask, vint8m8_t maskedoff, vint8m8_t op1, size_t shift, size_t vl) {1026 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1027}1028 1029// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vsll_vv_i16mf4_tum1030// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1031// CHECK-RV64-NEXT: entry:1032// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vsll.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]], <vscale x 1 x i16> [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)1033// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]1034//1035vint16mf4_t test_vsll_vv_i16mf4_tum(vbool64_t mask, vint16mf4_t maskedoff, vint16mf4_t op1, vuint16mf4_t shift, size_t vl) {1036 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1037}1038 1039// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vsll_vx_i16mf4_tum1040// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1041// CHECK-RV64-NEXT: entry:1042// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vsll.mask.nxv1i16.i64.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)1043// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]1044//1045vint16mf4_t test_vsll_vx_i16mf4_tum(vbool64_t mask, vint16mf4_t maskedoff, vint16mf4_t op1, size_t shift, size_t vl) {1046 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1047}1048 1049// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vsll_vv_i16mf2_tum1050// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1051// CHECK-RV64-NEXT: entry:1052// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vsll.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]], <vscale x 2 x i16> [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)1053// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]1054//1055vint16mf2_t test_vsll_vv_i16mf2_tum(vbool32_t mask, vint16mf2_t maskedoff, vint16mf2_t op1, vuint16mf2_t shift, size_t vl) {1056 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1057}1058 1059// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vsll_vx_i16mf2_tum1060// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1061// CHECK-RV64-NEXT: entry:1062// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vsll.mask.nxv2i16.i64.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)1063// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]1064//1065vint16mf2_t test_vsll_vx_i16mf2_tum(vbool32_t mask, vint16mf2_t maskedoff, vint16mf2_t op1, size_t shift, size_t vl) {1066 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1067}1068 1069// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vsll_vv_i16m1_tum1070// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1071// CHECK-RV64-NEXT: entry:1072// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vsll.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]], <vscale x 4 x i16> [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)1073// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]1074//1075vint16m1_t test_vsll_vv_i16m1_tum(vbool16_t mask, vint16m1_t maskedoff, vint16m1_t op1, vuint16m1_t shift, size_t vl) {1076 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1077}1078 1079// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vsll_vx_i16m1_tum1080// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1081// CHECK-RV64-NEXT: entry:1082// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vsll.mask.nxv4i16.i64.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)1083// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]1084//1085vint16m1_t test_vsll_vx_i16m1_tum(vbool16_t mask, vint16m1_t maskedoff, vint16m1_t op1, size_t shift, size_t vl) {1086 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1087}1088 1089// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vsll_vv_i16m2_tum1090// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1091// CHECK-RV64-NEXT: entry:1092// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vsll.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]], <vscale x 8 x i16> [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)1093// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]1094//1095vint16m2_t test_vsll_vv_i16m2_tum(vbool8_t mask, vint16m2_t maskedoff, vint16m2_t op1, vuint16m2_t shift, size_t vl) {1096 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1097}1098 1099// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vsll_vx_i16m2_tum1100// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1101// CHECK-RV64-NEXT: entry:1102// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vsll.mask.nxv8i16.i64.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)1103// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]1104//1105vint16m2_t test_vsll_vx_i16m2_tum(vbool8_t mask, vint16m2_t maskedoff, vint16m2_t op1, size_t shift, size_t vl) {1106 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1107}1108 1109// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vsll_vv_i16m4_tum1110// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1111// CHECK-RV64-NEXT: entry:1112// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vsll.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x i16> [[OP1]], <vscale x 16 x i16> [[SHIFT]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)1113// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]1114//1115vint16m4_t test_vsll_vv_i16m4_tum(vbool4_t mask, vint16m4_t maskedoff, vint16m4_t op1, vuint16m4_t shift, size_t vl) {1116 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1117}1118 1119// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vsll_vx_i16m4_tum1120// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1121// CHECK-RV64-NEXT: entry:1122// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vsll.mask.nxv16i16.i64.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)1123// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]1124//1125vint16m4_t test_vsll_vx_i16m4_tum(vbool4_t mask, vint16m4_t maskedoff, vint16m4_t op1, size_t shift, size_t vl) {1126 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1127}1128 1129// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vsll_vv_i16m8_tum1130// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1131// CHECK-RV64-NEXT: entry:1132// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vsll.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x i16> [[OP1]], <vscale x 32 x i16> [[SHIFT]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2)1133// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]1134//1135vint16m8_t test_vsll_vv_i16m8_tum(vbool2_t mask, vint16m8_t maskedoff, vint16m8_t op1, vuint16m8_t shift, size_t vl) {1136 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1137}1138 1139// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vsll_vx_i16m8_tum1140// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1141// CHECK-RV64-NEXT: entry:1142// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vsll.mask.nxv32i16.i64.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2)1143// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]1144//1145vint16m8_t test_vsll_vx_i16m8_tum(vbool2_t mask, vint16m8_t maskedoff, vint16m8_t op1, size_t shift, size_t vl) {1146 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1147}1148 1149// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vsll_vv_i32mf2_tum1150// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1151// CHECK-RV64-NEXT: entry:1152// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vsll.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x i32> [[OP1]], <vscale x 1 x i32> [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)1153// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]1154//1155vint32mf2_t test_vsll_vv_i32mf2_tum(vbool64_t mask, vint32mf2_t maskedoff, vint32mf2_t op1, vuint32mf2_t shift, size_t vl) {1156 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1157}1158 1159// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vsll_vx_i32mf2_tum1160// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1161// CHECK-RV64-NEXT: entry:1162// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vsll.mask.nxv1i32.i64.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x i32> [[OP1]], i64 [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)1163// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]1164//1165vint32mf2_t test_vsll_vx_i32mf2_tum(vbool64_t mask, vint32mf2_t maskedoff, vint32mf2_t op1, size_t shift, size_t vl) {1166 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1167}1168 1169// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vsll_vv_i32m1_tum1170// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1171// CHECK-RV64-NEXT: entry:1172// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vsll.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i32> [[OP1]], <vscale x 2 x i32> [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)1173// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]1174//1175vint32m1_t test_vsll_vv_i32m1_tum(vbool32_t mask, vint32m1_t maskedoff, vint32m1_t op1, vuint32m1_t shift, size_t vl) {1176 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1177}1178 1179// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vsll_vx_i32m1_tum1180// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1181// CHECK-RV64-NEXT: entry:1182// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vsll.mask.nxv2i32.i64.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i32> [[OP1]], i64 [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)1183// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]1184//1185vint32m1_t test_vsll_vx_i32m1_tum(vbool32_t mask, vint32m1_t maskedoff, vint32m1_t op1, size_t shift, size_t vl) {1186 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1187}1188 1189// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vsll_vv_i32m2_tum1190// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1191// CHECK-RV64-NEXT: entry:1192// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vsll.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x i32> [[OP1]], <vscale x 4 x i32> [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)1193// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]1194//1195vint32m2_t test_vsll_vv_i32m2_tum(vbool16_t mask, vint32m2_t maskedoff, vint32m2_t op1, vuint32m2_t shift, size_t vl) {1196 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1197}1198 1199// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vsll_vx_i32m2_tum1200// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1201// CHECK-RV64-NEXT: entry:1202// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vsll.mask.nxv4i32.i64.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x i32> [[OP1]], i64 [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)1203// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]1204//1205vint32m2_t test_vsll_vx_i32m2_tum(vbool16_t mask, vint32m2_t maskedoff, vint32m2_t op1, size_t shift, size_t vl) {1206 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1207}1208 1209// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vsll_vv_i32m4_tum1210// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1211// CHECK-RV64-NEXT: entry:1212// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vsll.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x i32> [[OP1]], <vscale x 8 x i32> [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)1213// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]1214//1215vint32m4_t test_vsll_vv_i32m4_tum(vbool8_t mask, vint32m4_t maskedoff, vint32m4_t op1, vuint32m4_t shift, size_t vl) {1216 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1217}1218 1219// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vsll_vx_i32m4_tum1220// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1221// CHECK-RV64-NEXT: entry:1222// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vsll.mask.nxv8i32.i64.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x i32> [[OP1]], i64 [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)1223// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]1224//1225vint32m4_t test_vsll_vx_i32m4_tum(vbool8_t mask, vint32m4_t maskedoff, vint32m4_t op1, size_t shift, size_t vl) {1226 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1227}1228 1229// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vsll_vv_i32m8_tum1230// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1231// CHECK-RV64-NEXT: entry:1232// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vsll.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x i32> [[OP1]], <vscale x 16 x i32> [[SHIFT]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)1233// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]1234//1235vint32m8_t test_vsll_vv_i32m8_tum(vbool4_t mask, vint32m8_t maskedoff, vint32m8_t op1, vuint32m8_t shift, size_t vl) {1236 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1237}1238 1239// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vsll_vx_i32m8_tum1240// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1241// CHECK-RV64-NEXT: entry:1242// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vsll.mask.nxv16i32.i64.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x i32> [[OP1]], i64 [[SHIFT]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)1243// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]1244//1245vint32m8_t test_vsll_vx_i32m8_tum(vbool4_t mask, vint32m8_t maskedoff, vint32m8_t op1, size_t shift, size_t vl) {1246 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1247}1248 1249// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vsll_vv_i64m1_tum1250// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1251// CHECK-RV64-NEXT: entry:1252// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vsll.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i64> [[OP1]], <vscale x 1 x i64> [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)1253// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]1254//1255vint64m1_t test_vsll_vv_i64m1_tum(vbool64_t mask, vint64m1_t maskedoff, vint64m1_t op1, vuint64m1_t shift, size_t vl) {1256 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1257}1258 1259// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vsll_vx_i64m1_tum1260// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1261// CHECK-RV64-NEXT: entry:1262// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vsll.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i64> [[OP1]], i64 [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)1263// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]1264//1265vint64m1_t test_vsll_vx_i64m1_tum(vbool64_t mask, vint64m1_t maskedoff, vint64m1_t op1, size_t shift, size_t vl) {1266 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1267}1268 1269// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vsll_vv_i64m2_tum1270// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1271// CHECK-RV64-NEXT: entry:1272// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vsll.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i64> [[OP1]], <vscale x 2 x i64> [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)1273// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]1274//1275vint64m2_t test_vsll_vv_i64m2_tum(vbool32_t mask, vint64m2_t maskedoff, vint64m2_t op1, vuint64m2_t shift, size_t vl) {1276 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1277}1278 1279// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vsll_vx_i64m2_tum1280// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1281// CHECK-RV64-NEXT: entry:1282// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vsll.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i64> [[OP1]], i64 [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)1283// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]1284//1285vint64m2_t test_vsll_vx_i64m2_tum(vbool32_t mask, vint64m2_t maskedoff, vint64m2_t op1, size_t shift, size_t vl) {1286 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1287}1288 1289// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vsll_vv_i64m4_tum1290// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1291// CHECK-RV64-NEXT: entry:1292// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vsll.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i64> [[OP1]], <vscale x 4 x i64> [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)1293// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]1294//1295vint64m4_t test_vsll_vv_i64m4_tum(vbool16_t mask, vint64m4_t maskedoff, vint64m4_t op1, vuint64m4_t shift, size_t vl) {1296 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1297}1298 1299// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vsll_vx_i64m4_tum1300// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1301// CHECK-RV64-NEXT: entry:1302// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vsll.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i64> [[OP1]], i64 [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)1303// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]1304//1305vint64m4_t test_vsll_vx_i64m4_tum(vbool16_t mask, vint64m4_t maskedoff, vint64m4_t op1, size_t shift, size_t vl) {1306 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1307}1308 1309// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vsll_vv_i64m8_tum1310// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1311// CHECK-RV64-NEXT: entry:1312// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vsll.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i64> [[OP1]], <vscale x 8 x i64> [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)1313// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]1314//1315vint64m8_t test_vsll_vv_i64m8_tum(vbool8_t mask, vint64m8_t maskedoff, vint64m8_t op1, vuint64m8_t shift, size_t vl) {1316 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1317}1318 1319// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vsll_vx_i64m8_tum1320// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1321// CHECK-RV64-NEXT: entry:1322// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vsll.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i64> [[OP1]], i64 [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)1323// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]1324//1325vint64m8_t test_vsll_vx_i64m8_tum(vbool8_t mask, vint64m8_t maskedoff, vint64m8_t op1, size_t shift, size_t vl) {1326 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1327}1328 1329// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vsll_vv_u8mf8_tum1330// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1331// CHECK-RV64-NEXT: entry:1332// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vsll.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], <vscale x 1 x i8> [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)1333// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]1334//1335vuint8mf8_t test_vsll_vv_u8mf8_tum(vbool64_t mask, vuint8mf8_t maskedoff, vuint8mf8_t op1, vuint8mf8_t shift, size_t vl) {1336 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1337}1338 1339// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vsll_vx_u8mf8_tum1340// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1341// CHECK-RV64-NEXT: entry:1342// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vsll.mask.nxv1i8.i64.i64(<vscale x 1 x i8> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)1343// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]1344//1345vuint8mf8_t test_vsll_vx_u8mf8_tum(vbool64_t mask, vuint8mf8_t maskedoff, vuint8mf8_t op1, size_t shift, size_t vl) {1346 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1347}1348 1349// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vsll_vv_u8mf4_tum1350// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1351// CHECK-RV64-NEXT: entry:1352// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vsll.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], <vscale x 2 x i8> [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)1353// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]1354//1355vuint8mf4_t test_vsll_vv_u8mf4_tum(vbool32_t mask, vuint8mf4_t maskedoff, vuint8mf4_t op1, vuint8mf4_t shift, size_t vl) {1356 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1357}1358 1359// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vsll_vx_u8mf4_tum1360// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1361// CHECK-RV64-NEXT: entry:1362// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vsll.mask.nxv2i8.i64.i64(<vscale x 2 x i8> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)1363// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]1364//1365vuint8mf4_t test_vsll_vx_u8mf4_tum(vbool32_t mask, vuint8mf4_t maskedoff, vuint8mf4_t op1, size_t shift, size_t vl) {1366 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1367}1368 1369// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vsll_vv_u8mf2_tum1370// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1371// CHECK-RV64-NEXT: entry:1372// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vsll.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF]], <vscale x 4 x i8> [[OP1]], <vscale x 4 x i8> [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)1373// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]1374//1375vuint8mf2_t test_vsll_vv_u8mf2_tum(vbool16_t mask, vuint8mf2_t maskedoff, vuint8mf2_t op1, vuint8mf2_t shift, size_t vl) {1376 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1377}1378 1379// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vsll_vx_u8mf2_tum1380// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1381// CHECK-RV64-NEXT: entry:1382// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vsll.mask.nxv4i8.i64.i64(<vscale x 4 x i8> [[MASKEDOFF]], <vscale x 4 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)1383// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]1384//1385vuint8mf2_t test_vsll_vx_u8mf2_tum(vbool16_t mask, vuint8mf2_t maskedoff, vuint8mf2_t op1, size_t shift, size_t vl) {1386 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1387}1388 1389// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vsll_vv_u8m1_tum1390// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1391// CHECK-RV64-NEXT: entry:1392// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vsll.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF]], <vscale x 8 x i8> [[OP1]], <vscale x 8 x i8> [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)1393// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]1394//1395vuint8m1_t test_vsll_vv_u8m1_tum(vbool8_t mask, vuint8m1_t maskedoff, vuint8m1_t op1, vuint8m1_t shift, size_t vl) {1396 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1397}1398 1399// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vsll_vx_u8m1_tum1400// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1401// CHECK-RV64-NEXT: entry:1402// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vsll.mask.nxv8i8.i64.i64(<vscale x 8 x i8> [[MASKEDOFF]], <vscale x 8 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)1403// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]1404//1405vuint8m1_t test_vsll_vx_u8m1_tum(vbool8_t mask, vuint8m1_t maskedoff, vuint8m1_t op1, size_t shift, size_t vl) {1406 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1407}1408 1409// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vsll_vv_u8m2_tum1410// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1411// CHECK-RV64-NEXT: entry:1412// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vsll.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF]], <vscale x 16 x i8> [[OP1]], <vscale x 16 x i8> [[SHIFT]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)1413// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]1414//1415vuint8m2_t test_vsll_vv_u8m2_tum(vbool4_t mask, vuint8m2_t maskedoff, vuint8m2_t op1, vuint8m2_t shift, size_t vl) {1416 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1417}1418 1419// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vsll_vx_u8m2_tum1420// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1421// CHECK-RV64-NEXT: entry:1422// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vsll.mask.nxv16i8.i64.i64(<vscale x 16 x i8> [[MASKEDOFF]], <vscale x 16 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)1423// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]1424//1425vuint8m2_t test_vsll_vx_u8m2_tum(vbool4_t mask, vuint8m2_t maskedoff, vuint8m2_t op1, size_t shift, size_t vl) {1426 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1427}1428 1429// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vsll_vv_u8m4_tum1430// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1431// CHECK-RV64-NEXT: entry:1432// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vsll.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF]], <vscale x 32 x i8> [[OP1]], <vscale x 32 x i8> [[SHIFT]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2)1433// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]1434//1435vuint8m4_t test_vsll_vv_u8m4_tum(vbool2_t mask, vuint8m4_t maskedoff, vuint8m4_t op1, vuint8m4_t shift, size_t vl) {1436 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1437}1438 1439// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vsll_vx_u8m4_tum1440// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1441// CHECK-RV64-NEXT: entry:1442// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vsll.mask.nxv32i8.i64.i64(<vscale x 32 x i8> [[MASKEDOFF]], <vscale x 32 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2)1443// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]1444//1445vuint8m4_t test_vsll_vx_u8m4_tum(vbool2_t mask, vuint8m4_t maskedoff, vuint8m4_t op1, size_t shift, size_t vl) {1446 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1447}1448 1449// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vsll_vv_u8m8_tum1450// CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1451// CHECK-RV64-NEXT: entry:1452// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vsll.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF]], <vscale x 64 x i8> [[OP1]], <vscale x 64 x i8> [[SHIFT]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 2)1453// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]1454//1455vuint8m8_t test_vsll_vv_u8m8_tum(vbool1_t mask, vuint8m8_t maskedoff, vuint8m8_t op1, vuint8m8_t shift, size_t vl) {1456 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1457}1458 1459// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vsll_vx_u8m8_tum1460// CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1461// CHECK-RV64-NEXT: entry:1462// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vsll.mask.nxv64i8.i64.i64(<vscale x 64 x i8> [[MASKEDOFF]], <vscale x 64 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 2)1463// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]1464//1465vuint8m8_t test_vsll_vx_u8m8_tum(vbool1_t mask, vuint8m8_t maskedoff, vuint8m8_t op1, size_t shift, size_t vl) {1466 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1467}1468 1469// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vsll_vv_u16mf4_tum1470// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1471// CHECK-RV64-NEXT: entry:1472// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vsll.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]], <vscale x 1 x i16> [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)1473// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]1474//1475vuint16mf4_t test_vsll_vv_u16mf4_tum(vbool64_t mask, vuint16mf4_t maskedoff, vuint16mf4_t op1, vuint16mf4_t shift, size_t vl) {1476 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1477}1478 1479// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vsll_vx_u16mf4_tum1480// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1481// CHECK-RV64-NEXT: entry:1482// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vsll.mask.nxv1i16.i64.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)1483// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]1484//1485vuint16mf4_t test_vsll_vx_u16mf4_tum(vbool64_t mask, vuint16mf4_t maskedoff, vuint16mf4_t op1, size_t shift, size_t vl) {1486 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1487}1488 1489// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vsll_vv_u16mf2_tum1490// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1491// CHECK-RV64-NEXT: entry:1492// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vsll.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]], <vscale x 2 x i16> [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)1493// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]1494//1495vuint16mf2_t test_vsll_vv_u16mf2_tum(vbool32_t mask, vuint16mf2_t maskedoff, vuint16mf2_t op1, vuint16mf2_t shift, size_t vl) {1496 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1497}1498 1499// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vsll_vx_u16mf2_tum1500// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1501// CHECK-RV64-NEXT: entry:1502// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vsll.mask.nxv2i16.i64.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)1503// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]1504//1505vuint16mf2_t test_vsll_vx_u16mf2_tum(vbool32_t mask, vuint16mf2_t maskedoff, vuint16mf2_t op1, size_t shift, size_t vl) {1506 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1507}1508 1509// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vsll_vv_u16m1_tum1510// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1511// CHECK-RV64-NEXT: entry:1512// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vsll.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]], <vscale x 4 x i16> [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)1513// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]1514//1515vuint16m1_t test_vsll_vv_u16m1_tum(vbool16_t mask, vuint16m1_t maskedoff, vuint16m1_t op1, vuint16m1_t shift, size_t vl) {1516 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1517}1518 1519// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vsll_vx_u16m1_tum1520// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1521// CHECK-RV64-NEXT: entry:1522// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vsll.mask.nxv4i16.i64.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)1523// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]1524//1525vuint16m1_t test_vsll_vx_u16m1_tum(vbool16_t mask, vuint16m1_t maskedoff, vuint16m1_t op1, size_t shift, size_t vl) {1526 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1527}1528 1529// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vsll_vv_u16m2_tum1530// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1531// CHECK-RV64-NEXT: entry:1532// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vsll.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]], <vscale x 8 x i16> [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)1533// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]1534//1535vuint16m2_t test_vsll_vv_u16m2_tum(vbool8_t mask, vuint16m2_t maskedoff, vuint16m2_t op1, vuint16m2_t shift, size_t vl) {1536 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1537}1538 1539// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vsll_vx_u16m2_tum1540// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1541// CHECK-RV64-NEXT: entry:1542// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vsll.mask.nxv8i16.i64.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)1543// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]1544//1545vuint16m2_t test_vsll_vx_u16m2_tum(vbool8_t mask, vuint16m2_t maskedoff, vuint16m2_t op1, size_t shift, size_t vl) {1546 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1547}1548 1549// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vsll_vv_u16m4_tum1550// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1551// CHECK-RV64-NEXT: entry:1552// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vsll.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x i16> [[OP1]], <vscale x 16 x i16> [[SHIFT]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)1553// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]1554//1555vuint16m4_t test_vsll_vv_u16m4_tum(vbool4_t mask, vuint16m4_t maskedoff, vuint16m4_t op1, vuint16m4_t shift, size_t vl) {1556 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1557}1558 1559// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vsll_vx_u16m4_tum1560// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1561// CHECK-RV64-NEXT: entry:1562// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vsll.mask.nxv16i16.i64.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)1563// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]1564//1565vuint16m4_t test_vsll_vx_u16m4_tum(vbool4_t mask, vuint16m4_t maskedoff, vuint16m4_t op1, size_t shift, size_t vl) {1566 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1567}1568 1569// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vsll_vv_u16m8_tum1570// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1571// CHECK-RV64-NEXT: entry:1572// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vsll.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x i16> [[OP1]], <vscale x 32 x i16> [[SHIFT]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2)1573// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]1574//1575vuint16m8_t test_vsll_vv_u16m8_tum(vbool2_t mask, vuint16m8_t maskedoff, vuint16m8_t op1, vuint16m8_t shift, size_t vl) {1576 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1577}1578 1579// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vsll_vx_u16m8_tum1580// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1581// CHECK-RV64-NEXT: entry:1582// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vsll.mask.nxv32i16.i64.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2)1583// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]1584//1585vuint16m8_t test_vsll_vx_u16m8_tum(vbool2_t mask, vuint16m8_t maskedoff, vuint16m8_t op1, size_t shift, size_t vl) {1586 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1587}1588 1589// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vsll_vv_u32mf2_tum1590// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1591// CHECK-RV64-NEXT: entry:1592// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vsll.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x i32> [[OP1]], <vscale x 1 x i32> [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)1593// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]1594//1595vuint32mf2_t test_vsll_vv_u32mf2_tum(vbool64_t mask, vuint32mf2_t maskedoff, vuint32mf2_t op1, vuint32mf2_t shift, size_t vl) {1596 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1597}1598 1599// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vsll_vx_u32mf2_tum1600// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1601// CHECK-RV64-NEXT: entry:1602// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vsll.mask.nxv1i32.i64.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x i32> [[OP1]], i64 [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)1603// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]1604//1605vuint32mf2_t test_vsll_vx_u32mf2_tum(vbool64_t mask, vuint32mf2_t maskedoff, vuint32mf2_t op1, size_t shift, size_t vl) {1606 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1607}1608 1609// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vsll_vv_u32m1_tum1610// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1611// CHECK-RV64-NEXT: entry:1612// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vsll.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i32> [[OP1]], <vscale x 2 x i32> [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)1613// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]1614//1615vuint32m1_t test_vsll_vv_u32m1_tum(vbool32_t mask, vuint32m1_t maskedoff, vuint32m1_t op1, vuint32m1_t shift, size_t vl) {1616 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1617}1618 1619// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vsll_vx_u32m1_tum1620// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1621// CHECK-RV64-NEXT: entry:1622// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vsll.mask.nxv2i32.i64.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i32> [[OP1]], i64 [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)1623// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]1624//1625vuint32m1_t test_vsll_vx_u32m1_tum(vbool32_t mask, vuint32m1_t maskedoff, vuint32m1_t op1, size_t shift, size_t vl) {1626 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1627}1628 1629// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vsll_vv_u32m2_tum1630// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1631// CHECK-RV64-NEXT: entry:1632// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vsll.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x i32> [[OP1]], <vscale x 4 x i32> [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)1633// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]1634//1635vuint32m2_t test_vsll_vv_u32m2_tum(vbool16_t mask, vuint32m2_t maskedoff, vuint32m2_t op1, vuint32m2_t shift, size_t vl) {1636 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1637}1638 1639// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vsll_vx_u32m2_tum1640// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1641// CHECK-RV64-NEXT: entry:1642// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vsll.mask.nxv4i32.i64.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x i32> [[OP1]], i64 [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)1643// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]1644//1645vuint32m2_t test_vsll_vx_u32m2_tum(vbool16_t mask, vuint32m2_t maskedoff, vuint32m2_t op1, size_t shift, size_t vl) {1646 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1647}1648 1649// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vsll_vv_u32m4_tum1650// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1651// CHECK-RV64-NEXT: entry:1652// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vsll.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x i32> [[OP1]], <vscale x 8 x i32> [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)1653// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]1654//1655vuint32m4_t test_vsll_vv_u32m4_tum(vbool8_t mask, vuint32m4_t maskedoff, vuint32m4_t op1, vuint32m4_t shift, size_t vl) {1656 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1657}1658 1659// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vsll_vx_u32m4_tum1660// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1661// CHECK-RV64-NEXT: entry:1662// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vsll.mask.nxv8i32.i64.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x i32> [[OP1]], i64 [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)1663// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]1664//1665vuint32m4_t test_vsll_vx_u32m4_tum(vbool8_t mask, vuint32m4_t maskedoff, vuint32m4_t op1, size_t shift, size_t vl) {1666 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1667}1668 1669// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vsll_vv_u32m8_tum1670// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1671// CHECK-RV64-NEXT: entry:1672// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vsll.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x i32> [[OP1]], <vscale x 16 x i32> [[SHIFT]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)1673// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]1674//1675vuint32m8_t test_vsll_vv_u32m8_tum(vbool4_t mask, vuint32m8_t maskedoff, vuint32m8_t op1, vuint32m8_t shift, size_t vl) {1676 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1677}1678 1679// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vsll_vx_u32m8_tum1680// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1681// CHECK-RV64-NEXT: entry:1682// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vsll.mask.nxv16i32.i64.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x i32> [[OP1]], i64 [[SHIFT]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)1683// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]1684//1685vuint32m8_t test_vsll_vx_u32m8_tum(vbool4_t mask, vuint32m8_t maskedoff, vuint32m8_t op1, size_t shift, size_t vl) {1686 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1687}1688 1689// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vsll_vv_u64m1_tum1690// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1691// CHECK-RV64-NEXT: entry:1692// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vsll.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i64> [[OP1]], <vscale x 1 x i64> [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)1693// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]1694//1695vuint64m1_t test_vsll_vv_u64m1_tum(vbool64_t mask, vuint64m1_t maskedoff, vuint64m1_t op1, vuint64m1_t shift, size_t vl) {1696 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1697}1698 1699// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vsll_vx_u64m1_tum1700// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1701// CHECK-RV64-NEXT: entry:1702// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vsll.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i64> [[OP1]], i64 [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)1703// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]1704//1705vuint64m1_t test_vsll_vx_u64m1_tum(vbool64_t mask, vuint64m1_t maskedoff, vuint64m1_t op1, size_t shift, size_t vl) {1706 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1707}1708 1709// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vsll_vv_u64m2_tum1710// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1711// CHECK-RV64-NEXT: entry:1712// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vsll.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i64> [[OP1]], <vscale x 2 x i64> [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)1713// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]1714//1715vuint64m2_t test_vsll_vv_u64m2_tum(vbool32_t mask, vuint64m2_t maskedoff, vuint64m2_t op1, vuint64m2_t shift, size_t vl) {1716 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1717}1718 1719// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vsll_vx_u64m2_tum1720// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1721// CHECK-RV64-NEXT: entry:1722// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vsll.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i64> [[OP1]], i64 [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)1723// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]1724//1725vuint64m2_t test_vsll_vx_u64m2_tum(vbool32_t mask, vuint64m2_t maskedoff, vuint64m2_t op1, size_t shift, size_t vl) {1726 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1727}1728 1729// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vsll_vv_u64m4_tum1730// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1731// CHECK-RV64-NEXT: entry:1732// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vsll.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i64> [[OP1]], <vscale x 4 x i64> [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)1733// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]1734//1735vuint64m4_t test_vsll_vv_u64m4_tum(vbool16_t mask, vuint64m4_t maskedoff, vuint64m4_t op1, vuint64m4_t shift, size_t vl) {1736 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1737}1738 1739// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vsll_vx_u64m4_tum1740// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1741// CHECK-RV64-NEXT: entry:1742// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vsll.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i64> [[OP1]], i64 [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)1743// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]1744//1745vuint64m4_t test_vsll_vx_u64m4_tum(vbool16_t mask, vuint64m4_t maskedoff, vuint64m4_t op1, size_t shift, size_t vl) {1746 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1747}1748 1749// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vsll_vv_u64m8_tum1750// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1751// CHECK-RV64-NEXT: entry:1752// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vsll.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i64> [[OP1]], <vscale x 8 x i64> [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)1753// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]1754//1755vuint64m8_t test_vsll_vv_u64m8_tum(vbool8_t mask, vuint64m8_t maskedoff, vuint64m8_t op1, vuint64m8_t shift, size_t vl) {1756 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1757}1758 1759// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vsll_vx_u64m8_tum1760// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1761// CHECK-RV64-NEXT: entry:1762// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vsll.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i64> [[OP1]], i64 [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)1763// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]1764//1765vuint64m8_t test_vsll_vx_u64m8_tum(vbool8_t mask, vuint64m8_t maskedoff, vuint64m8_t op1, size_t shift, size_t vl) {1766 return __riscv_vsll_tum(mask, maskedoff, op1, shift, vl);1767}1768 1769// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vsll_vv_i8mf8_tumu1770// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1771// CHECK-RV64-NEXT: entry:1772// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vsll.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], <vscale x 1 x i8> [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)1773// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]1774//1775vint8mf8_t test_vsll_vv_i8mf8_tumu(vbool64_t mask, vint8mf8_t maskedoff, vint8mf8_t op1, vuint8mf8_t shift, size_t vl) {1776 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);1777}1778 1779// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vsll_vx_i8mf8_tumu1780// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1781// CHECK-RV64-NEXT: entry:1782// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vsll.mask.nxv1i8.i64.i64(<vscale x 1 x i8> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)1783// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]1784//1785vint8mf8_t test_vsll_vx_i8mf8_tumu(vbool64_t mask, vint8mf8_t maskedoff, vint8mf8_t op1, size_t shift, size_t vl) {1786 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);1787}1788 1789// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vsll_vv_i8mf4_tumu1790// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1791// CHECK-RV64-NEXT: entry:1792// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vsll.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], <vscale x 2 x i8> [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)1793// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]1794//1795vint8mf4_t test_vsll_vv_i8mf4_tumu(vbool32_t mask, vint8mf4_t maskedoff, vint8mf4_t op1, vuint8mf4_t shift, size_t vl) {1796 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);1797}1798 1799// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vsll_vx_i8mf4_tumu1800// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1801// CHECK-RV64-NEXT: entry:1802// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vsll.mask.nxv2i8.i64.i64(<vscale x 2 x i8> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)1803// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]1804//1805vint8mf4_t test_vsll_vx_i8mf4_tumu(vbool32_t mask, vint8mf4_t maskedoff, vint8mf4_t op1, size_t shift, size_t vl) {1806 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);1807}1808 1809// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vsll_vv_i8mf2_tumu1810// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1811// CHECK-RV64-NEXT: entry:1812// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vsll.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF]], <vscale x 4 x i8> [[OP1]], <vscale x 4 x i8> [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)1813// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]1814//1815vint8mf2_t test_vsll_vv_i8mf2_tumu(vbool16_t mask, vint8mf2_t maskedoff, vint8mf2_t op1, vuint8mf2_t shift, size_t vl) {1816 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);1817}1818 1819// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vsll_vx_i8mf2_tumu1820// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1821// CHECK-RV64-NEXT: entry:1822// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vsll.mask.nxv4i8.i64.i64(<vscale x 4 x i8> [[MASKEDOFF]], <vscale x 4 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)1823// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]1824//1825vint8mf2_t test_vsll_vx_i8mf2_tumu(vbool16_t mask, vint8mf2_t maskedoff, vint8mf2_t op1, size_t shift, size_t vl) {1826 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);1827}1828 1829// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vsll_vv_i8m1_tumu1830// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1831// CHECK-RV64-NEXT: entry:1832// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vsll.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF]], <vscale x 8 x i8> [[OP1]], <vscale x 8 x i8> [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)1833// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]1834//1835vint8m1_t test_vsll_vv_i8m1_tumu(vbool8_t mask, vint8m1_t maskedoff, vint8m1_t op1, vuint8m1_t shift, size_t vl) {1836 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);1837}1838 1839// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vsll_vx_i8m1_tumu1840// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1841// CHECK-RV64-NEXT: entry:1842// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vsll.mask.nxv8i8.i64.i64(<vscale x 8 x i8> [[MASKEDOFF]], <vscale x 8 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)1843// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]1844//1845vint8m1_t test_vsll_vx_i8m1_tumu(vbool8_t mask, vint8m1_t maskedoff, vint8m1_t op1, size_t shift, size_t vl) {1846 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);1847}1848 1849// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vsll_vv_i8m2_tumu1850// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1851// CHECK-RV64-NEXT: entry:1852// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vsll.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF]], <vscale x 16 x i8> [[OP1]], <vscale x 16 x i8> [[SHIFT]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)1853// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]1854//1855vint8m2_t test_vsll_vv_i8m2_tumu(vbool4_t mask, vint8m2_t maskedoff, vint8m2_t op1, vuint8m2_t shift, size_t vl) {1856 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);1857}1858 1859// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vsll_vx_i8m2_tumu1860// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1861// CHECK-RV64-NEXT: entry:1862// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vsll.mask.nxv16i8.i64.i64(<vscale x 16 x i8> [[MASKEDOFF]], <vscale x 16 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)1863// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]1864//1865vint8m2_t test_vsll_vx_i8m2_tumu(vbool4_t mask, vint8m2_t maskedoff, vint8m2_t op1, size_t shift, size_t vl) {1866 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);1867}1868 1869// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vsll_vv_i8m4_tumu1870// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1871// CHECK-RV64-NEXT: entry:1872// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vsll.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF]], <vscale x 32 x i8> [[OP1]], <vscale x 32 x i8> [[SHIFT]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0)1873// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]1874//1875vint8m4_t test_vsll_vv_i8m4_tumu(vbool2_t mask, vint8m4_t maskedoff, vint8m4_t op1, vuint8m4_t shift, size_t vl) {1876 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);1877}1878 1879// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vsll_vx_i8m4_tumu1880// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1881// CHECK-RV64-NEXT: entry:1882// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vsll.mask.nxv32i8.i64.i64(<vscale x 32 x i8> [[MASKEDOFF]], <vscale x 32 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0)1883// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]1884//1885vint8m4_t test_vsll_vx_i8m4_tumu(vbool2_t mask, vint8m4_t maskedoff, vint8m4_t op1, size_t shift, size_t vl) {1886 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);1887}1888 1889// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vsll_vv_i8m8_tumu1890// CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1891// CHECK-RV64-NEXT: entry:1892// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vsll.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF]], <vscale x 64 x i8> [[OP1]], <vscale x 64 x i8> [[SHIFT]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 0)1893// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]1894//1895vint8m8_t test_vsll_vv_i8m8_tumu(vbool1_t mask, vint8m8_t maskedoff, vint8m8_t op1, vuint8m8_t shift, size_t vl) {1896 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);1897}1898 1899// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vsll_vx_i8m8_tumu1900// CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1901// CHECK-RV64-NEXT: entry:1902// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vsll.mask.nxv64i8.i64.i64(<vscale x 64 x i8> [[MASKEDOFF]], <vscale x 64 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 0)1903// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]1904//1905vint8m8_t test_vsll_vx_i8m8_tumu(vbool1_t mask, vint8m8_t maskedoff, vint8m8_t op1, size_t shift, size_t vl) {1906 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);1907}1908 1909// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vsll_vv_i16mf4_tumu1910// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1911// CHECK-RV64-NEXT: entry:1912// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vsll.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]], <vscale x 1 x i16> [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)1913// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]1914//1915vint16mf4_t test_vsll_vv_i16mf4_tumu(vbool64_t mask, vint16mf4_t maskedoff, vint16mf4_t op1, vuint16mf4_t shift, size_t vl) {1916 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);1917}1918 1919// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vsll_vx_i16mf4_tumu1920// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1921// CHECK-RV64-NEXT: entry:1922// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vsll.mask.nxv1i16.i64.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)1923// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]1924//1925vint16mf4_t test_vsll_vx_i16mf4_tumu(vbool64_t mask, vint16mf4_t maskedoff, vint16mf4_t op1, size_t shift, size_t vl) {1926 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);1927}1928 1929// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vsll_vv_i16mf2_tumu1930// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1931// CHECK-RV64-NEXT: entry:1932// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vsll.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]], <vscale x 2 x i16> [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)1933// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]1934//1935vint16mf2_t test_vsll_vv_i16mf2_tumu(vbool32_t mask, vint16mf2_t maskedoff, vint16mf2_t op1, vuint16mf2_t shift, size_t vl) {1936 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);1937}1938 1939// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vsll_vx_i16mf2_tumu1940// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1941// CHECK-RV64-NEXT: entry:1942// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vsll.mask.nxv2i16.i64.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)1943// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]1944//1945vint16mf2_t test_vsll_vx_i16mf2_tumu(vbool32_t mask, vint16mf2_t maskedoff, vint16mf2_t op1, size_t shift, size_t vl) {1946 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);1947}1948 1949// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vsll_vv_i16m1_tumu1950// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1951// CHECK-RV64-NEXT: entry:1952// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vsll.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]], <vscale x 4 x i16> [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)1953// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]1954//1955vint16m1_t test_vsll_vv_i16m1_tumu(vbool16_t mask, vint16m1_t maskedoff, vint16m1_t op1, vuint16m1_t shift, size_t vl) {1956 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);1957}1958 1959// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vsll_vx_i16m1_tumu1960// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1961// CHECK-RV64-NEXT: entry:1962// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vsll.mask.nxv4i16.i64.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)1963// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]1964//1965vint16m1_t test_vsll_vx_i16m1_tumu(vbool16_t mask, vint16m1_t maskedoff, vint16m1_t op1, size_t shift, size_t vl) {1966 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);1967}1968 1969// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vsll_vv_i16m2_tumu1970// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1971// CHECK-RV64-NEXT: entry:1972// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vsll.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]], <vscale x 8 x i16> [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)1973// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]1974//1975vint16m2_t test_vsll_vv_i16m2_tumu(vbool8_t mask, vint16m2_t maskedoff, vint16m2_t op1, vuint16m2_t shift, size_t vl) {1976 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);1977}1978 1979// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vsll_vx_i16m2_tumu1980// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1981// CHECK-RV64-NEXT: entry:1982// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vsll.mask.nxv8i16.i64.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)1983// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]1984//1985vint16m2_t test_vsll_vx_i16m2_tumu(vbool8_t mask, vint16m2_t maskedoff, vint16m2_t op1, size_t shift, size_t vl) {1986 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);1987}1988 1989// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vsll_vv_i16m4_tumu1990// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {1991// CHECK-RV64-NEXT: entry:1992// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vsll.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x i16> [[OP1]], <vscale x 16 x i16> [[SHIFT]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)1993// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]1994//1995vint16m4_t test_vsll_vv_i16m4_tumu(vbool4_t mask, vint16m4_t maskedoff, vint16m4_t op1, vuint16m4_t shift, size_t vl) {1996 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);1997}1998 1999// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vsll_vx_i16m4_tumu2000// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2001// CHECK-RV64-NEXT: entry:2002// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vsll.mask.nxv16i16.i64.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)2003// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]2004//2005vint16m4_t test_vsll_vx_i16m4_tumu(vbool4_t mask, vint16m4_t maskedoff, vint16m4_t op1, size_t shift, size_t vl) {2006 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2007}2008 2009// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vsll_vv_i16m8_tumu2010// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2011// CHECK-RV64-NEXT: entry:2012// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vsll.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x i16> [[OP1]], <vscale x 32 x i16> [[SHIFT]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0)2013// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]2014//2015vint16m8_t test_vsll_vv_i16m8_tumu(vbool2_t mask, vint16m8_t maskedoff, vint16m8_t op1, vuint16m8_t shift, size_t vl) {2016 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2017}2018 2019// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vsll_vx_i16m8_tumu2020// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2021// CHECK-RV64-NEXT: entry:2022// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vsll.mask.nxv32i16.i64.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0)2023// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]2024//2025vint16m8_t test_vsll_vx_i16m8_tumu(vbool2_t mask, vint16m8_t maskedoff, vint16m8_t op1, size_t shift, size_t vl) {2026 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2027}2028 2029// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vsll_vv_i32mf2_tumu2030// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2031// CHECK-RV64-NEXT: entry:2032// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vsll.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x i32> [[OP1]], <vscale x 1 x i32> [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)2033// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]2034//2035vint32mf2_t test_vsll_vv_i32mf2_tumu(vbool64_t mask, vint32mf2_t maskedoff, vint32mf2_t op1, vuint32mf2_t shift, size_t vl) {2036 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2037}2038 2039// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vsll_vx_i32mf2_tumu2040// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2041// CHECK-RV64-NEXT: entry:2042// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vsll.mask.nxv1i32.i64.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x i32> [[OP1]], i64 [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)2043// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]2044//2045vint32mf2_t test_vsll_vx_i32mf2_tumu(vbool64_t mask, vint32mf2_t maskedoff, vint32mf2_t op1, size_t shift, size_t vl) {2046 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2047}2048 2049// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vsll_vv_i32m1_tumu2050// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2051// CHECK-RV64-NEXT: entry:2052// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vsll.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i32> [[OP1]], <vscale x 2 x i32> [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)2053// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]2054//2055vint32m1_t test_vsll_vv_i32m1_tumu(vbool32_t mask, vint32m1_t maskedoff, vint32m1_t op1, vuint32m1_t shift, size_t vl) {2056 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2057}2058 2059// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vsll_vx_i32m1_tumu2060// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2061// CHECK-RV64-NEXT: entry:2062// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vsll.mask.nxv2i32.i64.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i32> [[OP1]], i64 [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)2063// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]2064//2065vint32m1_t test_vsll_vx_i32m1_tumu(vbool32_t mask, vint32m1_t maskedoff, vint32m1_t op1, size_t shift, size_t vl) {2066 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2067}2068 2069// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vsll_vv_i32m2_tumu2070// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2071// CHECK-RV64-NEXT: entry:2072// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vsll.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x i32> [[OP1]], <vscale x 4 x i32> [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)2073// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]2074//2075vint32m2_t test_vsll_vv_i32m2_tumu(vbool16_t mask, vint32m2_t maskedoff, vint32m2_t op1, vuint32m2_t shift, size_t vl) {2076 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2077}2078 2079// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vsll_vx_i32m2_tumu2080// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2081// CHECK-RV64-NEXT: entry:2082// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vsll.mask.nxv4i32.i64.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x i32> [[OP1]], i64 [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)2083// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]2084//2085vint32m2_t test_vsll_vx_i32m2_tumu(vbool16_t mask, vint32m2_t maskedoff, vint32m2_t op1, size_t shift, size_t vl) {2086 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2087}2088 2089// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vsll_vv_i32m4_tumu2090// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2091// CHECK-RV64-NEXT: entry:2092// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vsll.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x i32> [[OP1]], <vscale x 8 x i32> [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)2093// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]2094//2095vint32m4_t test_vsll_vv_i32m4_tumu(vbool8_t mask, vint32m4_t maskedoff, vint32m4_t op1, vuint32m4_t shift, size_t vl) {2096 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2097}2098 2099// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vsll_vx_i32m4_tumu2100// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2101// CHECK-RV64-NEXT: entry:2102// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vsll.mask.nxv8i32.i64.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x i32> [[OP1]], i64 [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)2103// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]2104//2105vint32m4_t test_vsll_vx_i32m4_tumu(vbool8_t mask, vint32m4_t maskedoff, vint32m4_t op1, size_t shift, size_t vl) {2106 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2107}2108 2109// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vsll_vv_i32m8_tumu2110// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2111// CHECK-RV64-NEXT: entry:2112// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vsll.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x i32> [[OP1]], <vscale x 16 x i32> [[SHIFT]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)2113// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]2114//2115vint32m8_t test_vsll_vv_i32m8_tumu(vbool4_t mask, vint32m8_t maskedoff, vint32m8_t op1, vuint32m8_t shift, size_t vl) {2116 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2117}2118 2119// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vsll_vx_i32m8_tumu2120// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2121// CHECK-RV64-NEXT: entry:2122// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vsll.mask.nxv16i32.i64.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x i32> [[OP1]], i64 [[SHIFT]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)2123// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]2124//2125vint32m8_t test_vsll_vx_i32m8_tumu(vbool4_t mask, vint32m8_t maskedoff, vint32m8_t op1, size_t shift, size_t vl) {2126 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2127}2128 2129// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vsll_vv_i64m1_tumu2130// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2131// CHECK-RV64-NEXT: entry:2132// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vsll.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i64> [[OP1]], <vscale x 1 x i64> [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)2133// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]2134//2135vint64m1_t test_vsll_vv_i64m1_tumu(vbool64_t mask, vint64m1_t maskedoff, vint64m1_t op1, vuint64m1_t shift, size_t vl) {2136 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2137}2138 2139// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vsll_vx_i64m1_tumu2140// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2141// CHECK-RV64-NEXT: entry:2142// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vsll.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i64> [[OP1]], i64 [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)2143// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]2144//2145vint64m1_t test_vsll_vx_i64m1_tumu(vbool64_t mask, vint64m1_t maskedoff, vint64m1_t op1, size_t shift, size_t vl) {2146 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2147}2148 2149// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vsll_vv_i64m2_tumu2150// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2151// CHECK-RV64-NEXT: entry:2152// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vsll.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i64> [[OP1]], <vscale x 2 x i64> [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)2153// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]2154//2155vint64m2_t test_vsll_vv_i64m2_tumu(vbool32_t mask, vint64m2_t maskedoff, vint64m2_t op1, vuint64m2_t shift, size_t vl) {2156 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2157}2158 2159// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vsll_vx_i64m2_tumu2160// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2161// CHECK-RV64-NEXT: entry:2162// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vsll.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i64> [[OP1]], i64 [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)2163// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]2164//2165vint64m2_t test_vsll_vx_i64m2_tumu(vbool32_t mask, vint64m2_t maskedoff, vint64m2_t op1, size_t shift, size_t vl) {2166 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2167}2168 2169// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vsll_vv_i64m4_tumu2170// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2171// CHECK-RV64-NEXT: entry:2172// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vsll.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i64> [[OP1]], <vscale x 4 x i64> [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)2173// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]2174//2175vint64m4_t test_vsll_vv_i64m4_tumu(vbool16_t mask, vint64m4_t maskedoff, vint64m4_t op1, vuint64m4_t shift, size_t vl) {2176 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2177}2178 2179// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vsll_vx_i64m4_tumu2180// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2181// CHECK-RV64-NEXT: entry:2182// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vsll.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i64> [[OP1]], i64 [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)2183// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]2184//2185vint64m4_t test_vsll_vx_i64m4_tumu(vbool16_t mask, vint64m4_t maskedoff, vint64m4_t op1, size_t shift, size_t vl) {2186 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2187}2188 2189// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vsll_vv_i64m8_tumu2190// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2191// CHECK-RV64-NEXT: entry:2192// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vsll.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i64> [[OP1]], <vscale x 8 x i64> [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)2193// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]2194//2195vint64m8_t test_vsll_vv_i64m8_tumu(vbool8_t mask, vint64m8_t maskedoff, vint64m8_t op1, vuint64m8_t shift, size_t vl) {2196 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2197}2198 2199// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vsll_vx_i64m8_tumu2200// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2201// CHECK-RV64-NEXT: entry:2202// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vsll.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i64> [[OP1]], i64 [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)2203// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]2204//2205vint64m8_t test_vsll_vx_i64m8_tumu(vbool8_t mask, vint64m8_t maskedoff, vint64m8_t op1, size_t shift, size_t vl) {2206 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2207}2208 2209// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vsll_vv_u8mf8_tumu2210// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2211// CHECK-RV64-NEXT: entry:2212// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vsll.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], <vscale x 1 x i8> [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)2213// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]2214//2215vuint8mf8_t test_vsll_vv_u8mf8_tumu(vbool64_t mask, vuint8mf8_t maskedoff, vuint8mf8_t op1, vuint8mf8_t shift, size_t vl) {2216 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2217}2218 2219// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vsll_vx_u8mf8_tumu2220// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2221// CHECK-RV64-NEXT: entry:2222// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vsll.mask.nxv1i8.i64.i64(<vscale x 1 x i8> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)2223// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]2224//2225vuint8mf8_t test_vsll_vx_u8mf8_tumu(vbool64_t mask, vuint8mf8_t maskedoff, vuint8mf8_t op1, size_t shift, size_t vl) {2226 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2227}2228 2229// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vsll_vv_u8mf4_tumu2230// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2231// CHECK-RV64-NEXT: entry:2232// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vsll.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], <vscale x 2 x i8> [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)2233// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]2234//2235vuint8mf4_t test_vsll_vv_u8mf4_tumu(vbool32_t mask, vuint8mf4_t maskedoff, vuint8mf4_t op1, vuint8mf4_t shift, size_t vl) {2236 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2237}2238 2239// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vsll_vx_u8mf4_tumu2240// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2241// CHECK-RV64-NEXT: entry:2242// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vsll.mask.nxv2i8.i64.i64(<vscale x 2 x i8> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)2243// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]2244//2245vuint8mf4_t test_vsll_vx_u8mf4_tumu(vbool32_t mask, vuint8mf4_t maskedoff, vuint8mf4_t op1, size_t shift, size_t vl) {2246 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2247}2248 2249// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vsll_vv_u8mf2_tumu2250// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2251// CHECK-RV64-NEXT: entry:2252// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vsll.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF]], <vscale x 4 x i8> [[OP1]], <vscale x 4 x i8> [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)2253// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]2254//2255vuint8mf2_t test_vsll_vv_u8mf2_tumu(vbool16_t mask, vuint8mf2_t maskedoff, vuint8mf2_t op1, vuint8mf2_t shift, size_t vl) {2256 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2257}2258 2259// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vsll_vx_u8mf2_tumu2260// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2261// CHECK-RV64-NEXT: entry:2262// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vsll.mask.nxv4i8.i64.i64(<vscale x 4 x i8> [[MASKEDOFF]], <vscale x 4 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)2263// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]2264//2265vuint8mf2_t test_vsll_vx_u8mf2_tumu(vbool16_t mask, vuint8mf2_t maskedoff, vuint8mf2_t op1, size_t shift, size_t vl) {2266 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2267}2268 2269// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vsll_vv_u8m1_tumu2270// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2271// CHECK-RV64-NEXT: entry:2272// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vsll.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF]], <vscale x 8 x i8> [[OP1]], <vscale x 8 x i8> [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)2273// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]2274//2275vuint8m1_t test_vsll_vv_u8m1_tumu(vbool8_t mask, vuint8m1_t maskedoff, vuint8m1_t op1, vuint8m1_t shift, size_t vl) {2276 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2277}2278 2279// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vsll_vx_u8m1_tumu2280// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2281// CHECK-RV64-NEXT: entry:2282// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vsll.mask.nxv8i8.i64.i64(<vscale x 8 x i8> [[MASKEDOFF]], <vscale x 8 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)2283// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]2284//2285vuint8m1_t test_vsll_vx_u8m1_tumu(vbool8_t mask, vuint8m1_t maskedoff, vuint8m1_t op1, size_t shift, size_t vl) {2286 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2287}2288 2289// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vsll_vv_u8m2_tumu2290// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2291// CHECK-RV64-NEXT: entry:2292// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vsll.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF]], <vscale x 16 x i8> [[OP1]], <vscale x 16 x i8> [[SHIFT]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)2293// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]2294//2295vuint8m2_t test_vsll_vv_u8m2_tumu(vbool4_t mask, vuint8m2_t maskedoff, vuint8m2_t op1, vuint8m2_t shift, size_t vl) {2296 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2297}2298 2299// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vsll_vx_u8m2_tumu2300// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2301// CHECK-RV64-NEXT: entry:2302// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vsll.mask.nxv16i8.i64.i64(<vscale x 16 x i8> [[MASKEDOFF]], <vscale x 16 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)2303// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]2304//2305vuint8m2_t test_vsll_vx_u8m2_tumu(vbool4_t mask, vuint8m2_t maskedoff, vuint8m2_t op1, size_t shift, size_t vl) {2306 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2307}2308 2309// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vsll_vv_u8m4_tumu2310// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2311// CHECK-RV64-NEXT: entry:2312// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vsll.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF]], <vscale x 32 x i8> [[OP1]], <vscale x 32 x i8> [[SHIFT]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0)2313// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]2314//2315vuint8m4_t test_vsll_vv_u8m4_tumu(vbool2_t mask, vuint8m4_t maskedoff, vuint8m4_t op1, vuint8m4_t shift, size_t vl) {2316 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2317}2318 2319// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vsll_vx_u8m4_tumu2320// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2321// CHECK-RV64-NEXT: entry:2322// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vsll.mask.nxv32i8.i64.i64(<vscale x 32 x i8> [[MASKEDOFF]], <vscale x 32 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0)2323// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]2324//2325vuint8m4_t test_vsll_vx_u8m4_tumu(vbool2_t mask, vuint8m4_t maskedoff, vuint8m4_t op1, size_t shift, size_t vl) {2326 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2327}2328 2329// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vsll_vv_u8m8_tumu2330// CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2331// CHECK-RV64-NEXT: entry:2332// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vsll.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF]], <vscale x 64 x i8> [[OP1]], <vscale x 64 x i8> [[SHIFT]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 0)2333// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]2334//2335vuint8m8_t test_vsll_vv_u8m8_tumu(vbool1_t mask, vuint8m8_t maskedoff, vuint8m8_t op1, vuint8m8_t shift, size_t vl) {2336 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2337}2338 2339// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vsll_vx_u8m8_tumu2340// CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2341// CHECK-RV64-NEXT: entry:2342// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vsll.mask.nxv64i8.i64.i64(<vscale x 64 x i8> [[MASKEDOFF]], <vscale x 64 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 0)2343// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]2344//2345vuint8m8_t test_vsll_vx_u8m8_tumu(vbool1_t mask, vuint8m8_t maskedoff, vuint8m8_t op1, size_t shift, size_t vl) {2346 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2347}2348 2349// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vsll_vv_u16mf4_tumu2350// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2351// CHECK-RV64-NEXT: entry:2352// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vsll.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]], <vscale x 1 x i16> [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)2353// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]2354//2355vuint16mf4_t test_vsll_vv_u16mf4_tumu(vbool64_t mask, vuint16mf4_t maskedoff, vuint16mf4_t op1, vuint16mf4_t shift, size_t vl) {2356 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2357}2358 2359// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vsll_vx_u16mf4_tumu2360// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2361// CHECK-RV64-NEXT: entry:2362// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vsll.mask.nxv1i16.i64.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)2363// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]2364//2365vuint16mf4_t test_vsll_vx_u16mf4_tumu(vbool64_t mask, vuint16mf4_t maskedoff, vuint16mf4_t op1, size_t shift, size_t vl) {2366 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2367}2368 2369// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vsll_vv_u16mf2_tumu2370// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2371// CHECK-RV64-NEXT: entry:2372// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vsll.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]], <vscale x 2 x i16> [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)2373// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]2374//2375vuint16mf2_t test_vsll_vv_u16mf2_tumu(vbool32_t mask, vuint16mf2_t maskedoff, vuint16mf2_t op1, vuint16mf2_t shift, size_t vl) {2376 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2377}2378 2379// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vsll_vx_u16mf2_tumu2380// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2381// CHECK-RV64-NEXT: entry:2382// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vsll.mask.nxv2i16.i64.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)2383// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]2384//2385vuint16mf2_t test_vsll_vx_u16mf2_tumu(vbool32_t mask, vuint16mf2_t maskedoff, vuint16mf2_t op1, size_t shift, size_t vl) {2386 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2387}2388 2389// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vsll_vv_u16m1_tumu2390// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2391// CHECK-RV64-NEXT: entry:2392// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vsll.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]], <vscale x 4 x i16> [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)2393// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]2394//2395vuint16m1_t test_vsll_vv_u16m1_tumu(vbool16_t mask, vuint16m1_t maskedoff, vuint16m1_t op1, vuint16m1_t shift, size_t vl) {2396 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2397}2398 2399// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vsll_vx_u16m1_tumu2400// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2401// CHECK-RV64-NEXT: entry:2402// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vsll.mask.nxv4i16.i64.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)2403// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]2404//2405vuint16m1_t test_vsll_vx_u16m1_tumu(vbool16_t mask, vuint16m1_t maskedoff, vuint16m1_t op1, size_t shift, size_t vl) {2406 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2407}2408 2409// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vsll_vv_u16m2_tumu2410// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2411// CHECK-RV64-NEXT: entry:2412// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vsll.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]], <vscale x 8 x i16> [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)2413// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]2414//2415vuint16m2_t test_vsll_vv_u16m2_tumu(vbool8_t mask, vuint16m2_t maskedoff, vuint16m2_t op1, vuint16m2_t shift, size_t vl) {2416 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2417}2418 2419// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vsll_vx_u16m2_tumu2420// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2421// CHECK-RV64-NEXT: entry:2422// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vsll.mask.nxv8i16.i64.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)2423// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]2424//2425vuint16m2_t test_vsll_vx_u16m2_tumu(vbool8_t mask, vuint16m2_t maskedoff, vuint16m2_t op1, size_t shift, size_t vl) {2426 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2427}2428 2429// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vsll_vv_u16m4_tumu2430// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2431// CHECK-RV64-NEXT: entry:2432// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vsll.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x i16> [[OP1]], <vscale x 16 x i16> [[SHIFT]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)2433// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]2434//2435vuint16m4_t test_vsll_vv_u16m4_tumu(vbool4_t mask, vuint16m4_t maskedoff, vuint16m4_t op1, vuint16m4_t shift, size_t vl) {2436 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2437}2438 2439// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vsll_vx_u16m4_tumu2440// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2441// CHECK-RV64-NEXT: entry:2442// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vsll.mask.nxv16i16.i64.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)2443// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]2444//2445vuint16m4_t test_vsll_vx_u16m4_tumu(vbool4_t mask, vuint16m4_t maskedoff, vuint16m4_t op1, size_t shift, size_t vl) {2446 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2447}2448 2449// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vsll_vv_u16m8_tumu2450// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2451// CHECK-RV64-NEXT: entry:2452// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vsll.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x i16> [[OP1]], <vscale x 32 x i16> [[SHIFT]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0)2453// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]2454//2455vuint16m8_t test_vsll_vv_u16m8_tumu(vbool2_t mask, vuint16m8_t maskedoff, vuint16m8_t op1, vuint16m8_t shift, size_t vl) {2456 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2457}2458 2459// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vsll_vx_u16m8_tumu2460// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2461// CHECK-RV64-NEXT: entry:2462// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vsll.mask.nxv32i16.i64.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0)2463// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]2464//2465vuint16m8_t test_vsll_vx_u16m8_tumu(vbool2_t mask, vuint16m8_t maskedoff, vuint16m8_t op1, size_t shift, size_t vl) {2466 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2467}2468 2469// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vsll_vv_u32mf2_tumu2470// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2471// CHECK-RV64-NEXT: entry:2472// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vsll.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x i32> [[OP1]], <vscale x 1 x i32> [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)2473// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]2474//2475vuint32mf2_t test_vsll_vv_u32mf2_tumu(vbool64_t mask, vuint32mf2_t maskedoff, vuint32mf2_t op1, vuint32mf2_t shift, size_t vl) {2476 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2477}2478 2479// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vsll_vx_u32mf2_tumu2480// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2481// CHECK-RV64-NEXT: entry:2482// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vsll.mask.nxv1i32.i64.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x i32> [[OP1]], i64 [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)2483// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]2484//2485vuint32mf2_t test_vsll_vx_u32mf2_tumu(vbool64_t mask, vuint32mf2_t maskedoff, vuint32mf2_t op1, size_t shift, size_t vl) {2486 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2487}2488 2489// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vsll_vv_u32m1_tumu2490// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2491// CHECK-RV64-NEXT: entry:2492// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vsll.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i32> [[OP1]], <vscale x 2 x i32> [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)2493// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]2494//2495vuint32m1_t test_vsll_vv_u32m1_tumu(vbool32_t mask, vuint32m1_t maskedoff, vuint32m1_t op1, vuint32m1_t shift, size_t vl) {2496 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2497}2498 2499// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vsll_vx_u32m1_tumu2500// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2501// CHECK-RV64-NEXT: entry:2502// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vsll.mask.nxv2i32.i64.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i32> [[OP1]], i64 [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)2503// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]2504//2505vuint32m1_t test_vsll_vx_u32m1_tumu(vbool32_t mask, vuint32m1_t maskedoff, vuint32m1_t op1, size_t shift, size_t vl) {2506 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2507}2508 2509// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vsll_vv_u32m2_tumu2510// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2511// CHECK-RV64-NEXT: entry:2512// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vsll.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x i32> [[OP1]], <vscale x 4 x i32> [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)2513// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]2514//2515vuint32m2_t test_vsll_vv_u32m2_tumu(vbool16_t mask, vuint32m2_t maskedoff, vuint32m2_t op1, vuint32m2_t shift, size_t vl) {2516 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2517}2518 2519// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vsll_vx_u32m2_tumu2520// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2521// CHECK-RV64-NEXT: entry:2522// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vsll.mask.nxv4i32.i64.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x i32> [[OP1]], i64 [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)2523// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]2524//2525vuint32m2_t test_vsll_vx_u32m2_tumu(vbool16_t mask, vuint32m2_t maskedoff, vuint32m2_t op1, size_t shift, size_t vl) {2526 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2527}2528 2529// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vsll_vv_u32m4_tumu2530// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2531// CHECK-RV64-NEXT: entry:2532// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vsll.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x i32> [[OP1]], <vscale x 8 x i32> [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)2533// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]2534//2535vuint32m4_t test_vsll_vv_u32m4_tumu(vbool8_t mask, vuint32m4_t maskedoff, vuint32m4_t op1, vuint32m4_t shift, size_t vl) {2536 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2537}2538 2539// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vsll_vx_u32m4_tumu2540// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2541// CHECK-RV64-NEXT: entry:2542// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vsll.mask.nxv8i32.i64.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x i32> [[OP1]], i64 [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)2543// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]2544//2545vuint32m4_t test_vsll_vx_u32m4_tumu(vbool8_t mask, vuint32m4_t maskedoff, vuint32m4_t op1, size_t shift, size_t vl) {2546 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2547}2548 2549// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vsll_vv_u32m8_tumu2550// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2551// CHECK-RV64-NEXT: entry:2552// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vsll.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x i32> [[OP1]], <vscale x 16 x i32> [[SHIFT]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)2553// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]2554//2555vuint32m8_t test_vsll_vv_u32m8_tumu(vbool4_t mask, vuint32m8_t maskedoff, vuint32m8_t op1, vuint32m8_t shift, size_t vl) {2556 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2557}2558 2559// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vsll_vx_u32m8_tumu2560// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2561// CHECK-RV64-NEXT: entry:2562// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vsll.mask.nxv16i32.i64.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x i32> [[OP1]], i64 [[SHIFT]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)2563// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]2564//2565vuint32m8_t test_vsll_vx_u32m8_tumu(vbool4_t mask, vuint32m8_t maskedoff, vuint32m8_t op1, size_t shift, size_t vl) {2566 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2567}2568 2569// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vsll_vv_u64m1_tumu2570// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2571// CHECK-RV64-NEXT: entry:2572// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vsll.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i64> [[OP1]], <vscale x 1 x i64> [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)2573// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]2574//2575vuint64m1_t test_vsll_vv_u64m1_tumu(vbool64_t mask, vuint64m1_t maskedoff, vuint64m1_t op1, vuint64m1_t shift, size_t vl) {2576 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2577}2578 2579// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vsll_vx_u64m1_tumu2580// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2581// CHECK-RV64-NEXT: entry:2582// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vsll.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i64> [[OP1]], i64 [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)2583// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]2584//2585vuint64m1_t test_vsll_vx_u64m1_tumu(vbool64_t mask, vuint64m1_t maskedoff, vuint64m1_t op1, size_t shift, size_t vl) {2586 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2587}2588 2589// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vsll_vv_u64m2_tumu2590// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2591// CHECK-RV64-NEXT: entry:2592// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vsll.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i64> [[OP1]], <vscale x 2 x i64> [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)2593// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]2594//2595vuint64m2_t test_vsll_vv_u64m2_tumu(vbool32_t mask, vuint64m2_t maskedoff, vuint64m2_t op1, vuint64m2_t shift, size_t vl) {2596 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2597}2598 2599// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vsll_vx_u64m2_tumu2600// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2601// CHECK-RV64-NEXT: entry:2602// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vsll.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i64> [[OP1]], i64 [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)2603// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]2604//2605vuint64m2_t test_vsll_vx_u64m2_tumu(vbool32_t mask, vuint64m2_t maskedoff, vuint64m2_t op1, size_t shift, size_t vl) {2606 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2607}2608 2609// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vsll_vv_u64m4_tumu2610// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2611// CHECK-RV64-NEXT: entry:2612// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vsll.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i64> [[OP1]], <vscale x 4 x i64> [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)2613// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]2614//2615vuint64m4_t test_vsll_vv_u64m4_tumu(vbool16_t mask, vuint64m4_t maskedoff, vuint64m4_t op1, vuint64m4_t shift, size_t vl) {2616 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2617}2618 2619// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vsll_vx_u64m4_tumu2620// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2621// CHECK-RV64-NEXT: entry:2622// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vsll.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i64> [[OP1]], i64 [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)2623// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]2624//2625vuint64m4_t test_vsll_vx_u64m4_tumu(vbool16_t mask, vuint64m4_t maskedoff, vuint64m4_t op1, size_t shift, size_t vl) {2626 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2627}2628 2629// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vsll_vv_u64m8_tumu2630// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2631// CHECK-RV64-NEXT: entry:2632// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vsll.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i64> [[OP1]], <vscale x 8 x i64> [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)2633// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]2634//2635vuint64m8_t test_vsll_vv_u64m8_tumu(vbool8_t mask, vuint64m8_t maskedoff, vuint64m8_t op1, vuint64m8_t shift, size_t vl) {2636 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2637}2638 2639// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vsll_vx_u64m8_tumu2640// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2641// CHECK-RV64-NEXT: entry:2642// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vsll.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i64> [[OP1]], i64 [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)2643// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]2644//2645vuint64m8_t test_vsll_vx_u64m8_tumu(vbool8_t mask, vuint64m8_t maskedoff, vuint64m8_t op1, size_t shift, size_t vl) {2646 return __riscv_vsll_tumu(mask, maskedoff, op1, shift, vl);2647}2648 2649// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vsll_vv_i8mf8_mu2650// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2651// CHECK-RV64-NEXT: entry:2652// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vsll.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], <vscale x 1 x i8> [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)2653// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]2654//2655vint8mf8_t test_vsll_vv_i8mf8_mu(vbool64_t mask, vint8mf8_t maskedoff, vint8mf8_t op1, vuint8mf8_t shift, size_t vl) {2656 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);2657}2658 2659// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vsll_vx_i8mf8_mu2660// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2661// CHECK-RV64-NEXT: entry:2662// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vsll.mask.nxv1i8.i64.i64(<vscale x 1 x i8> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)2663// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]2664//2665vint8mf8_t test_vsll_vx_i8mf8_mu(vbool64_t mask, vint8mf8_t maskedoff, vint8mf8_t op1, size_t shift, size_t vl) {2666 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);2667}2668 2669// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vsll_vv_i8mf4_mu2670// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2671// CHECK-RV64-NEXT: entry:2672// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vsll.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], <vscale x 2 x i8> [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)2673// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]2674//2675vint8mf4_t test_vsll_vv_i8mf4_mu(vbool32_t mask, vint8mf4_t maskedoff, vint8mf4_t op1, vuint8mf4_t shift, size_t vl) {2676 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);2677}2678 2679// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vsll_vx_i8mf4_mu2680// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2681// CHECK-RV64-NEXT: entry:2682// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vsll.mask.nxv2i8.i64.i64(<vscale x 2 x i8> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)2683// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]2684//2685vint8mf4_t test_vsll_vx_i8mf4_mu(vbool32_t mask, vint8mf4_t maskedoff, vint8mf4_t op1, size_t shift, size_t vl) {2686 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);2687}2688 2689// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vsll_vv_i8mf2_mu2690// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2691// CHECK-RV64-NEXT: entry:2692// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vsll.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF]], <vscale x 4 x i8> [[OP1]], <vscale x 4 x i8> [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)2693// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]2694//2695vint8mf2_t test_vsll_vv_i8mf2_mu(vbool16_t mask, vint8mf2_t maskedoff, vint8mf2_t op1, vuint8mf2_t shift, size_t vl) {2696 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);2697}2698 2699// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vsll_vx_i8mf2_mu2700// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2701// CHECK-RV64-NEXT: entry:2702// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vsll.mask.nxv4i8.i64.i64(<vscale x 4 x i8> [[MASKEDOFF]], <vscale x 4 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)2703// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]2704//2705vint8mf2_t test_vsll_vx_i8mf2_mu(vbool16_t mask, vint8mf2_t maskedoff, vint8mf2_t op1, size_t shift, size_t vl) {2706 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);2707}2708 2709// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vsll_vv_i8m1_mu2710// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2711// CHECK-RV64-NEXT: entry:2712// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vsll.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF]], <vscale x 8 x i8> [[OP1]], <vscale x 8 x i8> [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)2713// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]2714//2715vint8m1_t test_vsll_vv_i8m1_mu(vbool8_t mask, vint8m1_t maskedoff, vint8m1_t op1, vuint8m1_t shift, size_t vl) {2716 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);2717}2718 2719// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vsll_vx_i8m1_mu2720// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2721// CHECK-RV64-NEXT: entry:2722// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vsll.mask.nxv8i8.i64.i64(<vscale x 8 x i8> [[MASKEDOFF]], <vscale x 8 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)2723// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]2724//2725vint8m1_t test_vsll_vx_i8m1_mu(vbool8_t mask, vint8m1_t maskedoff, vint8m1_t op1, size_t shift, size_t vl) {2726 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);2727}2728 2729// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vsll_vv_i8m2_mu2730// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2731// CHECK-RV64-NEXT: entry:2732// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vsll.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF]], <vscale x 16 x i8> [[OP1]], <vscale x 16 x i8> [[SHIFT]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)2733// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]2734//2735vint8m2_t test_vsll_vv_i8m2_mu(vbool4_t mask, vint8m2_t maskedoff, vint8m2_t op1, vuint8m2_t shift, size_t vl) {2736 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);2737}2738 2739// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vsll_vx_i8m2_mu2740// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2741// CHECK-RV64-NEXT: entry:2742// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vsll.mask.nxv16i8.i64.i64(<vscale x 16 x i8> [[MASKEDOFF]], <vscale x 16 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)2743// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]2744//2745vint8m2_t test_vsll_vx_i8m2_mu(vbool4_t mask, vint8m2_t maskedoff, vint8m2_t op1, size_t shift, size_t vl) {2746 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);2747}2748 2749// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vsll_vv_i8m4_mu2750// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2751// CHECK-RV64-NEXT: entry:2752// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vsll.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF]], <vscale x 32 x i8> [[OP1]], <vscale x 32 x i8> [[SHIFT]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1)2753// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]2754//2755vint8m4_t test_vsll_vv_i8m4_mu(vbool2_t mask, vint8m4_t maskedoff, vint8m4_t op1, vuint8m4_t shift, size_t vl) {2756 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);2757}2758 2759// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vsll_vx_i8m4_mu2760// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2761// CHECK-RV64-NEXT: entry:2762// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vsll.mask.nxv32i8.i64.i64(<vscale x 32 x i8> [[MASKEDOFF]], <vscale x 32 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1)2763// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]2764//2765vint8m4_t test_vsll_vx_i8m4_mu(vbool2_t mask, vint8m4_t maskedoff, vint8m4_t op1, size_t shift, size_t vl) {2766 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);2767}2768 2769// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vsll_vv_i8m8_mu2770// CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2771// CHECK-RV64-NEXT: entry:2772// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vsll.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF]], <vscale x 64 x i8> [[OP1]], <vscale x 64 x i8> [[SHIFT]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 1)2773// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]2774//2775vint8m8_t test_vsll_vv_i8m8_mu(vbool1_t mask, vint8m8_t maskedoff, vint8m8_t op1, vuint8m8_t shift, size_t vl) {2776 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);2777}2778 2779// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vsll_vx_i8m8_mu2780// CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2781// CHECK-RV64-NEXT: entry:2782// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vsll.mask.nxv64i8.i64.i64(<vscale x 64 x i8> [[MASKEDOFF]], <vscale x 64 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 1)2783// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]2784//2785vint8m8_t test_vsll_vx_i8m8_mu(vbool1_t mask, vint8m8_t maskedoff, vint8m8_t op1, size_t shift, size_t vl) {2786 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);2787}2788 2789// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vsll_vv_i16mf4_mu2790// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2791// CHECK-RV64-NEXT: entry:2792// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vsll.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]], <vscale x 1 x i16> [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)2793// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]2794//2795vint16mf4_t test_vsll_vv_i16mf4_mu(vbool64_t mask, vint16mf4_t maskedoff, vint16mf4_t op1, vuint16mf4_t shift, size_t vl) {2796 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);2797}2798 2799// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vsll_vx_i16mf4_mu2800// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2801// CHECK-RV64-NEXT: entry:2802// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vsll.mask.nxv1i16.i64.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)2803// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]2804//2805vint16mf4_t test_vsll_vx_i16mf4_mu(vbool64_t mask, vint16mf4_t maskedoff, vint16mf4_t op1, size_t shift, size_t vl) {2806 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);2807}2808 2809// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vsll_vv_i16mf2_mu2810// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2811// CHECK-RV64-NEXT: entry:2812// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vsll.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]], <vscale x 2 x i16> [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)2813// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]2814//2815vint16mf2_t test_vsll_vv_i16mf2_mu(vbool32_t mask, vint16mf2_t maskedoff, vint16mf2_t op1, vuint16mf2_t shift, size_t vl) {2816 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);2817}2818 2819// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vsll_vx_i16mf2_mu2820// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2821// CHECK-RV64-NEXT: entry:2822// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vsll.mask.nxv2i16.i64.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)2823// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]2824//2825vint16mf2_t test_vsll_vx_i16mf2_mu(vbool32_t mask, vint16mf2_t maskedoff, vint16mf2_t op1, size_t shift, size_t vl) {2826 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);2827}2828 2829// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vsll_vv_i16m1_mu2830// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2831// CHECK-RV64-NEXT: entry:2832// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vsll.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]], <vscale x 4 x i16> [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)2833// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]2834//2835vint16m1_t test_vsll_vv_i16m1_mu(vbool16_t mask, vint16m1_t maskedoff, vint16m1_t op1, vuint16m1_t shift, size_t vl) {2836 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);2837}2838 2839// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vsll_vx_i16m1_mu2840// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2841// CHECK-RV64-NEXT: entry:2842// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vsll.mask.nxv4i16.i64.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)2843// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]2844//2845vint16m1_t test_vsll_vx_i16m1_mu(vbool16_t mask, vint16m1_t maskedoff, vint16m1_t op1, size_t shift, size_t vl) {2846 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);2847}2848 2849// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vsll_vv_i16m2_mu2850// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2851// CHECK-RV64-NEXT: entry:2852// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vsll.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]], <vscale x 8 x i16> [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)2853// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]2854//2855vint16m2_t test_vsll_vv_i16m2_mu(vbool8_t mask, vint16m2_t maskedoff, vint16m2_t op1, vuint16m2_t shift, size_t vl) {2856 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);2857}2858 2859// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vsll_vx_i16m2_mu2860// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2861// CHECK-RV64-NEXT: entry:2862// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vsll.mask.nxv8i16.i64.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)2863// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]2864//2865vint16m2_t test_vsll_vx_i16m2_mu(vbool8_t mask, vint16m2_t maskedoff, vint16m2_t op1, size_t shift, size_t vl) {2866 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);2867}2868 2869// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vsll_vv_i16m4_mu2870// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2871// CHECK-RV64-NEXT: entry:2872// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vsll.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x i16> [[OP1]], <vscale x 16 x i16> [[SHIFT]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)2873// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]2874//2875vint16m4_t test_vsll_vv_i16m4_mu(vbool4_t mask, vint16m4_t maskedoff, vint16m4_t op1, vuint16m4_t shift, size_t vl) {2876 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);2877}2878 2879// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vsll_vx_i16m4_mu2880// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2881// CHECK-RV64-NEXT: entry:2882// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vsll.mask.nxv16i16.i64.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)2883// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]2884//2885vint16m4_t test_vsll_vx_i16m4_mu(vbool4_t mask, vint16m4_t maskedoff, vint16m4_t op1, size_t shift, size_t vl) {2886 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);2887}2888 2889// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vsll_vv_i16m8_mu2890// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2891// CHECK-RV64-NEXT: entry:2892// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vsll.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x i16> [[OP1]], <vscale x 32 x i16> [[SHIFT]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1)2893// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]2894//2895vint16m8_t test_vsll_vv_i16m8_mu(vbool2_t mask, vint16m8_t maskedoff, vint16m8_t op1, vuint16m8_t shift, size_t vl) {2896 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);2897}2898 2899// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vsll_vx_i16m8_mu2900// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2901// CHECK-RV64-NEXT: entry:2902// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vsll.mask.nxv32i16.i64.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1)2903// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]2904//2905vint16m8_t test_vsll_vx_i16m8_mu(vbool2_t mask, vint16m8_t maskedoff, vint16m8_t op1, size_t shift, size_t vl) {2906 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);2907}2908 2909// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vsll_vv_i32mf2_mu2910// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2911// CHECK-RV64-NEXT: entry:2912// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vsll.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x i32> [[OP1]], <vscale x 1 x i32> [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)2913// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]2914//2915vint32mf2_t test_vsll_vv_i32mf2_mu(vbool64_t mask, vint32mf2_t maskedoff, vint32mf2_t op1, vuint32mf2_t shift, size_t vl) {2916 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);2917}2918 2919// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vsll_vx_i32mf2_mu2920// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2921// CHECK-RV64-NEXT: entry:2922// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vsll.mask.nxv1i32.i64.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x i32> [[OP1]], i64 [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)2923// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]2924//2925vint32mf2_t test_vsll_vx_i32mf2_mu(vbool64_t mask, vint32mf2_t maskedoff, vint32mf2_t op1, size_t shift, size_t vl) {2926 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);2927}2928 2929// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vsll_vv_i32m1_mu2930// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2931// CHECK-RV64-NEXT: entry:2932// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vsll.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i32> [[OP1]], <vscale x 2 x i32> [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)2933// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]2934//2935vint32m1_t test_vsll_vv_i32m1_mu(vbool32_t mask, vint32m1_t maskedoff, vint32m1_t op1, vuint32m1_t shift, size_t vl) {2936 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);2937}2938 2939// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vsll_vx_i32m1_mu2940// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2941// CHECK-RV64-NEXT: entry:2942// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vsll.mask.nxv2i32.i64.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i32> [[OP1]], i64 [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)2943// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]2944//2945vint32m1_t test_vsll_vx_i32m1_mu(vbool32_t mask, vint32m1_t maskedoff, vint32m1_t op1, size_t shift, size_t vl) {2946 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);2947}2948 2949// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vsll_vv_i32m2_mu2950// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2951// CHECK-RV64-NEXT: entry:2952// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vsll.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x i32> [[OP1]], <vscale x 4 x i32> [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)2953// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]2954//2955vint32m2_t test_vsll_vv_i32m2_mu(vbool16_t mask, vint32m2_t maskedoff, vint32m2_t op1, vuint32m2_t shift, size_t vl) {2956 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);2957}2958 2959// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vsll_vx_i32m2_mu2960// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2961// CHECK-RV64-NEXT: entry:2962// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vsll.mask.nxv4i32.i64.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x i32> [[OP1]], i64 [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)2963// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]2964//2965vint32m2_t test_vsll_vx_i32m2_mu(vbool16_t mask, vint32m2_t maskedoff, vint32m2_t op1, size_t shift, size_t vl) {2966 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);2967}2968 2969// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vsll_vv_i32m4_mu2970// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2971// CHECK-RV64-NEXT: entry:2972// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vsll.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x i32> [[OP1]], <vscale x 8 x i32> [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)2973// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]2974//2975vint32m4_t test_vsll_vv_i32m4_mu(vbool8_t mask, vint32m4_t maskedoff, vint32m4_t op1, vuint32m4_t shift, size_t vl) {2976 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);2977}2978 2979// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vsll_vx_i32m4_mu2980// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2981// CHECK-RV64-NEXT: entry:2982// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vsll.mask.nxv8i32.i64.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x i32> [[OP1]], i64 [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)2983// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]2984//2985vint32m4_t test_vsll_vx_i32m4_mu(vbool8_t mask, vint32m4_t maskedoff, vint32m4_t op1, size_t shift, size_t vl) {2986 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);2987}2988 2989// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vsll_vv_i32m8_mu2990// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {2991// CHECK-RV64-NEXT: entry:2992// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vsll.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x i32> [[OP1]], <vscale x 16 x i32> [[SHIFT]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)2993// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]2994//2995vint32m8_t test_vsll_vv_i32m8_mu(vbool4_t mask, vint32m8_t maskedoff, vint32m8_t op1, vuint32m8_t shift, size_t vl) {2996 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);2997}2998 2999// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vsll_vx_i32m8_mu3000// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3001// CHECK-RV64-NEXT: entry:3002// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vsll.mask.nxv16i32.i64.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x i32> [[OP1]], i64 [[SHIFT]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)3003// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]3004//3005vint32m8_t test_vsll_vx_i32m8_mu(vbool4_t mask, vint32m8_t maskedoff, vint32m8_t op1, size_t shift, size_t vl) {3006 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3007}3008 3009// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vsll_vv_i64m1_mu3010// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3011// CHECK-RV64-NEXT: entry:3012// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vsll.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i64> [[OP1]], <vscale x 1 x i64> [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)3013// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]3014//3015vint64m1_t test_vsll_vv_i64m1_mu(vbool64_t mask, vint64m1_t maskedoff, vint64m1_t op1, vuint64m1_t shift, size_t vl) {3016 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3017}3018 3019// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vsll_vx_i64m1_mu3020// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3021// CHECK-RV64-NEXT: entry:3022// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vsll.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i64> [[OP1]], i64 [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)3023// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]3024//3025vint64m1_t test_vsll_vx_i64m1_mu(vbool64_t mask, vint64m1_t maskedoff, vint64m1_t op1, size_t shift, size_t vl) {3026 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3027}3028 3029// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vsll_vv_i64m2_mu3030// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3031// CHECK-RV64-NEXT: entry:3032// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vsll.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i64> [[OP1]], <vscale x 2 x i64> [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)3033// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]3034//3035vint64m2_t test_vsll_vv_i64m2_mu(vbool32_t mask, vint64m2_t maskedoff, vint64m2_t op1, vuint64m2_t shift, size_t vl) {3036 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3037}3038 3039// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vsll_vx_i64m2_mu3040// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3041// CHECK-RV64-NEXT: entry:3042// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vsll.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i64> [[OP1]], i64 [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)3043// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]3044//3045vint64m2_t test_vsll_vx_i64m2_mu(vbool32_t mask, vint64m2_t maskedoff, vint64m2_t op1, size_t shift, size_t vl) {3046 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3047}3048 3049// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vsll_vv_i64m4_mu3050// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3051// CHECK-RV64-NEXT: entry:3052// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vsll.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i64> [[OP1]], <vscale x 4 x i64> [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)3053// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]3054//3055vint64m4_t test_vsll_vv_i64m4_mu(vbool16_t mask, vint64m4_t maskedoff, vint64m4_t op1, vuint64m4_t shift, size_t vl) {3056 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3057}3058 3059// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vsll_vx_i64m4_mu3060// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3061// CHECK-RV64-NEXT: entry:3062// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vsll.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i64> [[OP1]], i64 [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)3063// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]3064//3065vint64m4_t test_vsll_vx_i64m4_mu(vbool16_t mask, vint64m4_t maskedoff, vint64m4_t op1, size_t shift, size_t vl) {3066 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3067}3068 3069// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vsll_vv_i64m8_mu3070// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3071// CHECK-RV64-NEXT: entry:3072// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vsll.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i64> [[OP1]], <vscale x 8 x i64> [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)3073// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]3074//3075vint64m8_t test_vsll_vv_i64m8_mu(vbool8_t mask, vint64m8_t maskedoff, vint64m8_t op1, vuint64m8_t shift, size_t vl) {3076 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3077}3078 3079// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vsll_vx_i64m8_mu3080// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3081// CHECK-RV64-NEXT: entry:3082// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vsll.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i64> [[OP1]], i64 [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)3083// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]3084//3085vint64m8_t test_vsll_vx_i64m8_mu(vbool8_t mask, vint64m8_t maskedoff, vint64m8_t op1, size_t shift, size_t vl) {3086 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3087}3088 3089// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vsll_vv_u8mf8_mu3090// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3091// CHECK-RV64-NEXT: entry:3092// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vsll.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], <vscale x 1 x i8> [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)3093// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]3094//3095vuint8mf8_t test_vsll_vv_u8mf8_mu(vbool64_t mask, vuint8mf8_t maskedoff, vuint8mf8_t op1, vuint8mf8_t shift, size_t vl) {3096 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3097}3098 3099// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vsll_vx_u8mf8_mu3100// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3101// CHECK-RV64-NEXT: entry:3102// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vsll.mask.nxv1i8.i64.i64(<vscale x 1 x i8> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)3103// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]3104//3105vuint8mf8_t test_vsll_vx_u8mf8_mu(vbool64_t mask, vuint8mf8_t maskedoff, vuint8mf8_t op1, size_t shift, size_t vl) {3106 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3107}3108 3109// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vsll_vv_u8mf4_mu3110// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3111// CHECK-RV64-NEXT: entry:3112// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vsll.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], <vscale x 2 x i8> [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)3113// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]3114//3115vuint8mf4_t test_vsll_vv_u8mf4_mu(vbool32_t mask, vuint8mf4_t maskedoff, vuint8mf4_t op1, vuint8mf4_t shift, size_t vl) {3116 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3117}3118 3119// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vsll_vx_u8mf4_mu3120// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3121// CHECK-RV64-NEXT: entry:3122// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vsll.mask.nxv2i8.i64.i64(<vscale x 2 x i8> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)3123// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]3124//3125vuint8mf4_t test_vsll_vx_u8mf4_mu(vbool32_t mask, vuint8mf4_t maskedoff, vuint8mf4_t op1, size_t shift, size_t vl) {3126 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3127}3128 3129// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vsll_vv_u8mf2_mu3130// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3131// CHECK-RV64-NEXT: entry:3132// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vsll.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF]], <vscale x 4 x i8> [[OP1]], <vscale x 4 x i8> [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)3133// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]3134//3135vuint8mf2_t test_vsll_vv_u8mf2_mu(vbool16_t mask, vuint8mf2_t maskedoff, vuint8mf2_t op1, vuint8mf2_t shift, size_t vl) {3136 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3137}3138 3139// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vsll_vx_u8mf2_mu3140// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3141// CHECK-RV64-NEXT: entry:3142// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vsll.mask.nxv4i8.i64.i64(<vscale x 4 x i8> [[MASKEDOFF]], <vscale x 4 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)3143// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]3144//3145vuint8mf2_t test_vsll_vx_u8mf2_mu(vbool16_t mask, vuint8mf2_t maskedoff, vuint8mf2_t op1, size_t shift, size_t vl) {3146 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3147}3148 3149// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vsll_vv_u8m1_mu3150// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3151// CHECK-RV64-NEXT: entry:3152// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vsll.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF]], <vscale x 8 x i8> [[OP1]], <vscale x 8 x i8> [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)3153// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]3154//3155vuint8m1_t test_vsll_vv_u8m1_mu(vbool8_t mask, vuint8m1_t maskedoff, vuint8m1_t op1, vuint8m1_t shift, size_t vl) {3156 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3157}3158 3159// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vsll_vx_u8m1_mu3160// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3161// CHECK-RV64-NEXT: entry:3162// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vsll.mask.nxv8i8.i64.i64(<vscale x 8 x i8> [[MASKEDOFF]], <vscale x 8 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)3163// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]3164//3165vuint8m1_t test_vsll_vx_u8m1_mu(vbool8_t mask, vuint8m1_t maskedoff, vuint8m1_t op1, size_t shift, size_t vl) {3166 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3167}3168 3169// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vsll_vv_u8m2_mu3170// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3171// CHECK-RV64-NEXT: entry:3172// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vsll.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF]], <vscale x 16 x i8> [[OP1]], <vscale x 16 x i8> [[SHIFT]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)3173// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]3174//3175vuint8m2_t test_vsll_vv_u8m2_mu(vbool4_t mask, vuint8m2_t maskedoff, vuint8m2_t op1, vuint8m2_t shift, size_t vl) {3176 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3177}3178 3179// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vsll_vx_u8m2_mu3180// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3181// CHECK-RV64-NEXT: entry:3182// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vsll.mask.nxv16i8.i64.i64(<vscale x 16 x i8> [[MASKEDOFF]], <vscale x 16 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)3183// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]3184//3185vuint8m2_t test_vsll_vx_u8m2_mu(vbool4_t mask, vuint8m2_t maskedoff, vuint8m2_t op1, size_t shift, size_t vl) {3186 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3187}3188 3189// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vsll_vv_u8m4_mu3190// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3191// CHECK-RV64-NEXT: entry:3192// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vsll.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF]], <vscale x 32 x i8> [[OP1]], <vscale x 32 x i8> [[SHIFT]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1)3193// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]3194//3195vuint8m4_t test_vsll_vv_u8m4_mu(vbool2_t mask, vuint8m4_t maskedoff, vuint8m4_t op1, vuint8m4_t shift, size_t vl) {3196 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3197}3198 3199// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vsll_vx_u8m4_mu3200// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3201// CHECK-RV64-NEXT: entry:3202// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vsll.mask.nxv32i8.i64.i64(<vscale x 32 x i8> [[MASKEDOFF]], <vscale x 32 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1)3203// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]3204//3205vuint8m4_t test_vsll_vx_u8m4_mu(vbool2_t mask, vuint8m4_t maskedoff, vuint8m4_t op1, size_t shift, size_t vl) {3206 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3207}3208 3209// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vsll_vv_u8m8_mu3210// CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3211// CHECK-RV64-NEXT: entry:3212// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vsll.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF]], <vscale x 64 x i8> [[OP1]], <vscale x 64 x i8> [[SHIFT]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 1)3213// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]3214//3215vuint8m8_t test_vsll_vv_u8m8_mu(vbool1_t mask, vuint8m8_t maskedoff, vuint8m8_t op1, vuint8m8_t shift, size_t vl) {3216 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3217}3218 3219// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vsll_vx_u8m8_mu3220// CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3221// CHECK-RV64-NEXT: entry:3222// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vsll.mask.nxv64i8.i64.i64(<vscale x 64 x i8> [[MASKEDOFF]], <vscale x 64 x i8> [[OP1]], i64 [[SHIFT]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 1)3223// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]3224//3225vuint8m8_t test_vsll_vx_u8m8_mu(vbool1_t mask, vuint8m8_t maskedoff, vuint8m8_t op1, size_t shift, size_t vl) {3226 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3227}3228 3229// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vsll_vv_u16mf4_mu3230// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3231// CHECK-RV64-NEXT: entry:3232// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vsll.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]], <vscale x 1 x i16> [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)3233// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]3234//3235vuint16mf4_t test_vsll_vv_u16mf4_mu(vbool64_t mask, vuint16mf4_t maskedoff, vuint16mf4_t op1, vuint16mf4_t shift, size_t vl) {3236 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3237}3238 3239// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vsll_vx_u16mf4_mu3240// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3241// CHECK-RV64-NEXT: entry:3242// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vsll.mask.nxv1i16.i64.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)3243// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]3244//3245vuint16mf4_t test_vsll_vx_u16mf4_mu(vbool64_t mask, vuint16mf4_t maskedoff, vuint16mf4_t op1, size_t shift, size_t vl) {3246 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3247}3248 3249// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vsll_vv_u16mf2_mu3250// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3251// CHECK-RV64-NEXT: entry:3252// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vsll.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]], <vscale x 2 x i16> [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)3253// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]3254//3255vuint16mf2_t test_vsll_vv_u16mf2_mu(vbool32_t mask, vuint16mf2_t maskedoff, vuint16mf2_t op1, vuint16mf2_t shift, size_t vl) {3256 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3257}3258 3259// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vsll_vx_u16mf2_mu3260// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3261// CHECK-RV64-NEXT: entry:3262// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vsll.mask.nxv2i16.i64.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)3263// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]3264//3265vuint16mf2_t test_vsll_vx_u16mf2_mu(vbool32_t mask, vuint16mf2_t maskedoff, vuint16mf2_t op1, size_t shift, size_t vl) {3266 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3267}3268 3269// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vsll_vv_u16m1_mu3270// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3271// CHECK-RV64-NEXT: entry:3272// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vsll.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]], <vscale x 4 x i16> [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)3273// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]3274//3275vuint16m1_t test_vsll_vv_u16m1_mu(vbool16_t mask, vuint16m1_t maskedoff, vuint16m1_t op1, vuint16m1_t shift, size_t vl) {3276 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3277}3278 3279// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vsll_vx_u16m1_mu3280// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3281// CHECK-RV64-NEXT: entry:3282// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vsll.mask.nxv4i16.i64.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)3283// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]3284//3285vuint16m1_t test_vsll_vx_u16m1_mu(vbool16_t mask, vuint16m1_t maskedoff, vuint16m1_t op1, size_t shift, size_t vl) {3286 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3287}3288 3289// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vsll_vv_u16m2_mu3290// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3291// CHECK-RV64-NEXT: entry:3292// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vsll.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]], <vscale x 8 x i16> [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)3293// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]3294//3295vuint16m2_t test_vsll_vv_u16m2_mu(vbool8_t mask, vuint16m2_t maskedoff, vuint16m2_t op1, vuint16m2_t shift, size_t vl) {3296 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3297}3298 3299// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vsll_vx_u16m2_mu3300// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3301// CHECK-RV64-NEXT: entry:3302// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vsll.mask.nxv8i16.i64.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)3303// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]3304//3305vuint16m2_t test_vsll_vx_u16m2_mu(vbool8_t mask, vuint16m2_t maskedoff, vuint16m2_t op1, size_t shift, size_t vl) {3306 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3307}3308 3309// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vsll_vv_u16m4_mu3310// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3311// CHECK-RV64-NEXT: entry:3312// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vsll.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x i16> [[OP1]], <vscale x 16 x i16> [[SHIFT]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)3313// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]3314//3315vuint16m4_t test_vsll_vv_u16m4_mu(vbool4_t mask, vuint16m4_t maskedoff, vuint16m4_t op1, vuint16m4_t shift, size_t vl) {3316 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3317}3318 3319// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vsll_vx_u16m4_mu3320// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3321// CHECK-RV64-NEXT: entry:3322// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vsll.mask.nxv16i16.i64.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)3323// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]3324//3325vuint16m4_t test_vsll_vx_u16m4_mu(vbool4_t mask, vuint16m4_t maskedoff, vuint16m4_t op1, size_t shift, size_t vl) {3326 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3327}3328 3329// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vsll_vv_u16m8_mu3330// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3331// CHECK-RV64-NEXT: entry:3332// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vsll.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x i16> [[OP1]], <vscale x 32 x i16> [[SHIFT]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1)3333// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]3334//3335vuint16m8_t test_vsll_vv_u16m8_mu(vbool2_t mask, vuint16m8_t maskedoff, vuint16m8_t op1, vuint16m8_t shift, size_t vl) {3336 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3337}3338 3339// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vsll_vx_u16m8_mu3340// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3341// CHECK-RV64-NEXT: entry:3342// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vsll.mask.nxv32i16.i64.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x i16> [[OP1]], i64 [[SHIFT]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1)3343// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]3344//3345vuint16m8_t test_vsll_vx_u16m8_mu(vbool2_t mask, vuint16m8_t maskedoff, vuint16m8_t op1, size_t shift, size_t vl) {3346 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3347}3348 3349// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vsll_vv_u32mf2_mu3350// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3351// CHECK-RV64-NEXT: entry:3352// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vsll.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x i32> [[OP1]], <vscale x 1 x i32> [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)3353// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]3354//3355vuint32mf2_t test_vsll_vv_u32mf2_mu(vbool64_t mask, vuint32mf2_t maskedoff, vuint32mf2_t op1, vuint32mf2_t shift, size_t vl) {3356 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3357}3358 3359// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vsll_vx_u32mf2_mu3360// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3361// CHECK-RV64-NEXT: entry:3362// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vsll.mask.nxv1i32.i64.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x i32> [[OP1]], i64 [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)3363// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]3364//3365vuint32mf2_t test_vsll_vx_u32mf2_mu(vbool64_t mask, vuint32mf2_t maskedoff, vuint32mf2_t op1, size_t shift, size_t vl) {3366 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3367}3368 3369// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vsll_vv_u32m1_mu3370// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3371// CHECK-RV64-NEXT: entry:3372// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vsll.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i32> [[OP1]], <vscale x 2 x i32> [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)3373// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]3374//3375vuint32m1_t test_vsll_vv_u32m1_mu(vbool32_t mask, vuint32m1_t maskedoff, vuint32m1_t op1, vuint32m1_t shift, size_t vl) {3376 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3377}3378 3379// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vsll_vx_u32m1_mu3380// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3381// CHECK-RV64-NEXT: entry:3382// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vsll.mask.nxv2i32.i64.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i32> [[OP1]], i64 [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)3383// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]3384//3385vuint32m1_t test_vsll_vx_u32m1_mu(vbool32_t mask, vuint32m1_t maskedoff, vuint32m1_t op1, size_t shift, size_t vl) {3386 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3387}3388 3389// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vsll_vv_u32m2_mu3390// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3391// CHECK-RV64-NEXT: entry:3392// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vsll.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x i32> [[OP1]], <vscale x 4 x i32> [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)3393// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]3394//3395vuint32m2_t test_vsll_vv_u32m2_mu(vbool16_t mask, vuint32m2_t maskedoff, vuint32m2_t op1, vuint32m2_t shift, size_t vl) {3396 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3397}3398 3399// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vsll_vx_u32m2_mu3400// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3401// CHECK-RV64-NEXT: entry:3402// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vsll.mask.nxv4i32.i64.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x i32> [[OP1]], i64 [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)3403// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]3404//3405vuint32m2_t test_vsll_vx_u32m2_mu(vbool16_t mask, vuint32m2_t maskedoff, vuint32m2_t op1, size_t shift, size_t vl) {3406 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3407}3408 3409// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vsll_vv_u32m4_mu3410// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3411// CHECK-RV64-NEXT: entry:3412// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vsll.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x i32> [[OP1]], <vscale x 8 x i32> [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)3413// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]3414//3415vuint32m4_t test_vsll_vv_u32m4_mu(vbool8_t mask, vuint32m4_t maskedoff, vuint32m4_t op1, vuint32m4_t shift, size_t vl) {3416 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3417}3418 3419// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vsll_vx_u32m4_mu3420// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3421// CHECK-RV64-NEXT: entry:3422// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vsll.mask.nxv8i32.i64.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x i32> [[OP1]], i64 [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)3423// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]3424//3425vuint32m4_t test_vsll_vx_u32m4_mu(vbool8_t mask, vuint32m4_t maskedoff, vuint32m4_t op1, size_t shift, size_t vl) {3426 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3427}3428 3429// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vsll_vv_u32m8_mu3430// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3431// CHECK-RV64-NEXT: entry:3432// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vsll.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x i32> [[OP1]], <vscale x 16 x i32> [[SHIFT]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)3433// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]3434//3435vuint32m8_t test_vsll_vv_u32m8_mu(vbool4_t mask, vuint32m8_t maskedoff, vuint32m8_t op1, vuint32m8_t shift, size_t vl) {3436 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3437}3438 3439// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vsll_vx_u32m8_mu3440// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3441// CHECK-RV64-NEXT: entry:3442// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vsll.mask.nxv16i32.i64.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x i32> [[OP1]], i64 [[SHIFT]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)3443// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]3444//3445vuint32m8_t test_vsll_vx_u32m8_mu(vbool4_t mask, vuint32m8_t maskedoff, vuint32m8_t op1, size_t shift, size_t vl) {3446 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3447}3448 3449// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vsll_vv_u64m1_mu3450// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3451// CHECK-RV64-NEXT: entry:3452// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vsll.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i64> [[OP1]], <vscale x 1 x i64> [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)3453// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]3454//3455vuint64m1_t test_vsll_vv_u64m1_mu(vbool64_t mask, vuint64m1_t maskedoff, vuint64m1_t op1, vuint64m1_t shift, size_t vl) {3456 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3457}3458 3459// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vsll_vx_u64m1_mu3460// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3461// CHECK-RV64-NEXT: entry:3462// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vsll.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i64> [[OP1]], i64 [[SHIFT]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)3463// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]3464//3465vuint64m1_t test_vsll_vx_u64m1_mu(vbool64_t mask, vuint64m1_t maskedoff, vuint64m1_t op1, size_t shift, size_t vl) {3466 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3467}3468 3469// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vsll_vv_u64m2_mu3470// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3471// CHECK-RV64-NEXT: entry:3472// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vsll.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i64> [[OP1]], <vscale x 2 x i64> [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)3473// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]3474//3475vuint64m2_t test_vsll_vv_u64m2_mu(vbool32_t mask, vuint64m2_t maskedoff, vuint64m2_t op1, vuint64m2_t shift, size_t vl) {3476 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3477}3478 3479// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vsll_vx_u64m2_mu3480// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3481// CHECK-RV64-NEXT: entry:3482// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vsll.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i64> [[OP1]], i64 [[SHIFT]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)3483// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]3484//3485vuint64m2_t test_vsll_vx_u64m2_mu(vbool32_t mask, vuint64m2_t maskedoff, vuint64m2_t op1, size_t shift, size_t vl) {3486 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3487}3488 3489// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vsll_vv_u64m4_mu3490// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3491// CHECK-RV64-NEXT: entry:3492// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vsll.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i64> [[OP1]], <vscale x 4 x i64> [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)3493// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]3494//3495vuint64m4_t test_vsll_vv_u64m4_mu(vbool16_t mask, vuint64m4_t maskedoff, vuint64m4_t op1, vuint64m4_t shift, size_t vl) {3496 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3497}3498 3499// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vsll_vx_u64m4_mu3500// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3501// CHECK-RV64-NEXT: entry:3502// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vsll.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i64> [[OP1]], i64 [[SHIFT]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)3503// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]3504//3505vuint64m4_t test_vsll_vx_u64m4_mu(vbool16_t mask, vuint64m4_t maskedoff, vuint64m4_t op1, size_t shift, size_t vl) {3506 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3507}3508 3509// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vsll_vv_u64m8_mu3510// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3511// CHECK-RV64-NEXT: entry:3512// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vsll.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i64> [[OP1]], <vscale x 8 x i64> [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)3513// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]3514//3515vuint64m8_t test_vsll_vv_u64m8_mu(vbool8_t mask, vuint64m8_t maskedoff, vuint64m8_t op1, vuint64m8_t shift, size_t vl) {3516 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3517}3518 3519// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vsll_vx_u64m8_mu3520// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], i64 noundef [[SHIFT:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {3521// CHECK-RV64-NEXT: entry:3522// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vsll.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i64> [[OP1]], i64 [[SHIFT]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)3523// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]3524//3525vuint64m8_t test_vsll_vx_u64m8_mu(vbool8_t mask, vuint64m8_t maskedoff, vuint64m8_t op1, size_t shift, size_t vl) {3526 return __riscv_vsll_mu(mask, maskedoff, op1, shift, vl);3527}3528 3529