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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 22// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \4// RUN: -target-feature +zvbb \5// RUN: -target-feature +zvbc \6// RUN: -target-feature +zvkb \7// RUN: -target-feature +zvkg \8// RUN: -target-feature +zvkned \9// RUN: -target-feature +zvknhb \10// RUN: -target-feature +zvksed \11// RUN: -target-feature +zvksh \12// RUN: -disable-O0-optnone \13// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \14// RUN: FileCheck --check-prefix=CHECK-RV64 %s15 16#include <riscv_vector.h>17 18// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vclmul_vv_u64m119// CHECK-RV64-SAME: (<vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {20// CHECK-RV64-NEXT: entry:21// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> [[VS2]], <vscale x 1 x i64> [[VS1]], i64 [[VL]])22// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]23//24vuint64m1_t test_vclmul_vv_u64m1(vuint64m1_t vs2, vuint64m1_t vs1, size_t vl) {25 return __riscv_vclmul_vv_u64m1(vs2, vs1, vl);26}27 28// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vclmul_vx_u64m129// CHECK-RV64-SAME: (<vscale x 1 x i64> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {30// CHECK-RV64-NEXT: entry:31// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> [[VS2]], i64 [[RS1]], i64 [[VL]])32// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]33//34vuint64m1_t test_vclmul_vx_u64m1(vuint64m1_t vs2, uint64_t rs1, size_t vl) {35 return __riscv_vclmul_vx_u64m1(vs2, rs1, vl);36}37 38// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vclmul_vv_u64m239// CHECK-RV64-SAME: (<vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {40// CHECK-RV64-NEXT: entry:41// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> [[VS2]], <vscale x 2 x i64> [[VS1]], i64 [[VL]])42// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]43//44vuint64m2_t test_vclmul_vv_u64m2(vuint64m2_t vs2, vuint64m2_t vs1, size_t vl) {45 return __riscv_vclmul_vv_u64m2(vs2, vs1, vl);46}47 48// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vclmul_vx_u64m249// CHECK-RV64-SAME: (<vscale x 2 x i64> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {50// CHECK-RV64-NEXT: entry:51// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> [[VS2]], i64 [[RS1]], i64 [[VL]])52// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]53//54vuint64m2_t test_vclmul_vx_u64m2(vuint64m2_t vs2, uint64_t rs1, size_t vl) {55 return __riscv_vclmul_vx_u64m2(vs2, rs1, vl);56}57 58// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vclmul_vv_u64m459// CHECK-RV64-SAME: (<vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {60// CHECK-RV64-NEXT: entry:61// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> [[VS2]], <vscale x 4 x i64> [[VS1]], i64 [[VL]])62// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]63//64vuint64m4_t test_vclmul_vv_u64m4(vuint64m4_t vs2, vuint64m4_t vs1, size_t vl) {65 return __riscv_vclmul_vv_u64m4(vs2, vs1, vl);66}67 68// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vclmul_vx_u64m469// CHECK-RV64-SAME: (<vscale x 4 x i64> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {70// CHECK-RV64-NEXT: entry:71// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> [[VS2]], i64 [[RS1]], i64 [[VL]])72// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]73//74vuint64m4_t test_vclmul_vx_u64m4(vuint64m4_t vs2, uint64_t rs1, size_t vl) {75 return __riscv_vclmul_vx_u64m4(vs2, rs1, vl);76}77 78// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vclmul_vv_u64m879// CHECK-RV64-SAME: (<vscale x 8 x i64> [[VS2:%.*]], <vscale x 8 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {80// CHECK-RV64-NEXT: entry:81// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> [[VS2]], <vscale x 8 x i64> [[VS1]], i64 [[VL]])82// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]83//84vuint64m8_t test_vclmul_vv_u64m8(vuint64m8_t vs2, vuint64m8_t vs1, size_t vl) {85 return __riscv_vclmul_vv_u64m8(vs2, vs1, vl);86}87 88// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vclmul_vx_u64m889// CHECK-RV64-SAME: (<vscale x 8 x i64> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {90// CHECK-RV64-NEXT: entry:91// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> [[VS2]], i64 [[RS1]], i64 [[VL]])92// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]93//94vuint64m8_t test_vclmul_vx_u64m8(vuint64m8_t vs2, uint64_t rs1, size_t vl) {95 return __riscv_vclmul_vx_u64m8(vs2, rs1, vl);96}97 98// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vclmul_vv_u64m1_m99// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {100// CHECK-RV64-NEXT: entry:101// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vclmul.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> [[VS2]], <vscale x 1 x i64> [[VS1]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)102// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]103//104vuint64m1_t test_vclmul_vv_u64m1_m(vbool64_t mask, vuint64m1_t vs2, vuint64m1_t vs1, size_t vl) {105 return __riscv_vclmul_vv_u64m1_m(mask, vs2, vs1, vl);106}107 108// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vclmul_vx_u64m1_m109// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {110// CHECK-RV64-NEXT: entry:111// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vclmul.mask.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> [[VS2]], i64 [[RS1]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)112// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]113//114vuint64m1_t test_vclmul_vx_u64m1_m(vbool64_t mask, vuint64m1_t vs2, uint64_t rs1, size_t vl) {115 return __riscv_vclmul_vx_u64m1_m(mask, vs2, rs1, vl);116}117 118// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vclmul_vv_u64m2_m119// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {120// CHECK-RV64-NEXT: entry:121// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vclmul.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> [[VS2]], <vscale x 2 x i64> [[VS1]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)122// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]123//124vuint64m2_t test_vclmul_vv_u64m2_m(vbool32_t mask, vuint64m2_t vs2, vuint64m2_t vs1, size_t vl) {125 return __riscv_vclmul_vv_u64m2_m(mask, vs2, vs1, vl);126}127 128// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vclmul_vx_u64m2_m129// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {130// CHECK-RV64-NEXT: entry:131// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vclmul.mask.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> [[VS2]], i64 [[RS1]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)132// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]133//134vuint64m2_t test_vclmul_vx_u64m2_m(vbool32_t mask, vuint64m2_t vs2, uint64_t rs1, size_t vl) {135 return __riscv_vclmul_vx_u64m2_m(mask, vs2, rs1, vl);136}137 138// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vclmul_vv_u64m4_m139// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {140// CHECK-RV64-NEXT: entry:141// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vclmul.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> [[VS2]], <vscale x 4 x i64> [[VS1]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)142// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]143//144vuint64m4_t test_vclmul_vv_u64m4_m(vbool16_t mask, vuint64m4_t vs2, vuint64m4_t vs1, size_t vl) {145 return __riscv_vclmul_vv_u64m4_m(mask, vs2, vs1, vl);146}147 148// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vclmul_vx_u64m4_m149// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {150// CHECK-RV64-NEXT: entry:151// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vclmul.mask.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> [[VS2]], i64 [[RS1]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)152// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]153//154vuint64m4_t test_vclmul_vx_u64m4_m(vbool16_t mask, vuint64m4_t vs2, uint64_t rs1, size_t vl) {155 return __riscv_vclmul_vx_u64m4_m(mask, vs2, rs1, vl);156}157 158// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vclmul_vv_u64m8_m159// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[VS2:%.*]], <vscale x 8 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {160// CHECK-RV64-NEXT: entry:161// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vclmul.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> [[VS2]], <vscale x 8 x i64> [[VS1]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)162// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]163//164vuint64m8_t test_vclmul_vv_u64m8_m(vbool8_t mask, vuint64m8_t vs2, vuint64m8_t vs1, size_t vl) {165 return __riscv_vclmul_vv_u64m8_m(mask, vs2, vs1, vl);166}167 168// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vclmul_vx_u64m8_m169// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {170// CHECK-RV64-NEXT: entry:171// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vclmul.mask.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> [[VS2]], i64 [[RS1]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)172// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]173//174vuint64m8_t test_vclmul_vx_u64m8_m(vbool8_t mask, vuint64m8_t vs2, uint64_t rs1, size_t vl) {175 return __riscv_vclmul_vx_u64m8_m(mask, vs2, rs1, vl);176}177 178