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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 22// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \4// RUN: -target-feature +zvbb \5// RUN: -target-feature +zvbc \6// RUN: -target-feature +zvkb \7// RUN: -target-feature +zvkg \8// RUN: -target-feature +zvkned \9// RUN: -target-feature +zvknhb \10// RUN: -target-feature +zvksed \11// RUN: -target-feature +zvksh \12// RUN: -disable-O0-optnone \13// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \14// RUN: FileCheck --check-prefix=CHECK-RV64 %s15 16#include <riscv_vector.h>17 18// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vsm3c_vi_u32mf219// CHECK-RV64-SAME: (<vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {20// CHECK-RV64-NEXT: entry:21// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vsm3c.nxv1i32.i64.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i64 0, i64 [[VL]], i64 3)22// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]23//24vuint32mf2_t test_vsm3c_vi_u32mf2(vuint32mf2_t vd, vuint32mf2_t vs2, size_t vl) {25 return __riscv_vsm3c_vi_u32mf2(vd, vs2, 0, vl);26}27 28// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vsm3c_vi_u32m129// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {30// CHECK-RV64-NEXT: entry:31// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vsm3c.nxv2i32.i64.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i64 0, i64 [[VL]], i64 3)32// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]33//34vuint32m1_t test_vsm3c_vi_u32m1(vuint32m1_t vd, vuint32m1_t vs2, size_t vl) {35 return __riscv_vsm3c_vi_u32m1(vd, vs2, 0, vl);36}37 38// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vsm3c_vi_u32m239// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {40// CHECK-RV64-NEXT: entry:41// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vsm3c.nxv4i32.i64.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i64 0, i64 [[VL]], i64 3)42// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]43//44vuint32m2_t test_vsm3c_vi_u32m2(vuint32m2_t vd, vuint32m2_t vs2, size_t vl) {45 return __riscv_vsm3c_vi_u32m2(vd, vs2, 0, vl);46}47 48// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vsm3c_vi_u32m449// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {50// CHECK-RV64-NEXT: entry:51// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vsm3c.nxv8i32.i64.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i64 0, i64 [[VL]], i64 3)52// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]53//54vuint32m4_t test_vsm3c_vi_u32m4(vuint32m4_t vd, vuint32m4_t vs2, size_t vl) {55 return __riscv_vsm3c_vi_u32m4(vd, vs2, 0, vl);56}57 58// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vsm3c_vi_u32m859// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {60// CHECK-RV64-NEXT: entry:61// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vsm3c.nxv16i32.i64.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i64 0, i64 [[VL]], i64 3)62// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]63//64vuint32m8_t test_vsm3c_vi_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) {65 return __riscv_vsm3c_vi_u32m8(vd, vs2, 0, vl);66}67 68