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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 22// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \4// RUN: -target-feature +zvbb \5// RUN: -target-feature +zvbc \6// RUN: -target-feature +zvkb \7// RUN: -target-feature +zvkg \8// RUN: -target-feature +zvkned \9// RUN: -target-feature +zvknhb \10// RUN: -target-feature +zvksed \11// RUN: -target-feature +zvksh \12// RUN: -disable-O0-optnone \13// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \14// RUN: FileCheck --check-prefix=CHECK-RV64 %s15 16#include <riscv_vector.h>17 18// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vclmulh_vv_u64m1_tu19// CHECK-RV64-SAME: (<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {20// CHECK-RV64-NEXT: entry:21// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i64> [[VS2]], <vscale x 1 x i64> [[VS1]], i64 [[VL]])22// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]23//24vuint64m1_t test_vclmulh_vv_u64m1_tu(vuint64m1_t maskedoff, vuint64m1_t vs2, vuint64m1_t vs1, size_t vl) {25 return __riscv_vclmulh_vv_u64m1_tu(maskedoff, vs2, vs1, vl);26}27 28// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vclmulh_vx_u64m1_tu29// CHECK-RV64-SAME: (<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {30// CHECK-RV64-NEXT: entry:31// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.i64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i64> [[VS2]], i64 [[RS1]], i64 [[VL]])32// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]33//34vuint64m1_t test_vclmulh_vx_u64m1_tu(vuint64m1_t maskedoff, vuint64m1_t vs2, uint64_t rs1, size_t vl) {35 return __riscv_vclmulh_vx_u64m1_tu(maskedoff, vs2, rs1, vl);36}37 38// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vclmulh_vv_u64m2_tu39// CHECK-RV64-SAME: (<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {40// CHECK-RV64-NEXT: entry:41// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i64> [[VS2]], <vscale x 2 x i64> [[VS1]], i64 [[VL]])42// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]43//44vuint64m2_t test_vclmulh_vv_u64m2_tu(vuint64m2_t maskedoff, vuint64m2_t vs2, vuint64m2_t vs1, size_t vl) {45 return __riscv_vclmulh_vv_u64m2_tu(maskedoff, vs2, vs1, vl);46}47 48// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vclmulh_vx_u64m2_tu49// CHECK-RV64-SAME: (<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {50// CHECK-RV64-NEXT: entry:51// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.i64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i64> [[VS2]], i64 [[RS1]], i64 [[VL]])52// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]53//54vuint64m2_t test_vclmulh_vx_u64m2_tu(vuint64m2_t maskedoff, vuint64m2_t vs2, uint64_t rs1, size_t vl) {55 return __riscv_vclmulh_vx_u64m2_tu(maskedoff, vs2, rs1, vl);56}57 58// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vclmulh_vv_u64m4_tu59// CHECK-RV64-SAME: (<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {60// CHECK-RV64-NEXT: entry:61// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i64> [[VS2]], <vscale x 4 x i64> [[VS1]], i64 [[VL]])62// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]63//64vuint64m4_t test_vclmulh_vv_u64m4_tu(vuint64m4_t maskedoff, vuint64m4_t vs2, vuint64m4_t vs1, size_t vl) {65 return __riscv_vclmulh_vv_u64m4_tu(maskedoff, vs2, vs1, vl);66}67 68// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vclmulh_vx_u64m4_tu69// CHECK-RV64-SAME: (<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {70// CHECK-RV64-NEXT: entry:71// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.i64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i64> [[VS2]], i64 [[RS1]], i64 [[VL]])72// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]73//74vuint64m4_t test_vclmulh_vx_u64m4_tu(vuint64m4_t maskedoff, vuint64m4_t vs2, uint64_t rs1, size_t vl) {75 return __riscv_vclmulh_vx_u64m4_tu(maskedoff, vs2, rs1, vl);76}77 78// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vclmulh_vv_u64m8_tu79// CHECK-RV64-SAME: (<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[VS2:%.*]], <vscale x 8 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {80// CHECK-RV64-NEXT: entry:81// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i64> [[VS2]], <vscale x 8 x i64> [[VS1]], i64 [[VL]])82// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]83//84vuint64m8_t test_vclmulh_vv_u64m8_tu(vuint64m8_t maskedoff, vuint64m8_t vs2, vuint64m8_t vs1, size_t vl) {85 return __riscv_vclmulh_vv_u64m8_tu(maskedoff, vs2, vs1, vl);86}87 88// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vclmulh_vx_u64m8_tu89// CHECK-RV64-SAME: (<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {90// CHECK-RV64-NEXT: entry:91// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.i64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i64> [[VS2]], i64 [[RS1]], i64 [[VL]])92// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]93//94vuint64m8_t test_vclmulh_vx_u64m8_tu(vuint64m8_t maskedoff, vuint64m8_t vs2, uint64_t rs1, size_t vl) {95 return __riscv_vclmulh_vx_u64m8_tu(maskedoff, vs2, rs1, vl);96}97 98// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vclmulh_vv_u64m1_tum99// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {100// CHECK-RV64-NEXT: entry:101// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vclmulh.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i64> [[VS2]], <vscale x 1 x i64> [[VS1]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)102// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]103//104vuint64m1_t test_vclmulh_vv_u64m1_tum(vbool64_t mask, vuint64m1_t maskedoff, vuint64m1_t vs2, vuint64m1_t vs1, size_t vl) {105 return __riscv_vclmulh_vv_u64m1_tum(mask, maskedoff, vs2, vs1, vl);106}107 108// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vclmulh_vx_u64m1_tum109// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {110// CHECK-RV64-NEXT: entry:111// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vclmulh.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i64> [[VS2]], i64 [[RS1]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)112// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]113//114vuint64m1_t test_vclmulh_vx_u64m1_tum(vbool64_t mask, vuint64m1_t maskedoff, vuint64m1_t vs2, uint64_t rs1, size_t vl) {115 return __riscv_vclmulh_vx_u64m1_tum(mask, maskedoff, vs2, rs1, vl);116}117 118// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vclmulh_vv_u64m2_tum119// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {120// CHECK-RV64-NEXT: entry:121// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vclmulh.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i64> [[VS2]], <vscale x 2 x i64> [[VS1]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)122// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]123//124vuint64m2_t test_vclmulh_vv_u64m2_tum(vbool32_t mask, vuint64m2_t maskedoff, vuint64m2_t vs2, vuint64m2_t vs1, size_t vl) {125 return __riscv_vclmulh_vv_u64m2_tum(mask, maskedoff, vs2, vs1, vl);126}127 128// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vclmulh_vx_u64m2_tum129// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {130// CHECK-RV64-NEXT: entry:131// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vclmulh.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i64> [[VS2]], i64 [[RS1]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)132// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]133//134vuint64m2_t test_vclmulh_vx_u64m2_tum(vbool32_t mask, vuint64m2_t maskedoff, vuint64m2_t vs2, uint64_t rs1, size_t vl) {135 return __riscv_vclmulh_vx_u64m2_tum(mask, maskedoff, vs2, rs1, vl);136}137 138// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vclmulh_vv_u64m4_tum139// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {140// CHECK-RV64-NEXT: entry:141// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vclmulh.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i64> [[VS2]], <vscale x 4 x i64> [[VS1]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)142// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]143//144vuint64m4_t test_vclmulh_vv_u64m4_tum(vbool16_t mask, vuint64m4_t maskedoff, vuint64m4_t vs2, vuint64m4_t vs1, size_t vl) {145 return __riscv_vclmulh_vv_u64m4_tum(mask, maskedoff, vs2, vs1, vl);146}147 148// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vclmulh_vx_u64m4_tum149// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {150// CHECK-RV64-NEXT: entry:151// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vclmulh.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i64> [[VS2]], i64 [[RS1]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)152// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]153//154vuint64m4_t test_vclmulh_vx_u64m4_tum(vbool16_t mask, vuint64m4_t maskedoff, vuint64m4_t vs2, uint64_t rs1, size_t vl) {155 return __riscv_vclmulh_vx_u64m4_tum(mask, maskedoff, vs2, rs1, vl);156}157 158// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vclmulh_vv_u64m8_tum159// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[VS2:%.*]], <vscale x 8 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {160// CHECK-RV64-NEXT: entry:161// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vclmulh.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i64> [[VS2]], <vscale x 8 x i64> [[VS1]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)162// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]163//164vuint64m8_t test_vclmulh_vv_u64m8_tum(vbool8_t mask, vuint64m8_t maskedoff, vuint64m8_t vs2, vuint64m8_t vs1, size_t vl) {165 return __riscv_vclmulh_vv_u64m8_tum(mask, maskedoff, vs2, vs1, vl);166}167 168// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vclmulh_vx_u64m8_tum169// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {170// CHECK-RV64-NEXT: entry:171// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vclmulh.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i64> [[VS2]], i64 [[RS1]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)172// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]173//174vuint64m8_t test_vclmulh_vx_u64m8_tum(vbool8_t mask, vuint64m8_t maskedoff, vuint64m8_t vs2, uint64_t rs1, size_t vl) {175 return __riscv_vclmulh_vx_u64m8_tum(mask, maskedoff, vs2, rs1, vl);176}177 178// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vclmulh_vv_u64m1_tumu179// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {180// CHECK-RV64-NEXT: entry:181// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vclmulh.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i64> [[VS2]], <vscale x 1 x i64> [[VS1]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)182// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]183//184vuint64m1_t test_vclmulh_vv_u64m1_tumu(vbool64_t mask, vuint64m1_t maskedoff, vuint64m1_t vs2, vuint64m1_t vs1, size_t vl) {185 return __riscv_vclmulh_vv_u64m1_tumu(mask, maskedoff, vs2, vs1, vl);186}187 188// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vclmulh_vx_u64m1_tumu189// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {190// CHECK-RV64-NEXT: entry:191// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vclmulh.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i64> [[VS2]], i64 [[RS1]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)192// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]193//194vuint64m1_t test_vclmulh_vx_u64m1_tumu(vbool64_t mask, vuint64m1_t maskedoff, vuint64m1_t vs2, uint64_t rs1, size_t vl) {195 return __riscv_vclmulh_vx_u64m1_tumu(mask, maskedoff, vs2, rs1, vl);196}197 198// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vclmulh_vv_u64m2_tumu199// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {200// CHECK-RV64-NEXT: entry:201// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vclmulh.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i64> [[VS2]], <vscale x 2 x i64> [[VS1]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)202// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]203//204vuint64m2_t test_vclmulh_vv_u64m2_tumu(vbool32_t mask, vuint64m2_t maskedoff, vuint64m2_t vs2, vuint64m2_t vs1, size_t vl) {205 return __riscv_vclmulh_vv_u64m2_tumu(mask, maskedoff, vs2, vs1, vl);206}207 208// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vclmulh_vx_u64m2_tumu209// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {210// CHECK-RV64-NEXT: entry:211// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vclmulh.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i64> [[VS2]], i64 [[RS1]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)212// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]213//214vuint64m2_t test_vclmulh_vx_u64m2_tumu(vbool32_t mask, vuint64m2_t maskedoff, vuint64m2_t vs2, uint64_t rs1, size_t vl) {215 return __riscv_vclmulh_vx_u64m2_tumu(mask, maskedoff, vs2, rs1, vl);216}217 218// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vclmulh_vv_u64m4_tumu219// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {220// CHECK-RV64-NEXT: entry:221// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vclmulh.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i64> [[VS2]], <vscale x 4 x i64> [[VS1]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)222// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]223//224vuint64m4_t test_vclmulh_vv_u64m4_tumu(vbool16_t mask, vuint64m4_t maskedoff, vuint64m4_t vs2, vuint64m4_t vs1, size_t vl) {225 return __riscv_vclmulh_vv_u64m4_tumu(mask, maskedoff, vs2, vs1, vl);226}227 228// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vclmulh_vx_u64m4_tumu229// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {230// CHECK-RV64-NEXT: entry:231// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vclmulh.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i64> [[VS2]], i64 [[RS1]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)232// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]233//234vuint64m4_t test_vclmulh_vx_u64m4_tumu(vbool16_t mask, vuint64m4_t maskedoff, vuint64m4_t vs2, uint64_t rs1, size_t vl) {235 return __riscv_vclmulh_vx_u64m4_tumu(mask, maskedoff, vs2, rs1, vl);236}237 238// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vclmulh_vv_u64m8_tumu239// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[VS2:%.*]], <vscale x 8 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {240// CHECK-RV64-NEXT: entry:241// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vclmulh.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i64> [[VS2]], <vscale x 8 x i64> [[VS1]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)242// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]243//244vuint64m8_t test_vclmulh_vv_u64m8_tumu(vbool8_t mask, vuint64m8_t maskedoff, vuint64m8_t vs2, vuint64m8_t vs1, size_t vl) {245 return __riscv_vclmulh_vv_u64m8_tumu(mask, maskedoff, vs2, vs1, vl);246}247 248// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vclmulh_vx_u64m8_tumu249// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {250// CHECK-RV64-NEXT: entry:251// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vclmulh.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i64> [[VS2]], i64 [[RS1]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)252// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]253//254vuint64m8_t test_vclmulh_vx_u64m8_tumu(vbool8_t mask, vuint64m8_t maskedoff, vuint64m8_t vs2, uint64_t rs1, size_t vl) {255 return __riscv_vclmulh_vx_u64m8_tumu(mask, maskedoff, vs2, rs1, vl);256}257 258// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vclmulh_vv_u64m1_mu259// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {260// CHECK-RV64-NEXT: entry:261// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vclmulh.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i64> [[VS2]], <vscale x 1 x i64> [[VS1]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)262// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]263//264vuint64m1_t test_vclmulh_vv_u64m1_mu(vbool64_t mask, vuint64m1_t maskedoff, vuint64m1_t vs2, vuint64m1_t vs1, size_t vl) {265 return __riscv_vclmulh_vv_u64m1_mu(mask, maskedoff, vs2, vs1, vl);266}267 268// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vclmulh_vx_u64m1_mu269// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {270// CHECK-RV64-NEXT: entry:271// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vclmulh.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i64> [[VS2]], i64 [[RS1]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)272// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]273//274vuint64m1_t test_vclmulh_vx_u64m1_mu(vbool64_t mask, vuint64m1_t maskedoff, vuint64m1_t vs2, uint64_t rs1, size_t vl) {275 return __riscv_vclmulh_vx_u64m1_mu(mask, maskedoff, vs2, rs1, vl);276}277 278// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vclmulh_vv_u64m2_mu279// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {280// CHECK-RV64-NEXT: entry:281// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vclmulh.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i64> [[VS2]], <vscale x 2 x i64> [[VS1]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)282// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]283//284vuint64m2_t test_vclmulh_vv_u64m2_mu(vbool32_t mask, vuint64m2_t maskedoff, vuint64m2_t vs2, vuint64m2_t vs1, size_t vl) {285 return __riscv_vclmulh_vv_u64m2_mu(mask, maskedoff, vs2, vs1, vl);286}287 288// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vclmulh_vx_u64m2_mu289// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {290// CHECK-RV64-NEXT: entry:291// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vclmulh.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i64> [[VS2]], i64 [[RS1]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)292// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]293//294vuint64m2_t test_vclmulh_vx_u64m2_mu(vbool32_t mask, vuint64m2_t maskedoff, vuint64m2_t vs2, uint64_t rs1, size_t vl) {295 return __riscv_vclmulh_vx_u64m2_mu(mask, maskedoff, vs2, rs1, vl);296}297 298// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vclmulh_vv_u64m4_mu299// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {300// CHECK-RV64-NEXT: entry:301// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vclmulh.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i64> [[VS2]], <vscale x 4 x i64> [[VS1]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)302// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]303//304vuint64m4_t test_vclmulh_vv_u64m4_mu(vbool16_t mask, vuint64m4_t maskedoff, vuint64m4_t vs2, vuint64m4_t vs1, size_t vl) {305 return __riscv_vclmulh_vv_u64m4_mu(mask, maskedoff, vs2, vs1, vl);306}307 308// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vclmulh_vx_u64m4_mu309// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {310// CHECK-RV64-NEXT: entry:311// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vclmulh.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i64> [[VS2]], i64 [[RS1]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)312// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]313//314vuint64m4_t test_vclmulh_vx_u64m4_mu(vbool16_t mask, vuint64m4_t maskedoff, vuint64m4_t vs2, uint64_t rs1, size_t vl) {315 return __riscv_vclmulh_vx_u64m4_mu(mask, maskedoff, vs2, rs1, vl);316}317 318// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vclmulh_vv_u64m8_mu319// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[VS2:%.*]], <vscale x 8 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {320// CHECK-RV64-NEXT: entry:321// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vclmulh.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i64> [[VS2]], <vscale x 8 x i64> [[VS1]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)322// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]323//324vuint64m8_t test_vclmulh_vv_u64m8_mu(vbool8_t mask, vuint64m8_t maskedoff, vuint64m8_t vs2, vuint64m8_t vs1, size_t vl) {325 return __riscv_vclmulh_vv_u64m8_mu(mask, maskedoff, vs2, vs1, vl);326}327 328// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vclmulh_vx_u64m8_mu329// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {330// CHECK-RV64-NEXT: entry:331// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vclmulh.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i64> [[VS2]], i64 [[RS1]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)332// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]333//334vuint64m8_t test_vclmulh_vx_u64m8_mu(vbool8_t mask, vuint64m8_t maskedoff, vuint64m8_t vs2, uint64_t rs1, size_t vl) {335 return __riscv_vclmulh_vx_u64m8_mu(mask, maskedoff, vs2, rs1, vl);336}337 338