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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 42// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +zve64x \4// RUN: -target-feature +zvfbfmin -disable-O0-optnone \5// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \6// RUN: FileCheck --check-prefix=CHECK-RV64 %s7 8#include <riscv_vector.h>9 10// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vloxei32_v_bf16mf4(11// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], <vscale x 1 x i32> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {12// CHECK-RV64-NEXT: entry:13// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> poison, ptr [[RS1]], <vscale x 1 x i32> [[RS2]], i64 [[VL]])14// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]15//16vbfloat16mf4_t test_vloxei32_v_bf16mf4(const __bf16 *rs1, vuint32mf2_t rs2,17 size_t vl) {18 return __riscv_vloxei32_v_bf16mf4(rs1, rs2, vl);19}20 21// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vloxei32_v_bf16mf2(22// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], <vscale x 2 x i32> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {23// CHECK-RV64-NEXT: entry:24// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> poison, ptr [[RS1]], <vscale x 2 x i32> [[RS2]], i64 [[VL]])25// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]26//27vbfloat16mf2_t test_vloxei32_v_bf16mf2(const __bf16 *rs1, vuint32m1_t rs2,28 size_t vl) {29 return __riscv_vloxei32_v_bf16mf2(rs1, rs2, vl);30}31 32// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vloxei32_v_bf16m1(33// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], <vscale x 4 x i32> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {34// CHECK-RV64-NEXT: entry:35// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> poison, ptr [[RS1]], <vscale x 4 x i32> [[RS2]], i64 [[VL]])36// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]37//38vbfloat16m1_t test_vloxei32_v_bf16m1(const __bf16 *rs1, vuint32m2_t rs2,39 size_t vl) {40 return __riscv_vloxei32_v_bf16m1(rs1, rs2, vl);41}42 43// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vloxei32_v_bf16m2(44// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], <vscale x 8 x i32> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {45// CHECK-RV64-NEXT: entry:46// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> poison, ptr [[RS1]], <vscale x 8 x i32> [[RS2]], i64 [[VL]])47// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]48//49vbfloat16m2_t test_vloxei32_v_bf16m2(const __bf16 *rs1, vuint32m4_t rs2,50 size_t vl) {51 return __riscv_vloxei32_v_bf16m2(rs1, rs2, vl);52}53 54// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vloxei32_v_bf16m4(55// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], <vscale x 16 x i32> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {56// CHECK-RV64-NEXT: entry:57// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> poison, ptr [[RS1]], <vscale x 16 x i32> [[RS2]], i64 [[VL]])58// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]59//60vbfloat16m4_t test_vloxei32_v_bf16m4(const __bf16 *rs1, vuint32m8_t rs2,61 size_t vl) {62 return __riscv_vloxei32_v_bf16m4(rs1, rs2, vl);63}64 65// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vloxei32_v_bf16mf4_m(66// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], <vscale x 1 x i32> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {67// CHECK-RV64-NEXT: entry:68// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> poison, ptr [[RS1]], <vscale x 1 x i32> [[RS2]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)69// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]70//71vbfloat16mf4_t test_vloxei32_v_bf16mf4_m(vbool64_t vm, const __bf16 *rs1,72 vuint32mf2_t rs2, size_t vl) {73 return __riscv_vloxei32_v_bf16mf4_m(vm, rs1, rs2, vl);74}75 76// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vloxei32_v_bf16mf2_m(77// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], <vscale x 2 x i32> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {78// CHECK-RV64-NEXT: entry:79// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> poison, ptr [[RS1]], <vscale x 2 x i32> [[RS2]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)80// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]81//82vbfloat16mf2_t test_vloxei32_v_bf16mf2_m(vbool32_t vm, const __bf16 *rs1,83 vuint32m1_t rs2, size_t vl) {84 return __riscv_vloxei32_v_bf16mf2_m(vm, rs1, rs2, vl);85}86 87// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vloxei32_v_bf16m1_m(88// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], <vscale x 4 x i32> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {89// CHECK-RV64-NEXT: entry:90// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> poison, ptr [[RS1]], <vscale x 4 x i32> [[RS2]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)91// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]92//93vbfloat16m1_t test_vloxei32_v_bf16m1_m(vbool16_t vm, const __bf16 *rs1,94 vuint32m2_t rs2, size_t vl) {95 return __riscv_vloxei32_v_bf16m1_m(vm, rs1, rs2, vl);96}97 98// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vloxei32_v_bf16m2_m(99// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], <vscale x 8 x i32> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {100// CHECK-RV64-NEXT: entry:101// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> poison, ptr [[RS1]], <vscale x 8 x i32> [[RS2]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)102// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]103//104vbfloat16m2_t test_vloxei32_v_bf16m2_m(vbool8_t vm, const __bf16 *rs1,105 vuint32m4_t rs2, size_t vl) {106 return __riscv_vloxei32_v_bf16m2_m(vm, rs1, rs2, vl);107}108 109// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vloxei32_v_bf16m4_m(110// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], <vscale x 16 x i32> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {111// CHECK-RV64-NEXT: entry:112// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.mask.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> poison, ptr [[RS1]], <vscale x 16 x i32> [[RS2]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)113// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]114//115vbfloat16m4_t test_vloxei32_v_bf16m4_m(vbool4_t vm, const __bf16 *rs1,116 vuint32m8_t rs2, size_t vl) {117 return __riscv_vloxei32_v_bf16m4_m(vm, rs1, rs2, vl);118}119