249 lines · c
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 42// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +zve64x \4// RUN: -target-feature +zvfbfmin -disable-O0-optnone \5// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \6// RUN: FileCheck --check-prefix=CHECK-RV64 %s7 8#include <riscv_vector.h>9 10// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vreinterpret_v_i16mf4_bf16mf4(11// CHECK-RV64-SAME: <vscale x 1 x i16> [[SRC:%.*]]) #[[ATTR0:[0-9]+]] {12// CHECK-RV64-NEXT: entry:13// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 1 x i16> [[SRC]] to <vscale x 1 x bfloat>14// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]15//16vbfloat16mf4_t test_vreinterpret_v_i16mf4_bf16mf4(vint16mf4_t src) {17 return __riscv_vreinterpret_v_i16mf4_bf16mf4(src);18}19 20// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vreinterpret_v_i16mf2_bf16mf2(21// CHECK-RV64-SAME: <vscale x 2 x i16> [[SRC:%.*]]) #[[ATTR0]] {22// CHECK-RV64-NEXT: entry:23// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 2 x i16> [[SRC]] to <vscale x 2 x bfloat>24// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]25//26vbfloat16mf2_t test_vreinterpret_v_i16mf2_bf16mf2(vint16mf2_t src) {27 return __riscv_vreinterpret_v_i16mf2_bf16mf2(src);28}29 30// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vreinterpret_v_i16m1_bf16m1(31// CHECK-RV64-SAME: <vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {32// CHECK-RV64-NEXT: entry:33// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 4 x bfloat>34// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]35//36vbfloat16m1_t test_vreinterpret_v_i16m1_bf16m1(vint16m1_t src) {37 return __riscv_vreinterpret_v_i16m1_bf16m1(src);38}39 40// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vreinterpret_v_i16m2_bf16m2(41// CHECK-RV64-SAME: <vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {42// CHECK-RV64-NEXT: entry:43// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC]] to <vscale x 8 x bfloat>44// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]45//46vbfloat16m2_t test_vreinterpret_v_i16m2_bf16m2(vint16m2_t src) {47 return __riscv_vreinterpret_v_i16m2_bf16m2(src);48}49 50// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vreinterpret_v_i16m4_bf16m4(51// CHECK-RV64-SAME: <vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {52// CHECK-RV64-NEXT: entry:53// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC]] to <vscale x 16 x bfloat>54// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]55//56vbfloat16m4_t test_vreinterpret_v_i16m4_bf16m4(vint16m4_t src) {57 return __riscv_vreinterpret_v_i16m4_bf16m4(src);58}59 60// CHECK-RV64-LABEL: define dso_local <vscale x 32 x bfloat> @test_vreinterpret_v_i16m8_bf16m8(61// CHECK-RV64-SAME: <vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {62// CHECK-RV64-NEXT: entry:63// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC]] to <vscale x 32 x bfloat>64// CHECK-RV64-NEXT: ret <vscale x 32 x bfloat> [[TMP0]]65//66vbfloat16m8_t test_vreinterpret_v_i16m8_bf16m8(vint16m8_t src) {67 return __riscv_vreinterpret_v_i16m8_bf16m8(src);68}69 70// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vreinterpret_v_u16mf4_bf16mf4(71// CHECK-RV64-SAME: <vscale x 1 x i16> [[SRC:%.*]]) #[[ATTR0]] {72// CHECK-RV64-NEXT: entry:73// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 1 x i16> [[SRC]] to <vscale x 1 x bfloat>74// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]75//76vbfloat16mf4_t test_vreinterpret_v_u16mf4_bf16mf4(vuint16mf4_t src) {77 return __riscv_vreinterpret_v_u16mf4_bf16mf4(src);78}79 80// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vreinterpret_v_u16mf2_bf16mf2(81// CHECK-RV64-SAME: <vscale x 2 x i16> [[SRC:%.*]]) #[[ATTR0]] {82// CHECK-RV64-NEXT: entry:83// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 2 x i16> [[SRC]] to <vscale x 2 x bfloat>84// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]85//86vbfloat16mf2_t test_vreinterpret_v_u16mf2_bf16mf2(vuint16mf2_t src) {87 return __riscv_vreinterpret_v_u16mf2_bf16mf2(src);88}89 90// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vreinterpret_v_u16m1_bf16m1(91// CHECK-RV64-SAME: <vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {92// CHECK-RV64-NEXT: entry:93// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 4 x bfloat>94// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]95//96vbfloat16m1_t test_vreinterpret_v_u16m1_bf16m1(vuint16m1_t src) {97 return __riscv_vreinterpret_v_u16m1_bf16m1(src);98}99 100// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vreinterpret_v_u16m2_bf16m2(101// CHECK-RV64-SAME: <vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {102// CHECK-RV64-NEXT: entry:103// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC]] to <vscale x 8 x bfloat>104// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]105//106vbfloat16m2_t test_vreinterpret_v_u16m2_bf16m2(vuint16m2_t src) {107 return __riscv_vreinterpret_v_u16m2_bf16m2(src);108}109 110// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vreinterpret_v_u16m4_bf16m4(111// CHECK-RV64-SAME: <vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {112// CHECK-RV64-NEXT: entry:113// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC]] to <vscale x 16 x bfloat>114// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]115//116vbfloat16m4_t test_vreinterpret_v_u16m4_bf16m4(vuint16m4_t src) {117 return __riscv_vreinterpret_v_u16m4_bf16m4(src);118}119 120// CHECK-RV64-LABEL: define dso_local <vscale x 32 x bfloat> @test_vreinterpret_v_u16m8_bf16m8(121// CHECK-RV64-SAME: <vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {122// CHECK-RV64-NEXT: entry:123// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC]] to <vscale x 32 x bfloat>124// CHECK-RV64-NEXT: ret <vscale x 32 x bfloat> [[TMP0]]125//126vbfloat16m8_t test_vreinterpret_v_u16m8_bf16m8(vuint16m8_t src) {127 return __riscv_vreinterpret_v_u16m8_bf16m8(src);128}129 130// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vreinterpret_v_bf16mf4_i16mf4(131// CHECK-RV64-SAME: <vscale x 1 x bfloat> [[SRC:%.*]]) #[[ATTR0]] {132// CHECK-RV64-NEXT: entry:133// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 1 x bfloat> [[SRC]] to <vscale x 1 x i16>134// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]135//136vint16mf4_t test_vreinterpret_v_bf16mf4_i16mf4(vbfloat16mf4_t src) {137 return __riscv_vreinterpret_v_bf16mf4_i16mf4(src);138}139 140// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vreinterpret_v_bf16mf2_i16mf2(141// CHECK-RV64-SAME: <vscale x 2 x bfloat> [[SRC:%.*]]) #[[ATTR0]] {142// CHECK-RV64-NEXT: entry:143// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 2 x bfloat> [[SRC]] to <vscale x 2 x i16>144// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]145//146vint16mf2_t test_vreinterpret_v_bf16mf2_i16mf2(vbfloat16mf2_t src) {147 return __riscv_vreinterpret_v_bf16mf2_i16mf2(src);148}149 150// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_bf16m1_i16m1(151// CHECK-RV64-SAME: <vscale x 4 x bfloat> [[SRC:%.*]]) #[[ATTR0]] {152// CHECK-RV64-NEXT: entry:153// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 4 x bfloat> [[SRC]] to <vscale x 4 x i16>154// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]155//156vint16m1_t test_vreinterpret_v_bf16m1_i16m1(vbfloat16m1_t src) {157 return __riscv_vreinterpret_v_bf16m1_i16m1(src);158}159 160// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_bf16m2_i16m2(161// CHECK-RV64-SAME: <vscale x 8 x bfloat> [[SRC:%.*]]) #[[ATTR0]] {162// CHECK-RV64-NEXT: entry:163// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x bfloat> [[SRC]] to <vscale x 8 x i16>164// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]165//166vint16m2_t test_vreinterpret_v_bf16m2_i16m2(vbfloat16m2_t src) {167 return __riscv_vreinterpret_v_bf16m2_i16m2(src);168}169 170// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_bf16m4_i16m4(171// CHECK-RV64-SAME: <vscale x 16 x bfloat> [[SRC:%.*]]) #[[ATTR0]] {172// CHECK-RV64-NEXT: entry:173// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 16 x bfloat> [[SRC]] to <vscale x 16 x i16>174// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]175//176vint16m4_t test_vreinterpret_v_bf16m4_i16m4(vbfloat16m4_t src) {177 return __riscv_vreinterpret_v_bf16m4_i16m4(src);178}179 180// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_bf16m8_i16m8(181// CHECK-RV64-SAME: <vscale x 32 x bfloat> [[SRC:%.*]]) #[[ATTR0]] {182// CHECK-RV64-NEXT: entry:183// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 32 x bfloat> [[SRC]] to <vscale x 32 x i16>184// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]185//186vint16m8_t test_vreinterpret_v_bf16m8_i16m8(vbfloat16m8_t src) {187 return __riscv_vreinterpret_v_bf16m8_i16m8(src);188}189 190// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vreinterpret_v_bf16mf4_u16mf4(191// CHECK-RV64-SAME: <vscale x 1 x bfloat> [[SRC:%.*]]) #[[ATTR0]] {192// CHECK-RV64-NEXT: entry:193// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 1 x bfloat> [[SRC]] to <vscale x 1 x i16>194// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]195//196vuint16mf4_t test_vreinterpret_v_bf16mf4_u16mf4(vbfloat16mf4_t src) {197 return __riscv_vreinterpret_v_bf16mf4_u16mf4(src);198}199 200// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vreinterpret_v_bf16mf2_u16mf2(201// CHECK-RV64-SAME: <vscale x 2 x bfloat> [[SRC:%.*]]) #[[ATTR0]] {202// CHECK-RV64-NEXT: entry:203// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 2 x bfloat> [[SRC]] to <vscale x 2 x i16>204// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]205//206vuint16mf2_t test_vreinterpret_v_bf16mf2_u16mf2(vbfloat16mf2_t src) {207 return __riscv_vreinterpret_v_bf16mf2_u16mf2(src);208}209 210// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_bf16m1_u16m1(211// CHECK-RV64-SAME: <vscale x 4 x bfloat> [[SRC:%.*]]) #[[ATTR0]] {212// CHECK-RV64-NEXT: entry:213// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 4 x bfloat> [[SRC]] to <vscale x 4 x i16>214// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]215//216vuint16m1_t test_vreinterpret_v_bf16m1_u16m1(vbfloat16m1_t src) {217 return __riscv_vreinterpret_v_bf16m1_u16m1(src);218}219 220// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_bf16m2_u16m2(221// CHECK-RV64-SAME: <vscale x 8 x bfloat> [[SRC:%.*]]) #[[ATTR0]] {222// CHECK-RV64-NEXT: entry:223// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 8 x bfloat> [[SRC]] to <vscale x 8 x i16>224// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]225//226vuint16m2_t test_vreinterpret_v_bf16m2_u16m2(vbfloat16m2_t src) {227 return __riscv_vreinterpret_v_bf16m2_u16m2(src);228}229 230// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_bf16m4_u16m4(231// CHECK-RV64-SAME: <vscale x 16 x bfloat> [[SRC:%.*]]) #[[ATTR0]] {232// CHECK-RV64-NEXT: entry:233// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 16 x bfloat> [[SRC]] to <vscale x 16 x i16>234// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]235//236vuint16m4_t test_vreinterpret_v_bf16m4_u16m4(vbfloat16m4_t src) {237 return __riscv_vreinterpret_v_bf16m4_u16m4(src);238}239 240// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_bf16m8_u16m8(241// CHECK-RV64-SAME: <vscale x 32 x bfloat> [[SRC:%.*]]) #[[ATTR0]] {242// CHECK-RV64-NEXT: entry:243// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast <vscale x 32 x bfloat> [[SRC]] to <vscale x 32 x i16>244// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]245//246vuint16m8_t test_vreinterpret_v_bf16m8_u16m8(vbfloat16m8_t src) {247 return __riscv_vreinterpret_v_bf16m8_u16m8(src);248}249