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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 42// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +zve64x \4// RUN: -target-feature +zvfbfmin -disable-O0-optnone \5// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \6// RUN: FileCheck --check-prefix=CHECK-RV64 %s7 8#include <riscv_vector.h>9 10// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg2ei32_v_bf16mf4x2(11// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], <vscale x 1 x i32> [[VS2:%.*]], target("riscv.vector.tuple", <vscale x 2 x i8>, 2) [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {12// CHECK-RV64-NEXT: entry:13// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) [[VS3]], ptr [[RS1]], <vscale x 1 x i32> [[VS2]], i64 [[VL]], i64 4)14// CHECK-RV64-NEXT: ret void15//16void test_vsoxseg2ei32_v_bf16mf4x2(__bf16 *rs1, vuint32mf2_t vs2,17 vbfloat16mf4x2_t vs3, size_t vl) {18 return __riscv_vsoxseg2ei32_v_bf16mf4x2(rs1, vs2, vs3, vl);19}20 21// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg2ei32_v_bf16mf2x2(22// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], <vscale x 2 x i32> [[VS2:%.*]], target("riscv.vector.tuple", <vscale x 4 x i8>, 2) [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {23// CHECK-RV64-NEXT: entry:24// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) [[VS3]], ptr [[RS1]], <vscale x 2 x i32> [[VS2]], i64 [[VL]], i64 4)25// CHECK-RV64-NEXT: ret void26//27void test_vsoxseg2ei32_v_bf16mf2x2(__bf16 *rs1, vuint32m1_t vs2,28 vbfloat16mf2x2_t vs3, size_t vl) {29 return __riscv_vsoxseg2ei32_v_bf16mf2x2(rs1, vs2, vs3, vl);30}31 32// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg2ei32_v_bf16m1x2(33// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], <vscale x 4 x i32> [[VS2:%.*]], target("riscv.vector.tuple", <vscale x 8 x i8>, 2) [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {34// CHECK-RV64-NEXT: entry:35// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) [[VS3]], ptr [[RS1]], <vscale x 4 x i32> [[VS2]], i64 [[VL]], i64 4)36// CHECK-RV64-NEXT: ret void37//38void test_vsoxseg2ei32_v_bf16m1x2(__bf16 *rs1, vuint32m2_t vs2,39 vbfloat16m1x2_t vs3, size_t vl) {40 return __riscv_vsoxseg2ei32_v_bf16m1x2(rs1, vs2, vs3, vl);41}42 43// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg2ei32_v_bf16m2x2(44// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], <vscale x 8 x i32> [[VS2:%.*]], target("riscv.vector.tuple", <vscale x 16 x i8>, 2) [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {45// CHECK-RV64-NEXT: entry:46// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) [[VS3]], ptr [[RS1]], <vscale x 8 x i32> [[VS2]], i64 [[VL]], i64 4)47// CHECK-RV64-NEXT: ret void48//49void test_vsoxseg2ei32_v_bf16m2x2(__bf16 *rs1, vuint32m4_t vs2,50 vbfloat16m2x2_t vs3, size_t vl) {51 return __riscv_vsoxseg2ei32_v_bf16m2x2(rs1, vs2, vs3, vl);52}53 54// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg2ei32_v_bf16m4x2(55// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], <vscale x 16 x i32> [[VS2:%.*]], target("riscv.vector.tuple", <vscale x 32 x i8>, 2) [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {56// CHECK-RV64-NEXT: entry:57// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) [[VS3]], ptr [[RS1]], <vscale x 16 x i32> [[VS2]], i64 [[VL]], i64 4)58// CHECK-RV64-NEXT: ret void59//60void test_vsoxseg2ei32_v_bf16m4x2(__bf16 *rs1, vuint32m8_t vs2,61 vbfloat16m4x2_t vs3, size_t vl) {62 return __riscv_vsoxseg2ei32_v_bf16m4x2(rs1, vs2, vs3, vl);63}64 65// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg2ei32_v_bf16mf4x2_m(66// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], <vscale x 1 x i32> [[VS2:%.*]], target("riscv.vector.tuple", <vscale x 2 x i8>, 2) [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {67// CHECK-RV64-NEXT: entry:68// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) [[VS3]], ptr [[RS1]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 4)69// CHECK-RV64-NEXT: ret void70//71void test_vsoxseg2ei32_v_bf16mf4x2_m(vbool64_t vm, __bf16 *rs1,72 vuint32mf2_t vs2, vbfloat16mf4x2_t vs3,73 size_t vl) {74 return __riscv_vsoxseg2ei32_v_bf16mf4x2_m(vm, rs1, vs2, vs3, vl);75}76 77// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg2ei32_v_bf16mf2x2_m(78// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], <vscale x 2 x i32> [[VS2:%.*]], target("riscv.vector.tuple", <vscale x 4 x i8>, 2) [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {79// CHECK-RV64-NEXT: entry:80// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) [[VS3]], ptr [[RS1]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 4)81// CHECK-RV64-NEXT: ret void82//83void test_vsoxseg2ei32_v_bf16mf2x2_m(vbool32_t vm, __bf16 *rs1, vuint32m1_t vs2,84 vbfloat16mf2x2_t vs3, size_t vl) {85 return __riscv_vsoxseg2ei32_v_bf16mf2x2_m(vm, rs1, vs2, vs3, vl);86}87 88// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg2ei32_v_bf16m1x2_m(89// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], <vscale x 4 x i32> [[VS2:%.*]], target("riscv.vector.tuple", <vscale x 8 x i8>, 2) [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {90// CHECK-RV64-NEXT: entry:91// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) [[VS3]], ptr [[RS1]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 4)92// CHECK-RV64-NEXT: ret void93//94void test_vsoxseg2ei32_v_bf16m1x2_m(vbool16_t vm, __bf16 *rs1, vuint32m2_t vs2,95 vbfloat16m1x2_t vs3, size_t vl) {96 return __riscv_vsoxseg2ei32_v_bf16m1x2_m(vm, rs1, vs2, vs3, vl);97}98 99// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg2ei32_v_bf16m2x2_m(100// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], <vscale x 8 x i32> [[VS2:%.*]], target("riscv.vector.tuple", <vscale x 16 x i8>, 2) [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {101// CHECK-RV64-NEXT: entry:102// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) [[VS3]], ptr [[RS1]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 4)103// CHECK-RV64-NEXT: ret void104//105void test_vsoxseg2ei32_v_bf16m2x2_m(vbool8_t vm, __bf16 *rs1, vuint32m4_t vs2,106 vbfloat16m2x2_t vs3, size_t vl) {107 return __riscv_vsoxseg2ei32_v_bf16m2x2_m(vm, rs1, vs2, vs3, vl);108}109 110// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg2ei32_v_bf16m4x2_m(111// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], <vscale x 16 x i32> [[VS2:%.*]], target("riscv.vector.tuple", <vscale x 32 x i8>, 2) [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {112// CHECK-RV64-NEXT: entry:113// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) [[VS3]], ptr [[RS1]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 4)114// CHECK-RV64-NEXT: ret void115//116void test_vsoxseg2ei32_v_bf16m4x2_m(vbool4_t vm, __bf16 *rs1, vuint32m8_t vs2,117 vbfloat16m4x2_t vs3, size_t vl) {118 return __riscv_vsoxseg2ei32_v_bf16m4x2_m(vm, rs1, vs2, vs3, vl);119}120