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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 42// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +zve64x \4// RUN: -target-feature +zvfbfmin -disable-O0-optnone \5// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \6// RUN: FileCheck --check-prefix=CHECK-RV64 %s7 8#include <riscv_vector.h>9 10// CHECK-RV64-LABEL: define dso_local void @test_vsseg3e16_v_bf16mf4x3(11// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], target("riscv.vector.tuple", <vscale x 2 x i8>, 3) [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {12// CHECK-RV64-NEXT: entry:13// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) [[VS3]], ptr [[RS1]], i64 [[VL]], i64 4)14// CHECK-RV64-NEXT: ret void15//16void test_vsseg3e16_v_bf16mf4x3(__bf16 *rs1, vbfloat16mf4x3_t vs3, size_t vl) {17 return __riscv_vsseg3e16_v_bf16mf4x3(rs1, vs3, vl);18}19 20// CHECK-RV64-LABEL: define dso_local void @test_vsseg3e16_v_bf16mf2x3(21// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {22// CHECK-RV64-NEXT: entry:23// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[VS3]], ptr [[RS1]], i64 [[VL]], i64 4)24// CHECK-RV64-NEXT: ret void25//26void test_vsseg3e16_v_bf16mf2x3(__bf16 *rs1, vbfloat16mf2x3_t vs3, size_t vl) {27 return __riscv_vsseg3e16_v_bf16mf2x3(rs1, vs3, vl);28}29 30// CHECK-RV64-LABEL: define dso_local void @test_vsseg3e16_v_bf16m1x3(31// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], target("riscv.vector.tuple", <vscale x 8 x i8>, 3) [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {32// CHECK-RV64-NEXT: entry:33// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) [[VS3]], ptr [[RS1]], i64 [[VL]], i64 4)34// CHECK-RV64-NEXT: ret void35//36void test_vsseg3e16_v_bf16m1x3(__bf16 *rs1, vbfloat16m1x3_t vs3, size_t vl) {37 return __riscv_vsseg3e16_v_bf16m1x3(rs1, vs3, vl);38}39 40// CHECK-RV64-LABEL: define dso_local void @test_vsseg3e16_v_bf16m2x3(41// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], target("riscv.vector.tuple", <vscale x 16 x i8>, 3) [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {42// CHECK-RV64-NEXT: entry:43// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) [[VS3]], ptr [[RS1]], i64 [[VL]], i64 4)44// CHECK-RV64-NEXT: ret void45//46void test_vsseg3e16_v_bf16m2x3(__bf16 *rs1, vbfloat16m2x3_t vs3, size_t vl) {47 return __riscv_vsseg3e16_v_bf16m2x3(rs1, vs3, vl);48}49 50// CHECK-RV64-LABEL: define dso_local void @test_vsseg3e16_v_bf16mf4x3_m(51// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], target("riscv.vector.tuple", <vscale x 2 x i8>, 3) [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {52// CHECK-RV64-NEXT: entry:53// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) [[VS3]], ptr [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 4)54// CHECK-RV64-NEXT: ret void55//56void test_vsseg3e16_v_bf16mf4x3_m(vbool64_t vm, __bf16 *rs1,57 vbfloat16mf4x3_t vs3, size_t vl) {58 return __riscv_vsseg3e16_v_bf16mf4x3_m(vm, rs1, vs3, vl);59}60 61// CHECK-RV64-LABEL: define dso_local void @test_vsseg3e16_v_bf16mf2x3_m(62// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {63// CHECK-RV64-NEXT: entry:64// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[VS3]], ptr [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 4)65// CHECK-RV64-NEXT: ret void66//67void test_vsseg3e16_v_bf16mf2x3_m(vbool32_t vm, __bf16 *rs1,68 vbfloat16mf2x3_t vs3, size_t vl) {69 return __riscv_vsseg3e16_v_bf16mf2x3_m(vm, rs1, vs3, vl);70}71 72// CHECK-RV64-LABEL: define dso_local void @test_vsseg3e16_v_bf16m1x3_m(73// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], target("riscv.vector.tuple", <vscale x 8 x i8>, 3) [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {74// CHECK-RV64-NEXT: entry:75// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) [[VS3]], ptr [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 4)76// CHECK-RV64-NEXT: ret void77//78void test_vsseg3e16_v_bf16m1x3_m(vbool16_t vm, __bf16 *rs1, vbfloat16m1x3_t vs3,79 size_t vl) {80 return __riscv_vsseg3e16_v_bf16m1x3_m(vm, rs1, vs3, vl);81}82 83// CHECK-RV64-LABEL: define dso_local void @test_vsseg3e16_v_bf16m2x3_m(84// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], target("riscv.vector.tuple", <vscale x 16 x i8>, 3) [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {85// CHECK-RV64-NEXT: entry:86// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) [[VS3]], ptr [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 4)87// CHECK-RV64-NEXT: ret void88//89void test_vsseg3e16_v_bf16m2x3_m(vbool8_t vm, __bf16 *rs1, vbfloat16m2x3_t vs3,90 size_t vl) {91 return __riscv_vsseg3e16_v_bf16m2x3_m(vm, rs1, vs3, vl);92}93