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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 42// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +zve64x \4// RUN: -target-feature +zvfbfmin -disable-O0-optnone \5// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \6// RUN: FileCheck --check-prefix=CHECK-RV64 %s7 8#include <riscv_vector.h>9 10// CHECK-RV64-LABEL: define dso_local void @test_vsseg5e16_v_bf16mf4x5(11// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], target("riscv.vector.tuple", <vscale x 2 x i8>, 5) [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {12// CHECK-RV64-NEXT: entry:13// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) [[VS3]], ptr [[RS1]], i64 [[VL]], i64 4)14// CHECK-RV64-NEXT: ret void15//16void test_vsseg5e16_v_bf16mf4x5(__bf16 *rs1, vbfloat16mf4x5_t vs3, size_t vl) {17 return __riscv_vsseg5e16_v_bf16mf4x5(rs1, vs3, vl);18}19 20// CHECK-RV64-LABEL: define dso_local void @test_vsseg5e16_v_bf16mf2x5(21// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {22// CHECK-RV64-NEXT: entry:23// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[VS3]], ptr [[RS1]], i64 [[VL]], i64 4)24// CHECK-RV64-NEXT: ret void25//26void test_vsseg5e16_v_bf16mf2x5(__bf16 *rs1, vbfloat16mf2x5_t vs3, size_t vl) {27 return __riscv_vsseg5e16_v_bf16mf2x5(rs1, vs3, vl);28}29 30// CHECK-RV64-LABEL: define dso_local void @test_vsseg5e16_v_bf16m1x5(31// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], target("riscv.vector.tuple", <vscale x 8 x i8>, 5) [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {32// CHECK-RV64-NEXT: entry:33// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) [[VS3]], ptr [[RS1]], i64 [[VL]], i64 4)34// CHECK-RV64-NEXT: ret void35//36void test_vsseg5e16_v_bf16m1x5(__bf16 *rs1, vbfloat16m1x5_t vs3, size_t vl) {37 return __riscv_vsseg5e16_v_bf16m1x5(rs1, vs3, vl);38}39 40// CHECK-RV64-LABEL: define dso_local void @test_vsseg5e16_v_bf16mf4x5_m(41// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], target("riscv.vector.tuple", <vscale x 2 x i8>, 5) [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {42// CHECK-RV64-NEXT: entry:43// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) [[VS3]], ptr [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 4)44// CHECK-RV64-NEXT: ret void45//46void test_vsseg5e16_v_bf16mf4x5_m(vbool64_t vm, __bf16 *rs1,47 vbfloat16mf4x5_t vs3, size_t vl) {48 return __riscv_vsseg5e16_v_bf16mf4x5_m(vm, rs1, vs3, vl);49}50 51// CHECK-RV64-LABEL: define dso_local void @test_vsseg5e16_v_bf16mf2x5_m(52// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {53// CHECK-RV64-NEXT: entry:54// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[VS3]], ptr [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 4)55// CHECK-RV64-NEXT: ret void56//57void test_vsseg5e16_v_bf16mf2x5_m(vbool32_t vm, __bf16 *rs1,58 vbfloat16mf2x5_t vs3, size_t vl) {59 return __riscv_vsseg5e16_v_bf16mf2x5_m(vm, rs1, vs3, vl);60}61 62// CHECK-RV64-LABEL: define dso_local void @test_vsseg5e16_v_bf16m1x5_m(63// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], target("riscv.vector.tuple", <vscale x 8 x i8>, 5) [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {64// CHECK-RV64-NEXT: entry:65// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) [[VS3]], ptr [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 4)66// CHECK-RV64-NEXT: ret void67//68void test_vsseg5e16_v_bf16m1x5_m(vbool16_t vm, __bf16 *rs1, vbfloat16m1x5_t vs3,69 size_t vl) {70 return __riscv_vsseg5e16_v_bf16m1x5_m(vm, rs1, vs3, vl);71}72