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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 42// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +zve64x \4// RUN: -target-feature +zvfbfmin -disable-O0-optnone \5// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \6// RUN: FileCheck --check-prefix=CHECK-RV64 %s7 8#include <riscv_vector.h>9 10// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg6ei64_v_bf16mf4x6(11// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], <vscale x 1 x i64> [[VS2:%.*]], target("riscv.vector.tuple", <vscale x 2 x i8>, 6) [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {12// CHECK-RV64-NEXT: entry:13// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) [[VS3]], ptr [[RS1]], <vscale x 1 x i64> [[VS2]], i64 [[VL]], i64 4)14// CHECK-RV64-NEXT: ret void15//16void test_vsuxseg6ei64_v_bf16mf4x6(__bf16 *rs1, vuint64m1_t vs2,17 vbfloat16mf4x6_t vs3, size_t vl) {18 return __riscv_vsuxseg6ei64(rs1, vs2, vs3, vl);19}20 21// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg6ei64_v_bf16mf2x6(22// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], <vscale x 2 x i64> [[VS2:%.*]], target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {23// CHECK-RV64-NEXT: entry:24// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[VS3]], ptr [[RS1]], <vscale x 2 x i64> [[VS2]], i64 [[VL]], i64 4)25// CHECK-RV64-NEXT: ret void26//27void test_vsuxseg6ei64_v_bf16mf2x6(__bf16 *rs1, vuint64m2_t vs2,28 vbfloat16mf2x6_t vs3, size_t vl) {29 return __riscv_vsuxseg6ei64(rs1, vs2, vs3, vl);30}31 32// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg6ei64_v_bf16m1x6(33// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], <vscale x 4 x i64> [[VS2:%.*]], target("riscv.vector.tuple", <vscale x 8 x i8>, 6) [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {34// CHECK-RV64-NEXT: entry:35// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) [[VS3]], ptr [[RS1]], <vscale x 4 x i64> [[VS2]], i64 [[VL]], i64 4)36// CHECK-RV64-NEXT: ret void37//38void test_vsuxseg6ei64_v_bf16m1x6(__bf16 *rs1, vuint64m4_t vs2,39 vbfloat16m1x6_t vs3, size_t vl) {40 return __riscv_vsuxseg6ei64(rs1, vs2, vs3, vl);41}42 43// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg6ei64_v_bf16mf4x6_m(44// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], <vscale x 1 x i64> [[VS2:%.*]], target("riscv.vector.tuple", <vscale x 2 x i8>, 6) [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {45// CHECK-RV64-NEXT: entry:46// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) [[VS3]], ptr [[RS1]], <vscale x 1 x i64> [[VS2]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 4)47// CHECK-RV64-NEXT: ret void48//49void test_vsuxseg6ei64_v_bf16mf4x6_m(vbool64_t vm, __bf16 *rs1, vuint64m1_t vs2,50 vbfloat16mf4x6_t vs3, size_t vl) {51 return __riscv_vsuxseg6ei64(vm, rs1, vs2, vs3, vl);52}53 54// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg6ei64_v_bf16mf2x6_m(55// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], <vscale x 2 x i64> [[VS2:%.*]], target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {56// CHECK-RV64-NEXT: entry:57// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[VS3]], ptr [[RS1]], <vscale x 2 x i64> [[VS2]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 4)58// CHECK-RV64-NEXT: ret void59//60void test_vsuxseg6ei64_v_bf16mf2x6_m(vbool32_t vm, __bf16 *rs1, vuint64m2_t vs2,61 vbfloat16mf2x6_t vs3, size_t vl) {62 return __riscv_vsuxseg6ei64(vm, rs1, vs2, vs3, vl);63}64 65// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg6ei64_v_bf16m1x6_m(66// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], <vscale x 4 x i64> [[VS2:%.*]], target("riscv.vector.tuple", <vscale x 8 x i8>, 6) [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {67// CHECK-RV64-NEXT: entry:68// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) [[VS3]], ptr [[RS1]], <vscale x 4 x i64> [[VS2]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 4)69// CHECK-RV64-NEXT: ret void70//71void test_vsuxseg6ei64_v_bf16m1x6_m(vbool16_t vm, __bf16 *rs1, vuint64m4_t vs2,72 vbfloat16m1x6_t vs3, size_t vl) {73 return __riscv_vsuxseg6ei64(vm, rs1, vs2, vs3, vl);74}75