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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 42// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +zve64x \4// RUN: -target-feature +zvfbfmin -disable-O0-optnone \5// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \6// RUN: FileCheck --check-prefix=CHECK-RV64 %s7 8#include <riscv_vector.h>9 10// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vluxei32_v_bf16mf4_tu(11// CHECK-RV64-SAME: <vscale x 1 x bfloat> [[VD:%.*]], ptr noundef [[RS1:%.*]], <vscale x 1 x i32> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {12// CHECK-RV64-NEXT: entry:13// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> [[VD]], ptr [[RS1]], <vscale x 1 x i32> [[RS2]], i64 [[VL]])14// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]15//16vbfloat16mf4_t test_vluxei32_v_bf16mf4_tu(vbfloat16mf4_t vd, const __bf16 *rs1, vuint32mf2_t rs2, size_t vl) {17 return __riscv_vluxei32_v_bf16mf4_tu(vd, rs1, rs2, vl);18}19 20// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vluxei32_v_bf16mf2_tu(21// CHECK-RV64-SAME: <vscale x 2 x bfloat> [[VD:%.*]], ptr noundef [[RS1:%.*]], <vscale x 2 x i32> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {22// CHECK-RV64-NEXT: entry:23// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> [[VD]], ptr [[RS1]], <vscale x 2 x i32> [[RS2]], i64 [[VL]])24// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]25//26vbfloat16mf2_t test_vluxei32_v_bf16mf2_tu(vbfloat16mf2_t vd, const __bf16 *rs1, vuint32m1_t rs2, size_t vl) {27 return __riscv_vluxei32_v_bf16mf2_tu(vd, rs1, rs2, vl);28}29 30// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vluxei32_v_bf16m1_tu(31// CHECK-RV64-SAME: <vscale x 4 x bfloat> [[VD:%.*]], ptr noundef [[RS1:%.*]], <vscale x 4 x i32> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {32// CHECK-RV64-NEXT: entry:33// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> [[VD]], ptr [[RS1]], <vscale x 4 x i32> [[RS2]], i64 [[VL]])34// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]35//36vbfloat16m1_t test_vluxei32_v_bf16m1_tu(vbfloat16m1_t vd, const __bf16 *rs1, vuint32m2_t rs2, size_t vl) {37 return __riscv_vluxei32_v_bf16m1_tu(vd, rs1, rs2, vl);38}39 40// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vluxei32_v_bf16m2_tu(41// CHECK-RV64-SAME: <vscale x 8 x bfloat> [[VD:%.*]], ptr noundef [[RS1:%.*]], <vscale x 8 x i32> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {42// CHECK-RV64-NEXT: entry:43// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> [[VD]], ptr [[RS1]], <vscale x 8 x i32> [[RS2]], i64 [[VL]])44// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]45//46vbfloat16m2_t test_vluxei32_v_bf16m2_tu(vbfloat16m2_t vd, const __bf16 *rs1, vuint32m4_t rs2, size_t vl) {47 return __riscv_vluxei32_v_bf16m2_tu(vd, rs1, rs2, vl);48}49 50// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vluxei32_v_bf16m4_tu(51// CHECK-RV64-SAME: <vscale x 16 x bfloat> [[VD:%.*]], ptr noundef [[RS1:%.*]], <vscale x 16 x i32> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {52// CHECK-RV64-NEXT: entry:53// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> [[VD]], ptr [[RS1]], <vscale x 16 x i32> [[RS2]], i64 [[VL]])54// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]55//56vbfloat16m4_t test_vluxei32_v_bf16m4_tu(vbfloat16m4_t vd, const __bf16 *rs1, vuint32m8_t rs2, size_t vl) {57 return __riscv_vluxei32_v_bf16m4_tu(vd, rs1, rs2, vl);58}59 60// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vluxei32_v_bf16mf4_tum(61// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x bfloat> [[VD:%.*]], ptr noundef [[RS1:%.*]], <vscale x 1 x i32> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {62// CHECK-RV64-NEXT: entry:63// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> [[VD]], ptr [[RS1]], <vscale x 1 x i32> [[RS2]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)64// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]65//66vbfloat16mf4_t test_vluxei32_v_bf16mf4_tum(vbool64_t vm, vbfloat16mf4_t vd, const __bf16 *rs1, vuint32mf2_t rs2, size_t vl) {67 return __riscv_vluxei32_v_bf16mf4_tum(vm, vd, rs1, rs2, vl);68}69 70// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vluxei32_v_bf16mf2_tum(71// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x bfloat> [[VD:%.*]], ptr noundef [[RS1:%.*]], <vscale x 2 x i32> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {72// CHECK-RV64-NEXT: entry:73// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> [[VD]], ptr [[RS1]], <vscale x 2 x i32> [[RS2]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)74// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]75//76vbfloat16mf2_t test_vluxei32_v_bf16mf2_tum(vbool32_t vm, vbfloat16mf2_t vd, const __bf16 *rs1, vuint32m1_t rs2, size_t vl) {77 return __riscv_vluxei32_v_bf16mf2_tum(vm, vd, rs1, rs2, vl);78}79 80// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vluxei32_v_bf16m1_tum(81// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x bfloat> [[VD:%.*]], ptr noundef [[RS1:%.*]], <vscale x 4 x i32> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {82// CHECK-RV64-NEXT: entry:83// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> [[VD]], ptr [[RS1]], <vscale x 4 x i32> [[RS2]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)84// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]85//86vbfloat16m1_t test_vluxei32_v_bf16m1_tum(vbool16_t vm, vbfloat16m1_t vd, const __bf16 *rs1, vuint32m2_t rs2, size_t vl) {87 return __riscv_vluxei32_v_bf16m1_tum(vm, vd, rs1, rs2, vl);88}89 90// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vluxei32_v_bf16m2_tum(91// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x bfloat> [[VD:%.*]], ptr noundef [[RS1:%.*]], <vscale x 8 x i32> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {92// CHECK-RV64-NEXT: entry:93// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> [[VD]], ptr [[RS1]], <vscale x 8 x i32> [[RS2]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)94// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]95//96vbfloat16m2_t test_vluxei32_v_bf16m2_tum(vbool8_t vm, vbfloat16m2_t vd, const __bf16 *rs1, vuint32m4_t rs2, size_t vl) {97 return __riscv_vluxei32_v_bf16m2_tum(vm, vd, rs1, rs2, vl);98}99 100// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vluxei32_v_bf16m4_tum(101// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x bfloat> [[VD:%.*]], ptr noundef [[RS1:%.*]], <vscale x 16 x i32> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {102// CHECK-RV64-NEXT: entry:103// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.mask.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> [[VD]], ptr [[RS1]], <vscale x 16 x i32> [[RS2]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)104// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]105//106vbfloat16m4_t test_vluxei32_v_bf16m4_tum(vbool4_t vm, vbfloat16m4_t vd, const __bf16 *rs1, vuint32m8_t rs2, size_t vl) {107 return __riscv_vluxei32_v_bf16m4_tum(vm, vd, rs1, rs2, vl);108}109 110// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vluxei32_v_bf16mf4_tumu(111// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x bfloat> [[VD:%.*]], ptr noundef [[RS1:%.*]], <vscale x 1 x i32> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {112// CHECK-RV64-NEXT: entry:113// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> [[VD]], ptr [[RS1]], <vscale x 1 x i32> [[RS2]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)114// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]115//116vbfloat16mf4_t test_vluxei32_v_bf16mf4_tumu(vbool64_t vm, vbfloat16mf4_t vd, const __bf16 *rs1, vuint32mf2_t rs2, size_t vl) {117 return __riscv_vluxei32_v_bf16mf4_tumu(vm, vd, rs1, rs2, vl);118}119 120// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vluxei32_v_bf16mf2_tumu(121// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x bfloat> [[VD:%.*]], ptr noundef [[RS1:%.*]], <vscale x 2 x i32> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {122// CHECK-RV64-NEXT: entry:123// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> [[VD]], ptr [[RS1]], <vscale x 2 x i32> [[RS2]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)124// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]125//126vbfloat16mf2_t test_vluxei32_v_bf16mf2_tumu(vbool32_t vm, vbfloat16mf2_t vd, const __bf16 *rs1, vuint32m1_t rs2, size_t vl) {127 return __riscv_vluxei32_v_bf16mf2_tumu(vm, vd, rs1, rs2, vl);128}129 130// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vluxei32_v_bf16m1_tumu(131// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x bfloat> [[VD:%.*]], ptr noundef [[RS1:%.*]], <vscale x 4 x i32> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {132// CHECK-RV64-NEXT: entry:133// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> [[VD]], ptr [[RS1]], <vscale x 4 x i32> [[RS2]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)134// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]135//136vbfloat16m1_t test_vluxei32_v_bf16m1_tumu(vbool16_t vm, vbfloat16m1_t vd, const __bf16 *rs1, vuint32m2_t rs2, size_t vl) {137 return __riscv_vluxei32_v_bf16m1_tumu(vm, vd, rs1, rs2, vl);138}139 140// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vluxei32_v_bf16m2_tumu(141// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x bfloat> [[VD:%.*]], ptr noundef [[RS1:%.*]], <vscale x 8 x i32> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {142// CHECK-RV64-NEXT: entry:143// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> [[VD]], ptr [[RS1]], <vscale x 8 x i32> [[RS2]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)144// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]145//146vbfloat16m2_t test_vluxei32_v_bf16m2_tumu(vbool8_t vm, vbfloat16m2_t vd, const __bf16 *rs1, vuint32m4_t rs2, size_t vl) {147 return __riscv_vluxei32_v_bf16m2_tumu(vm, vd, rs1, rs2, vl);148}149 150// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vluxei32_v_bf16m4_tumu(151// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x bfloat> [[VD:%.*]], ptr noundef [[RS1:%.*]], <vscale x 16 x i32> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {152// CHECK-RV64-NEXT: entry:153// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.mask.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> [[VD]], ptr [[RS1]], <vscale x 16 x i32> [[RS2]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)154// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]155//156vbfloat16m4_t test_vluxei32_v_bf16m4_tumu(vbool4_t vm, vbfloat16m4_t vd, const __bf16 *rs1, vuint32m8_t rs2, size_t vl) {157 return __riscv_vluxei32_v_bf16m4_tumu(vm, vd, rs1, rs2, vl);158}159 160// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vluxei32_v_bf16mf4_mu(161// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x bfloat> [[VD:%.*]], ptr noundef [[RS1:%.*]], <vscale x 1 x i32> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {162// CHECK-RV64-NEXT: entry:163// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> [[VD]], ptr [[RS1]], <vscale x 1 x i32> [[RS2]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)164// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]165//166vbfloat16mf4_t test_vluxei32_v_bf16mf4_mu(vbool64_t vm, vbfloat16mf4_t vd, const __bf16 *rs1, vuint32mf2_t rs2, size_t vl) {167 return __riscv_vluxei32_v_bf16mf4_mu(vm, vd, rs1, rs2, vl);168}169 170// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vluxei32_v_bf16mf2_mu(171// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x bfloat> [[VD:%.*]], ptr noundef [[RS1:%.*]], <vscale x 2 x i32> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {172// CHECK-RV64-NEXT: entry:173// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> [[VD]], ptr [[RS1]], <vscale x 2 x i32> [[RS2]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)174// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]175//176vbfloat16mf2_t test_vluxei32_v_bf16mf2_mu(vbool32_t vm, vbfloat16mf2_t vd, const __bf16 *rs1, vuint32m1_t rs2, size_t vl) {177 return __riscv_vluxei32_v_bf16mf2_mu(vm, vd, rs1, rs2, vl);178}179 180// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vluxei32_v_bf16m1_mu(181// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x bfloat> [[VD:%.*]], ptr noundef [[RS1:%.*]], <vscale x 4 x i32> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {182// CHECK-RV64-NEXT: entry:183// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> [[VD]], ptr [[RS1]], <vscale x 4 x i32> [[RS2]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)184// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]185//186vbfloat16m1_t test_vluxei32_v_bf16m1_mu(vbool16_t vm, vbfloat16m1_t vd, const __bf16 *rs1, vuint32m2_t rs2, size_t vl) {187 return __riscv_vluxei32_v_bf16m1_mu(vm, vd, rs1, rs2, vl);188}189 190// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vluxei32_v_bf16m2_mu(191// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x bfloat> [[VD:%.*]], ptr noundef [[RS1:%.*]], <vscale x 8 x i32> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {192// CHECK-RV64-NEXT: entry:193// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> [[VD]], ptr [[RS1]], <vscale x 8 x i32> [[RS2]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)194// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]195//196vbfloat16m2_t test_vluxei32_v_bf16m2_mu(vbool8_t vm, vbfloat16m2_t vd, const __bf16 *rs1, vuint32m4_t rs2, size_t vl) {197 return __riscv_vluxei32_v_bf16m2_mu(vm, vd, rs1, rs2, vl);198}199 200// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vluxei32_v_bf16m4_mu(201// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x bfloat> [[VD:%.*]], ptr noundef [[RS1:%.*]], <vscale x 16 x i32> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {202// CHECK-RV64-NEXT: entry:203// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.mask.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> [[VD]], ptr [[RS1]], <vscale x 16 x i32> [[RS2]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)204// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]205//206vbfloat16m4_t test_vluxei32_v_bf16m4_mu(vbool4_t vm, vbfloat16m4_t vd, const __bf16 *rs1, vuint32m8_t rs2, size_t vl) {207 return __riscv_vluxei32_v_bf16m4_mu(vm, vd, rs1, rs2, vl);208}209