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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 42// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +zve64x \4// RUN: -target-feature +zvfbfmin -disable-O0-optnone \5// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \6// RUN: FileCheck --check-prefix=CHECK-RV64 %s7 8#include <riscv_vector.h>9 10// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_bf16mf4x5_tu(11// CHECK-RV64-SAME: target("riscv.vector.tuple", <vscale x 2 x i8>, 5) [[VD:%.*]], ptr noundef [[RS1:%.*]], <vscale x 1 x i32> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {12// CHECK-RV64-NEXT: entry:13// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) [[VD]], ptr [[RS1]], <vscale x 1 x i32> [[RS2]], i64 [[VL]], i64 4)14// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) [[TMP0]]15//16vbfloat16mf4x5_t test_vloxseg5ei32_v_bf16mf4x5_tu(vbfloat16mf4x5_t vd,17 const __bf16 *rs1,18 vuint32mf2_t rs2, size_t vl) {19 return __riscv_vloxseg5ei32_tu(vd, rs1, rs2, vl);20}21 22// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_bf16mf2x5_tu(23// CHECK-RV64-SAME: target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[VD:%.*]], ptr noundef [[RS1:%.*]], <vscale x 2 x i32> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {24// CHECK-RV64-NEXT: entry:25// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[VD]], ptr [[RS1]], <vscale x 2 x i32> [[RS2]], i64 [[VL]], i64 4)26// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[TMP0]]27//28vbfloat16mf2x5_t test_vloxseg5ei32_v_bf16mf2x5_tu(vbfloat16mf2x5_t vd,29 const __bf16 *rs1,30 vuint32m1_t rs2, size_t vl) {31 return __riscv_vloxseg5ei32_tu(vd, rs1, rs2, vl);32}33 34// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_bf16m1x5_tu(35// CHECK-RV64-SAME: target("riscv.vector.tuple", <vscale x 8 x i8>, 5) [[VD:%.*]], ptr noundef [[RS1:%.*]], <vscale x 4 x i32> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {36// CHECK-RV64-NEXT: entry:37// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) [[VD]], ptr [[RS1]], <vscale x 4 x i32> [[RS2]], i64 [[VL]], i64 4)38// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) [[TMP0]]39//40vbfloat16m1x5_t test_vloxseg5ei32_v_bf16m1x5_tu(vbfloat16m1x5_t vd,41 const __bf16 *rs1,42 vuint32m2_t rs2, size_t vl) {43 return __riscv_vloxseg5ei32_tu(vd, rs1, rs2, vl);44}45 46// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_bf16mf4x5_tum(47// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], target("riscv.vector.tuple", <vscale x 2 x i8>, 5) [[VD:%.*]], ptr noundef [[RS1:%.*]], <vscale x 1 x i32> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {48// CHECK-RV64-NEXT: entry:49// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) [[VD]], ptr [[RS1]], <vscale x 1 x i32> [[RS2]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2, i64 4)50// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) [[TMP0]]51//52vbfloat16mf4x5_t test_vloxseg5ei32_v_bf16mf4x5_tum(vbool64_t vm,53 vbfloat16mf4x5_t vd,54 const __bf16 *rs1,55 vuint32mf2_t rs2,56 size_t vl) {57 return __riscv_vloxseg5ei32_tum(vm, vd, rs1, rs2, vl);58}59 60// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_bf16mf2x5_tum(61// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[VD:%.*]], ptr noundef [[RS1:%.*]], <vscale x 2 x i32> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {62// CHECK-RV64-NEXT: entry:63// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[VD]], ptr [[RS1]], <vscale x 2 x i32> [[RS2]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2, i64 4)64// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[TMP0]]65//66vbfloat16mf2x5_t test_vloxseg5ei32_v_bf16mf2x5_tum(vbool32_t vm,67 vbfloat16mf2x5_t vd,68 const __bf16 *rs1,69 vuint32m1_t rs2, size_t vl) {70 return __riscv_vloxseg5ei32_tum(vm, vd, rs1, rs2, vl);71}72 73// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_bf16m1x5_tum(74// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], target("riscv.vector.tuple", <vscale x 8 x i8>, 5) [[VD:%.*]], ptr noundef [[RS1:%.*]], <vscale x 4 x i32> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {75// CHECK-RV64-NEXT: entry:76// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) [[VD]], ptr [[RS1]], <vscale x 4 x i32> [[RS2]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2, i64 4)77// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) [[TMP0]]78//79vbfloat16m1x5_t test_vloxseg5ei32_v_bf16m1x5_tum(vbool16_t vm,80 vbfloat16m1x5_t vd,81 const __bf16 *rs1,82 vuint32m2_t rs2, size_t vl) {83 return __riscv_vloxseg5ei32_tum(vm, vd, rs1, rs2, vl);84}85 86// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_bf16mf4x5_tumu(87// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], target("riscv.vector.tuple", <vscale x 2 x i8>, 5) [[VD:%.*]], ptr noundef [[RS1:%.*]], <vscale x 1 x i32> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {88// CHECK-RV64-NEXT: entry:89// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) [[VD]], ptr [[RS1]], <vscale x 1 x i32> [[RS2]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0, i64 4)90// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) [[TMP0]]91//92vbfloat16mf4x5_t test_vloxseg5ei32_v_bf16mf4x5_tumu(vbool64_t vm,93 vbfloat16mf4x5_t vd,94 const __bf16 *rs1,95 vuint32mf2_t rs2,96 size_t vl) {97 return __riscv_vloxseg5ei32_tumu(vm, vd, rs1, rs2, vl);98}99 100// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_bf16mf2x5_tumu(101// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[VD:%.*]], ptr noundef [[RS1:%.*]], <vscale x 2 x i32> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {102// CHECK-RV64-NEXT: entry:103// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[VD]], ptr [[RS1]], <vscale x 2 x i32> [[RS2]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0, i64 4)104// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[TMP0]]105//106vbfloat16mf2x5_t test_vloxseg5ei32_v_bf16mf2x5_tumu(vbool32_t vm,107 vbfloat16mf2x5_t vd,108 const __bf16 *rs1,109 vuint32m1_t rs2,110 size_t vl) {111 return __riscv_vloxseg5ei32_tumu(vm, vd, rs1, rs2, vl);112}113 114// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_bf16m1x5_tumu(115// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], target("riscv.vector.tuple", <vscale x 8 x i8>, 5) [[VD:%.*]], ptr noundef [[RS1:%.*]], <vscale x 4 x i32> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {116// CHECK-RV64-NEXT: entry:117// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) [[VD]], ptr [[RS1]], <vscale x 4 x i32> [[RS2]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0, i64 4)118// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) [[TMP0]]119//120vbfloat16m1x5_t test_vloxseg5ei32_v_bf16m1x5_tumu(vbool16_t vm,121 vbfloat16m1x5_t vd,122 const __bf16 *rs1,123 vuint32m2_t rs2, size_t vl) {124 return __riscv_vloxseg5ei32_tumu(vm, vd, rs1, rs2, vl);125}126 127// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_bf16mf4x5_mu(128// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], target("riscv.vector.tuple", <vscale x 2 x i8>, 5) [[VD:%.*]], ptr noundef [[RS1:%.*]], <vscale x 1 x i32> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {129// CHECK-RV64-NEXT: entry:130// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) [[VD]], ptr [[RS1]], <vscale x 1 x i32> [[RS2]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1, i64 4)131// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) [[TMP0]]132//133vbfloat16mf4x5_t test_vloxseg5ei32_v_bf16mf4x5_mu(vbool64_t vm,134 vbfloat16mf4x5_t vd,135 const __bf16 *rs1,136 vuint32mf2_t rs2, size_t vl) {137 return __riscv_vloxseg5ei32_mu(vm, vd, rs1, rs2, vl);138}139 140// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_bf16mf2x5_mu(141// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[VD:%.*]], ptr noundef [[RS1:%.*]], <vscale x 2 x i32> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {142// CHECK-RV64-NEXT: entry:143// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[VD]], ptr [[RS1]], <vscale x 2 x i32> [[RS2]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1, i64 4)144// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[TMP0]]145//146vbfloat16mf2x5_t test_vloxseg5ei32_v_bf16mf2x5_mu(vbool32_t vm,147 vbfloat16mf2x5_t vd,148 const __bf16 *rs1,149 vuint32m1_t rs2, size_t vl) {150 return __riscv_vloxseg5ei32_mu(vm, vd, rs1, rs2, vl);151}152 153// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_bf16m1x5_mu(154// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], target("riscv.vector.tuple", <vscale x 8 x i8>, 5) [[VD:%.*]], ptr noundef [[RS1:%.*]], <vscale x 4 x i32> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {155// CHECK-RV64-NEXT: entry:156// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) [[VD]], ptr [[RS1]], <vscale x 4 x i32> [[RS2]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1, i64 4)157// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) [[TMP0]]158//159vbfloat16m1x5_t test_vloxseg5ei32_v_bf16m1x5_mu(vbool16_t vm,160 vbfloat16m1x5_t vd,161 const __bf16 *rs1,162 vuint32m2_t rs2, size_t vl) {163 return __riscv_vloxseg5ei32_mu(vm, vd, rs1, rs2, vl);164}165