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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 42// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +zve64x \4// RUN: -target-feature +zvfbfmin -disable-O0-optnone \5// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \6// RUN: FileCheck --check-prefix=CHECK-RV64 %s7 8#include <riscv_vector.h>9 10// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_bf16mf4x4_tu(11// CHECK-RV64-SAME: target("riscv.vector.tuple", <vscale x 2 x i8>, 4) [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {12// CHECK-RV64-NEXT: entry:13// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) [[VD]], ptr [[RS1]], i64 [[VL]], i64 4)14// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) [[TMP0]]15//16vbfloat16mf4x4_t test_vlseg4e16_v_bf16mf4x4_tu(vbfloat16mf4x4_t vd,17 const __bf16 *rs1, size_t vl) {18 return __riscv_vlseg4e16_tu(vd, rs1, vl);19}20 21// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_bf16mf2x4_tu(22// CHECK-RV64-SAME: target("riscv.vector.tuple", <vscale x 4 x i8>, 4) [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {23// CHECK-RV64-NEXT: entry:24// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) [[VD]], ptr [[RS1]], i64 [[VL]], i64 4)25// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) [[TMP0]]26//27vbfloat16mf2x4_t test_vlseg4e16_v_bf16mf2x4_tu(vbfloat16mf2x4_t vd,28 const __bf16 *rs1, size_t vl) {29 return __riscv_vlseg4e16_tu(vd, rs1, vl);30}31 32// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_bf16m1x4_tu(33// CHECK-RV64-SAME: target("riscv.vector.tuple", <vscale x 8 x i8>, 4) [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {34// CHECK-RV64-NEXT: entry:35// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) [[VD]], ptr [[RS1]], i64 [[VL]], i64 4)36// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) [[TMP0]]37//38vbfloat16m1x4_t test_vlseg4e16_v_bf16m1x4_tu(vbfloat16m1x4_t vd,39 const __bf16 *rs1, size_t vl) {40 return __riscv_vlseg4e16_tu(vd, rs1, vl);41}42 43// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_bf16m2x4_tu(44// CHECK-RV64-SAME: target("riscv.vector.tuple", <vscale x 16 x i8>, 4) [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {45// CHECK-RV64-NEXT: entry:46// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) [[VD]], ptr [[RS1]], i64 [[VL]], i64 4)47// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) [[TMP0]]48//49vbfloat16m2x4_t test_vlseg4e16_v_bf16m2x4_tu(vbfloat16m2x4_t vd,50 const __bf16 *rs1, size_t vl) {51 return __riscv_vlseg4e16_tu(vd, rs1, vl);52}53 54// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_bf16mf4x4_tum(55// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], target("riscv.vector.tuple", <vscale x 2 x i8>, 4) [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {56// CHECK-RV64-NEXT: entry:57// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) [[VD]], ptr [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2, i64 4)58// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) [[TMP0]]59//60vbfloat16mf4x4_t test_vlseg4e16_v_bf16mf4x4_tum(vbool64_t vm,61 vbfloat16mf4x4_t vd,62 const __bf16 *rs1, size_t vl) {63 return __riscv_vlseg4e16_tum(vm, vd, rs1, vl);64}65 66// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_bf16mf2x4_tum(67// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], target("riscv.vector.tuple", <vscale x 4 x i8>, 4) [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {68// CHECK-RV64-NEXT: entry:69// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) [[VD]], ptr [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2, i64 4)70// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) [[TMP0]]71//72vbfloat16mf2x4_t test_vlseg4e16_v_bf16mf2x4_tum(vbool32_t vm,73 vbfloat16mf2x4_t vd,74 const __bf16 *rs1, size_t vl) {75 return __riscv_vlseg4e16_tum(vm, vd, rs1, vl);76}77 78// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_bf16m1x4_tum(79// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], target("riscv.vector.tuple", <vscale x 8 x i8>, 4) [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {80// CHECK-RV64-NEXT: entry:81// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) [[VD]], ptr [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2, i64 4)82// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) [[TMP0]]83//84vbfloat16m1x4_t test_vlseg4e16_v_bf16m1x4_tum(vbool16_t vm, vbfloat16m1x4_t vd,85 const __bf16 *rs1, size_t vl) {86 return __riscv_vlseg4e16_tum(vm, vd, rs1, vl);87}88 89// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_bf16m2x4_tum(90// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], target("riscv.vector.tuple", <vscale x 16 x i8>, 4) [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {91// CHECK-RV64-NEXT: entry:92// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) [[VD]], ptr [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2, i64 4)93// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) [[TMP0]]94//95vbfloat16m2x4_t test_vlseg4e16_v_bf16m2x4_tum(vbool8_t vm, vbfloat16m2x4_t vd,96 const __bf16 *rs1, size_t vl) {97 return __riscv_vlseg4e16_tum(vm, vd, rs1, vl);98}99 100// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_bf16mf4x4_tumu(101// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], target("riscv.vector.tuple", <vscale x 2 x i8>, 4) [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {102// CHECK-RV64-NEXT: entry:103// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) [[VD]], ptr [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0, i64 4)104// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) [[TMP0]]105//106vbfloat16mf4x4_t test_vlseg4e16_v_bf16mf4x4_tumu(vbool64_t vm,107 vbfloat16mf4x4_t vd,108 const __bf16 *rs1, size_t vl) {109 return __riscv_vlseg4e16_tumu(vm, vd, rs1, vl);110}111 112// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_bf16mf2x4_tumu(113// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], target("riscv.vector.tuple", <vscale x 4 x i8>, 4) [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {114// CHECK-RV64-NEXT: entry:115// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) [[VD]], ptr [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0, i64 4)116// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) [[TMP0]]117//118vbfloat16mf2x4_t test_vlseg4e16_v_bf16mf2x4_tumu(vbool32_t vm,119 vbfloat16mf2x4_t vd,120 const __bf16 *rs1, size_t vl) {121 return __riscv_vlseg4e16_tumu(vm, vd, rs1, vl);122}123 124// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_bf16m1x4_tumu(125// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], target("riscv.vector.tuple", <vscale x 8 x i8>, 4) [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {126// CHECK-RV64-NEXT: entry:127// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) [[VD]], ptr [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0, i64 4)128// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) [[TMP0]]129//130vbfloat16m1x4_t test_vlseg4e16_v_bf16m1x4_tumu(vbool16_t vm, vbfloat16m1x4_t vd,131 const __bf16 *rs1, size_t vl) {132 return __riscv_vlseg4e16_tumu(vm, vd, rs1, vl);133}134 135// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_bf16m2x4_tumu(136// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], target("riscv.vector.tuple", <vscale x 16 x i8>, 4) [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {137// CHECK-RV64-NEXT: entry:138// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) [[VD]], ptr [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0, i64 4)139// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) [[TMP0]]140//141vbfloat16m2x4_t test_vlseg4e16_v_bf16m2x4_tumu(vbool8_t vm, vbfloat16m2x4_t vd,142 const __bf16 *rs1, size_t vl) {143 return __riscv_vlseg4e16_tumu(vm, vd, rs1, vl);144}145 146// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_bf16mf4x4_mu(147// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], target("riscv.vector.tuple", <vscale x 2 x i8>, 4) [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {148// CHECK-RV64-NEXT: entry:149// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) [[VD]], ptr [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1, i64 4)150// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) [[TMP0]]151//152vbfloat16mf4x4_t test_vlseg4e16_v_bf16mf4x4_mu(vbool64_t vm,153 vbfloat16mf4x4_t vd,154 const __bf16 *rs1, size_t vl) {155 return __riscv_vlseg4e16_mu(vm, vd, rs1, vl);156}157 158// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_bf16mf2x4_mu(159// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], target("riscv.vector.tuple", <vscale x 4 x i8>, 4) [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {160// CHECK-RV64-NEXT: entry:161// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) [[VD]], ptr [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1, i64 4)162// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) [[TMP0]]163//164vbfloat16mf2x4_t test_vlseg4e16_v_bf16mf2x4_mu(vbool32_t vm,165 vbfloat16mf2x4_t vd,166 const __bf16 *rs1, size_t vl) {167 return __riscv_vlseg4e16_mu(vm, vd, rs1, vl);168}169 170// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_bf16m1x4_mu(171// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], target("riscv.vector.tuple", <vscale x 8 x i8>, 4) [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {172// CHECK-RV64-NEXT: entry:173// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) [[VD]], ptr [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1, i64 4)174// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) [[TMP0]]175//176vbfloat16m1x4_t test_vlseg4e16_v_bf16m1x4_mu(vbool16_t vm, vbfloat16m1x4_t vd,177 const __bf16 *rs1, size_t vl) {178 return __riscv_vlseg4e16_mu(vm, vd, rs1, vl);179}180 181// CHECK-RV64-LABEL: define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_bf16m2x4_mu(182// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], target("riscv.vector.tuple", <vscale x 16 x i8>, 4) [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {183// CHECK-RV64-NEXT: entry:184// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) [[VD]], ptr [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1, i64 4)185// CHECK-RV64-NEXT: ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) [[TMP0]]186//187vbfloat16m2x4_t test_vlseg4e16_v_bf16m2x4_mu(vbool8_t vm, vbfloat16m2x4_t vd,188 const __bf16 *rs1, size_t vl) {189 return __riscv_vlseg4e16_mu(vm, vd, rs1, vl);190}191